Re: [PATCH 0/2] arm: dts: Add Itap Delay Value For High Speed DDR
On 08/01/24 7:35 pm, Bryan Brattlof wrote: Hi Bhavya! On January 8, 2024 thus sayeth Bhavya Kapoor: This Series adds Itap Delay Value for DDR52 speed mode for eMMC in J7200 SoC and for DDR50 speed mode for MMCSD in J721s2 SoC. Bhavya Kapoor (2): arm: dts: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode arch/arm/dts/k3-j7200-main.dtsi | 1 + arch/arm/dts/k3-j721s2-main.dtsi | 1 + Because of the periodic syncs with the kernel, modifying these dt files in U-Boot will cause confusion. (Which node is correct why did we have to do this in U-Boot and not in the Kernel... bla bla bla) If they absolutely need to go in now please override these nodes in the *-u-boot.dtsi files with a comment so we can keep track of these changes during the next sync with Linux. ~Bryan Hi Bryan, Fyi, This patch went in kernel as well. Can be tracked below- https://lore.kernel.org/all/170266085077.3490141.14935960940418963459.b4...@ti.com/ So , kernel and uboot dt files will remain in sync. ~B-Kapoor
[PATCH 0/2] arm: dts: Add Itap Delay Value For High Speed DDR
This Series adds Itap Delay Value for DDR52 speed mode for eMMC in J7200 SoC and for DDR50 speed mode for MMCSD in J721s2 SoC. Bhavya Kapoor (2): arm: dts: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode arch/arm/dts/k3-j7200-main.dtsi | 1 + arch/arm/dts/k3-j721s2-main.dtsi | 1 + 2 files changed, 2 insertions(+) -- 2.40.1
[PATCH 2/2] arm: dts: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode
DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD Ultra High Speed DDR which is DDR50 speed mode for J721s2 SoC according to datasheet for J721s2 [1]. [1] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J721s2 datasheet - https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf Signed-off-by: Bhavya Kapoor --- arch/arm/dts/k3-j721s2-main.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/k3-j721s2-main.dtsi b/arch/arm/dts/k3-j721s2-main.dtsi index 084f8f5b66..8a86f6ce8e 100644 --- a/arch/arm/dts/k3-j721s2-main.dtsi +++ b/arch/arm/dts/k3-j721s2-main.dtsi @@ -766,6 +766,7 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent; -- 2.40.1
[PATCH 1/2] arm: dts: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode
DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for eMMC High Speed DDR which is DDR52 speed mode for J7200 SoC according to datasheet for J7200 [1]. [1] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface, in J7200 datasheet - https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf Signed-off-by: Bhavya Kapoor --- arch/arm/dts/k3-j7200-main.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/dts/k3-j7200-main.dtsi b/arch/arm/dts/k3-j7200-main.dtsi index cdb1d6b2a9..18531ba803 100644 --- a/arch/arm/dts/k3-j7200-main.dtsi +++ b/arch/arm/dts/k3-j7200-main.dtsi @@ -647,6 +647,7 @@ ti,otap-del-sel-hs400 = <0x5>; ti,itap-del-sel-legacy = <0x10>; ti,itap-del-sel-mmc-hs = <0xa>; + ti,itap-del-sel-ddr52 = <0x3>; ti,strobe-sel = <0x77>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; -- 2.40.1
Re: [PATCH 2/2] arm: mach-k3: j721s2: clk-data.c: Add main_uart5 clock data
On 12/05/23 23:12, Bryan Brattlof wrote:
> Hi Bhavya!
>
> On May 11, 2023 thus sayeth Bhavya Kapoor:
>> Add main_uart5 clocks in clk-data.c for J721S2. Now,
>> main_uart5 clocks will be set up while booting the J721S2 SoC.
>>
>> Signed-off-by: Bhavya Kapoor
>> ---
>> arch/arm/mach-k3/j721s2/clk-data.c | 7 +--
>> 1 file changed, 5 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-k3/j721s2/clk-data.c
>> b/arch/arm/mach-k3/j721s2/clk-data.c
>> index ad6bd991b7..0c5c321c1e 100644
>> --- a/arch/arm/mach-k3/j721s2/clk-data.c
>> +++ b/arch/arm/mach-k3/j721s2/clk-data.c
>> @@ -247,6 +247,7 @@ static const struct clk_data clk_list[] = {
>> CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2,
>> 0x1080b4, 16, 1, 0),
>> CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2,
>> 0x40f08010, 0, 1, 0),
>> CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0",
>> "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 4800),
>> +CLK_DIV("usart_programmable_clock_divider_out5",
>> "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
> Is this being used as an alternate console? idk if it would be
> appropriate to use CLK_DIV_DEFFREQ macro here to setup the uart's
> divider here.
>
> ~Bryan
Hi Bryan, yes we will be using this as alternative console.
And CLK-DIV macro is appropriate here and tested and working fine as well
~B-Kapoor
[PATCH 1/2] arm: mach-k3: j7200: dev-data.c: Add main_uart1 device data
Add device data for main_uart1 in dev-data.c for J7200. Now,
main_uart1 will be powered on while booting the J7200 SoC.
Signed-off-by: Bhavya Kapoor
---
arch/arm/mach-k3/j7200/dev-data.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/j7200/dev-data.c
b/arch/arm/mach-k3/j7200/dev-data.c
index d3194ae51a..c1a4dab694 100644
--- a/arch/arm/mach-k3/j7200/dev-data.c
+++ b/arch/arm/mach-k3/j7200/dev-data.c
@@ -53,6 +53,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(92, _lpsc_list[5]),
PSC_DEV(91, _lpsc_list[6]),
PSC_DEV(146, _lpsc_list[7]),
+ PSC_DEV(278, _lpsc_list[7]),
PSC_DEV(4, _lpsc_list[8]),
PSC_DEV(4, _lpsc_list[9]),
PSC_DEV(202, _lpsc_list[10]),
@@ -77,5 +78,5 @@ const struct ti_k3_pd_platdata j7200_pd_platdata = {
.num_psc = 2,
.num_pd = 6,
.num_lpsc = 17,
- .num_devs = 22,
+ .num_devs = 23,
};
--
2.34.1
[PATCH 2/2] arm: mach-k3: j7200: clk-data.c: Add main_uart1 clock data
Add main_uart1 clocks in clk-data.c for J7200. Now,
main_uart1 clocks will be set up while booting the J7200 SoC.
Signed-off-by: Bhavya Kapoor
---
arch/arm/mach-k3/j7200/clk-data.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/j7200/clk-data.c
b/arch/arm/mach-k3/j7200/clk-data.c
index 0437e30abb..9b45786a2d 100644
--- a/arch/arm/mach-k3/j7200/clk-data.c
+++ b/arch/arm/mach-k3/j7200/clk-data.c
@@ -379,6 +379,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2,
0x43008090, 4, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2,
0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0",
"hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 4800),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1",
"hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 4800),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk",
"pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk",
"pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk",
"pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
@@ -534,6 +535,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"),
+ DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"),
DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -546,7 +549,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
const struct ti_k3_clk_platdata j7200_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 108,
+ .clk_list_cnt = 109,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 127,
+ .soc_dev_clk_data_cnt = 129,
};
--
2.34.1
[PATCH 0/2] arm: mach-k3: j7200: Add main_uart1 device and clock data
Add device data and clock data for main_uart1 for J7200 SoC so that main_uart1 will be powered on and its clock will be set up while booting the J7200 SoC. Bhavya Kapoor (2): arm: mach-k3: j7200: dev-data.c: Add main_uart1 device data arm: mach-k3: j7200: clk-data.c: Add main_uart1 clock data arch/arm/mach-k3/j7200/clk-data.c | 7 +-- arch/arm/mach-k3/j7200/dev-data.c | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.34.1
[PATCH 2/2] arm: mach-k3: j721s2: clk-data.c: Add main_uart5 clock data
Add main_uart5 clocks in clk-data.c for J721S2. Now,
main_uart5 clocks will be set up while booting the J721S2 SoC.
Signed-off-by: Bhavya Kapoor
---
arch/arm/mach-k3/j721s2/clk-data.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/j721s2/clk-data.c
b/arch/arm/mach-k3/j721s2/clk-data.c
index ad6bd991b7..0c5c321c1e 100644
--- a/arch/arm/mach-k3/j721s2/clk-data.c
+++ b/arch/arm/mach-k3/j721s2/clk-data.c
@@ -247,6 +247,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2,
0x1080b4, 16, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2,
0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0",
"hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 4800),
+ CLK_DIV("usart_programmable_clock_divider_out5",
"hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0),
CLK_DIV("usart_programmable_clock_divider_out8",
"hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk",
"pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk",
"pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0),
@@ -383,6 +384,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"),
DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"),
+ DEV_CLK(354, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+ DEV_CLK(354, 3, "usart_programmable_clock_divider_out5"),
DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"),
DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -397,7 +400,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
const struct ti_k3_clk_platdata j721s2_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 104,
+ .clk_list_cnt = 105,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 122,
+ .soc_dev_clk_data_cnt = 124,
};
--
2.34.1
[PATCH 1/2] arm: mach-k3: j721s2: dev-data.c: Add main_uart5 device data
Add device data for main_uart5 in dev-data.c for J721S2. Now,
main_uart5 will be powered on while booting the J721S2 SoC.
Signed-off-by: Bhavya Kapoor
---
arch/arm/mach-k3/j721s2/dev-data.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/j721s2/dev-data.c
b/arch/arm/mach-k3/j721s2/dev-data.c
index e36f1edb78..35e8b17eb1 100644
--- a/arch/arm/mach-k3/j721s2/dev-data.c
+++ b/arch/arm/mach-k3/j721s2/dev-data.c
@@ -67,6 +67,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(99, _lpsc_list[12]),
PSC_DEV(98, _lpsc_list[13]),
PSC_DEV(146, _lpsc_list[14]),
+ PSC_DEV(354, _lpsc_list[15]),
PSC_DEV(357, _lpsc_list[15]),
PSC_DEV(4, _lpsc_list[16]),
PSC_DEV(202, _lpsc_list[17]),
@@ -81,5 +82,5 @@ const struct ti_k3_pd_platdata j721s2_pd_platdata = {
.num_psc = 2,
.num_pd = 6,
.num_lpsc = 19,
- .num_devs = 24,
+ .num_devs = 25,
};
--
2.34.1
[PATCH 0/2] arm: mach-k3: j721s2: Add main_uart5 device and clock data
Add device data and clock data for main_uart5 for J721S2 SoC so that main_uart5 will be powered on and its clock will be set up while booting the J721S2 SoC. Bhavya Kapoor (2): arm: mach-k3: j721s2: dev-data.c: Add main_uart5 device data arm: mach-k3: j721s2: clk-data.c: Add main_uart5 clock data arch/arm/mach-k3/j721s2/clk-data.c | 7 +-- arch/arm/mach-k3/j721s2/dev-data.c | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.34.1
[PATCH 2/2] arm: mach-k3: j721e: clk-data.c: Add main_uart2 clock data
Add main_uart2 clocks in clk-data.c for J721E. Now,
main_uart2 clocks will be set up while booting the J721E SoC.
Signed-off-by: Bhavya Kapoor
---
arch/arm/mach-k3/j721e/clk-data.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-k3/j721e/clk-data.c
b/arch/arm/mach-k3/j721e/clk-data.c
index 5ab795139e..e4511092c8 100644
--- a/arch/arm/mach-k3/j721e/clk-data.c
+++ b/arch/arm/mach-k3/j721e/clk-data.c
@@ -553,6 +553,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2,
0x43008090, 4, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2,
0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0",
"hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 4800),
+ CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out2",
"hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0, 4800),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk",
"pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk",
"pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk",
"pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
@@ -760,6 +761,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(279, 0, "usart_programmable_clock_divider_out2"),
+ DEV_CLK(279, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -780,7 +783,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
const struct ti_k3_clk_platdata j721e_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 156,
+ .clk_list_cnt = 157,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 171,
+ .soc_dev_clk_data_cnt = 173,
};
--
2.34.1
[PATCH 0/2] arm: mach-k3: j721e: Add main_uart2 device and clock data
Add device data and clock data for main_uart2 for J721E SoC so that main_uart2 will be powered on and its clock will be set up while booting the J721E SoC. Bhavya Kapoor (2): arm: mach-k3: j721e: dev-data.c: Add main_uart2 device data arm: mach-k3: j721e: clk-data.c: Add main_uart2 clock data arch/arm/mach-k3/j721e/clk-data.c | 7 +-- arch/arm/mach-k3/j721e/dev-data.c | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) -- 2.34.1
[PATCH 1/2] arm: mach-k3: j721e: dev-data.c: Add main_uart2 device data
Add device data for main_uart2 in dev-data.c for J721E. Now,
main_uart2 will be powered on while booting the J721E SoC.
Signed-off-by: Bhavya Kapoor
---
arch/arm/mach-k3/j721e/dev-data.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-k3/j721e/dev-data.c
b/arch/arm/mach-k3/j721e/dev-data.c
index 300d998c62..f0afa3552b 100644
--- a/arch/arm/mach-k3/j721e/dev-data.c
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -46,6 +46,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(30, _lpsc_list[0]),
PSC_DEV(61, _lpsc_list[0]),
PSC_DEV(146, _lpsc_list[1]),
+ PSC_DEV(279, _lpsc_list[1]),
PSC_DEV(90, _lpsc_list[2]),
PSC_DEV(47, _lpsc_list[3]),
PSC_DEV(288, _lpsc_list[4]),
@@ -75,5 +76,5 @@ const struct ti_k3_pd_platdata j721e_pd_platdata = {
.num_psc = 2,
.num_pd = 5,
.num_lpsc = 16,
- .num_devs = 22,
+ .num_devs = 23,
};
--
2.34.1
Re: [PATCH] arm: mach-k3: j721e: Add platform data for main_uart2
Hi Bryan, sure i can wait for that. Can i get the information when that gets merged. On 22/12/22 00:06, Bryan Brattlof wrote: Hi Bhavya! On December 19, 2022 thus sayeth Bhavya Kapoor: Add platform clock and powerdomain data for main_uart2 in J721e. This data is used by the driver to register main_uart2 device clocks and powerdomains for J721e. Signed-off-by: Bhavya Kapoor --- arch/arm/mach-k3/j721e/clk-data.c | 7 +-- arch/arm/mach-k3/j721e/dev-data.c | 3 ++- 2 files changed, 7 insertions(+), 3 deletions(-) I know there are a lot of changes coming up for the clock tree on all of our j7* devices. Would you be comfortable if we held off on this until we can get all the other changes lined up? ~Bryan
[PATCH] arm: mach-k3: j721e: Add platform data for main_uart2
Add platform clock and powerdomain data for main_uart2 in J721e. This
data is used by the driver to register main_uart2 device clocks and
powerdomains for J721e.
Signed-off-by: Bhavya Kapoor
---
arch/arm/mach-k3/j721e/clk-data.c | 7 +--
arch/arm/mach-k3/j721e/dev-data.c | 3 ++-
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-k3/j721e/clk-data.c
b/arch/arm/mach-k3/j721e/clk-data.c
index 5ab795139e..2b262bfbc3 100644
--- a/arch/arm/mach-k3/j721e/clk-data.c
+++ b/arch/arm/mach-k3/j721e/clk-data.c
@@ -553,6 +553,7 @@ static const struct clk_data clk_list[] = {
CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2,
0x43008090, 4, 1, 0),
CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2,
0x40f08010, 0, 1, 0),
CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0",
"hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 4800),
+ CLK_DIV("usart_programmable_clock_divider_out2",
"hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0),
CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk",
"pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk",
"pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0),
CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk",
"pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0),
@@ -760,6 +761,8 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(279, 0, "usart_programmable_clock_divider_out2"),
+ DEV_CLK(279, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"),
DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -780,7 +783,7 @@ static const struct dev_clk soc_dev_clk_data[] = {
const struct ti_k3_clk_platdata j721e_clk_platdata = {
.clk_list = clk_list,
- .clk_list_cnt = 156,
+ .clk_list_cnt = 157,
.soc_dev_clk_data = soc_dev_clk_data,
- .soc_dev_clk_data_cnt = 171,
+ .soc_dev_clk_data_cnt = 173,
};
diff --git a/arch/arm/mach-k3/j721e/dev-data.c
b/arch/arm/mach-k3/j721e/dev-data.c
index 300d998c62..f0afa3552b 100644
--- a/arch/arm/mach-k3/j721e/dev-data.c
+++ b/arch/arm/mach-k3/j721e/dev-data.c
@@ -46,6 +46,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(30, _lpsc_list[0]),
PSC_DEV(61, _lpsc_list[0]),
PSC_DEV(146, _lpsc_list[1]),
+ PSC_DEV(279, _lpsc_list[1]),
PSC_DEV(90, _lpsc_list[2]),
PSC_DEV(47, _lpsc_list[3]),
PSC_DEV(288, _lpsc_list[4]),
@@ -75,5 +76,5 @@ const struct ti_k3_pd_platdata j721e_pd_platdata = {
.num_psc = 2,
.num_pd = 5,
.num_lpsc = 16,
- .num_devs = 22,
+ .num_devs = 23,
};
--
2.37.2
