RE: [PATCH 06/13] clk: exynos: Move pll code into clk-exynos7420

[Chanho Park]

> -Original Message-
> From: U-Boot  On Behalf Of Sam Protsenko
> Sent: Wednesday, December 13, 2023 12:17 PM
> To: Minkyu Kang ; Tom Rini ;
> Lukasz Majewski ; Sean Anderson 
> Cc: Simon Glass ; Heinrich Schuchardt
> ; u-boot@lists.denx.de
> Subject: [PATCH 06/13] clk: exynos: Move pll code into clk-exynos7420
> 
> PLL utilities code is only used by clk-exynos7420 driver at the moment.
> Move it into clk-exynos7420 to make clk-pll.c file available for CCF PLL
> clocks implementation, which is coming in the next patches.
> 
> Signed-off-by: Sam Protsenko 

Reviewed-by: Chanho Park 

RE: [PATCH 04/13] soc: samsung: Add Exynos USI driver

[Chanho Park]

> -Original Message-
> From: U-Boot  On Behalf Of Sam Protsenko
> Sent: Wednesday, December 13, 2023 12:17 PM
> To: Minkyu Kang ; Tom Rini ;
> Lukasz Majewski ; Sean Anderson 
> Cc: Simon Glass ; Heinrich Schuchardt
> ; u-boot@lists.denx.de
> Subject: [PATCH 04/13] soc: samsung: Add Exynos USI driver
> 
> USIv2 IP-core is found on modern ARM64 Exynos SoCs (like Exynos850) and
> provides selectable serial protocol (one of: UART, SPI, I2C). USIv2
> registers usually reside in the same register map as a particular
> underlying protocol it implements, but have some particular offset. E.g.
> on Exynos850 the USI_UART has 0x1382 base address, where UART
> registers have 0x00..0x40 offsets, and USI registers have 0xc0..0xdc
> offsets. Desired protocol can be chosen via SW_CONF register from System
> Register block of the same domain as USI.
> 
> Before starting to use a particular protocol, USIv2 must be configured
> properly:
>   1. Select protocol to be used via System Register
>   2. Clear "reset" flag in USI_CON
>   3. Configure HWACG behavior (e.g. for UART Rx the HWACG must be
>  disabled, so that the IP clock is not gated automatically); this is
>  done using USI_OPTION register
>   4. Keep both USI clocks (PCLK and IPCLK) running during USI registers
>  modification
> 
> This driver implements the above behavior. Of course, USIv2 driver
> should be probed before UART/I2C/SPI drivers. It can be achieved by
> embedding UART/I2C/SPI nodes inside of the USI node (in Device Tree);
> driver then walks underlying nodes and instantiates those. Driver also
> handles USI configuration on PM resume, as register contents can be lost
> during CPU suspend.
> 
> This driver is designed with different USI versions in mind. So it
> should be relatively easy to add new USI revisions to it later.
> 
> Driver's code was copied over from Linux kernel [1] and adapted
> correspondingly for U-Boot API. UCLASS_MISC is used, and although no
> misc operations are implemented, it makes it easier to probe the driver
> this way (as compared to UCLASS_NOP) and keep the code compact.
> 
> [1] drivers/soc/samsung/exynos-usi.c
> 
> Signed-off-by: Sam Protsenko 

Reviewed-by: Chanho Park 

RE: [PATCH 05/13] soc: samsung: Add Exynos PMU driver

[Chanho Park]

> -Original Message-
> From: U-Boot  On Behalf Of Sam Protsenko
> Sent: Wednesday, December 13, 2023 12:17 PM
> To: Minkyu Kang ; Tom Rini ;
> Lukasz Majewski ; Sean Anderson 
> Cc: Simon Glass ; Heinrich Schuchardt
> ; u-boot@lists.denx.de
> Subject: [PATCH 05/13] soc: samsung: Add Exynos PMU driver
> 
> Add basic Power Management Unit (PMU) driver for Exynos SoCs. For now
> it's only capable of changing UART path in PMU, which is needed for
> E850-96 board. The driver's structure resembles the exynos-pmu driver
> from Linux kernel, and although it's very basic and slim at the moment,
> it can be easily extended in future if the need arises.
> 
> UCLASS_NOP is used, as there are no benefits in using more elaborate
> classes like UCLASS_MISC in this case. The DM_FLAG_PROBE_AFTER_BIND flag
> is added in bind function, as the probe function must be always called
> for this driver.
> 
> Signed-off-by: Sam Protsenko 

Reviewed-by: Chanho Park 

RE: [PATCH 07/13] clk: exynos: Add Samsung clock framework

[Chanho Park]

pll->con_reg);
> + pll_con5 = readl_relaxed(pll->con_reg + 8);
> + mdiv = (pll_con3 >> PLL0831X_MDIV_SHIFT) & PLL0831X_MDIV_MASK;
> + pdiv = (pll_con3 >> PLL0831X_PDIV_SHIFT) & PLL0831X_PDIV_MASK;
> + sdiv = (pll_con3 >> PLL0831X_SDIV_SHIFT) & PLL0831X_SDIV_MASK;
> + kdiv = (s16)((pll_con5 >> PLL0831X_KDIV_SHIFT) &
> PLL0831X_KDIV_MASK);
> +
> + fvco *= (mdiv << 16) + kdiv;
> + do_div(fvco, (pdiv << sdiv));
> + fvco >>= 16;
> +
> + return (unsigned long)fvco;
> +}
> +
> +static const struct clk_ops samsung_pll0831x_clk_min_ops = {
> + .get_rate = samsung_pll0831x_recalc_rate,
> +};
> +
> +static struct clk *_samsung_clk_register_pll(void __iomem *base,
> + const struct samsung_pll_clock
*pll_clk)
> +{
> + struct samsung_clk_pll *pll;
> + struct clk *clk;
> + const char *drv_name;
> + int ret;
> +
> + pll = kzalloc(sizeof(*pll), GFP_KERNEL);
> + if (!pll)
> + return ERR_PTR(-ENOMEM);
> +
> + pll->con_reg = base + pll_clk->con_offset;
> + pll->type = pll_clk->type;
> + clk = &pll->clk;
> + clk->flags = pll_clk->flags;
> +
> + switch (pll_clk->type) {
> + case pll_0822x:
> + drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0822X;
> + break;
> + case pll_0831x:
> + drv_name = UBOOT_DM_CLK_SAMSUNG_PLL0831X;
> + break;
> + default:
> + kfree(pll);
> + return ERR_PTR(-ENODEV);
> + }
> +
> + ret = clk_register(clk, drv_name, pll_clk->name, pll_clk-
> >parent_name);
> + if (ret) {
> + kfree(pll);
> + return ERR_PTR(ret);
> + }
> +
> + return clk;
> +}
> +
> +void samsung_clk_register_pll(void __iomem *base,
> +   const struct samsung_pll_clock *clk_list,
> +   unsigned int nr_clk)
> +{
> + unsigned int cnt;
> +
> + for (cnt = 0; cnt < nr_clk; cnt++) {
> + struct clk *clk;
> + const struct samsung_pll_clock *pll_clk;
> +
> + pll_clk = &clk_list[cnt];
> + clk = _samsung_clk_register_pll(base, pll_clk);
> + clk_dm(pll_clk->id, clk);
> + }
> +}
> +
> +U_BOOT_DRIVER(samsung_pll0822x_clk) = {
> + .name   = UBOOT_DM_CLK_SAMSUNG_PLL0822X,
> + .id = UCLASS_CLK,
> + .ops= &samsung_pll0822x_clk_min_ops,
> + .flags  = DM_FLAG_PRE_RELOC,
> +};
> +
> +U_BOOT_DRIVER(samsung_pll0831x_clk) = {
> + .name   = UBOOT_DM_CLK_SAMSUNG_PLL0831X,
> + .id = UCLASS_CLK,
> + .ops= &samsung_pll0831x_clk_min_ops,
> + .flags  = DM_FLAG_PRE_RELOC,
> +};
> diff --git a/drivers/clk/exynos/clk-pll.h b/drivers/clk/exynos/clk-pll.h
> new file mode 100644
> index ..3b477369aeb8
> --- /dev/null
> +++ b/drivers/clk/exynos/clk-pll.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2016 Samsung Electronics
> + * Copyright (C) 2023 Linaro Ltd.
> + *
> + * Authors:
> + *   Thomas Abraham 

Ditto.

Othewise,
Reviewed-by: Chanho Park 

RE: [PATCH 08/13] clk: exynos: Add Exynos850 clock driver

[Chanho Park]

> -Original Message-
> From: U-Boot  On Behalf Of Sam Protsenko
> Sent: Wednesday, December 13, 2023 12:17 PM
> To: Minkyu Kang ; Tom Rini ;
> Lukasz Majewski ; Sean Anderson 
> Cc: Simon Glass ; Heinrich Schuchardt
> ; u-boot@lists.denx.de
> Subject: [PATCH 08/13] clk: exynos: Add Exynos850 clock driver
> 
> Heavily influenced by its Linux kernel counterpart. It's implemented on
> top of recently added Samsung CCF clock framework API. For now only UART
> leaf clocks are implemented, along with all preceding clocks in CMU_TOP
> and CMU_PERI. The UART baud clock is required in the serial driver, to
> get its rate for the consequent baud rate calculation.
> 
> Signed-off-by: Sam Protsenko 

Reviewed-by: Chanho Park 

RE: [PATCH 09/13] pinctrl: exynos: Add pinctrl support for Exynos850

[Chanho Park]

> -Original Message-
> From: U-Boot  On Behalf Of Sam Protsenko
> Sent: Wednesday, December 13, 2023 12:17 PM
> To: Minkyu Kang ; Tom Rini ;
> Lukasz Majewski ; Sean Anderson 
> Cc: Simon Glass ; Heinrich Schuchardt
> ; u-boot@lists.denx.de
> Subject: [PATCH 09/13] pinctrl: exynos: Add pinctrl support for Exynos850
> 
> Add pinctrl support for Exynos850 SoC. It was mostly extracted from
> corresponding Linux kernel code [1]. Power down modes and external
> interrupt data were removed while converting the code for U-Boot, but
> everything else was kept almost unchanged.
> 
> [1] drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
> 
> Signed-off-by: Sam Protsenko 
> ---
>  drivers/pinctrl/exynos/Kconfig |   8 ++
>  drivers/pinctrl/exynos/Makefile|   1 +
>  drivers/pinctrl/exynos/pinctrl-exynos850.c | 125 +
>  3 files changed, 134 insertions(+)
>  create mode 100644 drivers/pinctrl/exynos/pinctrl-exynos850.c
> 
> diff --git a/drivers/pinctrl/exynos/Kconfig
> b/drivers/pinctrl/exynos/Kconfig
> index a60f49869b45..1b7fb62bc4ba 100644
> --- a/drivers/pinctrl/exynos/Kconfig
> +++ b/drivers/pinctrl/exynos/Kconfig
> @@ -16,3 +16,11 @@ config PINCTRL_EXYNOS78x0
>   help
> Support pin multiplexing and pin configuration control on
> Samsung's Exynos78x0 SoC.
> +
> +config PINCTRL_EXYNOS850
> + bool "Samsung Exynos850 pinctrl driver"
> + depends on ARCH_EXYNOS && PINCTRL_FULL
> + select PINCTRL_EXYNOS
> + help
> +   Support pin multiplexing and pin configuration control on
> +   Samsung's Exynos850 SoC.
> diff --git a/drivers/pinctrl/exynos/Makefile
> b/drivers/pinctrl/exynos/Makefile
> index 07db970ca942..3abe1226eb74 100644
> --- a/drivers/pinctrl/exynos/Makefile
> +++ b/drivers/pinctrl/exynos/Makefile
> @@ -6,3 +6,4 @@
>  obj-$(CONFIG_PINCTRL_EXYNOS) += pinctrl-exynos.o
>  obj-$(CONFIG_PINCTRL_EXYNOS7420) += pinctrl-exynos7420.o
>  obj-$(CONFIG_PINCTRL_EXYNOS78x0) += pinctrl-exynos78x0.o
> +obj-$(CONFIG_PINCTRL_EXYNOS850)  += pinctrl-exynos850.o
> diff --git a/drivers/pinctrl/exynos/pinctrl-exynos850.c
> b/drivers/pinctrl/exynos/pinctrl-exynos850.c
> new file mode 100644
> index ..2445dd752ea8
> --- /dev/null
> +++ b/drivers/pinctrl/exynos/pinctrl-exynos850.c
> @@ -0,0 +1,125 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2023 Linaro Ltd.
> + * Author: Sam Protsenko 
> + *
> + * Samsung Exynos USI driver (Universal Serial Interface).

Typo. It should be a subject for the pinctrl driver.

Otherwise,
Reviewed-by: Chanho Park 

RE: [PATCH v2 05/21] riscv: Add a reset_cpu() function

[Chanho Park]

> -Original Message-
> From: Simon Glass 
> Sent: Friday, December 15, 2023 1:50 AM
> To: U-Boot Mailing List 
> Cc: Tom Rini ; Simon Glass ; Chanho
> Park ; Heinrich Schuchardt
;
> Leo ; Nikita Shubin ; Rick Chen
> 
> Subject: [PATCH v2 05/21] riscv: Add a reset_cpu() function
> 
> The current do_reset() is called from a command context. Add a function
> which can be used from anywhere, as is done on ARM. Adjust do_reset()
> to call it.
> 
> Note that reset_cpu() is normally provided by SYSRESET so make this
> declaration conditional on that being disabled.
> 
> Signed-off-by: Simon Glass 

Reviewed-by: Chanho Park 
Tested-by: Chanho Park 


> ---
> 
> (no changes since v1)
> 
>  arch/riscv/cpu/cpu.c   | 13 +
>  arch/riscv/lib/reset.c |  7 ++-
>  2 files changed, 15 insertions(+), 5 deletions(-)
> 
> diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
> index ebd39cb41a60..8445c5823e17 100644
> --- a/arch/riscv/cpu/cpu.c
> +++ b/arch/riscv/cpu/cpu.c
> @@ -3,10 +3,13 @@
>   * Copyright (C) 2018, Bin Meng 
>   */
> 
> +#include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -162,3 +165,13 @@ int arch_early_init_r(void)
>  __weak void harts_early_init(void)
>  {
>  }
> +
> +#if !CONFIG_IS_ENABLED(SYSRESET)
> +void reset_cpu(void)
> +{
> + printf("resetting ...\n");
> +
> + printf("reset not supported yet\n");
> + hang();
> +}
> +#endif
> diff --git a/arch/riscv/lib/reset.c b/arch/riscv/lib/reset.c
> index 712e1bdb8e1d..c4153c9e6e02 100644
> --- a/arch/riscv/lib/reset.c
> +++ b/arch/riscv/lib/reset.c
> @@ -4,14 +4,11 @@
>   */
> 
>  #include 
> -#include 
> +#include 
> 
>  int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const
> argv[])
>  {
> - printf("resetting ...\n");
> -
> - printf("reset not supported yet\n");
> - hang();
> + reset_cpu();
> 
>   return 0;
>  }
> --
> 2.43.0.472.g3155946c3a-goog

[PATCH v2] watchdog: Correct watchdog timeout print message

[Chanho Park]

The wdt_start function takes timeout_ms as a parameter and starts the
watchdog with this value. However, when you output the message, it shows
the default timeout value for the watchdog device.
So this patch fixes that part to output the correct timeout value.

Before -->
StarFive # wdt start 3000
WDT:   Started watchdog@1307 without servicing  (60s timeout)

After -->
StarFive # wdt start 3000
WDT:   Started watchdog@1307 without servicing  (3s timeout)

Fixes: c2fd0ca1a822 ("watchdog: Integrate watchdog triggering into the cyclic 
framework")
Signed-off-by: Chanho Park 
---
Change from v1:
- Use lldiv to fix a build error of m68k arch

 drivers/watchdog/wdt-uclass.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index ed329284decb..417e8d7eef95 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -7,6 +7,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -141,7 +142,7 @@ int wdt_start(struct udevice *dev, u64 timeout_ms, ulong 
flags)
 
printf("WDT:   Started %s with%s servicing %s (%ds timeout)\n",
   dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out",
-  str, priv->timeout);
+  str, (u32)lldiv(timeout_ms, 1000));
}
 
return ret;
-- 
2.39.2

RE: [PATCH] watchdog: Correct watchdog timeout print message

[Chanho Park]

> -Original Message-
> From: Stefan Roese 
> Sent: Friday, December 1, 2023 7:39 PM
> To: Chanho Park ; u-boot@lists.denx.de
> Subject: Re: [PATCH] watchdog: Correct watchdog timeout print message
> 
> On 12/1/23 08:37, Stefan Roese wrote:
> > On 11/27/23 02:05, Chanho Park wrote:
> >> The wdt_start function takes timeout_ms as a parameter and starts the
> >> watchdog with this value. However, when you output the message, it
> shows
> >> the default timeout value for the watchdog device.
> >> So this patch fixes that part to output the correct timeout value.
> >>
> >> Before -->
> >> StarFive # wdt start 3000
> >> WDT:   Started watchdog@1307 without servicing  (60s timeout)
> >>
> >> After -->
> >> StarFive # wdt start 3000
> >> WDT:   Started watchdog@1307 without servicing  (3s timeout)
> >>
> >> Fixes: c2fd0ca1a822 ("watchdog: Integrate watchdog triggering into the
> >> cyclic framework")
> >> Signed-off-by: Chanho Park 
> >
> > Reviewed-by: Stefan Roese 
> >
> > Thanks,
> > Stefan
> >
> >> ---
> >>   drivers/watchdog/wdt-uclass.c | 2 +-
> >>   1 file changed, 1 insertion(+), 1 deletion(-)
> >>
> >> diff --git a/drivers/watchdog/wdt-uclass.c
> >> b/drivers/watchdog/wdt-uclass.c
> >> index ed329284decb..65a4bc1f90ed 100644
> >> --- a/drivers/watchdog/wdt-uclass.c
> >> +++ b/drivers/watchdog/wdt-uclass.c
> >> @@ -141,7 +141,7 @@ int wdt_start(struct udevice *dev, u64 timeout_ms,
> >> ulong flags)
> >>   printf("WDT:   Started %s with%s servicing %s (%ds
> timeout)\n",
> >>  dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out",
> >> -   str, priv->timeout);
> >> +   str, (u32)(timeout_ms / 1000));
> 
> Unfortunately this commit break CI build - I tested using Azure CI:
> 
> test.py for QEMU platforms qemu_m68k:
> 
> 
> Successfully installed attrs-23.1.0 jsonschema-4.17.3 pyrsistent-0.20.0
> pyyaml-6.0
> + tools/buildman/buildman -o /tmp/M5208EVBE -w -E -W -e --board
> M5208EVBE -a CONFIG_M68K_QEMU=y -a '~CONFIG_MCFTMR'
> Building current source for 1 boards (1 thread, 2 jobs per thread)
> 
> Starting build...
> 
> 
>  000 /1   -1  (starting)
> 
>m68k:  +   M5208EVBE
> +m68k-linux-ld.bfd: drivers/watchdog/wdt-uclass.o: in function `wdt_start':
> +drivers/watchdog/wdt-uclass.c:144:(.text.wdt_start+0xc6): undefined
> reference to `__udivdi3'
> +make[1]: *** [Makefile:1765: u-boot] Error 1
> +make: *** [Makefile:177: sub-make] Error 2
> 
>  001 /1  M5208EVBE
> Completed: 1 total built, 1 newly), duration 0:00:21, rate 0.05
> ##[error]Bash exited with code '100'.
> ##[warning]RetryHelper encountered task failure, will retry (attempt #:
> 1 out of 2) after 1000 ms
> Generating script.
> 
> Could you please take a look?

Sure. I'll fix it and post the v2 patch.

Best Regards,
Chanho Park

[PATCH] watchdog: Correct watchdog timeout print message

[Chanho Park]

The wdt_start function takes timeout_ms as a parameter and starts the
watchdog with this value. However, when you output the message, it shows
the default timeout value for the watchdog device.
So this patch fixes that part to output the correct timeout value.

Before -->
StarFive # wdt start 3000
WDT:   Started watchdog@1307 without servicing  (60s timeout)

After -->
StarFive # wdt start 3000
WDT:   Started watchdog@1307 without servicing  (3s timeout)

Fixes: c2fd0ca1a822 ("watchdog: Integrate watchdog triggering into the cyclic 
framework")
Signed-off-by: Chanho Park 
---
 drivers/watchdog/wdt-uclass.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
index ed329284decb..65a4bc1f90ed 100644
--- a/drivers/watchdog/wdt-uclass.c
+++ b/drivers/watchdog/wdt-uclass.c
@@ -141,7 +141,7 @@ int wdt_start(struct udevice *dev, u64 timeout_ms, ulong 
flags)
 
printf("WDT:   Started %s with%s servicing %s (%ds timeout)\n",
   dev->name, IS_ENABLED(CONFIG_WATCHDOG) ? "" : "out",
-  str, priv->timeout);
+  str, (u32)(timeout_ms / 1000));
}
 
return ret;
-- 
2.39.2

[PATCH 0/4] Support StarFive Watchdog driver

[Chanho Park]

This patchset adds to support StarFive Watchdog driver which is based on
Linux kernel's starfive-wdt driver. Actually, the original driver supports
both JH7100 and JH7110 with variant coding but this removes the JH7100
part of codes because JH7100 isn't supported in u-boot yet.
However, this patch tries to keep the variant coding style for future
work of JH7100 and have a consistency with the Linux driver.

Chanho Park (4):
  clk: starfive: jh7110: Add watchdog clocks
  watchdog: Add StarFive Watchdog driver
  riscv: dts: jh7110: Add watchdog device tree node
  configs: visionfive2: Enable watchdog driver

 arch/riscv/dts/jh7110.dtsi |  10 +
 configs/starfive_visionfive2_defconfig |   5 +
 drivers/clk/starfive/clk-jh7110.c  |   9 +
 drivers/watchdog/Kconfig   |   7 +
 drivers/watchdog/Makefile  |   1 +
 drivers/watchdog/starfive_wdt.c| 329 +
 6 files changed, 361 insertions(+)
 create mode 100644 drivers/watchdog/starfive_wdt.c

-- 
2.39.2

[PATCH 3/4] riscv: dts: jh7110: Add watchdog device tree node

[Chanho Park]

Adds jh7110 watchdog device tree node.

Signed-off-by: Chanho Park 
---
 arch/riscv/dts/jh7110.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index 13c47f7caa36..6d2675d6ceac 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -533,6 +533,16 @@
#gpio-cells = <2>;
};
 
+   watchdog@1307 {
+   compatible = "starfive,jh7110-wdt";
+   reg = <0x0 0x1307 0x0 0x1>;
+   clocks = <&syscrg JH7110_SYSCLK_WDT_APB>,
+<&syscrg JH7110_SYSCLK_WDT_CORE>;
+   clock-names = "apb", "core";
+   resets = <&syscrg JH7110_SYSRST_WDT_APB>,
+<&syscrg JH7110_SYSRST_WDT_CORE>;
+   };
+
mmc0: mmc@1601 {
compatible = "starfive,jh7110-mmc";
reg = <0x0 0x1601 0x0 0x1>;
-- 
2.39.2

[PATCH 2/4] watchdog: Add StarFive Watchdog driver

[Chanho Park]

Add to support StarFive watchdog driver. The driver is imported from
linux kernel's drivers/watchdog/starfive-wdt.c without jh7100 support
because there is no support of jh7100 SoC in u-boot yet.
Howver, this patch has been kept the variant coding style because JH7100
can be added later and have a consistency with the linux driver.

Signed-off-by: Chanho Park 
---
 drivers/watchdog/Kconfig|   7 +
 drivers/watchdog/Makefile   |   1 +
 drivers/watchdog/starfive_wdt.c | 329 
 3 files changed, 337 insertions(+)
 create mode 100644 drivers/watchdog/starfive_wdt.c

diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 07fc4940e918..569726119ca1 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -344,6 +344,13 @@ config WDT_STM32MP
  Enable the STM32 watchdog (IWDG) driver. Enable support to
  configure STM32's on-SoC watchdog.
 
+config WDT_STARFIVE
+   bool "StarFive watchdog timer support"
+   depends on WDT
+   imply WATCHDOG
+   help
+ Enable support for the watchdog timer of StarFive JH7110 SoC.
+
 config WDT_SUNXI
bool "Allwinner sunxi watchdog timer support"
depends on WDT && ARCH_SUNXI
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index eef786f5e74e..5520d3d9ae8a 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_WDT_SBSA) += sbsa_gwdt.o
 obj-$(CONFIG_WDT_K3_RTI) += rti_wdt.o
 obj-$(CONFIG_WDT_SL28CPLD) += sl28cpld-wdt.o
 obj-$(CONFIG_WDT_SP805) += sp805_wdt.o
+obj-$(CONFIG_WDT_STARFIVE) += starfive_wdt.o
 obj-$(CONFIG_WDT_STM32MP) += stm32mp_wdt.o
 obj-$(CONFIG_WDT_SUNXI) += sunxi_wdt.o
 obj-$(CONFIG_WDT_TANGIER) += tangier_wdt.o
diff --git a/drivers/watchdog/starfive_wdt.c b/drivers/watchdog/starfive_wdt.c
new file mode 100644
index ..ee9ec4cdc3a4
--- /dev/null
+++ b/drivers/watchdog/starfive_wdt.c
@@ -0,0 +1,329 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Starfive Watchdog driver
+ *
+ * Copyright (C) 2022 StarFive Technology Co., Ltd.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* JH7110 Watchdog register define */
+#define STARFIVE_WDT_JH7110_LOAD   0x000
+#define STARFIVE_WDT_JH7110_VALUE  0x004
+#define STARFIVE_WDT_JH7110_CONTROL0x008   /*
+* [0]: reset enable;
+* [1]: interrupt enable && 
watchdog enable
+* [31:2]: reserved.
+*/
+#define STARFIVE_WDT_JH7110_INTCLR 0x00c   /* clear intterupt and reload 
the counter */
+#define STARFIVE_WDT_JH7110_IMS0x014
+#define STARFIVE_WDT_JH7110_LOCK   0xc00   /* write 0x1ACCE551 to unlock */
+
+/* WDOGCONTROL */
+#define STARFIVE_WDT_ENABLE0x1
+#define STARFIVE_WDT_EN_SHIFT  0
+#define STARFIVE_WDT_RESET_EN  0x1
+#define STARFIVE_WDT_JH7110_RST_EN_SHIFT   1
+
+/* WDOGLOCK */
+#define STARFIVE_WDT_JH7110_UNLOCK_KEY 0x1acce551
+
+/* WDOGINTCLR */
+#define STARFIVE_WDT_INTCLR0x1
+#define STARFIVE_WDT_JH7100_INTCLR_AVA_SHIFT   1   /* Watchdog can clear 
interrupt when 0 */
+
+#define STARFIVE_WDT_MAXCNT0x
+#define STARFIVE_WDT_DEFAULT_TIME  (15)
+#define STARFIVE_WDT_DELAY_US  0
+#define STARFIVE_WDT_TIMEOUT_US1
+
+/* module parameter */
+#define STARFIVE_WDT_EARLY_ENA 0
+
+struct starfive_wdt_variant {
+   unsigned int control;   /* Watchdog Control Resgister for reset 
enable */
+   unsigned int load;  /* Watchdog Load register */
+   unsigned int reload;/* Watchdog Reload Control register */
+   unsigned int enable;/* Watchdog Enable Register */
+   unsigned int value; /* Watchdog Counter Value Register */
+   unsigned int int_clr;   /* Watchdog Interrupt Clear Register */
+   unsigned int unlock;/* Watchdog Lock Register */
+   unsigned int int_status;/* Watchdog Interrupt Status Register */
+
+   u32 unlock_key;
+   char enrst_shift;
+   char en_shift;
+   bool intclr_check;  /*  whether need to check it before 
clearing interrupt */
+   char intclr_ava_shift;
+   bool double_timeout;/* The watchdog need twice timeout to 
reboot */
+};
+
+struct starfive_wdt_priv {
+   void __iomem *base;
+   struct clk *core_clk;
+   struct clk *apb_clk;
+   struct reset_ctl_bulk *rst;
+   const struct starfive_wdt_variant *variant;
+   unsigned long freq;
+   u32 count;  /* count of timeout */
+   u32 reload; /* restore the count */
+};
+

[PATCH 4/4] configs: visionfive2: Enable watchdog driver

[Chanho Park]

Enables StarFive Watchdog driver and WDT command.

Signed-off-by: Chanho Park 
---
 configs/starfive_visionfive2_defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index b15e7d24db19..7b39a63359dc 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -72,6 +72,7 @@ CONFIG_CMD_MEMINFO=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
+CONFIG_CMD_WDT=y
 CONFIG_CMD_TFTPPUT=y
 CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_BOARD=y
@@ -133,3 +134,7 @@ CONFIG_USB_EHCI_PCI=y
 CONFIG_USB_OHCI_HCD=y
 CONFIG_USB_OHCI_PCI=y
 CONFIG_USB_KEYBOARD=y
+# CONFIG_WATCHDOG is not set
+# CONFIG_WATCHDOG_AUTOSTART is not set
+CONFIG_WDT=y
+CONFIG_WDT_STARFIVE=y
-- 
2.39.2

[PATCH 1/4] clk: starfive: jh7110: Add watchdog clocks

[Chanho Park]

Add JH7110_SYSCLK_WDT_APB and JH7110_SYSCLK_WDT_CORE clocks for JH7110
watchdog device.

Signed-off-by: Chanho Park 
---
 drivers/clk/starfive/clk-jh7110.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/starfive/clk-jh7110.c 
b/drivers/clk/starfive/clk-jh7110.c
index a835541e48e9..a38694809a00 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -434,6 +434,15 @@ static int jh7110_syscrg_init(struct udevice *dev)
   starfive_clk_gate(priv->reg,
 "i2c5_apb", "apb0",
 OFFSET(JH7110_SYSCLK_I2C5_APB)));
+   /* Watchdog clocks */
+   clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_APB),
+  starfive_clk_gate(priv->reg,
+"wdt_apb", "apb0",
+OFFSET(JH7110_SYSCLK_WDT_APB)));
+   clk_dm(JH7110_SYS_ID_TRANS(JH7110_SYSCLK_WDT_CORE),
+  starfive_clk_gate(priv->reg,
+"wdt_core", "oscillator",
+OFFSET(JH7110_SYSCLK_WDT_CORE)));
 
/* enable noc_bus_stg_axi clock */
if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))
-- 
2.39.2

[PATCH v4 1/5] riscv: import read/write_relaxed functions

[Chanho Park]

This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
to use read/write[b|w|l|q]_relaxed functions.

Signed-off-by: Chanho Park 
---
 arch/riscv/include/asm/io.h | 45 +
 1 file changed, 45 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index b16e6dfa3760..4170877a1ae0 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -323,6 +323,51 @@ static inline void writesl(unsigned int *addr, const void 
*data, int longlen)
 #define insw_p(port, to, len)  insw(port, to, len)
 #define insl_p(port, to, len)  insl(port, to, len)
 
+/*
+ * Unordered I/O memory access primitives.  These are even more relaxed than
+ * the relaxed versions, as they don't even order accesses between successive
+ * operations to the I/O regions.
+ */
+#define readb_cpu(c)   ({ u8  __r = __raw_readb(c); __r; })
+#define readw_cpu(c)   ({ u16 __r = le16_to_cpu((__force 
__le16)__raw_readw(c)); __r; })
+#define readl_cpu(c)   ({ u32 __r = le32_to_cpu((__force 
__le32)__raw_readl(c)); __r; })
+
+#define writeb_cpu(v, c)   ((void)__raw_writeb((v), (c)))
+#define writew_cpu(v, c)   ((void)__raw_writew((__force 
u16)cpu_to_le16(v), (c)))
+#define writel_cpu(v, c)   ((void)__raw_writel((__force 
u32)cpu_to_le32(v), (c)))
+
+#ifdef CONFIG_64BIT
+#define readq_cpu(c)   ({ u64 __r = le64_to_cpu((__force 
__le64)__raw_readq(c)); __r; })
+#define writeq_cpu(v, c)   ((void)__raw_writeq((__force 
u64)cpu_to_le64(v), (c)))
+#endif
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.  These are defined to order the indicated access (either a read or
+ * write) with all other I/O memory accesses to the same peripheral. Since the
+ * platform specification defines that all I/O regions are strongly ordered on
+ * channel 0, no explicit fences are required to enforce this ordering.
+ */
+/* FIXME: These are now the same as asm-generic */
+#define __io_rbr() do {} while (0)
+#define __io_rar() do {} while (0)
+#define __io_rbw() do {} while (0)
+#define __io_raw() do {} while (0)
+
+#define readb_relaxed(c)   ({ u8  __v; __io_rbr(); __v = readb_cpu(c); 
__io_rar(); __v; })
+#define readw_relaxed(c)   ({ u16 __v; __io_rbr(); __v = readw_cpu(c); 
__io_rar(); __v; })
+#define readl_relaxed(c)   ({ u32 __v; __io_rbr(); __v = readl_cpu(c); 
__io_rar(); __v; })
+
+#define writeb_relaxed(v, c)   ({ __io_rbw(); writeb_cpu((v), (c)); 
__io_raw(); })
+#define writew_relaxed(v, c)   ({ __io_rbw(); writew_cpu((v), (c)); 
__io_raw(); })
+#define writel_relaxed(v, c)   ({ __io_rbw(); writel_cpu((v), (c)); 
__io_raw(); })
+
+#ifdef CONFIG_64BIT
+#define readq_relaxed(c)   ({ u64 __v; __io_rbr(); __v = readq_cpu(c); 
__io_rar(); __v; })
+#define writeq_relaxed(v, c)   ({ __io_rbw(); writeq_cpu((v), (c)); 
__io_raw(); })
+#endif
+
 #include 
 
 #endif /* __ASM_RISCV_IO_H */
-- 
2.39.2

[PATCH v4 3/5] rng: Add StarFive JH7110 RNG driver

[Chanho Park]

Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.

Signed-off-by: Chanho Park 
---
 drivers/rng/Kconfig  |   6 +
 drivers/rng/Makefile |   1 +
 drivers/rng/jh7110_rng.c | 274 +++
 3 files changed, 281 insertions(+)
 create mode 100644 drivers/rng/jh7110_rng.c

diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 994cc35b2744..0dba1e06b429 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -91,4 +91,10 @@ config TPM_RNG
  functionality. Enable random number generator on TPM
  devices.
 
+config RNG_JH7110
+   bool "StarFive JH7110 Random Number Generator support"
+   depends on DM_RNG && STARFIVE_JH7110
+   help
+ Enable True Random Number Generator in StarFive JH7110 SoCs.
+
 endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 47b323e61ee3..9de762c8a1c3 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
 obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
 obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
 obj-$(CONFIG_TPM_RNG) += tpm_rng.o
+obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
new file mode 100644
index ..eb21afe4e7cb
--- /dev/null
+++ b/drivers/rng/jh7110_rng.c
@@ -0,0 +1,274 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * TRNG driver for the StarFive JH7110 SoC
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* trng register offset */
+#define STARFIVE_CTRL  0x00
+#define STARFIVE_STAT  0x04
+#define STARFIVE_MODE  0x08
+#define STARFIVE_SMODE 0x0C
+#define STARFIVE_IE0x10
+#define STARFIVE_ISTAT 0x14
+#define STARFIVE_RAND0 0x20
+#define STARFIVE_RAND1 0x24
+#define STARFIVE_RAND2 0x28
+#define STARFIVE_RAND3 0x2C
+#define STARFIVE_RAND4 0x30
+#define STARFIVE_RAND5 0x34
+#define STARFIVE_RAND6 0x38
+#define STARFIVE_RAND7 0x3C
+#define STARFIVE_AUTO_RQSTS0x60
+#define STARFIVE_AUTO_AGE  0x64
+
+/* CTRL CMD */
+#define STARFIVE_CTRL_EXEC_NOP 0x0
+#define STARFIVE_CTRL_GENE_RANDNUM 0x1
+#define STARFIVE_CTRL_EXEC_RANDRESEED  0x2
+
+/* STAT */
+#define STARFIVE_STAT_NONCE_MODE   BIT(2)
+#define STARFIVE_STAT_R256 BIT(3)
+#define STARFIVE_STAT_MISSION_MODE BIT(8)
+#define STARFIVE_STAT_SEEDED   BIT(9)
+#define STARFIVE_STAT_LAST_RESEED(x)   ((x) << 16)
+#define STARFIVE_STAT_SRVC_RQSTBIT(27)
+#define STARFIVE_STAT_RAND_GENERATING  BIT(30)
+#define STARFIVE_STAT_RAND_SEEDING BIT(31)
+#define STARFIVE_STAT_RUNNING  (STARFIVE_STAT_RAND_GENERATING | \
+STARFIVE_STAT_RAND_SEEDING)
+
+/* MODE */
+#define STARFIVE_MODE_R256 BIT(3)
+
+/* SMODE */
+#define STARFIVE_SMODE_NONCE_MODE  BIT(2)
+#define STARFIVE_SMODE_MISSION_MODEBIT(8)
+#define STARFIVE_SMODE_MAX_REJECTS(x)  ((x) << 16)
+
+/* IE */
+#define STARFIVE_IE_RAND_RDY_ENBIT(0)
+#define STARFIVE_IE_SEED_DONE_EN   BIT(1)
+#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
+#define STARFIVE_IE_GLBL_ENBIT(31)
+
+#define STARFIVE_IE_ALL(STARFIVE_IE_GLBL_EN | \
+STARFIVE_IE_RAND_RDY_EN | \
+STARFIVE_IE_SEED_DONE_EN | \
+STARFIVE_IE_LFSR_LOCKUP_EN)
+
+/* ISTAT */
+#define STARFIVE_ISTAT_RAND_RDYBIT(0)
+#define STARFIVE_ISTAT_SEED_DONE   BIT(1)
+#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
+
+#define STARFIVE_RAND_LEN  sizeof(u32)
+
+enum mode {
+   PRNG_128BIT,
+   PRNG_256BIT,
+};
+
+struct starfive_trng_plat {
+   void *base;
+   struct clk *hclk;
+   struct clk *ahb;
+   struct reset_ctl *rst;
+   u32 mode;
+};
+
+static inline int starfive_trng_wait_idle(struct starfive_trng_plat *trng)
+{
+   u32 stat;
+
+   return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
+ !(stat & STARFIVE_STAT_RUNNING),
+ 10);
+}
+
+static inline void starfive_trng_irq_mask_clear(struct starfive_trng_plat 
*trng)
+{
+   /* clear register: ISTAT */
+   u32 data = readl(trng->base + STARFIVE_ISTAT);
+
+   writel(data, trng->base + STARFIVE_ISTAT);
+}
+
+static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd)
+{
+   u32 stat, flg;
+   int ret;
+
+   switch

[PATCH v4 5/5] configs: visionfive2: Enable JH7110 RNG driver

[Chanho Park]

Enables JH7110 RNG driver to visionfive2 board.

Signed-off-by: Chanho Park 
Reviewed-by: Heinrich Schuchardt 
---
 configs/starfive_visionfive2_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index b21754feafce..b15e7d24db19 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -120,6 +120,8 @@ CONFIG_SPL_PINCTRL_STARFIVE=y
 CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
 CONFIG_PINCTRL_STARFIVE=y
 # CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RNG=y
+CONFIG_RNG_JH7110=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
-- 
2.39.2

[PATCH v4 2/5] clk: starfive: jh7110: Add security clocks

[Chanho Park]

Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.

Signed-off-by: Chanho Park 
---
 drivers/clk/starfive/clk-jh7110.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/starfive/clk-jh7110.c 
b/drivers/clk/starfive/clk-jh7110.c
index 31aaf3340f94..a835541e48e9 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -539,6 +539,16 @@ static int jh7110_stgcrg_init(struct udevice *dev)
 "pcie1_tl", "stg_axiahb",
 OFFSET(JH7110_STGCLK_PCIE1_TL)));
 
+   /* Security clocks */
+   clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+  starfive_clk_gate(priv->reg,
+"sec_ahb", "stg_axiahb",
+OFFSET(JH7110_STGCLK_SEC_HCLK)));
+   clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+  starfive_clk_gate(priv->reg,
+"sec_misc_ahb", "stg_axiahb",
+OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+
return 0;
 }
 
-- 
2.39.2

[PATCH v4 4/5] riscv: dts: jh7110: Add rng device tree node

[Chanho Park]

Adds jh7110 trng device tree node.

Signed-off-by: Chanho Park 
---
 arch/riscv/dts/jh7110.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index ec237a46ffba..13c47f7caa36 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -627,6 +627,16 @@
status = "disabled";
};
 
+   rng: rng@1600c000 {
+   compatible = "starfive,jh7110-trng";
+   reg = <0x0 0x1600C000 0x0 0x4000>;
+   clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+<&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+   clock-names = "hclk", "ahb";
+   resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+   interrupts = <30>;
+   };
+
aoncrg: clock-controller@1700 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x1700 0x0 0x1>;
-- 
2.39.2

[PATCH v4 0/5] Add support for StarFive JH7110 TRNG driver

[Chanho Park]

This patchset adds to support StarFive JH7110 TRNG driver. Due to lack
of readl_relaxed API, the first patch tries to import the
APIs(read/write_relaxed) from Linux kernel's implementation. The second
patch adds the missing security clocks which are required by the trng
IP.

This IP can support 128-bit and 256-bit random number generation but
this patch makes 256-bit default mode for convenience.

Change from v3:
- Patch #3: Make one call to generate random number according to 128 or
256 bits of entropy which is suggested by Heinrich.

Changes from v2:
- Patch #3: Add error handling codes of probe() which are suggested by Jaehoon

Changes from v1:
- Patch #3: Apply Heinrich's reviews and his codes
- Patch #5: Add Heinrich's R-b tag

Chanho Park (5):
  riscv: import read/write_relaxed functions
  clk: starfive: jh7110: Add security clocks
  rng: Add StarFive JH7110 RNG driver
  riscv: dts: jh7110: Add rng device tree node
  configs: visionfive2: Enable JH7110 RNG driver

 arch/riscv/dts/jh7110.dtsi |  10 +
 arch/riscv/include/asm/io.h|  45 
 configs/starfive_visionfive2_defconfig |   2 +
 drivers/clk/starfive/clk-jh7110.c  |  10 +
 drivers/rng/Kconfig|   6 +
 drivers/rng/Makefile   |   1 +
 drivers/rng/jh7110_rng.c   | 274 +
 7 files changed, 348 insertions(+)
 create mode 100644 drivers/rng/jh7110_rng.c

-- 
2.39.2

RE: [PATCH v3 3/5] rng: Add StarFive JH7110 RNG driver

[Chanho Park]

Hi,

> -Original Message-
> From: Heinrich Schuchardt 
> Sent: Wednesday, November 1, 2023 9:00 PM
> To: Chanho Park 
> Cc: Sughosh Ganu ; u-boot@lists.denx.de; Rick
> Chen ; Leo ; Jaehoon Chung
> 
> Subject: Re: [PATCH v3 3/5] rng: Add StarFive JH7110 RNG driver
> 
> On 11/1/23 13:40, Chanho Park wrote:
> > Adds to support JH7110 TRNG driver which is based on linux kernel's
> > jh7110-trng.c. This can support to generate 256-bit random numbers and
> > 128-bit but this makes 256-bit default for convenience.
> >
> > Signed-off-by: Chanho Park 
> > ---
> >   drivers/rng/Kconfig  |   6 +
> >   drivers/rng/Makefile |   1 +
> >   drivers/rng/jh7110_rng.c | 271 +++
> >   3 files changed, 278 insertions(+)
> >   create mode 100644 drivers/rng/jh7110_rng.c
> >
> > diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
> > index 994cc35b2744..0dba1e06b429 100644
> > --- a/drivers/rng/Kconfig
> > +++ b/drivers/rng/Kconfig
> > @@ -91,4 +91,10 @@ config TPM_RNG
> >   functionality. Enable random number generator on TPM
> >   devices.
> >
> > +config RNG_JH7110
> > +   bool "StarFive JH7110 Random Number Generator support"
> > +   depends on DM_RNG && STARFIVE_JH7110
> > +   help
> > + Enable True Random Number Generator in StarFive JH7110 SoCs.
> > +
> >   endif
> > diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
> > index 47b323e61ee3..9de762c8a1c3 100644
> > --- a/drivers/rng/Makefile
> > +++ b/drivers/rng/Makefile
> > @@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
> >   obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
> >   obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
> >   obj-$(CONFIG_TPM_RNG) += tpm_rng.o
> > +obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
> > diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
> > new file mode 100644
> > index ..075a2d78eb2c
> > --- /dev/null
> > +++ b/drivers/rng/jh7110_rng.c
> > @@ -0,0 +1,271 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * TRNG driver for the StarFive JH7110 SoC
> > + *
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* trng register offset */
> > +#define STARFIVE_CTRL  0x00
> > +#define STARFIVE_STAT  0x04
> > +#define STARFIVE_MODE  0x08
> > +#define STARFIVE_SMODE 0x0C
> > +#define STARFIVE_IE0x10
> > +#define STARFIVE_ISTAT 0x14
> > +#define STARFIVE_RAND0 0x20
> > +#define STARFIVE_RAND1 0x24
> > +#define STARFIVE_RAND2 0x28
> > +#define STARFIVE_RAND3 0x2C
> > +#define STARFIVE_RAND4 0x30
> > +#define STARFIVE_RAND5 0x34
> > +#define STARFIVE_RAND6 0x38
> > +#define STARFIVE_RAND7 0x3C
> > +#define STARFIVE_AUTO_RQSTS0x60
> > +#define STARFIVE_AUTO_AGE  0x64
> > +
> > +/* CTRL CMD */
> > +#define STARFIVE_CTRL_EXEC_NOP 0x0
> > +#define STARFIVE_CTRL_GENE_RANDNUM 0x1
> > +#define STARFIVE_CTRL_EXEC_RANDRESEED  0x2
> > +
> > +/* STAT */
> > +#define STARFIVE_STAT_NONCE_MODE   BIT(2)
> > +#define STARFIVE_STAT_R256 BIT(3)
> > +#define STARFIVE_STAT_MISSION_MODE BIT(8)
> > +#define STARFIVE_STAT_SEEDED   BIT(9)
> > +#define STARFIVE_STAT_LAST_RESEED(x)   ((x) << 16)
> > +#define STARFIVE_STAT_SRVC_RQSTBIT(27)
> > +#define STARFIVE_STAT_RAND_GENERATING  BIT(30)
> > +#define STARFIVE_STAT_RAND_SEEDING BIT(31)
> > +#define STARFIVE_STAT_RUNNING  (STARFIVE_STAT_RAND_GENERATING 
> > | \
> > +STARFIVE_STAT_RAND_SEEDING)
> > +
> > +/* MODE */
> > +#define STARFIVE_MODE_R256 BIT(3)
> > +
> > +/* SMODE */
> > +#define STARFIVE_SMODE_NONCE_MODE  BIT(2)
> > +#define STARFIVE_SMODE_MISSION_MODEBIT(8)
> > +#define STARFIVE_SMODE_MAX_REJECTS(x)  ((x) << 16)
> > +
> > +/* IE */
> > +#define STARFIVE_IE_RAND_RDY_ENBIT(0)
> > +#define STARFIVE_IE_SEED_DONE_EN   BIT(1)
> > +#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
> > +#define STARFIVE_IE_GLBL_ENBIT(31)
>

[PATCH v3 3/5] rng: Add StarFive JH7110 RNG driver

[Chanho Park]

Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.

Signed-off-by: Chanho Park 
---
 drivers/rng/Kconfig  |   6 +
 drivers/rng/Makefile |   1 +
 drivers/rng/jh7110_rng.c | 271 +++
 3 files changed, 278 insertions(+)
 create mode 100644 drivers/rng/jh7110_rng.c

diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 994cc35b2744..0dba1e06b429 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -91,4 +91,10 @@ config TPM_RNG
  functionality. Enable random number generator on TPM
  devices.
 
+config RNG_JH7110
+   bool "StarFive JH7110 Random Number Generator support"
+   depends on DM_RNG && STARFIVE_JH7110
+   help
+ Enable True Random Number Generator in StarFive JH7110 SoCs.
+
 endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 47b323e61ee3..9de762c8a1c3 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
 obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
 obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
 obj-$(CONFIG_TPM_RNG) += tpm_rng.o
+obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
new file mode 100644
index ..075a2d78eb2c
--- /dev/null
+++ b/drivers/rng/jh7110_rng.c
@@ -0,0 +1,271 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * TRNG driver for the StarFive JH7110 SoC
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* trng register offset */
+#define STARFIVE_CTRL  0x00
+#define STARFIVE_STAT  0x04
+#define STARFIVE_MODE  0x08
+#define STARFIVE_SMODE 0x0C
+#define STARFIVE_IE0x10
+#define STARFIVE_ISTAT 0x14
+#define STARFIVE_RAND0 0x20
+#define STARFIVE_RAND1 0x24
+#define STARFIVE_RAND2 0x28
+#define STARFIVE_RAND3 0x2C
+#define STARFIVE_RAND4 0x30
+#define STARFIVE_RAND5 0x34
+#define STARFIVE_RAND6 0x38
+#define STARFIVE_RAND7 0x3C
+#define STARFIVE_AUTO_RQSTS0x60
+#define STARFIVE_AUTO_AGE  0x64
+
+/* CTRL CMD */
+#define STARFIVE_CTRL_EXEC_NOP 0x0
+#define STARFIVE_CTRL_GENE_RANDNUM 0x1
+#define STARFIVE_CTRL_EXEC_RANDRESEED  0x2
+
+/* STAT */
+#define STARFIVE_STAT_NONCE_MODE   BIT(2)
+#define STARFIVE_STAT_R256 BIT(3)
+#define STARFIVE_STAT_MISSION_MODE BIT(8)
+#define STARFIVE_STAT_SEEDED   BIT(9)
+#define STARFIVE_STAT_LAST_RESEED(x)   ((x) << 16)
+#define STARFIVE_STAT_SRVC_RQSTBIT(27)
+#define STARFIVE_STAT_RAND_GENERATING  BIT(30)
+#define STARFIVE_STAT_RAND_SEEDING BIT(31)
+#define STARFIVE_STAT_RUNNING  (STARFIVE_STAT_RAND_GENERATING | \
+STARFIVE_STAT_RAND_SEEDING)
+
+/* MODE */
+#define STARFIVE_MODE_R256 BIT(3)
+
+/* SMODE */
+#define STARFIVE_SMODE_NONCE_MODE  BIT(2)
+#define STARFIVE_SMODE_MISSION_MODEBIT(8)
+#define STARFIVE_SMODE_MAX_REJECTS(x)  ((x) << 16)
+
+/* IE */
+#define STARFIVE_IE_RAND_RDY_ENBIT(0)
+#define STARFIVE_IE_SEED_DONE_EN   BIT(1)
+#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
+#define STARFIVE_IE_GLBL_ENBIT(31)
+
+#define STARFIVE_IE_ALL(STARFIVE_IE_GLBL_EN | \
+STARFIVE_IE_RAND_RDY_EN | \
+STARFIVE_IE_SEED_DONE_EN | \
+STARFIVE_IE_LFSR_LOCKUP_EN)
+
+/* ISTAT */
+#define STARFIVE_ISTAT_RAND_RDYBIT(0)
+#define STARFIVE_ISTAT_SEED_DONE   BIT(1)
+#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
+
+#define STARFIVE_RAND_LEN  sizeof(u32)
+
+enum mode {
+   PRNG_128BIT,
+   PRNG_256BIT,
+};
+
+struct starfive_trng_plat {
+   void *base;
+   struct clk *hclk;
+   struct clk *ahb;
+   struct reset_ctl *rst;
+   u32 mode;
+};
+
+static inline int starfive_trng_wait_idle(struct starfive_trng_plat *trng)
+{
+   u32 stat;
+
+   return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
+ !(stat & STARFIVE_STAT_RUNNING),
+ 10);
+}
+
+static inline void starfive_trng_irq_mask_clear(struct starfive_trng_plat 
*trng)
+{
+   /* clear register: ISTAT */
+   u32 data = readl(trng->base + STARFIVE_ISTAT);
+
+   writel(data, trng->base + STARFIVE_ISTAT);
+}
+
+static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd)
+{
+   u32 stat, flg;
+   int ret;
+
+   switch

[PATCH v3 0/5] Add support for StarFive JH7110 TRNG driver

[Chanho Park]

This patchset adds to support StarFive JH7110 TRNG driver. Due to lack
of readl_relaxed API, the first patch tries to import the
APIs(read/write_relaxed) from Linux kernel's implementation. The second
patch adds the missing security clocks which are required by the trng
IP.

This IP can support 128-bit and 256-bit random number generation but
this patch makes 256-bit default mode for convenience.

Changes from v2:
- Patch #3: Add error handling codes of probe() which are suggested by Jaehoon

Changes from v1:
- Patch #3: Apply Heinrich's reviews and his codes
- Patch #5: Add Heinrich's R-b tag

Chanho Park (5):
  riscv: import read/write_relaxed functions
  clk: starfive: jh7110: Add security clocks
  rng: Add StarFive JH7110 RNG driver
  riscv: dts: jh7110: Add rng device tree node
  configs: visionfive2: Enable JH7110 RNG driver

 arch/riscv/dts/jh7110.dtsi |  10 +
 arch/riscv/include/asm/io.h|  45 
 configs/starfive_visionfive2_defconfig |   2 +
 drivers/clk/starfive/clk-jh7110.c  |  10 +
 drivers/rng/Kconfig|   6 +
 drivers/rng/Makefile   |   1 +
 drivers/rng/jh7110_rng.c   | 271 +
 7 files changed, 345 insertions(+)
 create mode 100644 drivers/rng/jh7110_rng.c

-- 
2.39.2

[PATCH v3 2/5] clk: starfive: jh7110: Add security clocks

[Chanho Park]

Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.

Signed-off-by: Chanho Park 
---
 drivers/clk/starfive/clk-jh7110.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/starfive/clk-jh7110.c 
b/drivers/clk/starfive/clk-jh7110.c
index 31aaf3340f94..a835541e48e9 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -539,6 +539,16 @@ static int jh7110_stgcrg_init(struct udevice *dev)
 "pcie1_tl", "stg_axiahb",
 OFFSET(JH7110_STGCLK_PCIE1_TL)));
 
+   /* Security clocks */
+   clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+  starfive_clk_gate(priv->reg,
+"sec_ahb", "stg_axiahb",
+OFFSET(JH7110_STGCLK_SEC_HCLK)));
+   clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+  starfive_clk_gate(priv->reg,
+"sec_misc_ahb", "stg_axiahb",
+OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+
return 0;
 }
 
-- 
2.39.2

[PATCH v3 4/5] riscv: dts: jh7110: Add rng device tree node

[Chanho Park]

Adds jh7110 trng device tree node.

Signed-off-by: Chanho Park 
---
 arch/riscv/dts/jh7110.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index ec237a46ffba..13c47f7caa36 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -627,6 +627,16 @@
status = "disabled";
};
 
+   rng: rng@1600c000 {
+   compatible = "starfive,jh7110-trng";
+   reg = <0x0 0x1600C000 0x0 0x4000>;
+   clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+<&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+   clock-names = "hclk", "ahb";
+   resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+   interrupts = <30>;
+   };
+
aoncrg: clock-controller@1700 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x1700 0x0 0x1>;
-- 
2.39.2

[PATCH v3 5/5] configs: visionfive2: Enable JH7110 RNG driver

[Chanho Park]

Enables JH7110 RNG driver to visionfive2 board.

Signed-off-by: Chanho Park 
Reviewed-by: Heinrich Schuchardt 
---
 configs/starfive_visionfive2_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index b21754feafce..b15e7d24db19 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -120,6 +120,8 @@ CONFIG_SPL_PINCTRL_STARFIVE=y
 CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
 CONFIG_PINCTRL_STARFIVE=y
 # CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RNG=y
+CONFIG_RNG_JH7110=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
-- 
2.39.2

[PATCH v3 1/5] riscv: import read/write_relaxed functions

[Chanho Park]

This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
to use read/write[b|w|l|q]_relaxed functions.

Signed-off-by: Chanho Park 
---
 arch/riscv/include/asm/io.h | 45 +
 1 file changed, 45 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index b16e6dfa3760..4170877a1ae0 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -323,6 +323,51 @@ static inline void writesl(unsigned int *addr, const void 
*data, int longlen)
 #define insw_p(port, to, len)  insw(port, to, len)
 #define insl_p(port, to, len)  insl(port, to, len)
 
+/*
+ * Unordered I/O memory access primitives.  These are even more relaxed than
+ * the relaxed versions, as they don't even order accesses between successive
+ * operations to the I/O regions.
+ */
+#define readb_cpu(c)   ({ u8  __r = __raw_readb(c); __r; })
+#define readw_cpu(c)   ({ u16 __r = le16_to_cpu((__force 
__le16)__raw_readw(c)); __r; })
+#define readl_cpu(c)   ({ u32 __r = le32_to_cpu((__force 
__le32)__raw_readl(c)); __r; })
+
+#define writeb_cpu(v, c)   ((void)__raw_writeb((v), (c)))
+#define writew_cpu(v, c)   ((void)__raw_writew((__force 
u16)cpu_to_le16(v), (c)))
+#define writel_cpu(v, c)   ((void)__raw_writel((__force 
u32)cpu_to_le32(v), (c)))
+
+#ifdef CONFIG_64BIT
+#define readq_cpu(c)   ({ u64 __r = le64_to_cpu((__force 
__le64)__raw_readq(c)); __r; })
+#define writeq_cpu(v, c)   ((void)__raw_writeq((__force 
u64)cpu_to_le64(v), (c)))
+#endif
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.  These are defined to order the indicated access (either a read or
+ * write) with all other I/O memory accesses to the same peripheral. Since the
+ * platform specification defines that all I/O regions are strongly ordered on
+ * channel 0, no explicit fences are required to enforce this ordering.
+ */
+/* FIXME: These are now the same as asm-generic */
+#define __io_rbr() do {} while (0)
+#define __io_rar() do {} while (0)
+#define __io_rbw() do {} while (0)
+#define __io_raw() do {} while (0)
+
+#define readb_relaxed(c)   ({ u8  __v; __io_rbr(); __v = readb_cpu(c); 
__io_rar(); __v; })
+#define readw_relaxed(c)   ({ u16 __v; __io_rbr(); __v = readw_cpu(c); 
__io_rar(); __v; })
+#define readl_relaxed(c)   ({ u32 __v; __io_rbr(); __v = readl_cpu(c); 
__io_rar(); __v; })
+
+#define writeb_relaxed(v, c)   ({ __io_rbw(); writeb_cpu((v), (c)); 
__io_raw(); })
+#define writew_relaxed(v, c)   ({ __io_rbw(); writew_cpu((v), (c)); 
__io_raw(); })
+#define writel_relaxed(v, c)   ({ __io_rbw(); writel_cpu((v), (c)); 
__io_raw(); })
+
+#ifdef CONFIG_64BIT
+#define readq_relaxed(c)   ({ u64 __v; __io_rbr(); __v = readq_cpu(c); 
__io_rar(); __v; })
+#define writeq_relaxed(v, c)   ({ __io_rbw(); writeq_cpu((v), (c)); 
__io_raw(); })
+#endif
+
 #include 
 
 #endif /* __ASM_RISCV_IO_H */
-- 
2.39.2

RE: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver

[Chanho Park]

> -Original Message-
> From: Jaehoon Chung 
> Sent: Wednesday, November 1, 2023 9:52 AM
> To: 'Chanho Park' ; 'Sughosh Ganu'
> ; 'Heinrich Schuchardt' ;
> 'Rick Chen' ; 'Leo' ; u-
> b...@lists.denx.de
> Subject: RE: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
> 
> 
> 
> > -Original Message-
> > From: U-Boot  On Behalf Of Chanho Park
> > Sent: Wednesday, November 1, 2023 8:55 AM
> > To: Sughosh Ganu ; Heinrich Schuchardt
> ; Rick Chen
> > ; Leo ; u-boot@lists.denx.de
> > Cc: Chanho Park 
> > Subject: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
> >
> > Adds to support JH7110 TRNG driver which is based on linux kernel's
> > jh7110-trng.c. This can support to generate 256-bit random numbers and
> > 128-bit but this makes 256-bit default for convenience.
> >
> > Signed-off-by: Chanho Park 
> > ---
> >  drivers/rng/Kconfig  |   6 +
> >  drivers/rng/Makefile |   1 +
> >  drivers/rng/jh7110_rng.c | 258 +++
> >  3 files changed, 265 insertions(+)
> >  create mode 100644 drivers/rng/jh7110_rng.c
> >
> > diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
> > index 994cc35b2744..0dba1e06b429 100644
> > --- a/drivers/rng/Kconfig
> > +++ b/drivers/rng/Kconfig
> > @@ -91,4 +91,10 @@ config TPM_RNG
> >   functionality. Enable random number generator on TPM
> >   devices.
> >
> > +config RNG_JH7110
> > +   bool "StarFive JH7110 Random Number Generator support"
> > +   depends on DM_RNG && STARFIVE_JH7110
> > +   help
> > + Enable True Random Number Generator in StarFive JH7110 SoCs.
> > +
> >  endif
> > diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
> > index 47b323e61ee3..9de762c8a1c3 100644
> > --- a/drivers/rng/Makefile
> > +++ b/drivers/rng/Makefile
> > @@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
> >  obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
> >  obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
> >  obj-$(CONFIG_TPM_RNG) += tpm_rng.o
> > +obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
> > diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
> > new file mode 100644
> > index ..37ea8cc39945
> > --- /dev/null
> > +++ b/drivers/rng/jh7110_rng.c
> > @@ -0,0 +1,258 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * TRNG driver for the StarFive JH7110 SoC
> > + *
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* trng register offset */
> > +#define STARFIVE_CTRL  0x00
> > +#define STARFIVE_STAT  0x04
> > +#define STARFIVE_MODE  0x08
> > +#define STARFIVE_SMODE 0x0C
> > +#define STARFIVE_IE0x10
> > +#define STARFIVE_ISTAT 0x14
> > +#define STARFIVE_RAND0 0x20
> > +#define STARFIVE_RAND1 0x24
> > +#define STARFIVE_RAND2 0x28
> > +#define STARFIVE_RAND3 0x2C
> > +#define STARFIVE_RAND4 0x30
> > +#define STARFIVE_RAND5 0x34
> > +#define STARFIVE_RAND6 0x38
> > +#define STARFIVE_RAND7 0x3C
> > +#define STARFIVE_AUTO_RQSTS0x60
> > +#define STARFIVE_AUTO_AGE  0x64
> > +
> > +/* CTRL CMD */
> > +#define STARFIVE_CTRL_EXEC_NOP 0x0
> > +#define STARFIVE_CTRL_GENE_RANDNUM 0x1
> > +#define STARFIVE_CTRL_EXEC_RANDRESEED  0x2
> > +
> > +/* STAT */
> > +#define STARFIVE_STAT_NONCE_MODE   BIT(2)
> > +#define STARFIVE_STAT_R256 BIT(3)
> > +#define STARFIVE_STAT_MISSION_MODE BIT(8)
> > +#define STARFIVE_STAT_SEEDED   BIT(9)
> > +#define STARFIVE_STAT_LAST_RESEED(x)   ((x) << 16)
> > +#define STARFIVE_STAT_SRVC_RQSTBIT(27)
> > +#define STARFIVE_STAT_RAND_GENERATING  BIT(30)
> > +#define STARFIVE_STAT_RAND_SEEDING BIT(31)
> > +#define STARFIVE_STAT_RUNNING  (STARFIVE_STAT_RAND_GENERATING 
> > | \
> > +STARFIVE_STAT_RAND_SEEDING)
> > +
> > +/* MODE */
> > +#define STARFIVE_MODE_R256 BIT(3)
> > +
> > +/* SMODE */
> > +#define STARFIVE_SMODE_NONCE_MODE  BIT(2)
> > +#define STARFI

[PATCH v2 1/5] riscv: import read/write_relaxed functions

[Chanho Park]

This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
to use read/write[b|w|l|q]_relaxed functions.

Signed-off-by: Chanho Park 
---
 arch/riscv/include/asm/io.h | 45 +
 1 file changed, 45 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index b16e6dfa3760..4170877a1ae0 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -323,6 +323,51 @@ static inline void writesl(unsigned int *addr, const void 
*data, int longlen)
 #define insw_p(port, to, len)  insw(port, to, len)
 #define insl_p(port, to, len)  insl(port, to, len)
 
+/*
+ * Unordered I/O memory access primitives.  These are even more relaxed than
+ * the relaxed versions, as they don't even order accesses between successive
+ * operations to the I/O regions.
+ */
+#define readb_cpu(c)   ({ u8  __r = __raw_readb(c); __r; })
+#define readw_cpu(c)   ({ u16 __r = le16_to_cpu((__force 
__le16)__raw_readw(c)); __r; })
+#define readl_cpu(c)   ({ u32 __r = le32_to_cpu((__force 
__le32)__raw_readl(c)); __r; })
+
+#define writeb_cpu(v, c)   ((void)__raw_writeb((v), (c)))
+#define writew_cpu(v, c)   ((void)__raw_writew((__force 
u16)cpu_to_le16(v), (c)))
+#define writel_cpu(v, c)   ((void)__raw_writel((__force 
u32)cpu_to_le32(v), (c)))
+
+#ifdef CONFIG_64BIT
+#define readq_cpu(c)   ({ u64 __r = le64_to_cpu((__force 
__le64)__raw_readq(c)); __r; })
+#define writeq_cpu(v, c)   ((void)__raw_writeq((__force 
u64)cpu_to_le64(v), (c)))
+#endif
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.  These are defined to order the indicated access (either a read or
+ * write) with all other I/O memory accesses to the same peripheral. Since the
+ * platform specification defines that all I/O regions are strongly ordered on
+ * channel 0, no explicit fences are required to enforce this ordering.
+ */
+/* FIXME: These are now the same as asm-generic */
+#define __io_rbr() do {} while (0)
+#define __io_rar() do {} while (0)
+#define __io_rbw() do {} while (0)
+#define __io_raw() do {} while (0)
+
+#define readb_relaxed(c)   ({ u8  __v; __io_rbr(); __v = readb_cpu(c); 
__io_rar(); __v; })
+#define readw_relaxed(c)   ({ u16 __v; __io_rbr(); __v = readw_cpu(c); 
__io_rar(); __v; })
+#define readl_relaxed(c)   ({ u32 __v; __io_rbr(); __v = readl_cpu(c); 
__io_rar(); __v; })
+
+#define writeb_relaxed(v, c)   ({ __io_rbw(); writeb_cpu((v), (c)); 
__io_raw(); })
+#define writew_relaxed(v, c)   ({ __io_rbw(); writew_cpu((v), (c)); 
__io_raw(); })
+#define writel_relaxed(v, c)   ({ __io_rbw(); writel_cpu((v), (c)); 
__io_raw(); })
+
+#ifdef CONFIG_64BIT
+#define readq_relaxed(c)   ({ u64 __v; __io_rbr(); __v = readq_cpu(c); 
__io_rar(); __v; })
+#define writeq_relaxed(v, c)   ({ __io_rbw(); writeq_cpu((v), (c)); 
__io_raw(); })
+#endif
+
 #include 
 
 #endif /* __ASM_RISCV_IO_H */
-- 
2.39.2

[PATCH v2 5/5] configs: visionfive2: Enable JH7110 RNG driver

[Chanho Park]

Enables JH7110 RNG driver to visionfive2 board.

Signed-off-by: Chanho Park 
Reviewed-by: Heinrich Schuchardt 
---
 configs/starfive_visionfive2_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index b21754feafce..b15e7d24db19 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -120,6 +120,8 @@ CONFIG_SPL_PINCTRL_STARFIVE=y
 CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
 CONFIG_PINCTRL_STARFIVE=y
 # CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RNG=y
+CONFIG_RNG_JH7110=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
-- 
2.39.2

[PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver

[Chanho Park]

Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.

Signed-off-by: Chanho Park 
---
 drivers/rng/Kconfig  |   6 +
 drivers/rng/Makefile |   1 +
 drivers/rng/jh7110_rng.c | 258 +++
 3 files changed, 265 insertions(+)
 create mode 100644 drivers/rng/jh7110_rng.c

diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 994cc35b2744..0dba1e06b429 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -91,4 +91,10 @@ config TPM_RNG
  functionality. Enable random number generator on TPM
  devices.
 
+config RNG_JH7110
+   bool "StarFive JH7110 Random Number Generator support"
+   depends on DM_RNG && STARFIVE_JH7110
+   help
+ Enable True Random Number Generator in StarFive JH7110 SoCs.
+
 endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 47b323e61ee3..9de762c8a1c3 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
 obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
 obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
 obj-$(CONFIG_TPM_RNG) += tpm_rng.o
+obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
new file mode 100644
index ..37ea8cc39945
--- /dev/null
+++ b/drivers/rng/jh7110_rng.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * TRNG driver for the StarFive JH7110 SoC
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* trng register offset */
+#define STARFIVE_CTRL  0x00
+#define STARFIVE_STAT  0x04
+#define STARFIVE_MODE  0x08
+#define STARFIVE_SMODE 0x0C
+#define STARFIVE_IE0x10
+#define STARFIVE_ISTAT 0x14
+#define STARFIVE_RAND0 0x20
+#define STARFIVE_RAND1 0x24
+#define STARFIVE_RAND2 0x28
+#define STARFIVE_RAND3 0x2C
+#define STARFIVE_RAND4 0x30
+#define STARFIVE_RAND5 0x34
+#define STARFIVE_RAND6 0x38
+#define STARFIVE_RAND7 0x3C
+#define STARFIVE_AUTO_RQSTS0x60
+#define STARFIVE_AUTO_AGE  0x64
+
+/* CTRL CMD */
+#define STARFIVE_CTRL_EXEC_NOP 0x0
+#define STARFIVE_CTRL_GENE_RANDNUM 0x1
+#define STARFIVE_CTRL_EXEC_RANDRESEED  0x2
+
+/* STAT */
+#define STARFIVE_STAT_NONCE_MODE   BIT(2)
+#define STARFIVE_STAT_R256 BIT(3)
+#define STARFIVE_STAT_MISSION_MODE BIT(8)
+#define STARFIVE_STAT_SEEDED   BIT(9)
+#define STARFIVE_STAT_LAST_RESEED(x)   ((x) << 16)
+#define STARFIVE_STAT_SRVC_RQSTBIT(27)
+#define STARFIVE_STAT_RAND_GENERATING  BIT(30)
+#define STARFIVE_STAT_RAND_SEEDING BIT(31)
+#define STARFIVE_STAT_RUNNING  (STARFIVE_STAT_RAND_GENERATING | \
+STARFIVE_STAT_RAND_SEEDING)
+
+/* MODE */
+#define STARFIVE_MODE_R256 BIT(3)
+
+/* SMODE */
+#define STARFIVE_SMODE_NONCE_MODE  BIT(2)
+#define STARFIVE_SMODE_MISSION_MODEBIT(8)
+#define STARFIVE_SMODE_MAX_REJECTS(x)  ((x) << 16)
+
+/* IE */
+#define STARFIVE_IE_RAND_RDY_ENBIT(0)
+#define STARFIVE_IE_SEED_DONE_EN   BIT(1)
+#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
+#define STARFIVE_IE_GLBL_ENBIT(31)
+
+#define STARFIVE_IE_ALL(STARFIVE_IE_GLBL_EN | \
+STARFIVE_IE_RAND_RDY_EN | \
+STARFIVE_IE_SEED_DONE_EN | \
+STARFIVE_IE_LFSR_LOCKUP_EN)
+
+/* ISTAT */
+#define STARFIVE_ISTAT_RAND_RDYBIT(0)
+#define STARFIVE_ISTAT_SEED_DONE   BIT(1)
+#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
+
+#define STARFIVE_RAND_LEN  sizeof(u32)
+
+enum mode {
+   PRNG_128BIT,
+   PRNG_256BIT,
+};
+
+struct starfive_trng_plat {
+   void *base;
+   struct clk *hclk;
+   struct clk *ahb;
+   struct reset_ctl *rst;
+   u32 mode;
+};
+
+static inline int starfive_trng_wait_idle(struct starfive_trng_plat *trng)
+{
+   u32 stat;
+
+   return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
+ !(stat & STARFIVE_STAT_RUNNING),
+ 10);
+}
+
+static inline void starfive_trng_irq_mask_clear(struct starfive_trng_plat 
*trng)
+{
+   /* clear register: ISTAT */
+   u32 data = readl(trng->base + STARFIVE_ISTAT);
+
+   writel(data, trng->base + STARFIVE_ISTAT);
+}
+
+static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd)
+{
+   u32 stat, flg;
+   int ret;
+
+   switch

[PATCH v2 4/5] riscv: dts: jh7110: Add rng device tree node

[Chanho Park]

Adds jh7110 trng device tree node.

Signed-off-by: Chanho Park 
---
 arch/riscv/dts/jh7110.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index ec237a46ffba..13c47f7caa36 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -627,6 +627,16 @@
status = "disabled";
};
 
+   rng: rng@1600c000 {
+   compatible = "starfive,jh7110-trng";
+   reg = <0x0 0x1600C000 0x0 0x4000>;
+   clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+<&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+   clock-names = "hclk", "ahb";
+   resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+   interrupts = <30>;
+   };
+
aoncrg: clock-controller@1700 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x1700 0x0 0x1>;
-- 
2.39.2

[PATCH v2 2/5] clk: starfive: jh7110: Add security clocks

[Chanho Park]

Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.

Signed-off-by: Chanho Park 
---
 drivers/clk/starfive/clk-jh7110.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/starfive/clk-jh7110.c 
b/drivers/clk/starfive/clk-jh7110.c
index 31aaf3340f94..a835541e48e9 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -539,6 +539,16 @@ static int jh7110_stgcrg_init(struct udevice *dev)
 "pcie1_tl", "stg_axiahb",
 OFFSET(JH7110_STGCLK_PCIE1_TL)));
 
+   /* Security clocks */
+   clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+  starfive_clk_gate(priv->reg,
+"sec_ahb", "stg_axiahb",
+OFFSET(JH7110_STGCLK_SEC_HCLK)));
+   clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+  starfive_clk_gate(priv->reg,
+"sec_misc_ahb", "stg_axiahb",
+OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+
return 0;
 }
 
-- 
2.39.2

[PATCH v2 0/5] Add support for StarFive JH7110 TRNG driver

[Chanho Park]

This patchset adds to support StarFive JH7110 TRNG driver. Due to lack
of readl_relaxed API, the first patch tries to import the
APIs(read/write_relaxed) from Linux kernel's implementation. The second
patch adds the missing security clocks which are required by the trng
IP.

This IP can support 128-bit and 256-bit random number generation but
this patch makes 256-bit default mode for convenience.

Changes from v1:
- Patch #3: Apply Heinrich's reviews and his codes
- Patch #5: Add Heinrich's R-b tag

Chanho Park (5):
  riscv: import read/write_relaxed functions
  clk: starfive: jh7110: Add security clocks
  rng: Add StarFive JH7110 RNG driver
  riscv: dts: jh7110: Add rng device tree node
  configs: visionfive2: Enable JH7110 RNG driver

 arch/riscv/dts/jh7110.dtsi |  10 +
 arch/riscv/include/asm/io.h|  45 +
 configs/starfive_visionfive2_defconfig |   2 +
 drivers/clk/starfive/clk-jh7110.c  |  10 +
 drivers/rng/Kconfig|   6 +
 drivers/rng/Makefile   |   1 +
 drivers/rng/jh7110_rng.c   | 258 +
 7 files changed, 332 insertions(+)
 create mode 100644 drivers/rng/jh7110_rng.c

-- 
2.39.2

RE: [PATCH 3/5] rng: Add StarFive JH7110 RNG driver

[Chanho Park]

> -Original Message-
> From: Heinrich Schuchardt 
> Sent: Wednesday, November 1, 2023 6:18 AM
> To: Chanho Park 
> Cc: Sughosh Ganu ; Rick Chen ;
> Leo ; u-boot@lists.denx.de
> Subject: Re: [PATCH 3/5] rng: Add StarFive JH7110 RNG driver
> 
> On 10/30/23 09:32, Chanho Park wrote:
> > Adds to support JH7110 TRNG driver which is based on linux kernel's
> > jh7110-trng.c. This can support to generate 256-bit random numbers and
> > 128-bit but this makes 256-bit default for convenience.
> >
> > Signed-off-by: Chanho Park 
> > ---
> >   drivers/rng/Kconfig  |   6 +
> >   drivers/rng/Makefile |   1 +
> >   drivers/rng/jh7110_rng.c | 272 +++
> >   3 files changed, 279 insertions(+)
> >   create mode 100644 drivers/rng/jh7110_rng.c
> >
> > diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
> > index 994cc35b2744..0dba1e06b429 100644
> > --- a/drivers/rng/Kconfig
> > +++ b/drivers/rng/Kconfig
> > @@ -91,4 +91,10 @@ config TPM_RNG
> >   functionality. Enable random number generator on TPM
> >   devices.
> >
> > +config RNG_JH7110
> > +   bool "StarFive JH7110 Random Number Generator support"
> > +   depends on DM_RNG && STARFIVE_JH7110
> > +   help
> > + Enable True Random Number Generator in StarFive JH7110 SoCs.
> > +
> >   endif
> > diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
> > index 47b323e61ee3..9de762c8a1c3 100644
> > --- a/drivers/rng/Makefile
> > +++ b/drivers/rng/Makefile
> > @@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
> >   obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
> >   obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
> >   obj-$(CONFIG_TPM_RNG) += tpm_rng.o
> > +obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
> > diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
> > new file mode 100644
> > index ..e71bf188f017
> > --- /dev/null
> > +++ b/drivers/rng/jh7110_rng.c
> > @@ -0,0 +1,272 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * TRNG driver for the StarFive JH7110 SoC
> > + *
> > + */
> > +
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +#include 
> > +
> > +/* trng register offset */
> > +#define STARFIVE_CTRL  0x00
> > +#define STARFIVE_STAT  0x04
> > +#define STARFIVE_MODE  0x08
> > +#define STARFIVE_SMODE 0x0C
> > +#define STARFIVE_IE0x10
> > +#define STARFIVE_ISTAT 0x14
> > +#define STARFIVE_RAND0 0x20
> > +#define STARFIVE_RAND1 0x24
> > +#define STARFIVE_RAND2 0x28
> > +#define STARFIVE_RAND3 0x2C
> > +#define STARFIVE_RAND4 0x30
> > +#define STARFIVE_RAND5 0x34
> > +#define STARFIVE_RAND6 0x38
> > +#define STARFIVE_RAND7 0x3C
> > +#define STARFIVE_AUTO_RQSTS0x60
> > +#define STARFIVE_AUTO_AGE  0x64
> > +
> > +/* CTRL CMD */
> > +#define STARFIVE_CTRL_EXEC_NOP 0x0
> > +#define STARFIVE_CTRL_GENE_RANDNUM 0x1
> > +#define STARFIVE_CTRL_EXEC_RANDRESEED  0x2
> > +
> > +/* STAT */
> > +#define STARFIVE_STAT_NONCE_MODE   BIT(2)
> > +#define STARFIVE_STAT_R256 BIT(3)
> > +#define STARFIVE_STAT_MISSION_MODE BIT(8)
> > +#define STARFIVE_STAT_SEEDED   BIT(9)
> > +#define STARFIVE_STAT_LAST_RESEED(x)   ((x) << 16)
> > +#define STARFIVE_STAT_SRVC_RQSTBIT(27)
> > +#define STARFIVE_STAT_RAND_GENERATING  BIT(30)
> > +#define STARFIVE_STAT_RAND_SEEDING BIT(31)
> > +#define STARFIVE_STAT_RUNNING  (STARFIVE_STAT_RAND_GENERATING 
> > | \
> > +STARFIVE_STAT_RAND_SEEDING)
> > +
> > +/* MODE */
> > +#define STARFIVE_MODE_R256 BIT(3)
> > +
> > +/* SMODE */
> > +#define STARFIVE_SMODE_NONCE_MODE  BIT(2)
> > +#define STARFIVE_SMODE_MISSION_MODEBIT(8)
> > +#define STARFIVE_SMODE_MAX_REJECTS(x)  ((x) << 16)
> > +
> > +/* IE */
> > +#define STARFIVE_IE_RAND_RDY_ENBIT(0)
> > +#define STARFIVE_IE_SEED_DONE_EN   BIT(1)
> > +#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
> > +#define STARFIVE_IE_GLBL_ENBIT(31)
> > +
> > +#defi

[PATCH 0/2] Support JTAG for VisionFive2 board

[Chanho Park]

To support JTAG for VisionFive2 board, we need to control JTAG pins by
S/W. spl_board_init_f function seems to be proper place to initialize
these pins.

Chanho Park (2):
  riscv: cpu: jh7110: Add gpio helper macros
  board: starfive: spl: Support jtag for VisionFive2 board

 arch/riscv/include/asm/arch-jh7110/gpio.h | 85 +++
 board/starfive/visionfive2/spl.c  | 23 ++
 2 files changed, 108 insertions(+)
 create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h

-- 
2.39.2

[PATCH 2/2] board: starfive: spl: Support jtag for VisionFive2 board

[Chanho Park]

JTAG pins are mapped as below. To access the JTAG pins, we need to
control the GPIO pins from SPL which seems to be the earliest stage for
JTAG.

- JTAG nTRST:   GPIO36 / Input
- JTAG TDI: GPIO61 / Input
- JTAG TMS: GPIO63 / Input
- JTAG TCK: GPIO60 / Input
- JTAG TDO: GPIO44 / Output

Signed-off-by: Chanho Park 
---
 board/starfive/visionfive2/spl.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index ad5f71a20180..336f0cdfc90f 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -172,10 +173,32 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
/* Update the memory size which read form eeprom or DT */
fdt_fixup_memory(spl_image->fdt_addr, 0x4000, gd->ram_size);
 }
+
+static void jh7110_jtag_init(void)
+{
+   /* nTRST: GPIO36 */
+   SYS_IOMUX_DOEN(36, HIGH);
+   SYS_IOMUX_DIN(36, 4);
+   /* TDI: GPIO61 */
+   SYS_IOMUX_DOEN(61, HIGH);
+   SYS_IOMUX_DIN(61, 19);
+   /* TMS: GPIO63 */
+   SYS_IOMUX_DOEN(63, HIGH);
+   SYS_IOMUX_DIN(63, 20);
+   /* TCK: GPIO60 */
+   SYS_IOMUX_DOEN(60, HIGH);
+   SYS_IOMUX_DIN(60, 29);
+   /* TDO: GPIO44 */
+   SYS_IOMUX_DOEN(44, 8);
+   SYS_IOMUX_DOUT(44, 22);
+}
+
 int spl_board_init_f(void)
 {
int ret;
 
+   jh7110_jtag_init();
+
ret = spl_soc_init();
if (ret) {
debug("JH7110 SPL init failed: %d\n", ret);
-- 
2.39.2

[PATCH 1/2] riscv: cpu: jh7110: Add gpio helper macros

[Chanho Park]

Add gpio.h header file that includes JH7110 helper macros. The file is
imported from StarFive github[1] with small changes such as alignment.

[1]: https://github.com/starfive-tech/u-boot

Signed-off-by: Chanho Park 
---
 arch/riscv/include/asm/arch-jh7110/gpio.h | 85 +++
 1 file changed, 85 insertions(+)
 create mode 100644 arch/riscv/include/asm/arch-jh7110/gpio.h

diff --git a/arch/riscv/include/asm/arch-jh7110/gpio.h 
b/arch/riscv/include/asm/arch-jh7110/gpio.h
new file mode 100644
index ..90aa2f8a9ed4
--- /dev/null
+++ b/arch/riscv/include/asm/arch-jh7110/gpio.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ * Author: yanhong 
+ *
+ */
+
+#ifndef _GPIO_STARFIVE_H_
+#define _GPIO_STARFIVE_H_
+
+#include 
+
+#define GPIO_NUM_SHIFT 2 /*one dword include 4 gpios*/
+#define GPIO_BYTE_SHIFT3
+
+#define GPIO_INDEX_MASK0x3
+
+#define GPIO_DOEN_MASK 0x3f
+#define GPIO_DOUT_MASK 0x7f
+#define GPIO_DIN_MASK  0x7f
+#define GPIO_DS_MASK   0x06
+#define GPIO_DS_SHIFT  1
+#define GPIO_SLEW_MASK BIT(5)
+#define GPIO_SLEW_SHIFT5
+#define GPIO_PULL_MASK 0x18
+#define GPIO_PULL_SHIFT3
+#define GPIO_PULL_UP   1
+#define GPIO_PULL_DOWN 2
+
+#define NR_GPIOS   64
+
+#define GPIO_OFFSET(gpio)  \
+   (((gpio) >> GPIO_NUM_SHIFT) << GPIO_NUM_SHIFT)
+
+#define GPIO_SHIFT(gpio) \
+   (((gpio) & GPIO_INDEX_MASK) << GPIO_BYTE_SHIFT)
+
+enum gpio_state {
+   LOW,
+   HIGH
+};
+
+#define GPIO_DOEN  0x0
+#define GPIO_DOUT  0x40
+#define GPIO_DIN   0x80
+#define GPIO_EN0xdc
+#define GPIO_LOW_IE0x100
+#define GPIO_HIGH_IE   0x104
+#define GPIO_CONFIG0x120
+
+#define SYS_IOMUX_DOEN(gpio, oen) \
+   clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_OFFSET(gpio), \
+   GPIO_DOEN_MASK << GPIO_SHIFT(gpio), \
+   (oen) << GPIO_SHIFT(gpio))
+
+#define SYS_IOMUX_DOUT(gpio, gpo) \
+   clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DOUT + GPIO_OFFSET(gpio), \
+   GPIO_DOUT_MASK << GPIO_SHIFT(gpio), \
+   ((gpo) & GPIO_DOUT_MASK) << GPIO_SHIFT(gpio))
+
+#define SYS_IOMUX_DIN(gpio, gpi)\
+   clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_DIN + GPIO_OFFSET(gpi), \
+   GPIO_DIN_MASK << GPIO_SHIFT(gpi), \
+   ((gpio + 2) & GPIO_DIN_MASK) << GPIO_SHIFT(gpi))
+
+#define SYS_IOMUX_SET_DS(gpio, ds) \
+   clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+   GPIO_DS_MASK, (ds) << GPIO_DS_SHIFT)
+
+#define SYS_IOMUX_SET_SLEW(gpio, slew) \
+   clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+   GPIO_SLEW_MASK, (slew) << GPIO_SLEW_SHIFT)
+
+#define SYS_IOMUX_SET_PULL(gpio, pull) \
+   clrsetbits_le32(JH7110_SYS_IOMUX + GPIO_CONFIG + gpio * 4, \
+   GPIO_PULL_MASK, (pull) << GPIO_PULL_SHIFT)
+
+#define SYS_IOMUX_COMPLEX(gpio, gpi, gpo, oen) \
+   do { \
+   SYS_IOMUX_DOEN(gpio, oen); \
+   SYS_IOMUX_DOUT(gpio, gpo); \
+   SYS_IOMUX_DIN(gpio, gpi); \
+   } while (0)
+
+#endif /* _GPIO_STARFIVE_H_ */
-- 
2.39.2

[PATCH 3/5] rng: Add StarFive JH7110 RNG driver

[Chanho Park]

Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.

Signed-off-by: Chanho Park 
---
 drivers/rng/Kconfig  |   6 +
 drivers/rng/Makefile |   1 +
 drivers/rng/jh7110_rng.c | 272 +++
 3 files changed, 279 insertions(+)
 create mode 100644 drivers/rng/jh7110_rng.c

diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
index 994cc35b2744..0dba1e06b429 100644
--- a/drivers/rng/Kconfig
+++ b/drivers/rng/Kconfig
@@ -91,4 +91,10 @@ config TPM_RNG
  functionality. Enable random number generator on TPM
  devices.
 
+config RNG_JH7110
+   bool "StarFive JH7110 Random Number Generator support"
+   depends on DM_RNG && STARFIVE_JH7110
+   help
+ Enable True Random Number Generator in StarFive JH7110 SoCs.
+
 endif
diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
index 47b323e61ee3..9de762c8a1c3 100644
--- a/drivers/rng/Makefile
+++ b/drivers/rng/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
 obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
 obj-$(CONFIG_RNG_ARM_RNDR) += arm_rndr.o
 obj-$(CONFIG_TPM_RNG) += tpm_rng.o
+obj-$(CONFIG_RNG_JH7110) += jh7110_rng.o
diff --git a/drivers/rng/jh7110_rng.c b/drivers/rng/jh7110_rng.c
new file mode 100644
index ..e71bf188f017
--- /dev/null
+++ b/drivers/rng/jh7110_rng.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * TRNG driver for the StarFive JH7110 SoC
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/* trng register offset */
+#define STARFIVE_CTRL  0x00
+#define STARFIVE_STAT  0x04
+#define STARFIVE_MODE  0x08
+#define STARFIVE_SMODE 0x0C
+#define STARFIVE_IE0x10
+#define STARFIVE_ISTAT 0x14
+#define STARFIVE_RAND0 0x20
+#define STARFIVE_RAND1 0x24
+#define STARFIVE_RAND2 0x28
+#define STARFIVE_RAND3 0x2C
+#define STARFIVE_RAND4 0x30
+#define STARFIVE_RAND5 0x34
+#define STARFIVE_RAND6 0x38
+#define STARFIVE_RAND7 0x3C
+#define STARFIVE_AUTO_RQSTS0x60
+#define STARFIVE_AUTO_AGE  0x64
+
+/* CTRL CMD */
+#define STARFIVE_CTRL_EXEC_NOP 0x0
+#define STARFIVE_CTRL_GENE_RANDNUM 0x1
+#define STARFIVE_CTRL_EXEC_RANDRESEED  0x2
+
+/* STAT */
+#define STARFIVE_STAT_NONCE_MODE   BIT(2)
+#define STARFIVE_STAT_R256 BIT(3)
+#define STARFIVE_STAT_MISSION_MODE BIT(8)
+#define STARFIVE_STAT_SEEDED   BIT(9)
+#define STARFIVE_STAT_LAST_RESEED(x)   ((x) << 16)
+#define STARFIVE_STAT_SRVC_RQSTBIT(27)
+#define STARFIVE_STAT_RAND_GENERATING  BIT(30)
+#define STARFIVE_STAT_RAND_SEEDING BIT(31)
+#define STARFIVE_STAT_RUNNING  (STARFIVE_STAT_RAND_GENERATING | \
+STARFIVE_STAT_RAND_SEEDING)
+
+/* MODE */
+#define STARFIVE_MODE_R256 BIT(3)
+
+/* SMODE */
+#define STARFIVE_SMODE_NONCE_MODE  BIT(2)
+#define STARFIVE_SMODE_MISSION_MODEBIT(8)
+#define STARFIVE_SMODE_MAX_REJECTS(x)  ((x) << 16)
+
+/* IE */
+#define STARFIVE_IE_RAND_RDY_ENBIT(0)
+#define STARFIVE_IE_SEED_DONE_EN   BIT(1)
+#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
+#define STARFIVE_IE_GLBL_ENBIT(31)
+
+#define STARFIVE_IE_ALL(STARFIVE_IE_GLBL_EN | \
+STARFIVE_IE_RAND_RDY_EN | \
+STARFIVE_IE_SEED_DONE_EN | \
+STARFIVE_IE_LFSR_LOCKUP_EN)
+
+/* ISTAT */
+#define STARFIVE_ISTAT_RAND_RDYBIT(0)
+#define STARFIVE_ISTAT_SEED_DONE   BIT(1)
+#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
+
+#define STARFIVE_RAND_LEN  sizeof(u32)
+
+enum mode {
+   PRNG_128BIT,
+   PRNG_256BIT,
+};
+
+struct starfive_trng_plat {
+   void *base;
+   struct clk *hclk;
+   struct clk *ahb;
+   struct reset_ctl *rst;
+   u32 mode;
+};
+
+static inline int starfive_trng_wait_idle(struct starfive_trng_plat *trng)
+{
+   u32 stat;
+
+   return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
+ !(stat & STARFIVE_STAT_RUNNING),
+ 10);
+}
+
+static inline void starfive_trng_irq_mask_clear(struct starfive_trng_plat 
*trng)
+{
+   /* clear register: ISTAT */
+   u32 data = readl(trng->base + STARFIVE_ISTAT);
+
+   writel(data, trng->base + STARFIVE_ISTAT);
+}
+
+static int starfive_trng_cmd(struct starfive_trng_plat *trng, u32 cmd)
+{
+   u32 stat, flg;
+   int ret;
+
+   switch

[PATCH 1/5] riscv: import read/write_relaxed functions

[Chanho Park]

This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
to use read/write[b|w|l|q]_relaxed functions.

Signed-off-by: Chanho Park 
---
 arch/riscv/include/asm/io.h | 45 +
 1 file changed, 45 insertions(+)

diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h
index b16e6dfa3760..4170877a1ae0 100644
--- a/arch/riscv/include/asm/io.h
+++ b/arch/riscv/include/asm/io.h
@@ -323,6 +323,51 @@ static inline void writesl(unsigned int *addr, const void 
*data, int longlen)
 #define insw_p(port, to, len)  insw(port, to, len)
 #define insl_p(port, to, len)  insl(port, to, len)
 
+/*
+ * Unordered I/O memory access primitives.  These are even more relaxed than
+ * the relaxed versions, as they don't even order accesses between successive
+ * operations to the I/O regions.
+ */
+#define readb_cpu(c)   ({ u8  __r = __raw_readb(c); __r; })
+#define readw_cpu(c)   ({ u16 __r = le16_to_cpu((__force 
__le16)__raw_readw(c)); __r; })
+#define readl_cpu(c)   ({ u32 __r = le32_to_cpu((__force 
__le32)__raw_readl(c)); __r; })
+
+#define writeb_cpu(v, c)   ((void)__raw_writeb((v), (c)))
+#define writew_cpu(v, c)   ((void)__raw_writew((__force 
u16)cpu_to_le16(v), (c)))
+#define writel_cpu(v, c)   ((void)__raw_writel((__force 
u32)cpu_to_le32(v), (c)))
+
+#ifdef CONFIG_64BIT
+#define readq_cpu(c)   ({ u64 __r = le64_to_cpu((__force 
__le64)__raw_readq(c)); __r; })
+#define writeq_cpu(v, c)   ((void)__raw_writeq((__force 
u64)cpu_to_le64(v), (c)))
+#endif
+
+/*
+ * Relaxed I/O memory access primitives. These follow the Device memory
+ * ordering rules but do not guarantee any ordering relative to Normal memory
+ * accesses.  These are defined to order the indicated access (either a read or
+ * write) with all other I/O memory accesses to the same peripheral. Since the
+ * platform specification defines that all I/O regions are strongly ordered on
+ * channel 0, no explicit fences are required to enforce this ordering.
+ */
+/* FIXME: These are now the same as asm-generic */
+#define __io_rbr() do {} while (0)
+#define __io_rar() do {} while (0)
+#define __io_rbw() do {} while (0)
+#define __io_raw() do {} while (0)
+
+#define readb_relaxed(c)   ({ u8  __v; __io_rbr(); __v = readb_cpu(c); 
__io_rar(); __v; })
+#define readw_relaxed(c)   ({ u16 __v; __io_rbr(); __v = readw_cpu(c); 
__io_rar(); __v; })
+#define readl_relaxed(c)   ({ u32 __v; __io_rbr(); __v = readl_cpu(c); 
__io_rar(); __v; })
+
+#define writeb_relaxed(v, c)   ({ __io_rbw(); writeb_cpu((v), (c)); 
__io_raw(); })
+#define writew_relaxed(v, c)   ({ __io_rbw(); writew_cpu((v), (c)); 
__io_raw(); })
+#define writel_relaxed(v, c)   ({ __io_rbw(); writel_cpu((v), (c)); 
__io_raw(); })
+
+#ifdef CONFIG_64BIT
+#define readq_relaxed(c)   ({ u64 __v; __io_rbr(); __v = readq_cpu(c); 
__io_rar(); __v; })
+#define writeq_relaxed(v, c)   ({ __io_rbw(); writeq_cpu((v), (c)); 
__io_raw(); })
+#endif
+
 #include 
 
 #endif /* __ASM_RISCV_IO_H */
-- 
2.39.2

[PATCH 5/5] configs: visionfive2: Enable JH7110 RNG driver

[Chanho Park]

Enables JH7110 RNG driver to visionfive2 board.

Signed-off-by: Chanho Park 
---
 configs/starfive_visionfive2_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index b21754feafce..b15e7d24db19 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -120,6 +120,8 @@ CONFIG_SPL_PINCTRL_STARFIVE=y
 CONFIG_SPL_PINCTRL_STARFIVE_JH7110=y
 CONFIG_PINCTRL_STARFIVE=y
 # CONFIG_RAM_SIFIVE is not set
+CONFIG_DM_RNG=y
+CONFIG_RNG_JH7110=y
 CONFIG_SYS_NS16550=y
 CONFIG_CADENCE_QSPI=y
 CONFIG_TIMER_EARLY=y
-- 
2.39.2

[PATCH 0/5] Add support for StarFive JH7110 TRNG driver

[Chanho Park]

This patchset adds to support StarFive JH7110 TRNG driver. Due to lack
of readl_relaxed API, the first patch tries to import the
APIs(read/write_relaxed) from Linux kernel's implementation. The second
patch adds the missing security clocks which are required by the trng
IP.

This IP can support 128-bit and 256-bit random number generation but
this patch makes 256-bit default mode for convenience.

Chanho Park (5):
  riscv: import read/write_relaxed functions
  clk: starfive: jh7110: Add security clocks
  rng: Add StarFive JH7110 RNG driver
  riscv: dts: jh7110: Add rng device tree node
  configs: visionfive2: Enable JH7110 RNG driver

 arch/riscv/dts/jh7110.dtsi |  10 +
 arch/riscv/include/asm/io.h|  45 
 configs/starfive_visionfive2_defconfig |   2 +
 drivers/clk/starfive/clk-jh7110.c  |  10 +
 drivers/rng/Kconfig|   6 +
 drivers/rng/Makefile   |   1 +
 drivers/rng/jh7110_rng.c   | 272 +
 7 files changed, 346 insertions(+)
 create mode 100644 drivers/rng/jh7110_rng.c

-- 
2.39.2

[PATCH 4/5] riscv: dts: jh7110: Add rng device tree node

[Chanho Park]

Adds jh7110 trng device tree node.

Signed-off-by: Chanho Park 
---
 arch/riscv/dts/jh7110.dtsi | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index ec237a46ffba..13c47f7caa36 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch/riscv/dts/jh7110.dtsi
@@ -627,6 +627,16 @@
status = "disabled";
};
 
+   rng: rng@1600c000 {
+   compatible = "starfive,jh7110-trng";
+   reg = <0x0 0x1600C000 0x0 0x4000>;
+   clocks = <&stgcrg JH7110_STGCLK_SEC_HCLK>,
+<&stgcrg JH7110_STGCLK_SEC_MISCAHB>;
+   clock-names = "hclk", "ahb";
+   resets = <&stgcrg JH7110_STGRST_SEC_TOP_HRESETN>;
+   interrupts = <30>;
+   };
+
aoncrg: clock-controller@1700 {
compatible = "starfive,jh7110-aoncrg";
reg = <0x0 0x1700 0x0 0x1>;
-- 
2.39.2

[PATCH 2/5] clk: starfive: jh7110: Add security clocks

[Chanho Park]

Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.

Signed-off-by: Chanho Park 
---
 drivers/clk/starfive/clk-jh7110.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/starfive/clk-jh7110.c 
b/drivers/clk/starfive/clk-jh7110.c
index 31aaf3340f94..a835541e48e9 100644
--- a/drivers/clk/starfive/clk-jh7110.c
+++ b/drivers/clk/starfive/clk-jh7110.c
@@ -539,6 +539,16 @@ static int jh7110_stgcrg_init(struct udevice *dev)
 "pcie1_tl", "stg_axiahb",
 OFFSET(JH7110_STGCLK_PCIE1_TL)));
 
+   /* Security clocks */
+   clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_HCLK),
+  starfive_clk_gate(priv->reg,
+"sec_ahb", "stg_axiahb",
+OFFSET(JH7110_STGCLK_SEC_HCLK)));
+   clk_dm(JH7110_STG_ID_TRANS(JH7110_STGCLK_SEC_MISCAHB),
+  starfive_clk_gate(priv->reg,
+"sec_misc_ahb", "stg_axiahb",
+OFFSET(JH7110_STGCLK_SEC_MISCAHB)));
+
return 0;
 }
 
-- 
2.39.2

RE: [RFC 1/1] rng: Provide a RNG based on the RISC-V Zkr ISA extension

[Chanho Park]

Hi,

> -Original Message-
> From: U-Boot  On Behalf Of Heinrich
> Schuchardt
> Sent: Sunday, October 29, 2023 8:26 AM
> To: Rick Chen ; Leo 
> Cc: Sughosh Ganu ; u-boot@lists.denx.de; Heinrich
> Schuchardt 
> Subject: [RFC 1/1] rng: Provide a RNG based on the RISC-V Zkr ISA
> extension
> 
> The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
> provides an interface to a physical entropy source.
> 
> A RNG driver based on the seed CSR is provided. It depends on
> mseccfg.sseed being set in the SBI firmware.
> 
> Signed-off-by: Heinrich Schuchardt 

This works fine on my qemu risv with your opensbi patch and KASLR has been
tested as well.
Feel free to add my reviewed/tested-by tag.

Reviewed-by: Chanho Park 
Tested-by: Chanho Park 

Best Regards,
Chanho Park

> ---
>  drivers/rng/Kconfig |  11 
>  drivers/rng/Makefile|   1 +
>  drivers/rng/riscv_zkr_rng.c | 102 
>  3 files changed, 114 insertions(+)
>  create mode 100644 drivers/rng/riscv_zkr_rng.c
> 
> diff --git a/drivers/rng/Kconfig b/drivers/rng/Kconfig
> index 994cc35b27..f8f1d91ed2 100644
> --- a/drivers/rng/Kconfig
> +++ b/drivers/rng/Kconfig
> @@ -48,6 +48,17 @@ config RNG_OPTEE
> accessible to normal world but reserved and used by the OP-TEE
> to avoid the weakness of a software PRNG.
> 
> +config RNG_RISCV_ZKR
> + bool "RISC-V Zkr random number generator"
> + depends on RISCV_SMODE
> + help
> +   This driver provides a Random Number Generator based on the
> +   Zkr RISC-V ISA extension which provides an interface to an
> +   NIST SP 800-90B or BSI AIS-31 compliant physical entropy source.
> +
> +   Using this driver will lead to an exception if the M-mode
> firmware
> +   has not set mseccfg.sseed=1.
> +
>  config RNG_STM32
>   bool "Enable random number generator for STM32"
>   depends on ARCH_STM32 || ARCH_STM32MP
> diff --git a/drivers/rng/Makefile b/drivers/rng/Makefile
> index 47b323e61e..a5d3ca4130 100644
> --- a/drivers/rng/Makefile
> +++ b/drivers/rng/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_RNG_MSM) += msm_rng.o
>  obj-$(CONFIG_RNG_NPCM) += npcm_rng.o
>  obj-$(CONFIG_RNG_OPTEE) += optee_rng.o
>  obj-$(CONFIG_RNG_STM32) += stm32_rng.o
> +obj-$(CONFIG_RNG_RISCV_ZKR) += riscv_zkr_rng.o
>  obj-$(CONFIG_RNG_ROCKCHIP) += rockchip_rng.o
>  obj-$(CONFIG_RNG_IPROC200) += iproc_rng200.o
>  obj-$(CONFIG_RNG_SMCCC_TRNG) += smccc_trng.o
> diff --git a/drivers/rng/riscv_zkr_rng.c b/drivers/rng/riscv_zkr_rng.c
> new file mode 100644
> index 00..f48ae35410
> --- /dev/null
> +++ b/drivers/rng/riscv_zkr_rng.c
> @@ -0,0 +1,102 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * The RISC-V Zkr extension provides CSR seed which provides access to a
> + * random number generator.
> + */
> +
> +#define LOG_CATEGORY UCLASS_RNG
> +
> +#include 
> +#include 
> +#include 
> +
> +#define DRIVER_NAME "riscv_zkr"
> +
> +enum opst {
> + /** @BIST: built in self test running */
> + BIST = 0b00,
> + /** @WAIT: sufficient amount of entropy is not yet available */
> + WAIT = 0b01,
> + /** @ES16: 16bits of entropy available */
> + ES16 = 0b10,
> + /** @DEAD: unrecoverable self-test error */
> + DEAD = 0b11,
> +};
> +
> +static unsigned long read_seed(void)
> +{
> + unsigned long ret;
> +
> + __asm__ __volatile__("csrrw %0, seed, x0" : "=r" (ret) : :
> "memory");
> +
> + return ret;
> +}
> +
> +static int riscv_zkr_read(struct udevice *dev, void *data, size_t len)
> +{
> + u8 *ptr = data;
> +
> + while (len) {
> + u32 val;
> +
> + val = read_seed();
> +
> + switch (val >> 30) {
> + case BIST:
> + continue;
> + case WAIT:
> + continue;
> + case ES16:
> + *ptr++ = val & 0xff;
> + if (--len) {
> + *ptr++ = val >> 8;
> + --len;
> + }
> + break;
> + case DEAD:
> + return -ENODEV;
> + }
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * riscv_zkr_probe() - check if the seed register is available
> + *
> + * If the SBI software has not set mseccfg.sseed=1 or the Zkr
> + * extension is not available this probe function will result
> + * in an exception. Currently we cannot recover from this.
> + *
&g

[PATCH] configs: visionfive2: enable bootstage configs

[Chanho Park]

Enable BOOTSTAGE configuration and its command for visionfive2 board.
The feature can be useful for analyzing the elapsed time between boot
stages.

TODO: define / reserve memory region for boot stage stash

StarFive # bootstage report
Timer summary in microseconds (10 records):
   MarkElapsed  Stage
  0  0  reset
  3,139,338  3,139,338  board_init_f
  3,176,753 37,415  board_init_r
  4,036,111859,358  eth_common_init
  4,101,599 65,488  eth_initialize
  4,105,799  4,200  main_loop
  4,145,207 39,408  usb_start
  5,440,963  1,295,756  cli_loop

Accumulated time:
10,093  dm_f
15,867  dm_r

Signed-off-by: Chanho Park 
---
 configs/starfive_visionfive2_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 6590727fe750..b21754feafce 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -31,6 +31,7 @@ CONFIG_RISCV_SMODE=y
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
 CONFIG_FIT=y
 CONFIG_DISTRO_DEFAULTS=y
+CONFIG_BOOTSTAGE=y
 CONFIG_QSPI_BOOT=y
 CONFIG_SD_BOOT=y
 CONFIG_OF_BOARD_SETUP=y
@@ -72,6 +73,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_USB=y
 CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_BOOTSTAGE=y
 CONFIG_OF_BOARD=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_NOWHERE=y
-- 
2.39.2

[PATCH] spl: add __noreturn attribute to spl_invoke_atf function

[Chanho Park]

spl_invoke_atf function will not be returned to SPL. Thus, we need to
set __noreturn function attribute to the function.

Signed-off-by: Chanho Park 
---
 common/spl/spl_atf.c | 8 
 include/spl.h| 2 +-
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/common/spl/spl_atf.c b/common/spl/spl_atf.c
index 2c10252834f6..3bdd013a35fe 100644
--- a/common/spl/spl_atf.c
+++ b/common/spl/spl_atf.c
@@ -187,10 +187,10 @@ static inline void raw_write_daif(unsigned int daif)
__asm__ __volatile__("msr DAIF, %x0\n\t" : : "r" (daif) : "memory");
 }
 
-typedef void (*atf_entry_t)(struct bl31_params *params, void *plat_params);
+typedef void __noreturn (*atf_entry_t)(struct bl31_params *params, void 
*plat_params);
 
-static void bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
-  uintptr_t bl33_entry, uintptr_t fdt_addr)
+static void __noreturn bl31_entry(uintptr_t bl31_entry, uintptr_t bl32_entry,
+ uintptr_t bl33_entry, uintptr_t fdt_addr)
 {
atf_entry_t  atf_entry = (atf_entry_t)bl31_entry;
void *bl31_params;
@@ -251,7 +251,7 @@ uintptr_t spl_fit_images_get_entry(void *blob, int node)
return val;
 }
 
-void spl_invoke_atf(struct spl_image_info *spl_image)
+void __noreturn spl_invoke_atf(struct spl_image_info *spl_image)
 {
uintptr_t  bl32_entry = 0;
uintptr_t  bl33_entry = CONFIG_TEXT_BASE;
diff --git a/include/spl.h b/include/spl.h
index 93e906431e7d..01ed8f58afd8 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -770,7 +770,7 @@ int spl_ymodem_load_image(struct spl_image_info *spl_image,
 /**
  * spl_invoke_atf - boot using an ARM trusted firmware image
  */
-void spl_invoke_atf(struct spl_image_info *spl_image);
+void __noreturn spl_invoke_atf(struct spl_image_info *spl_image);
 
 /**
  * bl2_plat_get_bl31_params() - return params for bl31.
-- 
2.39.2

RE: [PATCH v3 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

Hi,

> -Original Message-
> From: Heinrich Schuchardt 
> Sent: Thursday, September 7, 2023 2:27 AM
> To: Chanho Park ; Simon Glass
> 
> Cc: u-boot@lists.denx.de; Rick Chen ; Leo
> 
> Subject: Re: [PATCH v3 3/3] timer: riscv_aclint_timer: add
> timer_get_boot_us for BOOTSTAGE
> 
> On 06.09.23 07:18, Chanho Park wrote:
> > timer_get_boot_us function is required to record the boot stages as
> > us-based timestamp.
> > To get a micro-second time from a timer tick, this converts the
> > formula like below to avoid zero result of (tick / rate) part.
> >
> > From: time(us) = (tick / rate) * 1000
Still typo 1000 -> 100
> 
> Where is the old implementation that you refer to?

I referred it from timer_get_boot_us function of lib/time.c

lib/time.c
55 else if (timer_rate > 100)
56 return lldiv(count, timer_rate / 100);
57 else
58 return (unsigned long long)count * 100 / timer_rate;

> 
> > To  : time(us) = (tick * 1000) / (rate / 1000)
> >
> > Signed-off-by: Chanho Park 
> > ---
> >   drivers/timer/riscv_aclint_timer.c | 23 +++
> >   1 file changed, 23 insertions(+)
> >
> > diff --git a/drivers/timer/riscv_aclint_timer.c
> b/drivers/timer/riscv_aclint_timer.c
> > index e29d527c8d77..73fb87912851 100644
> > --- a/drivers/timer/riscv_aclint_timer.c
> > +++ b/drivers/timer/riscv_aclint_timer.c
> > @@ -6,6 +6,7 @@
> >
> >   #include 
> >   #include 
> > +#include 
> >   #include 
> >   #include 
> >   #include 
> > @@ -44,6 +45,28 @@ u64 notrace timer_early_get_count(void)
> >   }
> >   #endif
> >
> > +#if CONFIG_IS_ENABLED(RISCV_MMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
> > +ulong timer_get_boot_us(void)
> > +{
> > +   int ret;
> > +   u64 ticks = 0;
> > +   u32 rate;
> > +
> > +   ret = dm_timer_init();
> > +   if (!ret) {
> > +   rate = timer_get_rate(gd->timer);
> > +   timer_get_count(gd->timer, &ticks);
> > +   } else {
> > +   rate = RISCV_MMODE_TIMER_FREQ;
> > +   ticks = readq((void __iomem
> *)MTIME_REG(RISCV_MMODE_TIMERBASE,
> > +   RISCV_MMODE_TIMEROFF));
> > +   }
> > +
> > +   /* Below is converted from time(us) = (tick / rate) * 1000 */
> > +   return lldiv(ticks * 1000, (rate / 1000));
> 
> I found similar code in drivers/timer/cadence-ttc.c and
> drivers/timer/omap-timer.c with
> 
>  us = (ticks * 1000) / rate;
>  return us.
> 
> Either their code or yours must be wrong.
> 
> What I am missing in include/timer.h is a documentation that defines if
> timer_dev_priv.clock_rate and timer_get_rate() yield the frequency in Hz
> or kHz.

'rate' seems to be Hz not kHz. So, I think they need to be corrected.

> 
> Once we have added the missing information in the include we can start
> reviewing this patch.
> 
> I really dislike that we have code per architecture and don't update and
> use a implementation in lib/time.c (where we also have an
> implementation) or drivers/timer/timer-uclass.c. Can't we have a single
> implementation which is driver model based and eliminate all others?

Actually, I tried to use lib/time.c's implementation or make a generic function 
in timer-uclass.c as you mentioned.
However, there are different implementations in cadence-ttc.c, 
rockchip_timer.c, tegra-timer.c, omap-timer.c and tsc_timer.c.
The basic codes seems to be almost identical if we can get a DM timer 
successfully but fallback codes look different.
If timer_get_boot_us can be implement in the timer-uclass.c, we still need 
per-driver callback function for supporting these different fallback codes.

Best Regards,
Chanho Park

RE: [PATCH 2/2] riscv: dts: starfive: generate u-boot-spl.bin.normal.out

[Chanho Park]

> -Original Message-
> From: Heinrich Schuchardt 
> Sent: Wednesday, September 6, 2023 7:08 PM
> To: Rick Chen ; Leo ; Yanhong
> Wang 
> Cc: Simon Glass ; Marc Kleine-Budde
;
> Chanho Park ; u-boot@lists.denx.de; Heinrich
> Schuchardt 
> Subject: [PATCH 2/2] riscv: dts: starfive: generate u-boot-
> spl.bin.normal.out
> 
> The StarFive VisionFive 2 board cannot load spl/u-boot-spl.bin but needs a
> prefixed header. We have referring to a vendor tool (spl_tool) for this
> task. 'mkimage -T sfspl' can generate the prefixed file.
> 
> Use binman to invoke mkimage for the generation of file
> spl/u-boot-spl.bin.normal.out.
> 
> Update the documentation.
> 
> Signed-off-by: Heinrich Schuchardt 

Tested-by: Chanho Park 

Best Regards,
Chanho Park

> ---
>  .../dts/jh7110-starfive-visionfive-2-u-boot.dtsi   | 10 ++
>  doc/board/starfive/visionfive2.rst | 14 ++
>  2 files changed, 12 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> index 13f69da31e..defe2b605f 100644
> --- a/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> +++ b/arch/riscv/dts/jh7110-starfive-visionfive-2-u-boot.dtsi
> @@ -103,4 +103,14 @@
>   };
>   };
>   };
> + u-boot-spl {
> + filename = "spl/u-boot-spl.bin.normal.out";
> +
> + mkimage {
> + args = "-T sfspl";
> + blob {
> + filename = "spl/u-boot-spl.bin";
> + };
> + };
> + };
>  };
> diff --git a/doc/board/starfive/visionfive2.rst
> b/doc/board/starfive/visionfive2.rst
> index 941899a0a4..f5575ab68b 100644
> --- a/doc/board/starfive/visionfive2.rst
> +++ b/doc/board/starfive/visionfive2.rst
> @@ -65,18 +65,8 @@ Now build the U-Boot SPL and U-Boot proper
>   make starfive_visionfive2_defconfig
>   make
> OPENSBI=$(opensbi_dir)/opensbi/build/platform/generic/firmware/fw_dynamic.
> bin
> 
> -This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
> -
> -u-boot-spl.bin cannot be used directly on StarFive VisionFive2,we need
> -to convert the u-boot-spl.bin to u-boot-spl.bin.normal.out with
> -the below command:
> -
> - ./spl_tool -c -f $(Uboot_PATH)/spl/u-boot-spl.bin
> -
> -More detailed description of spl_tool,please refer spl_tool documenation.
> -(Note: spl_tool git repo is at
> https://protect2.fireeye.com/v1/url?k=501ce742-3197f262-501d6c0d-
> 74fe485fb347-9a3f03c95f77a084&q=1&e=490deaec-ec5a-4b0d-a03c-
> def31f4b19ad&u=https%3A%2F%2Fgithub.com%2Fstarfive-
> tech%2FTools%2Ftree%2Fmaster%2Fspl_tool)
> -
> -This will generate u-boot-spl.bin.normal.out file.
> +This will generate the U-Boot SPL image (spl/u-boot-spl.bin.normal.out)
> as well
> +as the FIT image (u-boot.itb) with OpenSBI and U-Boot.
> 
>  Flashing
>  
> --
> 2.40.1

RE: [PATCH 1/2] tools: mkimage: Add StarFive SPL image support

[Chanho Park]

Hi,

> -Original Message-
> From: Heinrich Schuchardt 
> Sent: Wednesday, September 6, 2023 7:08 PM
> To: Rick Chen ; Leo ; Yanhong
> Wang 
> Cc: Simon Glass ; Marc Kleine-Budde
;
> Chanho Park ; u-boot@lists.denx.de; Heinrich
> Schuchardt 
> Subject: [PATCH 1/2] tools: mkimage: Add StarFive SPL image support
> 
> The StarFive JH7110 base boards require a header to be prefixed to the SPL
> binary image. This has previously done with a vendor tool 'spl_tool'
> published under a GPL-2-or-later license. Integrate this capability into
> mkimage.
> 
> Signed-off-by: Heinrich Schuchardt 
> ---
>  boot/image.c|   1 +
>  include/image.h |   1 +
>  tools/Makefile  |   1 +
>  tools/sfspl.c   | 174 
>  4 files changed, 177 insertions(+)
>  create mode 100644 tools/sfspl.c
> 
> diff --git a/boot/image.c b/boot/image.c
> index 5c4f9b807d..3a99d2e897 100644
> --- a/boot/image.c
> +++ b/boot/image.c
> @@ -182,6 +182,7 @@ static const table_entry_t uimage_type[] = {
>   {   IH_TYPE_SUNXI_TOC0, "sunxi_toc0",  "Allwinner TOC0 Boot
> Image" },
>   {   IH_TYPE_FDT_LEGACY, "fdt_legacy", "legacy Image with Flat
> Device Tree ", },
>   {   IH_TYPE_RENESAS_SPKG, "spkgimage", "Renesas SPKG Image" },
> + {   IH_TYPE_STARFIVE_SPL, "sfspl", "StarFive SPL Image" },
>   {   -1, "",   "",   },
>  };
> 
> diff --git a/include/image.h b/include/image.h
> index 01a6787d21..5f85bf84a2 100644
> --- a/include/image.h
> +++ b/include/image.h
> @@ -231,6 +231,7 @@ enum image_type_t {
>   IH_TYPE_SUNXI_TOC0, /* Allwinner TOC0 Boot Image */
>   IH_TYPE_FDT_LEGACY, /* Binary Flat Device Tree Blob in a
> Legacy Image */
>   IH_TYPE_RENESAS_SPKG,   /* Renesas SPKG image */
> + IH_TYPE_STARFIVE_SPL,   /* StarFive SPL image */
> 
>   IH_TYPE_COUNT,  /* Number of image types */
>  };
> diff --git a/tools/Makefile b/tools/Makefile
> index 3d0c4b0dd6..1aa1e36137 100644
> --- a/tools/Makefile
> +++ b/tools/Makefile
> @@ -123,6 +123,7 @@ dumpimage-mkimage-objs := aisimage.o \
>   pblimage.o \
>   pbl_crc32.o \
>   renesas_spkgimage.o \
> + sfspl.o \
>   vybridimage.o \
>   stm32image.o \
>   $(ROCKCHIP_OBS) \
> diff --git a/tools/sfspl.c b/tools/sfspl.c
> new file mode 100644
> index 00..428542d885
> --- /dev/null
> +++ b/tools/sfspl.c
> @@ -0,0 +1,174 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright Heinrich Schuchardt 
> + *
> + * The StarFive JH710 requires to prepend a header to u-boot-spl.bin
> describing

Nit: JH7110 or JH7100? If you'd like to indicate both, JH71x0?

Tested-by: Chanho Park 

Best Regards,
Chanho Park

> + * the payload length and CRC32.
> + *
> + * This module implements support in mkimage and dumpimage for this file
> format.
> + *
> + * StarFive's spl_tool available under GPL-2.0-and-later at
> + * https://protect2.fireeye.com/v1/url?k=d38f2235-b204371a-d38ea97a-
> 74fe485cbfe7-db3f73ac8e80b9ed&q=1&e=f143c01a-a53d-425d-a99e-
> dab4877e8097&u=https%3A%2F%2Fgithub.com%2Fstarfive-tech%2FTools implements
> writing the same file
> + * format and served as a reference.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +#include "imagetool.h"
> +
> +#define DEFAULT_VERSION 0x01010101
> +#define DEFAULT_BACKUP 0x20U
> +#define DEFAULT_OFFSET 0x240
> +
> +/**
> + * struct spl_hdr - header for SPL on JH7110
> + *
> + * All fields are low-endian.
> + */
> +struct spl_hdr {
> + /** @offset:offset to SPL header (0x240) */
> + unsigned int offset;
> + /** @bkp_offs:  address of backup SPL, defaults to
> DEFAULT_BACKUP */
> + unsigned int bkp_offs;
> + /** @zero1: set to zero */
> + unsigned int zero1[159];
> + /** @version:   header version, defaults to DEFAULT_VERSION */
> + unsigned int version;
> + /** @file_size: file size */
> + unsigned int file_size;
> + /** @hdr_size:  size of the file header (0x400) */
> + unsigned int hdr_size;
> + /** @crc32: CRC32 */
> + unsigned int crc32;
> + /** @zero2: set to zero */
> + unsigned int zero2[91];
> +};
> +
> +static int sfspl_check_params(struct image_tool_params *params)
> +{
> + /* Only the RIS

[PATCH v3 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.

From: time(us) = (tick / rate) * 1000
To  : time(us) = (tick * 1000) / (rate / 1000)

Signed-off-by: Chanho Park 
---
 drivers/timer/riscv_aclint_timer.c | 23 +++
 1 file changed, 23 insertions(+)

diff --git a/drivers/timer/riscv_aclint_timer.c 
b/drivers/timer/riscv_aclint_timer.c
index e29d527c8d77..73fb87912851 100644
--- a/drivers/timer/riscv_aclint_timer.c
+++ b/drivers/timer/riscv_aclint_timer.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -44,6 +45,28 @@ u64 notrace timer_early_get_count(void)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+   int ret;
+   u64 ticks = 0;
+   u32 rate;
+
+   ret = dm_timer_init();
+   if (!ret) {
+   rate = timer_get_rate(gd->timer);
+   timer_get_count(gd->timer, &ticks);
+   } else {
+   rate = RISCV_MMODE_TIMER_FREQ;
+   ticks = readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
+   RISCV_MMODE_TIMEROFF));
+   }
+
+   /* Below is converted from time(us) = (tick / rate) * 1000 */
+   return lldiv(ticks * 1000, (rate / 1000));
+}
+#endif
+
 static const struct timer_ops riscv_aclint_timer_ops = {
.get_count = riscv_aclint_timer_get_count,
 };
-- 
2.39.2

[PATCH v3 2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

timer_get_boot_us function is required to record the boot stages as
us-based timestamp.
To get a micro-second time from a timer tick, this converts the
formula like below to avoid zero result of (tick / rate) part.

From: time(us) = (tick / rate) * 1000
To  : time(us) = (tick * 1000) / (rate / 1000)

Signed-off-by: Chanho Park 
---
 drivers/timer/riscv_timer.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 28a6a6870b81..169c03dcb5c1 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -11,6 +11,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -51,6 +52,27 @@ u64 notrace timer_early_get_count(void)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+   int ret;
+   u64 ticks = 0;
+   u32 rate;
+
+   ret = dm_timer_init();
+   if (!ret) {
+   rate = timer_get_rate(gd->timer);
+   timer_get_count(gd->timer, &ticks);
+   } else {
+   rate = RISCV_SMODE_TIMER_FREQ;
+   ticks = riscv_timer_get_count(NULL);
+   }
+
+   /* Below is converted from time(us) = (tick / rate) * 1000 */
+   return lldiv(ticks * 1000, (rate / 1000));
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-- 
2.39.2

[PATCH v3 1/3] riscv: bootstage: correct bootstage_report guard

[Chanho Park]

Below warning can be occurred when CONFIG_BOOTSTAGE and
!CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED
for SPL build.

arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of
function 'bootstage_report'
   46 | bootstage_report();
  | ^~~~
  | bootstage_error

Signed-off-by: Chanho Park 
Reviewed-by: Leo Yu-Chi Liang 
---
 arch/riscv/lib/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 276677a5e2f9..cc30efc90498 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -42,7 +42,7 @@ static void announce_and_cleanup(int fake)
 #ifdef CONFIG_BOOTSTAGE_FDT
bootstage_fdt_add_report();
 #endif
-#ifdef CONFIG_BOOTSTAGE_REPORT
+#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT)
bootstage_report();
 #endif
 
-- 
2.39.2

[PATCH v3 0/3] bootstage support for risc-v

[Chanho Park]

This adds to support bootstage for risc-v. timer_get_boot_us function
is required to record each boot stages with microsecond timestamp.

Changes from v2:
- Add a Leo's RB tag of 1/3 patch
- Add a description of the calculation formula
- Correct the divisor value typo of 3/3 patch

Chanho Park (3):
  riscv: bootstage: correct bootstage_report guard
  riscv: timer: add timer_get_boot_us for BOOTSTAGE
  timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

 arch/riscv/lib/bootm.c |  2 +-
 drivers/timer/riscv_aclint_timer.c | 23 +++
 drivers/timer/riscv_timer.c| 22 ++
 3 files changed, 46 insertions(+), 1 deletion(-)

-- 
2.39.2

RE: [PATCH v2 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

Hi Simon,

> -Original Message-
> From: Simon Glass 
> Sent: Tuesday, September 5, 2023 1:49 AM
> To: Chanho Park 
> Cc: Rick Chen ; Leo ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH v2 3/3] timer: riscv_aclint_timer: add
> timer_get_boot_us for BOOTSTAGE
> 
> Hi Chanho,
> 
> On Mon, 28 Aug 2023 at 03:50, Chanho Park 
> wrote:
> >
> > timer_get_boot_us function is required to record the boot stages as
> > us-based timestamp.
> >
> > Signed-off-by: Chanho Park 
> > ---
> >  drivers/timer/riscv_aclint_timer.c | 22 ++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/drivers/timer/riscv_aclint_timer.c
> b/drivers/timer/riscv_aclint_timer.c
> > index e29d527c8d77..8b67745bb4a2 100644
> > --- a/drivers/timer/riscv_aclint_timer.c
> > +++ b/drivers/timer/riscv_aclint_timer.c
> > @@ -6,6 +6,7 @@
> >
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -44,6 +45,27 @@ u64 notrace timer_early_get_count(void)
> >  }
> >  #endif
> >
> > +#if CONFIG_IS_ENABLED(RISCV_MMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
> 
> Just a nit...you should not need this #if, since if the function is
> not used it will be stripped from the image by the linker.

Thank you for the suggestion.
Without these guards, compile error can be occurred due to multiple 
timer_get_boot_us definitions.
For risc-v, there are two timers for S-mode and M-mode, respectively.
So, I put them to avoid below build errors.

riscv64-unknown-linux-gnu-ld.bfd: drivers/timer/riscv_aclint_timer.o: in 
function `timer_get_boot_us':

/data/risc-v/qemu/u-boot/drivers/timer/riscv_aclint_timer.c:49: multiple 
definition of `timer_get_boot_us'; 
drivers/timer/riscv_timer.o:/data/risc-v/qemu/u-boot/drivers/timer/riscv_timer.c:55:
 first defined here

make[1]: *** [scripts/Makefile.spl:527: spl/u-boot-spl] Error 1

Best Regards,
Chanho Park

RE: [PATCH v2 0/2] risc-v: implement DBCN based debug console

[Chanho Park]

Hi,

> -Original Message-
> From: Heinrich Schuchardt 
> Sent: Monday, September 4, 2023 8:24 PM
> To: Rick Chen ; Leo 
> Cc: Bin Meng ; Anup Patel ;
> Chanho Park ; u-boot@lists.denx.de; Heinrich
> Schuchardt 
> Subject: [PATCH v2 0/2] risc-v: implement DBCN based debug console
> 
> Currently we only offer an SBI based debug UART for SBI v0.1.
> With OpenSBI 1.3 the Debug Console Extension (DBCN) has become available.
> This allows us to implement a debug UART in a device independent manor.
> 
> v2:
>   In the driver check that we are in S-mode.

Thanks for the update. I've tested both patches on my VisionFive2 board.

Reviewed-by: Chanho Park 
Tested-by: Chanho Park 

Best Regards,
Chanho Park

RE: [PATCH 2/2] risc-v: implement DBCN based debug console

[Chanho Park]

Hi,

> -Original Message-
> From: U-Boot  On Behalf Of Heinrich
> Schuchardt
> Sent: Saturday, August 19, 2023 10:13 PM
> To: Rick Chen ; Leo 
> Cc: Bin Meng ; Anup Patel ;
> u-boot@lists.denx.de; Heinrich Schuchardt
> 
> Subject: [PATCH 2/2] risc-v: implement DBCN based debug console
> 
> Use the DBCN SBI extension to implement a debug console.
> Make it the default for S-mode RISC-V.
> 
> Signed-off-by: Heinrich Schuchardt 
> ---
>  drivers/serial/Kconfig  |  3 ++-
>  drivers/serial/serial_sbi.c | 19 +++
>  2 files changed, 21 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index
> a1e089962a..8421c5c047 100644
> --- a/drivers/serial/Kconfig
> +++ b/drivers/serial/Kconfig
> @@ -218,6 +218,7 @@ config DEBUG_UART
>  choice
>   prompt "Select which UART will provide the debug UART"
>   depends on DEBUG_UART
> + default DEBUG_SBI_CONSOLE if RISCV_SMODE
>   default DEBUG_UART_NS16550
> 
>  config DEBUG_UART_ALTERA_JTAGUART
> @@ -289,7 +290,7 @@ config DEBUG_EFI_CONSOLE
> 
>  config DEBUG_SBI_CONSOLE
>   bool "SBI"
> - depends on SBI_V01
> + depends on RISCV_SMODE
>   help
> Select this to enable a debug console which calls back to SBI to
> output to the console. This can be useful for early debugging of
> diff --git a/drivers/serial/serial_sbi.c b/drivers/serial/serial_sbi.c
> index b9f35ed36e..093c7309d3 100644
> --- a/drivers/serial/serial_sbi.c
> +++ b/drivers/serial/serial_sbi.c
> @@ -3,6 +3,8 @@
>  #include 
>  #include 
> 
> +#ifdef CONFIG_SBI_V01
> +
>  static inline void _debug_uart_init(void)  {  } @@ -13,4 +15,21 @@ static
> inline void _debug_uart_putc(int c)
>   sbi_console_putchar(c);
>  }
> 
> +#else
> +
> +static int sbi_dbcn_available;
> +
> +static inline void _debug_uart_init(void) {
> + sbi_dbcn_available = sbi_probe_extension(SBI_EXT_DBCN);
> +}
> +
> +static inline void _debug_uart_putc(int ch) {
> + if (sbi_dbcn_available)
> + sbi_dbcn_write_byte(ch);
> +}
> +
> +#endif
> +
>  DEBUG_UART_FUNCS
> --
> 2.40.1

I've got below error when I tried to build it with VisionFive2 board
configuration(starfive_visionfive2_defconfig).
To test this patch, I enabled CONFIG_DEBUG_SBI_CONSOLE. Seems like spl also
includes the driver when DEBUG_SBI_CONSOLE is enabled.
Do I need to do any more configurations to test this?

LD  spl/u-boot-spl
riscv64-unknown-linux-gnu-ld.bfd: drivers/serial/serial_sbi.o: in function
`_debug_uart_putc':
/data/risc-v/vf2/mainline/u-boot/drivers/serial/serial_sbi.c:30: undefined
reference to `sbi_dbcn_write_byte'
riscv64-unknown-linux-gnu-ld.bfd:
/data/risc-v/vf2/mainline/u-boot/drivers/serial/serial_sbi.c:30: undefined
reference to `sbi_dbcn_write_byte'
riscv64-unknown-linux-gnu-ld.bfd: drivers/serial/serial_sbi.o: in function
`_debug_uart_init':
/data/risc-v/vf2/mainline/u-boot/drivers/serial/serial_sbi.c:24: undefined
reference to `sbi_probe_extension'
make[2]: *** [/data/risc-v/vf2/mainline/u-boot/scripts/Makefile.spl:527:
spl/u-boot-spl] Error 1

Best Regards,
Chanho Park

RE: [PATCH v2 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

Hi,

> -Original Message-
> From: Leo Liang 
> Sent: Monday, September 4, 2023 4:02 PM
> To: Chanho Park 
> Cc: Rick Chen ; Simon Glass ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH v2 3/3] timer: riscv_aclint_timer: add
> timer_get_boot_us for BOOTSTAGE
> 
> Hi Chanho,
> 
> On Mon, Aug 28, 2023 at 06:49:38PM +0900, Chanho Park wrote:
> > timer_get_boot_us function is required to record the boot stages as
> > us-based timestamp.
> >
> > Signed-off-by: Chanho Park 
> > ---
> >  drivers/timer/riscv_aclint_timer.c | 22 ++
> >  1 file changed, 22 insertions(+)
> >
> > diff --git a/drivers/timer/riscv_aclint_timer.c
> > b/drivers/timer/riscv_aclint_timer.c
> > index e29d527c8d77..8b67745bb4a2 100644
> > --- a/drivers/timer/riscv_aclint_timer.c
> > +++ b/drivers/timer/riscv_aclint_timer.c
> > @@ -6,6 +6,7 @@
> >
> >  #include 
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -44,6 +45,27 @@ u64 notrace timer_early_get_count(void)  }  #endif
> >
> > +#if CONFIG_IS_ENABLED(RISCV_MMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
> > +ulong timer_get_boot_us(void) {
> > +   int ret;
> > +   u64 ticks = 0;
> > +   u32 rate;
> > +
> > +   ret = dm_timer_init();
> > +   if (!ret) {
> > +   rate = timer_get_rate(gd->timer);
> > +   timer_get_count(gd->timer, &ticks);
> > +   } else {
> > +   rate = RISCV_MMODE_TIMER_FREQ;
> > +   ticks = readq((void __iomem
> *)MTIME_REG(RISCV_MMODE_TIMERBASE,
> > +
RISCV_MMODE_TIMEROFF));
> > +   }
> > +
> > +   return lldiv(ticks * 1001, (rate / 1000));
> 
> Why is this dividend 1001 ?

It's a typo. I'll correct when I send v2.

Best Regards,
Chanho Park

RE: [PATCH v2 2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

Hi,

> -Original Message-
> From: Leo Liang 
> Sent: Monday, September 4, 2023 4:01 PM
> To: Chanho Park 
> Cc: Rick Chen ; Simon Glass ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH v2 2/3] riscv: timer: add timer_get_boot_us for
> BOOTSTAGE
> 
> Hi Chanho,
> 
> On Mon, Aug 28, 2023 at 06:49:37PM +0900, Chanho Park wrote:
> > timer_get_boot_us function is required to record the boot stages as
> > us-based timestamp.
> >
> > Signed-off-by: Chanho Park 
> > ---
> >  drivers/timer/riscv_timer.c | 21 +
> >  1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
> > index 3627ed79b819..6cb589fcdc45 100644
> > --- a/drivers/timer/riscv_timer.c
> > +++ b/drivers/timer/riscv_timer.c
> > @@ -11,6 +11,7 @@
> >   */
> >
> >  #include 
> > +#include 
> >  #include 
> >  #include 
> >  #include 
> > @@ -50,6 +51,26 @@ u64 notrace timer_early_get_count(void)  }  #endif
> >
> > +#if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
> > +ulong timer_get_boot_us(void) {
> > +   int ret;
> > +   u64 ticks = 0;
> > +   u32 rate;
> > +
> > +   ret = dm_timer_init();
> > +   if (!ret) {
> > +   rate = timer_get_rate(gd->timer);
> > +   timer_get_count(gd->timer, &ticks);
> > +   } else {
> > +   rate = RISCV_SMODE_TIMER_FREQ;
> > +   ticks = riscv_timer_get_count(NULL);
> > +   }
> > +
> > +   return lldiv(ticks * 1000, (rate / 1000));
> 
> Could you elaborate a little how this formula is derived?

Sure. Below is the original formula. To avoid zero of (tick/rate), I split
the calculation to ticks and rate, respectively.

Time(us) = (ticks / rate) * 100
  Or (ticks * 100) / rate
  Or tick / (rate / 1000)

Best Regards,
Chanho Park

[PATCH v2] fpga: define dummy fpga_load function for debug build

[Chanho Park]

This fixes below build error when CC_OPTIMIZE_FOR_DEBUG is enabled and
CONFIG_FPGA or CONFIG_SPL_FPGA are not enabled.
When CC_OPTIMIZE_FOR_DEBUG is enabled, unused code will not be optimized
out. Hence, fpga_load function must have a dummy implementation to avoid
the build error.

../common/spl/spl_fit.c:591: undefined reference to `fpga_load'
collect2: error: ld returned 1 exit status

Signed-off-by: Chanho Park 
---
Change from v1:
- Rewrite the commit message to include a CONFIG_FPGA

 include/fpga.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/fpga.h b/include/fpga.h
index ed688cc0fa3b..44f2755a3f10 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -60,8 +60,16 @@ int fpga_add(fpga_type devtype, void *desc);
 int fpga_count(void);
 const fpga_desc *const fpga_get_desc(int devnum);
 int fpga_is_partial_data(int devnum, size_t img_len);
+#if CONFIG_IS_ENABLED(FPGA)
 int fpga_load(int devnum, const void *buf, size_t bsize,
  bitstream_type bstype, int flags);
+#else
+static inline int fpga_load(int devnum, const void *buf, size_t bsize,
+ bitstream_type bstype, int flags)
+{
+   return FPGA_FAIL;
+}
+#endif
 int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
 int fpga_loads(int devnum, const void *buf, size_t size,
-- 
2.39.2

RE: [PATCH] fpga: define dummy fpga_load function for debug build

[Chanho Park]

> On 8/16/23 08:54, Chanho Park wrote:
> > This fixes below build error when CC_OPTIMIZE_FOR_DEBUG is enabled and
> > CONFIG_SPL_FPGA is not enabled.
> 
> I would rewrite this because the connection to SPL_FPGA is just one part
> of it.
> It is also taken when CONFIG_FPGA is not enabled.

Sure. Will you rewrite while you pick this patch in your tree or do you want me 
to post v2 patch?

Best Regards,
Chanho Park

RE: [PATCH v2] spl: bootstage: move bootstage_stash before jumping to image

[Chanho Park]

Hi Simon,

> -Original Message-
> From: Simon Glass 
> Sent: Wednesday, August 30, 2023 1:38 AM
> To: Chanho Park 
> Cc: Nikhil M Jain ; Marek Vasut ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH v2] spl: bootstage: move bootstage_stash before
> jumping to image
> 
> Hi Chanho,
> 
> On Mon, 28 Aug 2023 at 22:28, Chanho Park 
> wrote:
> >
> > Regarding IH_OS_OPENSBI, IH_OS_LINUX and IH_OS_TEE, there is no chance
> > to stash bootstage record because they do not return to SPL after
> > jumping to the image.
> > Hence, this patch separates the final stage bootstage code into
> > spl_bootstage_finish and call the function before jumping to the image.
> >
> > Signed-off-by: Chanho Park 
> > ---
> > Changes from v1
> > - Separate the final stage bootstage code into spl_bootstage_finish.
> > - As Simon suggests, call the function before jumping to the image.
> 
> I think you misunderstood me here. I mean, you cannot jump off somewhere
> in your board code. You must change it so it returns correctly, and the
> jump happens from spl.c's board_init_r() function.
> The way it works is you set up the spl_image structure, then it SPL jumps
> to it at the end of the functions.

I feel like I'm still not clear on what you mean. Sorry.

switch (spl_image.os) {
case IH_OS_U_BOOT:
case IH_OS_ARM_TRUSTED_FIRMWARE:
case IH_OS_TEE:
case IH_OS_OPENSBI:
case IH_OS_LINUX:
}

Regarding ATF/TEE/OPENSBI and Linux, they need different number of arguments 
and formats to jump to the image, respectively.
I think that's why they can't go to the final stage and can't use 
jump_to_image_no_args.

Do you want to move jump codes at the end of the board_init_r function?
The easiest way is that we just move the whole switch statements to the final 
stage of the function.
Otherwise, the arguments can be prepared from switch statement and make 
jump_to_image function to support variable length of arguments.
(Or we can put switch statement there to support various jump of the image)

Can you elaborate a bit more?

Best Regards,
Chanho Park

[PATCH v2] spl: bootstage: move bootstage_stash before jumping to image

[Chanho Park]

Regarding IH_OS_OPENSBI, IH_OS_LINUX and IH_OS_TEE, there is no chance
to stash bootstage record because they do not return to SPL after
jumping to the image.
Hence, this patch separates the final stage bootstage code into
spl_bootstage_finish and call the function before jumping to the image.

Signed-off-by: Chanho Park 
---
Changes from v1
- Separate the final stage bootstage code into spl_bootstage_finish.
- As Simon suggests, call the function before jumping to the image.

 common/spl/spl.c | 24 +---
 1 file changed, 17 insertions(+), 7 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 0062f3f45d9a..eaf2f076ddd1 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -738,6 +738,19 @@ void board_init_f(ulong dummy)
 }
 #endif
 
+static void spl_bootstage_finish(void)
+{
+   int ret;
+
+   bootstage_mark_name(get_bootstage_id(false), "end phase");
+#ifdef CONFIG_BOOTSTAGE_STASH
+   ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
+ CONFIG_BOOTSTAGE_STASH_SIZE);
+   if (ret)
+   debug("Failed to stash bootstage: err=%d\n", ret);
+#endif
+}
+
 void board_init_r(gd_t *dummy1, ulong dummy2)
 {
u32 spl_boot_list[] = {
@@ -865,12 +878,14 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
case IH_OS_TEE:
debug("Jumping to U-Boot via OP-TEE\n");
spl_board_prepare_for_optee(spl_image.fdt_addr);
+   spl_bootstage_finish();
jump_to_image_optee(&spl_image);
break;
 #endif
 #if CONFIG_IS_ENABLED(OPENSBI)
case IH_OS_OPENSBI:
debug("Jumping to U-Boot via RISC-V OpenSBI\n");
+   spl_bootstage_finish();
spl_invoke_opensbi(&spl_image);
break;
 #endif
@@ -881,6 +896,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
spl_fixup_fdt((void *)CONFIG_SYS_SPL_ARGS_ADDR);
 #endif
spl_board_prepare_for_linux();
+   spl_bootstage_finish();
jump_to_image_linux(&spl_image);
 #endif
default:
@@ -890,13 +906,7 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
debug("SPL malloc() used 0x%lx bytes (%ld KB)\n", gd->malloc_ptr,
  gd->malloc_ptr / 1024);
 #endif
-   bootstage_mark_name(get_bootstage_id(false), "end phase");
-#ifdef CONFIG_BOOTSTAGE_STASH
-   ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
- CONFIG_BOOTSTAGE_STASH_SIZE);
-   if (ret)
-   debug("Failed to stash bootstage: err=%d\n", ret);
-#endif
+   spl_bootstage_finish();
 
if (IS_ENABLED(CONFIG_SPL_VIDEO_REMOVE)) {
struct udevice *dev;
-- 
2.39.2

RE: [PATCH] spl: bootstage: move bootstage_stash before jumping to image

[Chanho Park]

Hi Simon,

> -Original Message-
> From: Simon Glass 
> Sent: Tuesday, August 29, 2023 2:55 AM
> To: Chanho Park 
> Cc: Nikhil M Jain ; Marek Vasut ; u-
> b...@lists.denx.de
> Subject: Re: [PATCH] spl: bootstage: move bootstage_stash before jumping
> to image
> 
> Hi Chanho,
> 
> On Mon, 28 Aug 2023 at 03:46, Chanho Park 
> wrote:
> >
> > For IH_OS_OPENSBI and IH_OS_LINUX, there is no chance to stash
> > bootstare record because it will not return after jumping to the image.
> > Hence, this patch moves the location of bootstage_stash before jumping
> > to image.
> >
> 
> Please fix your implementation instead. You must jump to the OS at the end
> of this function and not before.

In case of OS_TEE/OPENSBI/LINUX images, they will not be returned to SPL so 
they can't get a chance to stash boot stage records.

> 
> In fact I have a patch to move bootstage later in this function!

Will you post the patch soon? Or it was already posted?

Best Regards,
Chanho Park

[PATCH] spl: add __noreturn attribute to spl_invoke_opensbi function

[Chanho Park]

spl_invoke_opensbi function is not returned to SPL. Thus, we need to
set __noreturn function attribute.

Signed-off-by: Chanho Park 
---
 common/spl/spl_opensbi.c | 7 ---
 include/spl.h| 2 +-
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/common/spl/spl_opensbi.c b/common/spl/spl_opensbi.c
index b0f40076c345..e2aaa460468c 100644
--- a/common/spl/spl_opensbi.c
+++ b/common/spl/spl_opensbi.c
@@ -43,11 +43,12 @@ static int spl_opensbi_find_uboot_node(void *blob, int 
*uboot_node)
return -ENODEV;
 }
 
-void spl_invoke_opensbi(struct spl_image_info *spl_image)
+void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image)
 {
int ret, uboot_node;
ulong uboot_entry;
-   void (*opensbi_entry)(ulong hartid, ulong dtb, ulong info);
+   typedef void __noreturn (*opensbi_entry_t)(ulong hartid, ulong dtb, 
ulong info);
+   opensbi_entry_t opensbi_entry;
 
if (!spl_image->fdt_addr) {
pr_err("No device tree specified in SPL image\n");
@@ -74,7 +75,7 @@ void spl_invoke_opensbi(struct spl_image_info *spl_image)
opensbi_info.options = CONFIG_SPL_OPENSBI_SCRATCH_OPTIONS;
opensbi_info.boot_hart = gd->arch.boot_hart;
 
-   opensbi_entry = (void (*)(ulong, ulong, ulong))spl_image->entry_point;
+   opensbi_entry = (opensbi_entry_t)spl_image->entry_point;
invalidate_icache_all();
 
 #ifdef CONFIG_SPL_SMP
diff --git a/include/spl.h b/include/spl.h
index 92bcaa90a4af..93e906431e7d 100644
--- a/include/spl.h
+++ b/include/spl.h
@@ -862,7 +862,7 @@ void __noreturn spl_optee_entry(void *arg0, void *arg1, 
void *arg2, void *arg3);
 /**
  * spl_invoke_opensbi - boot using a RISC-V OpenSBI image
  */
-void spl_invoke_opensbi(struct spl_image_info *spl_image);
+void __noreturn spl_invoke_opensbi(struct spl_image_info *spl_image);
 
 /**
  * board_return_to_bootrom - allow for boards to continue with the boot ROM
-- 
2.39.2

RE: [PATCH RESEND v3] fpga: add inline stub for fpga_load

[Chanho Park]

Hi Eugen,

> -Original Message-
> From: Eugen Hristev 
> Sent: Monday, August 28, 2023 8:47 PM
> To: Michal Simek ; u-boot@lists.denx.de;
> s...@chromium.org; Chanho Park 
> Subject: Re: [PATCH RESEND v3] fpga: add inline stub for fpga_load
> 
> On 8/28/23 13:53, Michal Simek wrote:
> > Hi Eugen, + Chanho,
> >
> > On 8/8/23 12:22, Eugen Hristev wrote:
> >> In case CC_OPTIMIZE_FOR_DEBUG is set, unused code will not be
> >> optimized out, hence the reference to fpga_load will be compiled.
> >> if DM_FPGA and SPL_FPGA are not set, the build will fail with :
> >
> > this is not correct. It is not DM_FPGA but only FPGA.
> >
> >
> >>
> >> aarch64-none-linux-gnu-ld.bfd: common/spl/spl_fit.o: in function
> >> `spl_fit_upload_fpga':
> >> u-boot/common/spl/spl_fit.c:595: undefined reference to `fpga_load'
> >>
> >> To solve this, added an inline empty stub in the header if
> >> CC_OPTIMIZE_FOR_DEBUG is set such that the build will succeed.
> >>
> >> Signed-off-by: Eugen Hristev 
> >> ---
> >> Changes in v3:
> >> - return -ENOSYS
> >> Changes in v2:
> >> - this is a rework as suggested by Simon of this previous patch :
> >> https://protect2.fireeye.com/v1/url?k=eed360f4-8f5875c2-eed2ebbb-74fe
> >> 485cbff1-6ddceb7720c8265c&q=1&e=f4039d69-e052-4de7-b3b0-f25e8f4581a3&
> >> u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Fpatch%2F2023
> >> 0619102839.277902-1-eugen.hristev%40collabora.com%2F
> >>
> >>   include/fpga.h | 9 +
> >>   1 file changed, 9 insertions(+)
> >>
> >> diff --git a/include/fpga.h b/include/fpga.h index
> >> ed688cc0fa3b..33d0dbbe2ba4 100644
> >> --- a/include/fpga.h
> >> +++ b/include/fpga.h
> >> @@ -60,8 +60,17 @@ int fpga_add(fpga_type devtype, void *desc);
> >>   int fpga_count(void);
> >>   const fpga_desc *const fpga_get_desc(int devnum);
> >>   int fpga_is_partial_data(int devnum, size_t img_len);
> >> +#if defined(CONFIG_CC_OPTIMIZE_FOR_DEBUG)
> >
> > And when you enable CONFIG_CC_OPTIMIZE_FOR_DEBUG and FPGA you get
> > compilation warnings.
> >
> > drivers/fpga/fpga.c:265:5: error: redefinition of 'fpga_load'
> >265 | int fpga_load(int devnum, const void *buf, size_t bsize,
> > bitstream_type bstype,
> >| ^
> > In file included from include/xilinx.h:7,
> >   from drivers/fpga/fpga.c:11:
> > include/fpga.h:64:19: note: previous definition of 'fpga_load' with
> > type 'int(int,  const void *, size_t,  bitstream_type,  int)' {aka
> > 'int(int, const void *, long unsigned int,  bitstream_type,  int)'}
> > 64 | static inline int fpga_load(int devnum, const void *buf,
> > size_t bsize,
> >|   ^
> > make[2]: *** [scripts/Makefile.build:257: drivers/fpga/fpga.o] Error 1
> >
> > I means please tune that condition properly not to create additional
> > compilation warnings for other combinations.
> >
> > Thanks,
> > Michal
> >
> 
> Hello Michal,
> 
> Thanks for reviewing .
> 
> Chanho, I cannot try this at the moment, if you are in a hurry you can
> send a v4 or v2 to your patch addressing this (or maybe your patch does
> not have this problem)

Sure. Actually, my patch does not have the problem.
Michal, could review my patch?

Best Regards,
Chanho Park

RE: [PATCH] fpga: define dummy fpga_load function for debug build

[Chanho Park]

Hi,

> -Original Message-
> From: Eugen Hristev 
> Sent: Monday, August 28, 2023 5:47 PM
> To: Chanho Park ; 'Michal Simek'
> ; u-boot@lists.denx.de
> Cc: Simon Glass 
> Subject: Re: [PATCH] fpga: define dummy fpga_load function for debug build
> 
> On 8/28/23 03:21, Chanho Park wrote:
> > Hi,
> >
> >> -Original Message-
> >> From: Michal Simek 
> >> Sent: Friday, August 25, 2023 4:23 PM
> >> To: Chanho Park ; u-boot@lists.denx.de
> >> Subject: Re: [PATCH] fpga: define dummy fpga_load function for debug
> >> build
> >>
> >> Hi,
> >>
> >> On 8/16/23 08:54, Chanho Park wrote:
> >>> This fixes below build error when CC_OPTIMIZE_FOR_DEBUG is enabled
> >>> and CONFIG_SPL_FPGA is not enabled.
> >>>
> >>> ../common/spl/spl_fit.c:591: undefined reference to `fpga_load'
> >>> collect2: error: ld returned 1 exit status
> >>>
> >>> Signed-off-by: Chanho Park 
> >>> ---
> >>>include/fpga.h | 8 
> >>>1 file changed, 8 insertions(+)
> >>>
> >>> diff --git a/include/fpga.h b/include/fpga.h index
> >>> ed688cc0fa3b..44f2755a3f10 100644
> >>> --- a/include/fpga.h
> >>> +++ b/include/fpga.h
> >>> @@ -60,8 +60,16 @@ int fpga_add(fpga_type devtype, void *desc);
> >>>int fpga_count(void);
> >>>const fpga_desc *const fpga_get_desc(int devnum);
> >>>int fpga_is_partial_data(int devnum, size_t img_len);
> >>> +#if CONFIG_IS_ENABLED(FPGA)
> >>>int fpga_load(int devnum, const void *buf, size_t bsize,
> >>> bitstream_type bstype, int flags);
> >>> +#else
> >>> +static inline int fpga_load(int devnum, const void *buf, size_t bsize,
> >>> +   bitstream_type bstype, int flags) {
> >>> + return FPGA_FAIL;
> >>> +}
> >>> +#endif
> >>>int fpga_fsload(int devnum, const void *buf, size_t size,
> >>>   fpga_fs_info *fpga_fsinfo);
> >>>int fpga_loads(int devnum, const void *buf, size_t size,
> >>
> >> There is another patch targeting the same code.
> >> Please take a look at
> >> https://lore.kernel.org/r/20230808102227.34233-1-
> >> eugen.hris...@collabora.com
> >
> > I wasn't aware that there was an attempt to fix the issue. If I knew it,
> I would reply the patch...
> >
> >>
> >> and work together to come up with the patch which covers both cases.
> >
> > Yes. I also tried to make the patch with CONFIG_CC_OPTIMIZE_FOR_DEBUG
> guard but I couldn't find any codes that uses the guard.
> > And I was also worried about the CC_OPTIMIZE_FOR_DEBUG's behavior. It
> could be related with the optimization level of the compiler.
> > That's why I put the guard with #if CONFIG_IS_ENABLED(FPGA).
> >
> > Best Regards,
> > Chanho Park
> >
> 
> 
> Hi Chanho,
> 
> Simon suggested to use CONFIG_CC_OPTIMIZE_FOR_DEBUG in this case here:
> 
> https://protect2.fireeye.com/v1/url?k=a911b2cb-c86a1843-a9103984-
> 74fe4860018a-146c33e2b586dc8a&q=1&e=e288ab48-75e8-400b-91c9-
> e8bd95520918&u=https%3A%2F%2Fpatchwork.ozlabs.org%2Fproject%2Fuboot%2Fpatc
> h%2F20230619102839.277902-1-eugen.hristev%40collabora.com%2F
> 
> As I told Michal, basically your patch and my patch do the same thing.
> I suggested him to pick the one that he thinks it's best. (or even suggest
> another way)

I agree. Either way, I'm fine with it.

Best Regards,
Chanho Park

[PATCH v2 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

timer_get_boot_us function is required to record the boot stages as
us-based timestamp.

Signed-off-by: Chanho Park 
---
 drivers/timer/riscv_aclint_timer.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/timer/riscv_aclint_timer.c 
b/drivers/timer/riscv_aclint_timer.c
index e29d527c8d77..8b67745bb4a2 100644
--- a/drivers/timer/riscv_aclint_timer.c
+++ b/drivers/timer/riscv_aclint_timer.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -44,6 +45,27 @@ u64 notrace timer_early_get_count(void)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(RISCV_MMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+   int ret;
+   u64 ticks = 0;
+   u32 rate;
+
+   ret = dm_timer_init();
+   if (!ret) {
+   rate = timer_get_rate(gd->timer);
+   timer_get_count(gd->timer, &ticks);
+   } else {
+   rate = RISCV_MMODE_TIMER_FREQ;
+   ticks = readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
+   RISCV_MMODE_TIMEROFF));
+   }
+
+   return lldiv(ticks * 1001, (rate / 1000));
+}
+#endif
+
 static const struct timer_ops riscv_aclint_timer_ops = {
.get_count = riscv_aclint_timer_get_count,
 };
-- 
2.39.2

[PATCH v2 2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

timer_get_boot_us function is required to record the boot stages as
us-based timestamp.

Signed-off-by: Chanho Park 
---
 drivers/timer/riscv_timer.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 3627ed79b819..6cb589fcdc45 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -11,6 +11,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -50,6 +51,26 @@ u64 notrace timer_early_get_count(void)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(RISCV_SMODE) && CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+   int ret;
+   u64 ticks = 0;
+   u32 rate;
+
+   ret = dm_timer_init();
+   if (!ret) {
+   rate = timer_get_rate(gd->timer);
+   timer_get_count(gd->timer, &ticks);
+   } else {
+   rate = RISCV_SMODE_TIMER_FREQ;
+   ticks = riscv_timer_get_count(NULL);
+   }
+
+   return lldiv(ticks * 1000, (rate / 1000));
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-- 
2.39.2

[PATCH v2 0/3] bootstage support for risc-v

[Chanho Park]

This adds to support bootstage for risc-v. timer_get_boot_us function
is required to record each boot stages with microsecond timestamp.

Changes from v1:
- Correct #ifdef guard for riscv_aclint_timer and riscv_timer

Chanho Park (3):
  riscv: bootstage: correct bootstage_report guard
  riscv: timer: add timer_get_boot_us for BOOTSTAGE
  timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

 arch/riscv/lib/bootm.c |  2 +-
 drivers/timer/riscv_aclint_timer.c | 22 ++
 drivers/timer/riscv_timer.c| 21 +
 3 files changed, 44 insertions(+), 1 deletion(-)

-- 
2.39.2

[PATCH v2 1/3] riscv: bootstage: correct bootstage_report guard

[Chanho Park]

Below warning can be occurred when CONFIG_BOOTSTAGE and
!CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED
for SPL build.

arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of
function 'bootstage_report'
   46 | bootstage_report();
  | ^~~~
  | bootstage_error

Signed-off-by: Chanho Park 
---
 arch/riscv/lib/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 276677a5e2f9..cc30efc90498 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -42,7 +42,7 @@ static void announce_and_cleanup(int fake)
 #ifdef CONFIG_BOOTSTAGE_FDT
bootstage_fdt_add_report();
 #endif
-#ifdef CONFIG_BOOTSTAGE_REPORT
+#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT)
bootstage_report();
 #endif
 
-- 
2.39.2

[PATCH] spl: bootstage: move bootstage_stash before jumping to image

[Chanho Park]

For IH_OS_OPENSBI and IH_OS_LINUX, there is no chance to stash
bootstare record because it will not return after jumping to the image.
Hence, this patch moves the location of bootstage_stash before jumping
to image.

Signed-off-by: Chanho Park 
---
 common/spl/spl.c | 15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/common/spl/spl.c b/common/spl/spl.c
index 0062f3f45d9a..364d439f65e2 100644
--- a/common/spl/spl.c
+++ b/common/spl/spl.c
@@ -850,6 +850,14 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
   ret);
}
 
+   bootstage_mark_name(get_bootstage_id(false), "end phase");
+#ifdef CONFIG_BOOTSTAGE_STASH
+   ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
+ CONFIG_BOOTSTAGE_STASH_SIZE);
+   if (ret)
+   debug("Failed to stash bootstage: err=%d\n", ret);
+#endif
+
switch (spl_image.os) {
case IH_OS_U_BOOT:
debug("Jumping to %s...\n", spl_phase_name(spl_next_phase()));
@@ -890,13 +898,6 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
debug("SPL malloc() used 0x%lx bytes (%ld KB)\n", gd->malloc_ptr,
  gd->malloc_ptr / 1024);
 #endif
-   bootstage_mark_name(get_bootstage_id(false), "end phase");
-#ifdef CONFIG_BOOTSTAGE_STASH
-   ret = bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
- CONFIG_BOOTSTAGE_STASH_SIZE);
-   if (ret)
-   debug("Failed to stash bootstage: err=%d\n", ret);
-#endif
 
if (IS_ENABLED(CONFIG_SPL_VIDEO_REMOVE)) {
struct udevice *dev;
-- 
2.39.2

RE: [PATCH] fpga: define dummy fpga_load function for debug build

[Chanho Park]

Hi,

> -Original Message-
> From: Michal Simek 
> Sent: Friday, August 25, 2023 4:23 PM
> To: Chanho Park ; u-boot@lists.denx.de
> Subject: Re: [PATCH] fpga: define dummy fpga_load function for debug build
> 
> Hi,
> 
> On 8/16/23 08:54, Chanho Park wrote:
> > This fixes below build error when CC_OPTIMIZE_FOR_DEBUG is enabled and
> > CONFIG_SPL_FPGA is not enabled.
> >
> > ../common/spl/spl_fit.c:591: undefined reference to `fpga_load'
> > collect2: error: ld returned 1 exit status
> >
> > Signed-off-by: Chanho Park 
> > ---
> >   include/fpga.h | 8 
> >   1 file changed, 8 insertions(+)
> >
> > diff --git a/include/fpga.h b/include/fpga.h index
> > ed688cc0fa3b..44f2755a3f10 100644
> > --- a/include/fpga.h
> > +++ b/include/fpga.h
> > @@ -60,8 +60,16 @@ int fpga_add(fpga_type devtype, void *desc);
> >   int fpga_count(void);
> >   const fpga_desc *const fpga_get_desc(int devnum);
> >   int fpga_is_partial_data(int devnum, size_t img_len);
> > +#if CONFIG_IS_ENABLED(FPGA)
> >   int fpga_load(int devnum, const void *buf, size_t bsize,
> >   bitstream_type bstype, int flags);
> > +#else
> > +static inline int fpga_load(int devnum, const void *buf, size_t bsize,
> > + bitstream_type bstype, int flags) {
> > +   return FPGA_FAIL;
> > +}
> > +#endif
> >   int fpga_fsload(int devnum, const void *buf, size_t size,
> > fpga_fs_info *fpga_fsinfo);
> >   int fpga_loads(int devnum, const void *buf, size_t size,
> 
> There is another patch targeting the same code.
> Please take a look at
> https://lore.kernel.org/r/20230808102227.34233-1-
> eugen.hris...@collabora.com

I wasn't aware that there was an attempt to fix the issue. If I knew it, I 
would reply the patch...

> 
> and work together to come up with the patch which covers both cases.

Yes. I also tried to make the patch with CONFIG_CC_OPTIMIZE_FOR_DEBUG guard but 
I couldn't find any codes that uses the guard.
And I was also worried about the CC_OPTIMIZE_FOR_DEBUG's behavior. It could be 
related with the optimization level of the compiler.
That's why I put the guard with #if CONFIG_IS_ENABLED(FPGA).

Best Regards,
Chanho Park

[PATCH 3/3] timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

timer_get_boot_us function is required to record the boot stages as
us-based timestamp.

Signed-off-by: Chanho Park 
---
 drivers/timer/riscv_aclint_timer.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/drivers/timer/riscv_aclint_timer.c 
b/drivers/timer/riscv_aclint_timer.c
index e29d527c8d77..442b48d55adf 100644
--- a/drivers/timer/riscv_aclint_timer.c
+++ b/drivers/timer/riscv_aclint_timer.c
@@ -6,6 +6,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -44,6 +45,27 @@ u64 notrace timer_early_get_count(void)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+   int ret;
+   u64 ticks = 0;
+   u32 rate;
+
+   ret = dm_timer_init();
+   if (!ret) {
+   rate = timer_get_rate(gd->timer);
+   timer_get_count(gd->timer, &ticks);
+   } else {
+   rate = RISCV_MMODE_TIMER_FREQ;
+   ticks = readq((void __iomem *)MTIME_REG(RISCV_MMODE_TIMERBASE,
+   RISCV_MMODE_TIMEROFF));
+   }
+
+   return lldiv(ticks * 1001, (rate / 1000));
+}
+#endif
+
 static const struct timer_ops riscv_aclint_timer_ops = {
.get_count = riscv_aclint_timer_get_count,
 };
-- 
2.39.2

[PATCH 0/3] bootstage support for risc-v

[Chanho Park]

This adds to support bootstage for risc-v. timer_get_boot_us function
is required to record each boot stages with microsecond timestamp.

Chanho Park (3):
  riscv: bootstage: correct bootstage_report guard
  riscv: timer: add timer_get_boot_us for BOOTSTAGE
  timer: riscv_aclint_timer: add timer_get_boot_us for BOOTSTAGE

 arch/riscv/lib/bootm.c |  2 +-
 drivers/timer/riscv_aclint_timer.c | 22 ++
 drivers/timer/riscv_timer.c| 21 +
 3 files changed, 44 insertions(+), 1 deletion(-)

-- 
2.39.2

[PATCH 1/3] riscv: bootstage: correct bootstage_report guard

[Chanho Park]

Below warning can be occurred when CONFIG_BOOTSTAGE and
!CONFIG_SPL_BOOTSTAGE. It should be guarded by using CONFIG_IS_ENABLED
for SPL build.

arch/riscv/lib/bootm.c:46:9: warning: implicit declaration of
function 'bootstage_report'
   46 | bootstage_report();
  | ^~~~
  | bootstage_error

Signed-off-by: Chanho Park 
---
 arch/riscv/lib/bootm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/lib/bootm.c b/arch/riscv/lib/bootm.c
index 276677a5e2f9..cc30efc90498 100644
--- a/arch/riscv/lib/bootm.c
+++ b/arch/riscv/lib/bootm.c
@@ -42,7 +42,7 @@ static void announce_and_cleanup(int fake)
 #ifdef CONFIG_BOOTSTAGE_FDT
bootstage_fdt_add_report();
 #endif
-#ifdef CONFIG_BOOTSTAGE_REPORT
+#if CONFIG_IS_ENABLED(BOOTSTAGE_REPORT)
bootstage_report();
 #endif
 
-- 
2.39.2

[PATCH 2/3] riscv: timer: add timer_get_boot_us for BOOTSTAGE

[Chanho Park]

timer_get_boot_us function is required to record the boot stages as
us-based timestamp.

Signed-off-by: Chanho Park 
---
 drivers/timer/riscv_timer.c | 21 +
 1 file changed, 21 insertions(+)

diff --git a/drivers/timer/riscv_timer.c b/drivers/timer/riscv_timer.c
index 3627ed79b819..f9fc7dae37d0 100644
--- a/drivers/timer/riscv_timer.c
+++ b/drivers/timer/riscv_timer.c
@@ -11,6 +11,7 @@
  */
 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -50,6 +51,26 @@ u64 notrace timer_early_get_count(void)
 }
 #endif
 
+#if CONFIG_IS_ENABLED(BOOTSTAGE)
+ulong timer_get_boot_us(void)
+{
+   int ret;
+   u64 ticks = 0;
+   u32 rate;
+
+   ret = dm_timer_init();
+   if (!ret) {
+   rate = timer_get_rate(gd->timer);
+   timer_get_count(gd->timer, &ticks);
+   } else {
+   rate = RISCV_SMODE_TIMER_FREQ;
+   ticks = riscv_timer_get_count(NULL);
+   }
+
+   return lldiv(ticks * 1000, (rate / 1000));
+}
+#endif
+
 static int riscv_timer_probe(struct udevice *dev)
 {
struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev);
-- 
2.39.2

[PATCH v2 2/2] riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback

[Chanho Park]

Since the Patch 55171aedda88, VisionFive2 booting has been broken [1].
VisionFive2 board requires to enable CONFIG_TIMER_EARLY but booting went
to panic from initr_dm_devices due to lack of a timer device.

- Error logs
initcall sequence fffd8d38 failed at call 402185e4
(err=-19)

Thus, we need to move riscv_cpu_probe function in order to register
the timer earlier than initr_dm_devices.

Fixes: 7fe32b3442f0 ("event: Convert arch_cpu_init_dm() to use events")
Cc: Simon Glass 
Cc: Bin Meng 
Signed-off-by: Chanho Park 
---
 arch/riscv/cpu/cpu.c | 11 +++
 1 file changed, 3 insertions(+), 8 deletions(-)

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index ecfb1fb08c4b..0b4208e72199 100644
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -66,7 +66,7 @@ static inline bool supports_extension(char ext)
 #endif /* CONFIG_CPU */
 }
 
-static int riscv_cpu_probe(void)
+static int riscv_cpu_probe(void *ctx, struct event *event)
 {
 #ifdef CONFIG_CPU
int ret;
@@ -79,6 +79,7 @@ static int riscv_cpu_probe(void)
 
return 0;
 }
+EVENT_SPY(EVT_DM_POST_INIT_R, riscv_cpu_probe);
 
 /*
  * This is called on secondary harts just after the IPI is init'd. Currently
@@ -95,7 +96,7 @@ int riscv_cpu_setup(void *ctx, struct event *event)
 {
int ret;
 
-   ret = riscv_cpu_probe();
+   ret = riscv_cpu_probe(ctx, event);
if (ret)
return ret;
 
@@ -149,12 +150,6 @@ EVENT_SPY(EVT_DM_POST_INIT_F, riscv_cpu_setup);
 
 int arch_early_init_r(void)
 {
-   int ret;
-
-   ret = riscv_cpu_probe();
-   if (ret)
-   return ret;
-
if (IS_ENABLED(CONFIG_SYSRESET_SBI))
device_bind_driver(gd->dm_root, "sbi-sysreset",
   "sbi-sysreset", NULL);
-- 
2.39.2

[PATCH v2 0/2] introduce EVT_DM_POST_INIT_R to fix VF2 boot fail

[Chanho Park]

Since the Patch 55171aedda88, VisionFive2 booting has been broken [1].
VisionFive2 board requires to enable CONFIG_TIMER_EARLY but booting went
to panic from initr_dm_devices due to lack of a timer device.

- Error logs
initcall sequence fffd8d38 failed at call 402185e4
(err=-19)

We can reproduce it on Qemu Sifive HiFive Unleashed emulation[2] after
enabling CONFIG_TIMER_EARLY manually.

As suggested by Simon[3], we can address this by adding
EVT_DM_POST_INIT_R event and it's spy-callback function.

Changes from v1:
- Add EVT_DM_POST_INIT_R event type and emit it after relocation
- Make riscv_cpu_probe as the callback of EVT_DM_POST_INIT_R

[1]: https://lists.denx.de/pipermail/u-boot/2023-June/521220.html
[2]: https://www.qemu.org/docs/master/system/riscv/sifive_u.html#running-u-boot
[3]: 
https://lore.kernel.org/u-boot/capnjgz2pbhvy_wlvq7xcd-hykkwoh8r3lgxfoo7s6sbvj0+...@mail.gmail.com/

Chanho Park (2):
  dm: event: add EVT_DM_POST_INIT_R event type
  riscv: cpu: make riscv_cpu_probe to EVT_DM_POST_INIT_R callback

 arch/riscv/cpu/cpu.c | 11 +++
 drivers/core/root.c  |  6 --
 include/event.h  |  1 +
 3 files changed, 8 insertions(+), 10 deletions(-)

-- 
2.39.2

[PATCH v2 1/2] dm: event: add EVT_DM_POST_INIT_R event type

[Chanho Park]

This patch introduces EVT_DM_POST_INIT_R event type for handling hooks
after relocation.

Fixes: 55171aedda88 ("dm: Emit the arch_cpu_init_dm() even only before 
relocation")
Suggested-by: Simon Glass 
Cc: Bin Meng 
Signed-off-by: Chanho Park 
---
 drivers/core/root.c | 6 --
 include/event.h | 1 +
 2 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/core/root.c b/drivers/core/root.c
index 6775fb0b6575..79d871ab291a 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -436,8 +436,10 @@ int dm_init_and_scan(bool pre_reloc_only)
return ret;
}
}
-   if (CONFIG_IS_ENABLED(DM_EVENT) && !(gd->flags & GD_FLG_RELOC)) {
-   ret = event_notify_null(EVT_DM_POST_INIT_F);
+   if (CONFIG_IS_ENABLED(DM_EVENT)) {
+   ret = event_notify_null(gd->flags & GD_FLG_RELOC ?
+   EVT_DM_POST_INIT_R :
+   EVT_DM_POST_INIT_F);
if (ret)
return log_msg_ret("ev", ret);
}
diff --git a/include/event.h b/include/event.h
index daf44bf8a83b..bb38ba98e73b 100644
--- a/include/event.h
+++ b/include/event.h
@@ -24,6 +24,7 @@ enum event_t {
 
/* Events related to driver model */
EVT_DM_POST_INIT_F,
+   EVT_DM_POST_INIT_R,
EVT_DM_PRE_PROBE,
EVT_DM_POST_PROBE,
EVT_DM_PRE_REMOVE,
-- 
2.39.2

RE: [PATCH] dm: core: allow DM_POST_INIT_F notification for TIMER_EARLY

[Chanho Park]

Hi Simon,

> -Original Message-
> From: Simon Glass 
> Sent: Wednesday, August 9, 2023 2:54 AM
> To: Chanho Park 
> Cc: u-boot@lists.denx.de; Bin Meng 
> Subject: Re: [PATCH] dm: core: allow DM_POST_INIT_F notification for
> TIMER_EARLY
> 
> Hi Chanho,
> 
> On Tue, 8 Aug 2023 at 01:35, Chanho Park  wrote:
> >
> > Since the Patch 55171aedda88, VisionFive2 booting has been broken [1].
> > VisionFive2 board requires to enable CONFIG_TIMER_EARLY but booting
> > went to panic from initr_dm_devices due to lack of a timer device.
> >
> > - Error logs
> > initcall sequence fffd8d38 failed at call 402185e4
> > (err=-19)
> >
> > We can reproduce it on Qemu Sifive HiFive Unleashed emulation[2] after
> > enabling CONFIG_TIMER_EARLY manually.
> >
> > [1]:
> > https://protect2.fireeye.com/v1/url?k=38a0f71d-592be204-38a17c52-74fe4
> > 85cbfec-8b0f4f7ae7f889ef&q=1&e=3bf1c52b-7aa0-464a-86d3-ecec3db1395d&u=
> > https%3A%2F%2Flists.denx.de%2Fpipermail%2Fu-boot%2F2023-June%2F521220.
> > html
> > [2]:
> > https://www.qemu.org/docs/master/system/riscv/sifive_u.html#running-u-
> > boot
> > Fixes: 55171aedda88 ("dm: Emit the arch_cpu_init_dm() even only before
> > relocation")
> > Cc: Simon Glass 
> > Cc: Bin Meng 
> > Signed-off-by: Chanho Park 
> > ---
> >  drivers/core/root.c | 3 ++-
> >  1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/core/root.c b/drivers/core/root.c index
> > 6775fb0b6575..e939da484b2a 100644
> > --- a/drivers/core/root.c
> > +++ b/drivers/core/root.c
> > @@ -436,7 +436,8 @@ int dm_init_and_scan(bool pre_reloc_only)
> > return ret;
> > }
> > }
> > -   if (CONFIG_IS_ENABLED(DM_EVENT) && !(gd->flags & GD_FLG_RELOC)) {
> > +   if (CONFIG_IS_ENABLED(DM_EVENT) &&
> > +   (!(gd->flags & GD_FLG_RELOC) ||
> > + CONFIG_IS_ENABLED(TIMER_EARLY))) {
> > ret = event_notify_null(EVT_DM_POST_INIT_F);
> > if (ret)
> > return log_msg_ret("ev", ret);
> > --
> > 2.39.2
> >
> 
> It looks like you need a new notification. The correct fix would be to add
> a new EVT_DM_POST_INIT_R event and emit that after relocation, e.g.
> 
> if (CONFIG_IS_ENABLED(DM_EVENT) {
>ret = event_notify_null(gd->flags & GD_FLG_RELOC ?
>  EVT_DM_POST_INIT_R : EVT_DM_POST_INIT_F);
>if (ret)
>   return log_msg_ret("ev", ret);
> }

Sorry for this late reply.
I feel like I need to move riscv_cpu_probe call from arch_early_init_r and make 
it as the callback of the new event.
I'll send v2 with the changes.

Best Regards,
Chanho Park

[PATCH] fpga: define dummy fpga_load function for debug build

[Chanho Park]

This fixes below build error when CC_OPTIMIZE_FOR_DEBUG is enabled and
CONFIG_SPL_FPGA is not enabled.

../common/spl/spl_fit.c:591: undefined reference to `fpga_load'
collect2: error: ld returned 1 exit status

Signed-off-by: Chanho Park 
---
 include/fpga.h | 8 
 1 file changed, 8 insertions(+)

diff --git a/include/fpga.h b/include/fpga.h
index ed688cc0fa3b..44f2755a3f10 100644
--- a/include/fpga.h
+++ b/include/fpga.h
@@ -60,8 +60,16 @@ int fpga_add(fpga_type devtype, void *desc);
 int fpga_count(void);
 const fpga_desc *const fpga_get_desc(int devnum);
 int fpga_is_partial_data(int devnum, size_t img_len);
+#if CONFIG_IS_ENABLED(FPGA)
 int fpga_load(int devnum, const void *buf, size_t bsize,
  bitstream_type bstype, int flags);
+#else
+static inline int fpga_load(int devnum, const void *buf, size_t bsize,
+ bitstream_type bstype, int flags)
+{
+   return FPGA_FAIL;
+}
+#endif
 int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_fs_info *fpga_fsinfo);
 int fpga_loads(int devnum, const void *buf, size_t size,
-- 
2.39.2

[PATCH] dm: core: allow DM_POST_INIT_F notification for TIMER_EARLY

[Chanho Park]

Since the Patch 55171aedda88, VisionFive2 booting has been broken [1].
VisionFive2 board requires to enable CONFIG_TIMER_EARLY but booting went
to panic from initr_dm_devices due to lack of a timer device.

- Error logs
initcall sequence fffd8d38 failed at call 402185e4
(err=-19)

We can reproduce it on Qemu Sifive HiFive Unleashed emulation[2] after
enabling CONFIG_TIMER_EARLY manually.

[1]: https://lists.denx.de/pipermail/u-boot/2023-June/521220.html
[2]: https://www.qemu.org/docs/master/system/riscv/sifive_u.html#running-u-boot
Fixes: 55171aedda88 ("dm: Emit the arch_cpu_init_dm() even only before 
relocation")
Cc: Simon Glass 
Cc: Bin Meng 
Signed-off-by: Chanho Park 
---
 drivers/core/root.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/core/root.c b/drivers/core/root.c
index 6775fb0b6575..e939da484b2a 100644
--- a/drivers/core/root.c
+++ b/drivers/core/root.c
@@ -436,7 +436,8 @@ int dm_init_and_scan(bool pre_reloc_only)
return ret;
}
}
-   if (CONFIG_IS_ENABLED(DM_EVENT) && !(gd->flags & GD_FLG_RELOC)) {
+   if (CONFIG_IS_ENABLED(DM_EVENT) &&
+   (!(gd->flags & GD_FLG_RELOC) || CONFIG_IS_ENABLED(TIMER_EARLY))) {
ret = event_notify_null(EVT_DM_POST_INIT_F);
if (ret)
return log_msg_ret("ev", ret);
-- 
2.39.2

[PATCH 1/2] configs: visionfive2: add a trailing space to prompt

[Chanho Park]

Adds a trailing space to SYS_PROMPT to make it easier to distinguish
between commands and the prompt.

Signed-off-by: Chanho Park 
---
 configs/starfive_visionfive2_defconfig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/configs/starfive_visionfive2_defconfig 
b/configs/starfive_visionfive2_defconfig
index 570a1f53a19b..75b727472da4 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -9,7 +9,7 @@ CONFIG_SF_DEFAULT_SPEED=1
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2"
 CONFIG_SPL_TEXT_BASE=0x800
-CONFIG_SYS_PROMPT="StarFive #"
+CONFIG_SYS_PROMPT="StarFive # "
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_DM_RESET=y
 CONFIG_SPL_MMC=y
-- 
2.39.2

[PATCH 2/2] doc: visionfive2: apply a trailing space to the prompt

[Chanho Park]

Apply the trailing space changes in the guide document.

Signed-off-by: Chanho Park 
---
 doc/board/starfive/visionfive2.rst | 18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/doc/board/starfive/visionfive2.rst 
b/doc/board/starfive/visionfive2.rst
index 951e0d80fb9d..941899a0a4e9 100644
--- a/doc/board/starfive/visionfive2.rst
+++ b/doc/board/starfive/visionfive2.rst
@@ -206,16 +206,16 @@ Sample boot log from StarFive VisionFive2 board
Working FDT set to ff74a340
Hit any key to stop autoboot:  0
StarFive #
-   StarFive #version
+   StarFive # version
U-Boot 2023.04-rc2-00055-gfc43b9c51a-dirty (Mar 02 2023 - 10:51:39 
+0800)
 
riscv64-buildroot-linux-gnu-gcc.br_real (Buildroot VF2_515_v1.0.0_rc4) 
10.3.0
GNU ld (GNU Binutils) 2.36.1
StarFive #
-   StarFive #mmc dev 1
+   StarFive # mmc dev 1
switch to partitions #0, OK
mmc1 is current device
-   StarFive #mmc info
+   StarFive # mmc info
Device: mmc@1602
Manufacturer ID: 9f
OEM: 5449
@@ -229,7 +229,7 @@ Sample boot log from StarFive VisionFive2 board
Bus Width: 4-bit
Erase Group Size: 512 Bytes
StarFive #
-   StarFive #mmc part
+   StarFive # mmc part
 
Partition Map for MMC device 1  --   Partition Type: EFI
 
@@ -253,7 +253,7 @@ Sample boot log from StarFive VisionFive2 board
(data)
guid:   539a6df9-4655-4953-8541-733ca36eb1db
StarFive #
-   StarFive #fatls mmc 1:3
+   StarFive # fatls mmc 1:3
6429424   Image.gz
717705   u-boot.itb
125437   u-boot-spl.bin.normal.out
@@ -262,13 +262,13 @@ Sample boot log from StarFive VisionFive2 board
 
5 file(s), 0 dir(s)
 
-   StarFive #fatload mmc 1:3 ${kernel_addr_r} Image.gz
+   StarFive # fatload mmc 1:3 ${kernel_addr_r} Image.gz
6429424 bytes read in 394 ms (15.6 MiB/s)
-   StarFive #fatload mmc 1:3 ${fdt_addr_r} jh7110-starfive-visionfive-2.dtb
+   StarFive # fatload mmc 1:3 ${fdt_addr_r} 
jh7110-starfive-visionfive-2.dtb
11285 bytes read in 5 ms (2.2 MiB/s)
-   StarFive #fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
+   StarFive # fatload mmc 1:3 ${ramdisk_addr_r} initramfs.cpio.gz
152848495 bytes read in 9271 ms (15.7 MiB/s)
-   StarFive #booti ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} 
${fdt_addr_r}
+   StarFive # booti ${kernel_addr_r} ${ramdisk_addr_r}:${filesize} 
${fdt_addr_r}
Uncompressing Kernel Image
## Flattened Device Tree blob at 4600
Booting using the fdt blob at 0x4600
-- 
2.39.2

[PATCH 0/2] add a trailing space to prompt for visionfive2 board

[Chanho Park]

Adds a trailing space to SYS_PROMPT to make it easier to distinguish
between commands and the prompt.

Chanho Park (2):
  configs: visionfive2: add a trailing space to prompt
  doc: visionfive2: apply a trailing space to the prompt

 configs/starfive_visionfive2_defconfig |  2 +-
 doc/board/starfive/visionfive2.rst | 18 +-
 2 files changed, 10 insertions(+), 10 deletions(-)

-- 
2.39.2