[U-Boot] [PATCH] powerpc/85xx: Integrated Flash Controller NAND support

2011-04-20 Thread Dipen Dudhat 
Add nand_spl and 8-bit NAND support on IFC controller.

Signed-off-by: Dipen Dudhat 
---
Changes from v1:
- Integrated Scott's comments
 arch/powerpc/cpu/mpc85xx/cpu_init_nand.c |   10 +
 arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds |   18 +-
 drivers/mtd/nand/Makefile|1 +
 drivers/mtd/nand/fsl_ifc_nand.c  |  638 ++
 nand_spl/nand_boot_fsl_ifc.c |  225 +
 5 files changed, 889 insertions(+), 3 deletions(-)
 create mode 100644 drivers/mtd/nand/fsl_ifc_nand.c
 create mode 100644 nand_spl/nand_boot_fsl_ifc.c

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
index 796d398..6d01479 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
@@ -21,10 +21,12 @@
  */
 
 #include 
+#include 
 #include 
 
 void cpu_init_f(void)
 {
+#ifdef CONFIG_FSL_LBC
fsl_lbc_t *lbc = LBC_BASE_ADDR;
 
/*
@@ -39,6 +41,14 @@ void cpu_init_f(void)
 #else
 #error  CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM must be defined
 #endif
+#endif
+#ifdef CONFIG_FSL_IFC
+#if defined(CONFIG_SYS_CSPR0) && defined(CONFIG_SYS_CSOR0)
+   set_ifc_cspr(IFC_CS0, CONFIG_SYS_CSPR0);
+   set_ifc_amask(IFC_CS0, CONFIG_SYS_AMASK0);
+   set_ifc_csor(IFC_CS0, CONFIG_SYS_CSOR0);
+#endif
+#endif
 
 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds 
b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 8410bd7..852f9aa 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -23,6 +23,8 @@
  * MA 02111-1307 USA
  */
 
+#include "config.h"/* CONFIG_BOARDDIR */
+
 OUTPUT_ARCH(powerpc)
 SECTIONS
 {
@@ -52,8 +54,18 @@ SECTIONS
. = ALIGN(8);
__init_begin = .;
__init_end = .;
-
-   .resetvec ADDR(.text) + 0xffc : {
+#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
+   .bootpg ADDR(.text) + 0x1000 :
+   {
+   start.o (.bootpg)
+   }
+#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
+#elif defined(CONFIG_FSL_ELBC)
+#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
+#else
+#error unknown NAND controller
+#endif
+   .resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0x
 
@@ -64,4 +76,4 @@ SECTIONS
}
__bss_end__ = .;
 }
-ASSERT(__init_end <= 0xfff00ffc, "NAND bootstrap too big");
+ASSERT(__init_end <= (0xfff0 + RESET_VECTOR_OFFSET), "NAND bootstrap too 
big");
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index 8b598f6..3353dcd 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -37,6 +37,7 @@ COBJS-$(CONFIG_NAND_ATMEL) += atmel_nand.o
 COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
 COBJS-$(CONFIG_NAND_DAVINCI) += davinci_nand.o
 COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
+COBJS-$(CONFIG_NAND_FSL_IFC) += fsl_ifc_nand.o
 COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
 COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
 COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
diff --git a/drivers/mtd/nand/fsl_ifc_nand.c b/drivers/mtd/nand/fsl_ifc_nand.c
new file mode 100644
index 000..3c4d0aa
--- /dev/null
+++ b/drivers/mtd/nand/fsl_ifc_nand.c
@@ -0,0 +1,638 @@
+/*
+ * Integrated Flash Controller NAND Machine Driver
+ *
+ * Copyright (c) 2011 Freescale Semiconductor, Inc
+ *
+ * Authors: Dipen Dudhat 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#define MAX_BANKS  4
+#define ERR_BYTE   0xFF /* Value returned for read bytes
+   when read failed */
+#define IFC_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for IFC
+   NAND Machine */
+
+struct fsl_ifc_ctrl;
+
+/* mtd information per set */
+struct fsl_ifc_mtd {
+   struct mtd_info mtd;
+   struct nand_chip chip;
+   struct fsl_ifc_ctrl *ctrl;
+
+   struct device *dev;
+   int bank;   /* Chi

[U-Boot] [PATCH v1] powerpc/85xx: Add support for Integrated Flash Controller (IFC)

2011-01-20 Thread Dipen Dudhat 
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.

Features supported by IFC are,
- Functional muxing of pins between NAND, NOR and GPCM
- Support memory banks of size 64KByte to 4 GBytes
- Write protection capability (only for NAND and NOR)
- Provision of Software Reset
- Flexible Timing programmability for every chip select
- NAND Machine
- x8/ x16 NAND Flash Interface
- SLC and MLC NAND Flash devices support with
  configurable
  page sizes of upto 4KB
- Internal SRAM of 9KB which is directly mapped and
  availble at
  boot time for NAND Boot
- Configurable block size
- Boot chip select (CS0) available at system reset
- NOR Machine
- Data bus width of 8/16/32
- Compatible with asynchronous NOR Flash
- Directly memory mapped
- Supports address data multiplexed (ADM) NOR device
- Boot chip select (CS0) available at system reset
- GPCM Machine (NORMAL GPCM Mode)
- Support for x8/16/32 bit device
- Compatible with general purpose addressable device
  e.g. SRAM, ROM
- External clock is supported with programmable division
  ratio
- GPCM Machine (Generic ASIC Mode)
- Support for x8/16/32 bit device
- Address and Data are shared on I/O bus
- Following Address and Data sequences can be supported
  on I/O bus
   - 32 bit I/O: AD
   - 16 bit I/O: AADD
   - 8 bit I/O : 
- Configurable Even/Odd Parity on Address/Data bus
  supported

Signed-off-by: Dipen Dudhat 
Acked-by: Scott Wood 
---
Changes from v0:
- Integrated Wolfgang's comments
 arch/powerpc/cpu/mpc85xx/cpu.c|7 +-
 arch/powerpc/cpu/mpc8xxx/Makefile |1 +
 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c|   84 +++
 arch/powerpc/include/asm/config.h |2 +
 arch/powerpc/include/asm/fsl_ifc.h|  947 +
 arch/powerpc/include/asm/fsl_law.h|1 +
 arch/powerpc/include/asm/immap_85xx.h |4 +
 7 files changed, 1045 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
 create mode 100644 arch/powerpc/include/asm/fsl_ifc.h

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1aad2ba..49ea6cc 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -280,7 +281,8 @@ int cpu_mmc_init(bd_t *bis)
 
 /*
  * Print out the state of various machine registers.
- * Currently prints out LAWs, BR0/OR0, and TLBs
+ * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
+ * parameters for IFC and TLBs
  */
 void mpc85xx_reginfo(void)
 {
@@ -289,6 +291,9 @@ void mpc85xx_reginfo(void)
 #if defined(CONFIG_FSL_LBC)
print_lbc_regs();
 #endif
+#ifdef CONFIG_FSL_IFC
+   print_ifc_regs();
+#endif
 
 }
 
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile 
b/arch/powerpc/cpu/mpc8xxx/Makefile
index 5dfd65b..4ae26e4 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -15,6 +15,7 @@ COBJS-y   += cpu.o
 endif
 
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 COBJS-$(CONFIG_SYS_SRIO) += srio.o
 
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c 
b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
new file mode 100644
index 000..39a4556
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Dipen Dudhat 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+
+void print_ifc_regs(void)
+{
+   int i, j;
+
+   p

[U-Boot] [PATCH] powerpc/85xx: Add support for Integrated Flash Controller (IFC)

2011-01-20 Thread Dipen Dudhat 
The Integrated Flash Controller (IFC) is used to access the external
NAND Flash, NOR Flash, EPROM, SRAM and Generic ASIC memories.Four chip
selects are provided in IFC so that maximum of four Flash devices can be
hooked, but only one can be accessed at a given time.

Features supported by IFC are,
- Functional muxing of pins between NAND, NOR and GPCM
- Support memory banks of size 64KByte to 4 GBytes
- Write protection capability (only for NAND and NOR)
- Provision of Software Reset
- Flexible Timing programmability for every chip select
- NAND Machine
- x8/ x16 NAND Flash Interface
- SLC and MLC NAND Flash devices support with
  configurable
  page sizes of upto 4KB
- Internal SRAM of 9KB which is directly mapped and
  availble at
  boot time for NAND Boot
- Configurable block size
- Boot chip select (CS0) available at system reset
- NOR Machine
- Data bus width of 8/16/32
- Compatible with asynchronous NOR Flash
- Directly memory mapped
- Supports address data multiplexed (ADM) NOR device
- Boot chip select (CS0) available at system reset
- GPCM Machine (NORMAL GPCM Mode)
- Support for x8/16/32 bit device
- Compatible with general purpose addressable device
  e.g. SRAM, ROM
- External clock is supported with programmable division
  ratio
- GPCM Machine (Generic ASIC Mode)
- Support for x8/16/32 bit device
- Address and Data are shared on I/O bus
- Following Address and Data sequences can be supported
  on I/O bus
— 32 bit I/O: AD
— 16 bit I/O: AADD
— 8 bit I/O : 
- Configurable Even/Odd Parity on Address/Data bus
  supported

Signed-off-by: Dipen Dudhat 
Acked-by: Scott Wood 
---
 arch/powerpc/cpu/mpc85xx/cpu.c|7 +-
 arch/powerpc/cpu/mpc8xxx/Makefile |1 +
 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c|   84 +++
 arch/powerpc/include/asm/config.h |2 +
 arch/powerpc/include/asm/fsl_ifc.h|  929 +
 arch/powerpc/include/asm/fsl_law.h|1 +
 arch/powerpc/include/asm/immap_85xx.h |4 +
 7 files changed, 1027 insertions(+), 1 deletions(-)
 create mode 100644 arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
 create mode 100644 arch/powerpc/include/asm/fsl_ifc.h

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 1aad2ba..49ea6cc 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -280,7 +281,8 @@ int cpu_mmc_init(bd_t *bis)
 
 /*
  * Print out the state of various machine registers.
- * Currently prints out LAWs, BR0/OR0, and TLBs
+ * Currently prints out LAWs, BR0/OR0 for LBC, CSPR/CSOR/Timing
+ * parameters for IFC and TLBs
  */
 void mpc85xx_reginfo(void)
 {
@@ -289,6 +291,9 @@ void mpc85xx_reginfo(void)
 #if defined(CONFIG_FSL_LBC)
print_lbc_regs();
 #endif
+#ifdef CONFIG_FSL_IFC
+   print_ifc_regs();
+#endif
 
 }
 
diff --git a/arch/powerpc/cpu/mpc8xxx/Makefile 
b/arch/powerpc/cpu/mpc8xxx/Makefile
index 5dfd65b..4ae26e4 100644
--- a/arch/powerpc/cpu/mpc8xxx/Makefile
+++ b/arch/powerpc/cpu/mpc8xxx/Makefile
@@ -15,6 +15,7 @@ COBJS-y   += cpu.o
 endif
 
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS-$(CONFIG_FSL_IFC) += fsl_ifc.o
 COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
 COBJS-$(CONFIG_SYS_SRIO) += srio.o
 
diff --git a/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c 
b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
new file mode 100644
index 000..8d840e2
--- /dev/null
+++ b/arch/powerpc/cpu/mpc8xxx/fsl_ifc.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright 2010-2011 Freescale Semiconductor, Inc.
+ * Author: Dipen Dudhat 
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include 
+#include 
+
+void print_ifc_regs(void)
+{
+   int i, j;
+
+   printf("\nIFC Controller Registers\n");
+

[U-Boot] [PATCH ] powerpc/85xx: Protect all LBC code with CONFIG_FSL_LBC

2011-01-18 Thread Dipen Dudhat 
Future SoC (like the P1010) replace the LBC controller with the new IFC
(Integrated Flash Controller) so ensure we properly protect code that is
related to the LBC.

Signed-off-by: Dipen Dudhat 
Acked-by: Kumar Gala 
---
 arch/powerpc/cpu/mpc85xx/cpu.c   |9 -
 arch/powerpc/cpu/mpc85xx/speed.c |6 +-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 2f5a505..700e292 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004,2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004,2007-2011 Freescale Semiconductor, Inc.
  * (C) Copyright 2002, 2003 Motorola Inc.
  * Xianghua Xiao (x.x...@motorola.com)
  *
@@ -166,12 +166,14 @@ int checkcpu (void)
}
 #endif
 
+#if defined(CONFIG_FSL_LBC)
if (sysinfo.freqLocalBus > LCRR_CLKDIV) {
printf("LBC:%-4s MHz\n", strmhz(buf1, sysinfo.freqLocalBus));
} else {
printf("LBC: unknown (LCRR[CLKDIV] = 0x%02lx)\n",
   sysinfo.freqLocalBus);
}
+#endif
 
 #ifdef CONFIG_CPM2
printf("CPM:   %s MHz\n", strmhz(buf1, sysinfo.freqSystemBus));
@@ -284,7 +286,10 @@ void mpc85xx_reginfo(void)
 {
print_tlbcam();
print_laws();
+#if defined(CONFIG_FSL_LBC)
print_lbc_regs();
+#endif
+
 }
 
 /* Common ddr init for non-corenet fsl 85xx platforms */
@@ -330,8 +335,10 @@ phys_size_t initdram(int board_type)
ddr_enable_ecc(dram_size);
 #endif
 
+#if defined(CONFIG_FSL_LBC)
/* Some boards also have sdram on the lbc */
lbc_sdram_init();
+#endif
 
puts("DDR: ");
return dram_size;
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index dd4c6b3..f2aa8d0 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc.
  *
  * (C) Copyright 2003 Motorola Inc.
  * Xianghua Xiao, (x.x...@motorola.com)
@@ -131,7 +131,9 @@ void get_sys_info (sys_info_t * sysInfo)
 
 #else
uint plat_ratio,e500_ratio,half_freqSystemBus;
+#if defined(CONFIG_FSL_LBC)
uint lcrr_div;
+#endif
int i;
 #ifdef CONFIG_QE
u32 qe_ratio;
@@ -168,6 +170,7 @@ void get_sys_info (sys_info_t * sysInfo)
sysInfo->freqQE = qe_ratio * CONFIG_SYS_CLK_FREQ;
 #endif
 
+#if defined(CONFIG_FSL_LBC)
 #if defined(CONFIG_SYS_LBC_LCRR)
/* We will program LCRR to this value later */
lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
@@ -193,6 +196,7 @@ void get_sys_info (sys_info_t * sysInfo)
/* In case anyone cares what the unknown value is */
sysInfo->freqLocalBus = lcrr_div;
}
+#endif
 }
 
 
-- 
1.6.5.6


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[U-Boot] [PATCH v1]ppc/P1_P2_RDB: Data width for eSDHC using I2C device on P1 & P2 RDB Platforms

2009-10-14 Thread Dipen Dudhat 
On P1 and P2 RDB Platforms read the I2C EEPROM to get various board 
switch settings like NOR Flash Bank selection, SD Data width etc.

Depending on,
switch SW5[6] - select width for eSDHC 
  ON  - 4-bit [Enable eSPI]
  OFF - 8-bit [Disable eSPI]

Signed-off-by: Dipen Dudhat 
---
- applies to http://git.denx.de/u-boot.git
 board/freescale/p1_p2_rdb/p1_p2_rdb.c |   21 +
 1 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c 
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 4c03468..e3ab73c 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -130,9 +130,30 @@ int checkboard (void)
 
 int board_early_init_r(void)
 {
+   u8 i2c_data;
+   volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
const u8 flash_esel = 2;
 
+   i2c_set_bus_num(1);
+   if (i2c_read(0x18, 0, 1, &i2c_data, sizeof(i2c_data)) == 0) {
+   if (i2c_data & 0x2)
+   printf("NOR Flash Bank : Secondary\n");
+   else
+   printf("NOR Flash Bank : Primary\n");
+
+   if (i2c_data & 0x1) {
+   setbits_be32(&gur->pmuxcr,MPC85xx_PMUXCR_SD_DATA);
+   printf("SD/MMC : 8-bit Mode\n");
+   printf("eSPI : Disabled\n");
+   } else {
+   printf("SD/MMC : 4-bit Mode\n");
+   printf("eSPI : Enabled\n");
+   }
+   }
+   else
+   printf("Failed reading I2C Chip 0x18 on bus 1\n");
+
/*
 * Remap Boot flash region to caching-inhibited
 * so that flash can be erased properly.
-- 
1.5.6.3

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[U-Boot] [PATCH v3 3/3] ppc/p1_p2_RDB: DDR Relocation support for NAND/SD/eSPI Boot

2009-10-09 Thread Dipen Dudhat 
DDR support to boot from NAND/eSDHC/eSPI on P1 & P2 RDB platforms.
Specifically this support needed when L2 Cache size is less than 512K.

Signed-off-by: Dipen Dudhat 
---
- Applies to http://git.denx.de/u-boot.git
- Changes from v2: integrated kumar's comments.
 board/freescale/p1_p2_rdb/config.mk|8 +++
 board/freescale/p1_p2_rdb/ddr.c|3 +
 board/freescale/p1_p2_rdb/tlb.c|9 +++-
 include/configs/P1_P2_RDB.h|   31 
 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c |   59 
 5 files changed, 109 insertions(+), 1 deletions(-)

diff --git a/board/freescale/p1_p2_rdb/config.mk 
b/board/freescale/p1_p2_rdb/config.mk
index 0f7a048..e782928 100644
--- a/board/freescale/p1_p2_rdb/config.mk
+++ b/board/freescale/p1_p2_rdb/config.mk
@@ -33,13 +33,21 @@ endif
 
 ifeq ($(CONFIG_MK_SDCARD), y)
 TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifdef CONFIG_SYS_FSL_BOOT_DDR
+RESET_VECTOR_ADDRESS = 0x1107fffc
+else
 RESET_VECTOR_ADDRESS = 0xf8fc
 endif
+endif
 
 ifeq ($(CONFIG_MK_SPIFLASH), y)
 TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifdef CONFIG_SYS_FSL_BOOT_DDR
+RESET_VECTOR_ADDRESS = 0x1107fffc
+else
 RESET_VECTOR_ADDRESS = 0xf8fc
 endif
+endif
 
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff8
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 37c4b0a..dc967de 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -246,6 +246,9 @@ phys_size_t initdram(int board_type)
 {
phys_size_t dram_size = 0;
 
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_FSL_BOOT_DDR)
+   return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+#endif
dram_size = fixed_sdram();
set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
 
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index 0009913..c250e3e 100644
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -78,7 +78,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_INIT_L2_ADDR)
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -87,6 +88,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x4,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256K, 1),
+#else
+   /* *I*G - DDR */
+   SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 7, BOOKE_PAGESZ_1G, 1)
+#endif
 #endif
 };
 
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 310242e..dae2e8d 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -43,21 +43,40 @@
 #define CONFIG_P2020
 #endif
 
+/* Boot using DDR for eSDHC/eSPI/NAND boot because L2 Cache size
+ * on these platforms is 256K.
+ */
+#if defined(CONFIG_P1011) || defined(CONFIG_P1020)
+#define CONFIG_SYS_FSL_BOOT_DDR
+#endif
+
 #ifdef CONFIG_MK_NAND
 #define CONFIG_NAND_U_BOOT 1
 #define CONFIG_RAMBOOT_NAND1
+#ifdef CONFIG_SYS_FSL_BOOT_DDR
+#define CONFIG_RAMBOOT_TEXT_BASE   0x01001000
+#else
 #define CONFIG_RAMBOOT_TEXT_BASE   0xf8f82000
 #endif
+#endif
 
 #ifdef CONFIG_MK_SDCARD
 #define CONFIG_RAMBOOT_SDCARD  1
+#ifdef CONFIG_SYS_FSL_BOOT_DDR
+#define CONFIG_RAMBOOT_TEXT_BASE   0x1100
+#else
 #define CONFIG_RAMBOOT_TEXT_BASE   0xf8f8
 #endif
+#endif
 
 #ifdef CONFIG_MK_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH1
+#ifdef CONFIG_SYS_FSL_BOOT_DDR
+#define CONFIG_RAMBOOT_TEXT_BASE   0x1100
+#else
 #define CONFIG_RAMBOOT_TEXT_BASE   0xf8f8
 #endif
+#endif
 
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
@@ -101,6 +120,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  /*
   * Config the L2 Cache as L2 SRAM
   */
+#ifndef CONFIG_SYS_FSL_BOOT_DDR
 #define CONFIG_SYS_INIT_L2_ADDR0xf8f8
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS   0xff8f8ull
@@ -109,6 +129,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_L2_SIZE (512 << 10)
 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + 
CONFIG_SYS_L2_SIZE)
+#endif
 
 /*
  * Base addresses -- Note these are effective addresses where the
@@ -233,6 +254,15 @@ extern unsigned long get_board_sys_clk(unsigned long 
dummy);
 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
 
 /* NAND boot: 4

[U-Boot] [PATCH v2 3/3] ppc/p1_p1_RDB: DDR Relocation support for NAND/SD/eSPI Boot

2009-10-08 Thread Dipen Dudhat 
This patch adds support to boot from NAND/eSDHC/eSPI using DDR on P1 & P2 RDB 
platforms.
Specifically this support needed when L2 Cache size is less than 512K.

For this one define "CONFIG_L2_RELOC" has added in platform config file.

Signed-off-by: Dipen Dudhat 
---
- Applies to http://git.denx.de/u-boot.git
 board/freescale/p1_p2_rdb/config.mk|8 +++
 board/freescale/p1_p2_rdb/ddr.c|3 +
 board/freescale/p1_p2_rdb/tlb.c|9 +++-
 include/configs/P1_P2_RDB.h|   27 +++
 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c |   59 
 5 files changed, 105 insertions(+), 1 deletions(-)

diff --git a/board/freescale/p1_p2_rdb/config.mk 
b/board/freescale/p1_p2_rdb/config.mk
index 0f7a048..e76b59c 100644
--- a/board/freescale/p1_p2_rdb/config.mk
+++ b/board/freescale/p1_p2_rdb/config.mk
@@ -33,12 +33,20 @@ endif
 
 ifeq ($(CONFIG_MK_SDCARD), y)
 TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifdef CONFIG_L2_RELOC
 RESET_VECTOR_ADDRESS = 0xf8fc
+else
+RESET_VECTOR_ADDRESS = 0x1107F000
+endif
 endif
 
 ifeq ($(CONFIG_MK_SPIFLASH), y)
 TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+ifdef CONFIG_L2_RELOC
 RESET_VECTOR_ADDRESS = 0xf8fc
+else
+RESET_VECTOR_ADDRESS = 0x1107F000
+endif
 endif
 
 ifndef TEXT_BASE
diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c
index 37c4b0a..884ff3f 100644
--- a/board/freescale/p1_p2_rdb/ddr.c
+++ b/board/freescale/p1_p2_rdb/ddr.c
@@ -246,6 +246,9 @@ phys_size_t initdram(int board_type)
 {
phys_size_t dram_size = 0;
 
+#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_L2_RELOC)
+   return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
+#endif
dram_size = fixed_sdram();
set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
 
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index 0009913..c250e3e 100644
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -78,7 +78,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
 
-#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+#if defined(CONFIG_SYS_RAMBOOT)
+#if defined(CONFIG_SYS_INIT_L2_ADDR)
/* *I*G - L2SRAM */
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -87,6 +88,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x4,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 8, BOOKE_PAGESZ_256K, 1),
+#else
+   /* *I*G - DDR */
+   SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 7, BOOKE_PAGESZ_1G, 1)
+#endif
 #endif
 };
 
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 310242e..e8cf902 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -43,20 +43,35 @@
 #define CONFIG_P2020
 #endif
 
+/* Remove this define to Boot using DDR instead of L2 SRAM */
+#define CONFIG_L2_RELOC
+
 #ifdef CONFIG_MK_NAND
 #define CONFIG_NAND_U_BOOT 1
 #define CONFIG_RAMBOOT_NAND1
+#ifdef CONFIG_L2_RELOC
 #define CONFIG_RAMBOOT_TEXT_BASE   0xf8f82000
+#else
+#define CONFIG_RAMBOOT_TEXT_BASE   0x01001000
+#endif
 #endif
 
 #ifdef CONFIG_MK_SDCARD
 #define CONFIG_RAMBOOT_SDCARD  1
+#ifdef CONFIG_L2_RELOC
 #define CONFIG_RAMBOOT_TEXT_BASE   0xf8f8
+#else
+#define CONFIG_RAMBOOT_TEXT_BASE   0x1100
+#endif
 #endif
 
 #ifdef CONFIG_MK_SPIFLASH
 #define CONFIG_RAMBOOT_SPIFLASH1
+#ifdef CONFIG_L2_RELOC
 #define CONFIG_RAMBOOT_TEXT_BASE   0xf8f8
+#else
+#define CONFIG_RAMBOOT_TEXT_BASE   0x1100
+#endif
 #endif
 
 /* High Level Configuration Options */
@@ -101,6 +116,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
  /*
   * Config the L2 Cache as L2 SRAM
   */
+#ifdef CONFIG_L2_RELOC
 #define CONFIG_SYS_INIT_L2_ADDR0xf8f8
 #ifdef CONFIG_PHYS_64BIT
 #define CONFIG_SYS_INIT_L2_ADDR_PHYS   0xff8f8ull
@@ -109,6 +125,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #endif
 #define CONFIG_SYS_L2_SIZE (512 << 10)
 #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + 
CONFIG_SYS_L2_SIZE)
+#endif
 
 /*
  * Base addresses -- Note these are effective addresses where the
@@ -233,6 +250,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024)
 
 /* NAND boot: 4K NAND loader config */
+#ifdef CONFIG_L2_RELOC
 #define CONFIG_SYS_NAND_SPL_SIZE   0x1000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE((512 << 10) - 0x2000)
 #define CONFIG_SYS_NA

[U-Boot] [PATCH v2 2/3] ppc/P1_P2_RDB: On-chip BootROM support

2009-10-08 Thread Dipen Dudhat 
On Chip BootROM support for P1 and P2 series RDB platforms.

This patch is derived from latest On Chip BootROM support on MPC8536DS by 
Mingkai Hu.

Signed-off-by: Dipen Dudhat 
---
- Applies to http://git.denx.de/u-boot.git
 MAKEALL |8 
 Makefile|   10 +-
 board/freescale/p1_p2_rdb/config.mk |   12 
 include/configs/P1_P2_RDB.h |   17 -
 4 files changed, 45 insertions(+), 2 deletions(-)

diff --git a/MAKEALL b/MAKEALL
index cb5e3d5..2eb197b 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -396,12 +396,20 @@ LIST_85xx="   \
P2020DS_36BIT   \
P1011RDB\
P1011RDB_NAND   \
+   P1011RDB_SDCARD \
+   P1011RDB_SPIFLASH   \
P1020RDB\
P1020RDB_NAND   \
+   P1020RDB_SDCARD \
+   P1020RDB_SPIFLASH   \
P2010RDB\
P2010RDB_NAND   \
+   P2010RDB_SDCARD \
+   P2010RDB_SPIFLASH   \
P2020RDB\
P2020RDB_NAND   \
+   P2020RDB_SDCARD \
+   P2020RDB_SPIFLASH   \
PM854   \
PM856   \
sbc8540 \
diff --git a/Makefile b/Makefile
index 106fb54..f585fa0 100644
--- a/Makefile
+++ b/Makefile
@@ -2525,12 +2525,20 @@ P2020DS_config: unconfig
 
 P1011RDB_config\
 P1011RDB_NAND_config \
+P1011RDB_SDCARD_config \
+P1011RDB_SPIFLASH_config \
 P1020RDB_config\
 P1020RDB_NAND_config \
+P1020RDB_SDCARD_config \
+P1020RDB_SPIFLASH_config \
 P2010RDB_config \
 P2010RDB_NAND_config \
+P2010RDB_SDCARD_config \
+P2010RDB_SPIFLASH_config \
 P2020RDB_config \
-P2020RDB_NAND_config:  unconfig
+P2020RDB_NAND_config \
+P2020RDB_SDCARD_config \
+P2020RDB_SPIFLASH_config:  unconfig
@$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
 
 PM854_config:  unconfig
diff --git a/board/freescale/p1_p2_rdb/config.mk 
b/board/freescale/p1_p2_rdb/config.mk
index 17abcf8..0f7a048 100644
--- a/board/freescale/p1_p2_rdb/config.mk
+++ b/board/freescale/p1_p2_rdb/config.mk
@@ -31,8 +31,20 @@ LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
 endif
 endif
 
+ifeq ($(CONFIG_MK_SDCARD), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+RESET_VECTOR_ADDRESS = 0xf8fc
+endif
+
+ifeq ($(CONFIG_MK_SPIFLASH), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+RESET_VECTOR_ADDRESS = 0xf8fc
+endif
+
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff8
 endif
 
+ifndef RESET_VECTOR_ADDRESS
 RESET_VECTOR_ADDRESS = 0xeffc
+endif
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index aacd4ca..310242e 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -49,6 +49,16 @@
 #define CONFIG_RAMBOOT_TEXT_BASE   0xf8f82000
 #endif
 
+#ifdef CONFIG_MK_SDCARD
+#define CONFIG_RAMBOOT_SDCARD  1
+#define CONFIG_RAMBOOT_TEXT_BASE   0xf8f8
+#endif
+
+#ifdef CONFIG_MK_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH1
+#define CONFIG_RAMBOOT_TEXT_BASE   0xf8f8
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
@@ -182,7 +192,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_MONITOR_BASETEXT_BASE   /* start of monitor */
 
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
+   || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef CONFIG_SYS_RAMBOOT
@@ -426,6 +437,10 @@ extern unsigned long get_board_sys_clk(unsigned long 
dummy);
#define CONFIG_ENV_IS_IN_NAND   1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET   ((512 * 1024) + 
CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+   #define CONFIG_ENV_IS_NOWHERE   1   /* Store ENV in memory only */
+   #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+   #define CONFIG_ENV_SIZE 0x2000
 #endif
 #else
#define CONFIG_ENV_IS_IN_FLASH  1
-- 
1.5.6.3

___
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[U-Boot] [PATCH v2 1/3] ppc/P1_P2_RDB: NAND Boot Support

2009-10-08 Thread Dipen Dudhat 
NAND Boot support for P1 and P2 series RDB platforms.

This patch is derived from latest NAND Boot support on MPC8536DS by Mingkai Hu.

Signed-off-by: Dipen Dudhat 
---
- Applies to http://git.denx.de/u-boot.git
- Changes from v1: Integrated kumar's comments
 MAKEALL|4 +
 Makefile   |6 +-
 board/freescale/p1_p2_rdb/config.mk|7 ++
 board/freescale/p1_p2_rdb/tlb.c|   10 ++
 include/configs/P1_P2_RDB.h|   72 --
 nand_spl/board/freescale/p1_p2_rdb/Makefile|  127 
 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c |   97 ++
 7 files changed, 315 insertions(+), 8 deletions(-)
 create mode 100644 nand_spl/board/freescale/p1_p2_rdb/Makefile
 create mode 100644 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c

diff --git a/MAKEALL b/MAKEALL
index 0a54d75..cb5e3d5 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -395,9 +395,13 @@ LIST_85xx="\
P2020DS \
P2020DS_36BIT   \
P1011RDB\
+   P1011RDB_NAND   \
P1020RDB\
+   P1020RDB_NAND   \
P2010RDB\
+   P2010RDB_NAND   \
P2020RDB\
+   P2020RDB_NAND   \
PM854   \
PM856   \
sbc8540 \
diff --git a/Makefile b/Makefile
index c8a883c..106fb54 100644
--- a/Makefile
+++ b/Makefile
@@ -2524,9 +2524,13 @@ P2020DS_config:  unconfig
@$(MKCONFIG) -t $(@:_config=) P2020DS ppc mpc85xx p2020ds freescale
 
 P1011RDB_config\
+P1011RDB_NAND_config \
 P1020RDB_config\
+P1020RDB_NAND_config \
 P2010RDB_config \
-P2020RDB_config:   unconfig
+P2010RDB_NAND_config \
+P2020RDB_config \
+P2020RDB_NAND_config:  unconfig
@$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
 
 PM854_config:  unconfig
diff --git a/board/freescale/p1_p2_rdb/config.mk 
b/board/freescale/p1_p2_rdb/config.mk
index a56b536..17abcf8 100644
--- a/board/freescale/p1_p2_rdb/config.mk
+++ b/board/freescale/p1_p2_rdb/config.mk
@@ -24,6 +24,13 @@
 # p1_p2rdb board
 #
 
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+endif
+endif
+
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff8
 endif
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index cf9bffe..0009913 100644
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -78,6 +78,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
 
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+   /* *I*G - L2SRAM */
+   SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 7, BOOKE_PAGESZ_256K, 1),
+   SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x4,
+   CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x4,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 8, BOOKE_PAGESZ_256K, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 8e97ad0..aacd4ca 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -43,6 +43,12 @@
 #define CONFIG_P2020
 #endif
 
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT 1
+#define CONFIG_RAMBOOT_NAND1
+#define CONFIG_RAMBOOT_TEXT_BASE   0xf8f82000
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
@@ -82,16 +88,34 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_MEMTEST_END 0x1fff
 #define CONFIG_PANIC_HANG  /* do not reset board on panic */
 
+ /*
+  * Config the L2 Cache as L2 SRAM
+  */
+#define CONFIG_SYS_INIT_L2_ADDR0xf8f8
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS   0xff8f8ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS   CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE (512 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + 
CONFIG_SYS_L2_SIZE)
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70  /* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR 0xffe0  /* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYSCONFIG_SYS_CCSRBAR  /* physical 
addr of */
/* CCSRBAR */
 #define CONFIG_SYS_IMMR

[U-Boot] [PATCH v1]ppc/P1_P2_RDB: On-chip ROM boot

2009-10-05 Thread Dipen Dudhat 
On Chip BootROM support for P1 and P2 series RDB platforms.

This patch is derived from latest On Chip BootROM support on MPC8536DS by 
Mingkai Hu.

Signed-off-by: Dipen Dudhat 
---
- Applies to http://git.denx.de/u-boot.git
 MAKEALL |2 ++
 Makefile|2 ++
 board/freescale/p1_p2_rdb/config.mk |   12 
 include/configs/P1_P2_RDB.h |   17 -
 4 files changed, 32 insertions(+), 1 deletions(-)

diff --git a/MAKEALL b/MAKEALL
index de81c93..3daee59 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -399,6 +399,8 @@ LIST_85xx=" \
P2010RDB\
P2020RDB\
P2020RDB_NAND   \
+   P2020RDB_SDCARD \
+   P2020RDB_SPIFLASH   \
PM854   \
PM856   \
sbc8540 \
diff --git a/Makefile b/Makefile
index 652d930..9afb145 100644
--- a/Makefile
+++ b/Makefile
@@ -2527,6 +2527,8 @@ P1011RDB_config   \
 P1020RDB_config\
 P2010RDB_config \
 P2020RDB_NAND_config \
+P2020RDB_SDCARD_config \
+P2020RDB_SPIFLASH_config \
 P2020RDB_config:   unconfig
@$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
 
diff --git a/board/freescale/p1_p2_rdb/config.mk 
b/board/freescale/p1_p2_rdb/config.mk
index 17abcf8..0f7a048 100644
--- a/board/freescale/p1_p2_rdb/config.mk
+++ b/board/freescale/p1_p2_rdb/config.mk
@@ -31,8 +31,20 @@ LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
 endif
 endif
 
+ifeq ($(CONFIG_MK_SDCARD), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+RESET_VECTOR_ADDRESS = 0xf8fc
+endif
+
+ifeq ($(CONFIG_MK_SPIFLASH), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+RESET_VECTOR_ADDRESS = 0xf8fc
+endif
+
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff8
 endif
 
+ifndef RESET_VECTOR_ADDRESS
 RESET_VECTOR_ADDRESS = 0xeffc
+endif
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index aacd4ca..310242e 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -49,6 +49,16 @@
 #define CONFIG_RAMBOOT_TEXT_BASE   0xf8f82000
 #endif
 
+#ifdef CONFIG_MK_SDCARD
+#define CONFIG_RAMBOOT_SDCARD  1
+#define CONFIG_RAMBOOT_TEXT_BASE   0xf8f8
+#endif
+
+#ifdef CONFIG_MK_SPIFLASH
+#define CONFIG_RAMBOOT_SPIFLASH1
+#define CONFIG_RAMBOOT_TEXT_BASE   0xf8f8
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
@@ -182,7 +192,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 
 #define CONFIG_SYS_MONITOR_BASETEXT_BASE   /* start of monitor */
 
-#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND)
+#if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \
+   || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
 #define CONFIG_SYS_RAMBOOT
 #else
 #undef CONFIG_SYS_RAMBOOT
@@ -426,6 +437,10 @@ extern unsigned long get_board_sys_clk(unsigned long 
dummy);
#define CONFIG_ENV_IS_IN_NAND   1
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET   ((512 * 1024) + 
CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
+   #define CONFIG_ENV_IS_NOWHERE   1   /* Store ENV in memory only */
+   #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
+   #define CONFIG_ENV_SIZE 0x2000
 #endif
 #else
#define CONFIG_ENV_IS_IN_FLASH  1
-- 
1.5.6.3

___
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U-Boot@lists.denx.de
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[U-Boot] [PATCH v1] ppc/P1_P2_RDB: NAND Boot Support

2009-10-05 Thread Dipen Dudhat 
NAND Boot support for P1 and P2 series RDB platforms.

This patch is derived from latest NAND Boot support on MPC8536DS by Mingkai Hu.

Signed-off-by: Dipen Dudhat 
---
- Applies to http://git.denx.de/u-boot.git
 MAKEALL|1 +
 Makefile   |1 +
 board/freescale/p1_p2_rdb/config.mk|7 ++
 board/freescale/p1_p2_rdb/tlb.c|   10 ++
 include/configs/P1_P2_RDB.h|   72 +--
 nand_spl/board/freescale/p1_p2_rdb/Makefile|  123 
 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c |   97 +++
 7 files changed, 304 insertions(+), 7 deletions(-)
 create mode 100644 nand_spl/board/freescale/p1_p2_rdb/Makefile
 create mode 100644 nand_spl/board/freescale/p1_p2_rdb/nand_boot.c

diff --git a/MAKEALL b/MAKEALL
index 0a54d75..de81c93 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -398,6 +398,7 @@ LIST_85xx=" \
P1020RDB\
P2010RDB\
P2020RDB\
+   P2020RDB_NAND   \
PM854   \
PM856   \
sbc8540 \
diff --git a/Makefile b/Makefile
index c8a883c..652d930 100644
--- a/Makefile
+++ b/Makefile
@@ -2526,6 +2526,7 @@ P2020DS_config:   unconfig
 P1011RDB_config\
 P1020RDB_config\
 P2010RDB_config \
+P2020RDB_NAND_config \
 P2020RDB_config:   unconfig
@$(MKCONFIG) -t $(@:_config=) P1_P2_RDB ppc mpc85xx p1_p2_rdb freescale
 
diff --git a/board/freescale/p1_p2_rdb/config.mk 
b/board/freescale/p1_p2_rdb/config.mk
index a56b536..17abcf8 100644
--- a/board/freescale/p1_p2_rdb/config.mk
+++ b/board/freescale/p1_p2_rdb/config.mk
@@ -24,6 +24,13 @@
 # p1_p2rdb board
 #
 
+ifndef NAND_SPL
+ifeq ($(CONFIG_MK_NAND), y)
+TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
+LDSCRIPT := $(TOPDIR)/cpu/$(CPU)/u-boot-nand.lds
+endif
+endif
+
 ifndef TEXT_BASE
 TEXT_BASE = 0xeff8
 endif
diff --git a/board/freescale/p1_p2_rdb/tlb.c b/board/freescale/p1_p2_rdb/tlb.c
index cf9bffe..0009913 100644
--- a/board/freescale/p1_p2_rdb/tlb.c
+++ b/board/freescale/p1_p2_rdb/tlb.c
@@ -78,6 +78,16 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 6, BOOKE_PAGESZ_1M, 1),
 
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
+   /* *I*G - L2SRAM */
+   SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 7, BOOKE_PAGESZ_256K, 1),
+   SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x4,
+   CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x4,
+   MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+   0, 8, BOOKE_PAGESZ_256K, 1),
+#endif
 };
 
 int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h
index 8e97ad0..aacd4ca 100644
--- a/include/configs/P1_P2_RDB.h
+++ b/include/configs/P1_P2_RDB.h
@@ -43,6 +43,12 @@
 #define CONFIG_P2020
 #endif
 
+#ifdef CONFIG_MK_NAND
+#define CONFIG_NAND_U_BOOT 1
+#define CONFIG_RAMBOOT_NAND1
+#define CONFIG_RAMBOOT_TEXT_BASE   0xf8f82000
+#endif
+
 /* High Level Configuration Options */
 #define CONFIG_BOOKE   1   /* BOOKE */
 #define CONFIG_E5001   /* BOOKE e500 family */
@@ -82,16 +88,34 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
 #define CONFIG_SYS_MEMTEST_END 0x1fff
 #define CONFIG_PANIC_HANG  /* do not reset board on panic */
 
+ /*
+  * Config the L2 Cache as L2 SRAM
+  */
+#define CONFIG_SYS_INIT_L2_ADDR0xf8f8
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS   0xff8f8ull
+#else
+#define CONFIG_SYS_INIT_L2_ADDR_PHYS   CONFIG_SYS_INIT_L2_ADDR
+#endif
+#define CONFIG_SYS_L2_SIZE (512 << 10)
+#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + 
CONFIG_SYS_L2_SIZE)
+
 /*
  * Base addresses -- Note these are effective addresses where the
  * actual resources get mapped (not physical addresses)
  */
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70  /* CCSRBAR Default */
 #define CONFIG_SYS_CCSRBAR 0xffe0  /* relocated CCSRBAR */
 #define CONFIG_SYS_CCSRBAR_PHYSCONFIG_SYS_CCSRBAR  /* physical 
addr of */
/* CCSRBAR */
 #define CONFIG_SYS_IMMRCONFIG_SYS_CCSRBAR  /* PQII uses */
/* CONFIG_SYS_IMMR */
+
+#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL)
+#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR
+#else
+#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff70  /* CCSRBAR Default */
+#endif
+
 #define CONFIG_SYS_PCIE2_ADDR  (CONFIG_S

[U-Boot] [PATCH v3] ppc/85xx: PIO Support for FSL eSDHC Controller Driver

2009-10-05 Thread Dipen Dudhat 
On some Freescale SoC Internal DMA of eSDHC controller has bug.
So PIO Mode has been introduced to do data transfer using CPU.

Signed-off-by: Dipen Dudhat 
---
Changes from v2:
- Integated wolfgang and Bin Meng's Comments.
 drivers/mmc/fsl_esdhc.c |   87 +-
 include/fsl_esdhc.h |2 +
 2 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 27e4c48..b510bf3 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -73,8 +73,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
uint xfertyp = 0;
 
if (data) {
-   xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
-
+   xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   xfertyp |= XFERTYP_DMAEN;
+#endif
if (data->blocks > 1) {
xfertyp |= XFERTYP_MSBSEL;
xfertyp |= XFERTYP_BCEN;
@@ -98,12 +100,88 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static int
+esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
+{
+   struct fsl_esdhc *regs = mmc->priv;
+   uint blocks;
+   char *buffer;
+   uint databuf;
+   uint size;
+   uint irqstat;
+   uint timeout;
+
+   if (data->flags & MMC_DATA_READ) {
+   blocks = data->blocks;
+   buffer = data->dest;
+   while (blocks) {
+   timeout = PIO_TIMEOUT;
+   size = data->blocksize;
+   irqstat = in_be32(®s->irqstat);
+   while (!(in_be32(®s->prsstat) & PRSSTAT_BREN)
+   && --timeout);
+   if (timeout <= 0) {
+   printf("\nData Read Failed in PIO Mode.");
+   return timeout;
+   }
+   while (size && (!(irqstat & IRQSTAT_TC))) {
+   udelay(100); /* Wait before last byte transfer 
complete */
+   irqstat = in_be32(®s->irqstat);
+   databuf = in_le32(®s->datport);
+   *((uint *)buffer) = databuf;
+   buffer += 4;
+   size -= 4;
+   }
+   blocks--;
+   }
+   } else {
+   blocks = data->blocks;
+   buffer = data->src;
+   while (blocks) {
+   timeout = PIO_TIMEOUT;
+   size = data->blocksize;
+   irqstat = in_be32(®s->irqstat);
+   while (!(in_be32(®s->prsstat) & PRSSTAT_BWEN)
+   && --timeout);
+   if (timeout <= 0) {
+   printf("\nData Write Failed in PIO Mode.");
+   return timeout;
+   }
+   while (size && (!(irqstat & IRQSTAT_TC))) {
+   udelay(100); /* Wait before last byte transfer 
complete */
+   databuf = *((uint *)buffer);
+   buffer += 4;
+   size -= 4;
+   irqstat = in_be32(®s->irqstat);
+   out_le32(®s->datport, databuf);
+   }
+   blocks--;
+   }
+   }
+}
+#endif
+
 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 {
uint wml_value;
int timeout;
struct fsl_esdhc *regs = mmc->priv;
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   if (!(data->flags & MMC_DATA_READ)) {
+   if ((in_be32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
+   printf("\nThe SD card is locked. "
+   "Can not write to a locked card.\n\n");
+   return TIMEOUT;
+   }
+   out_be32(®s->dsaddr, (u32)data->src);
+   } else
+   out_be32(®s->dsaddr, (u32)data->dest);
+#else
wml_value = data->blocksize/4;
 
if (data->flags & MMC_DATA_READ) {
@@ -125,6 +203,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
}
 
out_be32(®s->wml, wml_value);
+#endif
 
out_be32(®s->blkattr, data->blocks << 16 | data->blocksize);
 
@@ -217,6 +296,9 @@ esdhc_send_cmd(struct mmc *mmc, s

[U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver

2009-09-13 Thread Dipen Dudhat 
On some Freescale SoC Internal DMA of eSDHC controller has bug.

So PIO Mode has introduced to do data transfer using CPU.
In PIO mode data transfer performance will be degraded by a large extent.

Note: 
In PIO mode multiple block read/write requires delay to complete the transfer.

Signed-off-by: Dipen Dudhat 
---
Changes from v1:
- Integrated comments for error handling
- Formatting errors removed
 drivers/mmc/fsl_esdhc.c |   87 +-
 include/fsl_esdhc.h |2 +
 2 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 27e4c48..7db8c0c 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -73,8 +73,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
uint xfertyp = 0;
 
if (data) {
-   xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
-
+   xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   xfertyp |= XFERTYP_DMAEN;
+#endif
if (data->blocks > 1) {
xfertyp |= XFERTYP_MSBSEL;
xfertyp |= XFERTYP_BCEN;
@@ -98,12 +100,88 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static int
+esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
+{
+   struct fsl_esdhc *regs = mmc->priv;
+   uint blocks;
+   char *buffer;
+   uint databuf;
+   uint size;
+   uint irqstat;
+   uint timeout;
+
+   if (data->flags & MMC_DATA_READ) {
+   blocks = data->blocks;
+   buffer = data->dest;
+   while (blocks) {
+   timeout = MAX_TIMEOUT;
+   size = data->blocksize;
+   irqstat = in_be32(®s->irqstat);
+   while (!(in_be32(®s->prsstat) & PRSSTAT_BREN)
+   && --timeout);
+   if (timeout <= 0) {
+   printf("\nData Read Failed in PIO Mode.");
+   return TIMEOUT;
+   }
+   while (size && (!(irqstat & IRQSTAT_TC))) {
+   udelay(100);
+   irqstat = in_be32(®s->irqstat);
+   databuf = in_le32(®s->datport);
+   *((uint *)buffer) = databuf;
+   buffer += 4;
+   size -= 4;
+   }
+   blocks--;
+   }
+   } else {
+   blocks = data->blocks;
+   buffer = data->src;
+   while (blocks) {
+   timeout = MAX_TIMEOUT;
+   size = data->blocksize;
+   irqstat = in_be32(®s->irqstat);
+   while (!(in_be32(®s->prsstat) & PRSSTAT_BWEN)
+   && --timeout);
+   if (timeout <= 0) {
+   printf("\nData Write Failed in PIO Mode.");
+   return TIMEOUT;
+   }
+   while (size && (!(irqstat & IRQSTAT_TC))) {
+   udelay(100);
+   databuf = *((uint *)buffer);
+   buffer += 4;
+   size -= 4;
+   irqstat = in_be32(®s->irqstat);
+   out_le32(®s->datport, databuf);
+   }
+   blocks--;
+   }
+   }
+}
+#endif
+
 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 {
uint wml_value;
int timeout;
struct fsl_esdhc *regs = mmc->priv;
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   if (!(data->flags & MMC_DATA_READ)) {
+   if ((in_be32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
+   printf("\nThe SD card is locked. "
+   "Can not write to a locked card.\n\n");
+   return TIMEOUT;
+   }
+   out_be32(®s->dsaddr, (u32)data->src);
+   } else
+   out_be32(®s->dsaddr, (u32)data->dest);
+#else
wml_value = data->blocksize/4;
 
if (data->flags & MMC_DATA_READ) {
@@ -125,6 +203,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
}
 
out_be32(®s->wml, wml_value);
+#endif
 
out_be32(®s->blkattr, data->blocks << 1

[U-Boot] [PATCH v2] ppc/85xx: PIO Support for FSL eSDHC Controller Driver

2009-09-10 Thread Dipen Dudhat 
On some Freescale SoC Internal DMA of eSDHC controller has bug.

So PIO Mode has introduced to do data transfer using CPU.
In PIO mode data transfer performance will be degraded by a large extent.

Note: 
In PIO mode multiple block read/write requires delay to complete the transfer.

Signed-off-by: Dipen Dudhat 
---
 drivers/mmc/fsl_esdhc.c |   87 +-
 include/fsl_esdhc.h |2 +
 2 files changed, 87 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 27e4c48..7db8c0c 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -73,8 +73,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
uint xfertyp = 0;
 
if (data) {
-   xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
-
+   xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   xfertyp |= XFERTYP_DMAEN;
+#endif
if (data->blocks > 1) {
xfertyp |= XFERTYP_MSBSEL;
xfertyp |= XFERTYP_BCEN;
@@ -98,12 +100,88 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static int
+esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
+{
+   struct fsl_esdhc *regs = mmc->priv;
+   uint blocks;
+   char *buffer;
+   uint databuf;
+   uint size;
+   uint irqstat;
+   uint timeout;
+
+   if (data->flags & MMC_DATA_READ) {
+   blocks = data->blocks;
+   buffer = data->dest;
+   while (blocks) {
+   timeout = MAX_TIMEOUT;
+   size = data->blocksize;
+   irqstat = in_be32(®s->irqstat);
+   while (!(in_be32(®s->prsstat) & PRSSTAT_BREN)
+   && --timeout);
+   if (timeout <= 0) {
+   printf("\nData Read Failed in PIO Mode.");
+   return TIMEOUT;
+   }
+   while (size && (!(irqstat & IRQSTAT_TC))) {
+   udelay(100);
+   irqstat = in_be32(®s->irqstat);
+   databuf = in_le32(®s->datport);
+   *((uint *)buffer) = databuf;
+   buffer += 4;
+   size -= 4;
+   }
+   blocks--;
+   }
+   } else {
+   blocks = data->blocks;
+   buffer = data->src;
+   while (blocks) {
+   timeout = MAX_TIMEOUT;
+   size = data->blocksize;
+   irqstat = in_be32(®s->irqstat);
+   while (!(in_be32(®s->prsstat) & PRSSTAT_BWEN)
+   && --timeout);
+   if (timeout <= 0) {
+   printf("\nData Write Failed in PIO Mode.");
+   return TIMEOUT;
+   }
+   while (size && (!(irqstat & IRQSTAT_TC))) {
+   udelay(100);
+   databuf = *((uint *)buffer);
+   buffer += 4;
+   size -= 4;
+   irqstat = in_be32(®s->irqstat);
+   out_le32(®s->datport, databuf);
+   }
+   blocks--;
+   }
+   }
+}
+#endif
+
 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 {
uint wml_value;
int timeout;
struct fsl_esdhc *regs = mmc->priv;
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   if (!(data->flags & MMC_DATA_READ)) {
+   if ((in_be32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
+   printf("\nThe SD card is locked. "
+   "Can not write to a locked card.\n\n");
+   return TIMEOUT;
+   }
+   out_be32(®s->dsaddr, (u32)data->src);
+   } else
+   out_be32(®s->dsaddr, (u32)data->dest);
+#else
wml_value = data->blocksize/4;
 
if (data->flags & MMC_DATA_READ) {
@@ -125,6 +203,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
}
 
out_be32(®s->wml, wml_value);
+#endif
 
out_be32(®s->blkattr, data->blocks << 16 | data->blocksize);
 
@@ -217,6 +296,9 @@ esdhc_send_cmd(struct mmc *mmc, struct

[U-Boot] [PATCH v1] ppc/85xx: PIO Support for FSL eSDHC Controller Driver

2009-09-09 Thread Dipen Dudhat 
PIO Mode Support for eSDHC Controller Driver on Freescale SoCs.

Signed-off-by: Dipen Dudhat 
---
- applies on git.denx.de/u-boot-mpc85xx.git branch->next
 drivers/mmc/fsl_esdhc.c |   80 +-
 include/fsl_esdhc.h |2 +
 2 files changed, 80 insertions(+), 2 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index c6e9e6e..f02fc8a 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -73,8 +73,10 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
uint xfertyp = 0;
 
if (data) {
-   xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
-
+   xfertyp |= XFERTYP_DPSEL;
+#ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   xfertyp |= XFERTYP_DMAEN;
+#endif
if (data->blocks > 1) {
xfertyp |= XFERTYP_MSBSEL;
xfertyp |= XFERTYP_BCEN;
@@ -98,12 +100,80 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+static int
+esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
+{
+   struct fsl_esdhc *regs = mmc->priv;
+   uint blocks;
+   char *buffer;
+   uint databuf;
+   uint size;
+   uint irqstat;
+   uint timeout;
+
+   if (data->flags & MMC_DATA_READ) {
+   blocks = data->blocks;
+   buffer = data->dest;
+   while (blocks) {
+   size = data->blocksize;
+   while (size && (!(irqstat & IRQSTAT_TC))) {
+   udelay(1000);
+   irqstat = in_be32(®s->irqstat);
+   databuf = in_le32(®s->datport);
+   *((uint *)buffer) = databuf;
+   buffer += 4;
+   size -= 4;
+   }
+   blocks--;
+   }
+   } else {
+   blocks = data->blocks;
+   buffer = data->src;
+   while (blocks) {
+   timeout = MAX_TIMEOUT;
+   size = data->blocksize;
+   irqstat = in_be32(®s->irqstat);
+   while (!(in_be32(®s->prsstat) & PRSSTAT_BWEN) && 
--timeout);
+   if (timeout <= 0) {
+   printf("\nData Write Failed in PIO Mode.");
+   return TIMEOUT;
+   } else {
+   while (size && (!(irqstat & IRQSTAT_TC))) {
+   databuf = *((uint *)buffer);
+   buffer += 4;
+   size -= 4;
+   udelay(1000);
+   irqstat = in_be32(®s->irqstat);
+   out_le32(®s->datport, databuf);
+   }
+   }
+   blocks--;
+   }
+   }
+}
+#endif
+
 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 {
uint wml_value;
int timeout;
struct fsl_esdhc *regs = mmc->priv;
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   if (!(data->flags & MMC_DATA_READ)) {
+   if ((in_be32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
+   printf("\nThe SD card is locked. "
+   "Can not write to a locked card.\n\n");
+   return TIMEOUT;
+   }
+   out_be32(®s->dsaddr, (u32)data->src);
+   } else
+   out_be32(®s->dsaddr, (u32)data->dest);
+#else
wml_value = data->blocksize/4;
 
if (data->flags & MMC_DATA_READ) {
@@ -125,6 +195,7 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
}
 
out_be32(®s->wml, wml_value);
+#endif
 
out_be32(®s->blkattr, data->blocks << 16 | data->blocksize);
 
@@ -201,6 +272,7 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct 
mmc_data *data)
return TIMEOUT;
 
/* Copy the response to the response buffer */
+   udelay(1000);
if (cmd->resp_type & MMC_RSP_136) {
u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
 
@@ -217,6 +289,9 @@ esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct 
mmc_data *data)
 
/* Wait until all of the blocks are transferred */
if (data) {
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   esdhc_pio_read_write(mm

[U-Boot] [PATCH][v1] ppc/85xx: Fix up eSDHC controller clock frequency in the device tree

2009-09-01 Thread Dipen Dudhat 
Signed-off-by: Dipen Dudhat 
Acked-by: Kumar Gala 
---
- applies on http://git.denx.de/u-boot-mpc85xx.git branch->next
 cpu/mpc85xx/fdt.c |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index 53b184f..73886bd 100644
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -352,4 +352,8 @@ void ft_cpu_setup(void *blob, bd_t *bd)
ft_fixup_num_cores(blob);
 
ft_fixup_cache(blob);
+
+#if defined(CONFIG_FSL_ESDHC)
+   fdt_fixup_esdhc(blob, bd);
+#endif
 }
-- 
1.5.6.3

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[U-Boot] [PATCH][v1] ppc/85xx: Fix up eSDHC controller clock frequency in the device tree for P1 & P2 RDB platforms

2009-09-01 Thread Dipen Dudhat 
Fix up eSDHC controller clock frequency in the device tree for P1 & P2 RDB 
platforms

Signed-off-by: Dipen Dudhat 
---
- applies on git.denx.de/u-boot-mpc85xx.git branch->next
 board/freescale/p1_p2_rdb/p1_p2_rdb.c |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/board/freescale/p1_p2_rdb/p1_p2_rdb.c 
b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
index 4c03468..4d99e43 100644
--- a/board/freescale/p1_p2_rdb/p1_p2_rdb.c
+++ b/board/freescale/p1_p2_rdb/p1_p2_rdb.c
@@ -209,6 +209,9 @@ void ft_board_setup(void *blob, bd_t *bd)
size = getenv_bootm_size();
 
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#ifdef CONFIG_FSL_ESDHC
+   fdt_fixup_esdhc(blob, bd);
+#endif
 }
 #endif
 
-- 
1.5.6.3

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[U-Boot] [PATCH][v1] ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clk

2009-09-01 Thread Dipen Dudhat 
Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a 
platform define.
This will enable all the 85xx platforms to use sdhc_clk based on 
CONFIG_FSL_ESDHC.

Signed-off-by: Gao Guanhua 
Signed-off-by: Dipen Dudhat 
---
- applies on git.denx.de/u-boot-mpc85xx.git branch->next
 cpu/mpc85xx/speed.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/cpu/mpc85xx/speed.c b/cpu/mpc85xx/speed.c
index 3ef49b4..2fdcefb 100644
--- a/cpu/mpc85xx/speed.c
+++ b/cpu/mpc85xx/speed.c
@@ -153,7 +153,7 @@ int get_clocks (void)
 #endif
gd->i2c2_clk = gd->i2c1_clk;
 
-#if defined(CONFIG_MPC8536)
+#if defined(CONFIG_FSL_ESDHC)
gd->sdhc_clk = gd->bus_clk / 2;
 #endif
 
-- 
1.5.6.3

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[U-Boot] [PATCH] PIO Mode Read/Write support for FSL eSDHC

2009-04-03 Thread Dipen Dudhat 
PIO mode support for freescale eSDHC Driver.
PIO has added to enable data transfer without use of eSDHC DMA Engine.

Signed-off-by: Dipen Dudhat 
---
 drivers/mmc/fsl_esdhc.c |  136 +++
 include/fsl_esdhc.h |1 +
 2 files changed, 127 insertions(+), 10 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 0ba45cd..c96011f 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -71,8 +71,12 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
uint xfertyp = 0;
 
if (data) {
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+   xfertyp |= XFERTYP_DPSEL;
+#else
xfertyp |= XFERTYP_DPSEL | XFERTYP_DMAEN;
 
+#endif
if (data->blocks > 1) {
xfertyp |= XFERTYP_MSBSEL;
xfertyp |= XFERTYP_BCEN;
@@ -96,6 +100,102 @@ uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data 
*data)
return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
 }
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+static int esdhc_setup_pio_data(struct mmc *mmc, struct mmc_data *data)
+{
+   int timeout;
+   struct fsl_esdhc *regs = mmc->priv;
+
+   if (!(data->flags & MMC_DATA_READ)) {
+   if ((in_be32(®s->prsstat) & PRSSTAT_WPSPL) == 0) {
+   printf("\nThe SD card is locked. "
+   "Can not write to a locked card.\n\n");
+   return TIMEOUT;
+   }
+   out_be32(®s->dsaddr, (u32)data->src);
+   } else
+   out_be32(®s->dsaddr, (u32)data->dest);
+
+   out_be32(®s->blkattr, data->blocks << 16 | data->blocksize);
+
+   /* Calculate the timeout period for data transactions */
+   timeout = __ilog2(mmc->tran_speed/10);
+   timeout -= 13;
+
+   if (timeout > 14)
+   timeout = 14;
+
+   if (timeout < 0)
+   timeout = 0;
+
+   clrsetbits_be32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
+
+   return 0;
+}
+
+/*
+ * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
+ */
+
+static void
+esdhc_pio_read_write(struct mmc *mmc, struct mmc_data *data)
+{
+   volatile struct fsl_esdhc *regs = mmc->priv;
+   uint blocks;
+   uchar* buffer;
+   uint chunk_remain;
+   uint databuf;
+   uint size,irqstat;
+
+   if (data->flags & MMC_DATA_READ) {
+   blocks = data->blocks;
+   buffer = (uchar*) data->dest;
+   chunk_remain = 0;
+   while(blocks) {
+   size = data->blocksize;
+   irqstat = in_be32(®s->irqstat);
+   while(!(in_be32(®s->prsstat) & PRSSTAT_BREN));
+   while(size && (!(irqstat & IRQSTAT_TC))) {
+   if(chunk_remain == 0) {
+   udelay(1000);
+   irqstat = in_be32(®s->irqstat);
+   databuf = in_be32(®s->datport);
+   chunk_remain =4;
+   }
+   *buffer = databuf & 0xFF;
+   buffer++;
+   databuf >>= 8;
+   size--;
+   chunk_remain--;
+   }
+   blocks--;
+   }
+   } else {
+   blocks = data->blocks;
+   buffer = (uchar*) data->src;
+   chunk_remain = 4;
+   while(blocks) {
+   size = data->blocksize;
+   irqstat = in_be32(®s->irqstat);
+   while(!(in_be32(®s->prsstat) & PRSSTAT_BWEN));
+   while(size && (!(irqstat & IRQSTAT_TC))) {
+   databuf >>=8;
+   databuf |= (u32)*buffer<<24;
+   buffer++;
+   size--;
+   chunk_remain--;
+   if(chunk_remain == 0) {
+   irqstat = in_be32(®s->irqstat);
+   out_be32(®s->datport,databuf);
+   chunk_remain =4;
+   }
+   }
+   blocks--;
+   }
+   }
+}
+#endif
+
 static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data)
 {
uint wml_value;
@@ -141,6 +241,23 @@ static int esdhc_setup_data(struct mmc *mmc, struct 
mmc_data *data)
return 0;
 }
 
+static void
+esdhc_dma_read_write(s