Re: [U-Boot] [PATCH] armv8: ls1012a: Updating CONFIG_EXTRA_ENV_SETTINGS
From: york sun: > On 08/05/2016 02:47 AM, Pratiyush Mohan Srivastava wrote: >> Remove ramdisk_addr, ramdisk_size and update UART baud-rate. >> ... >> +++ b/include/configs/ls1012a_common.h ... >> - "ramdisk_addr=0x80\0" \ >> - "ramdisk_size=0x200\0" \ >> "fdt_high=0x\0" \ >> "initrd_high=0x\0" \ While you are fixing these, can you remove the earlier 32-bit initrd_high=0x? >> - "console=ttyAMA0,38400n8\0" >> + "console=ttyAMA0,115200n8\0" > Is console variable correct here? Might as well just delete it since $console is not used in BOOTARGS. Ed ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] armv8: Enable CPUECTLR.SMPEN for data coherency
From: Prabhakar Kushwaha >> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of york >> On 06/30/2016 02:03 AM, Gong Qianyu wrote: >> > From: Mingkai Hu >> > >> > Data coherency is enabled only when the CPUECTLR.SMPEN bit is set. >> > The SMPEN bit should be set before enabling the data cache. >> > If not enabled, the cache is not coherent with other cores and data >> > corruption could occur. >> > >> > + /* Enalbe SMPEN bit */ >> > + mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ >> > + orr x0, x0, #0x40 >> > + msr S3_1_c15_c2_1, x0 >> > + >> >> I wonder what impact this patch has. Did you find it effective on A53 core? >> According to ARM documents, A57 and A72 seem don't care this bit. > >I have seen big difference on LS1012A with A53 cores after enabling this bit. >If I don't enable this bit many IPs like SATA, SDHC show coherency issue. But LS1012A only has a single A53 core. The multicore part, LS1043A, sets this bit in the bootrom: 34: d539f221mrs x1, s3_1_c15_c2_1 38: b27a0021orr x1, x1, #0x40 3c: d519f221msr s3_1_c15_c2_1, x1 Ed ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [u-boot-release] [PATCH 06/10][v3] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
From: York Sun [mailto:york@nxp.com]
> On 05/17/2016 09:35 AM, Edward L Swarthout wrote:
> > From: Prabhakar Kushwaha:
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> >> + unsigned int svr, ver;
> > ...
> >> + svr = gur_in32(&gur->svr);
> >> + ver = SVR_SOC_VER(svr);
> >> + if (ver == SVR_LS1012) {
> >> + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> >
> > Why introduce a run-time check for every board when this could be handled
> > at compile time?
> >
> Do you mean the platform PLL is fixed and not controlled by RCW?
I mean use "#ifdef CONFIG_LS1012A" instead of reading and comparing SVR at
run-time.
(Note: the platform ratio is controlled by the RCW - it's just that only 4:1 is
currently documented)
LS1012 is unique in that the core frequency is not based on sysclk but its own
CGA_CLK_FREQ.
Instead of twisting the meaning of CONFIG_SYS_CLK_FREQ and CONFIG_DDR_CLK_FREQ
as the code does here, how about introducing CONFIG_CGA_CLK_FREQ for the
freq_processor calculation?
Ed
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Re: [U-Boot] [u-boot-release] [PATCH 06/10][v3] armv8: fsl-layerscape: Add support of QorIQ LS1012A SoC
From: Prabhakar Kushwaha:
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c
> unsigned int cpu;
> + unsigned int svr, ver;
> const u8 core_cplx_pll[8] = {
...
> - FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK;
> + svr = gur_in32(&gur->svr);
> + ver = SVR_SOC_VER(svr);
> + if (ver == SVR_LS1012) {
> + sys_info->freq_ddrbus *= (gur_in32(&gur->rcwsr[0]) >>
> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
> + } else {
> + sys_info->freq_systembus *= (gur_in32(&gur->rcwsr[0]) >>
> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_SHIFT) &
> + FSL_CHASSIS2_RCWSR0_SYS_PLL_RAT_MASK;
Why introduce a run-time check for every board when this could be handled at
compile time?
Ed
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Re: [U-Boot] [PATCH 8/9][v2] armv8: ls1012a: Add support of ls1012aqds board
From: York Sun > On 05/11/2016 12:30 AM, Prabhakar Kushwaha wrote: > > QorIQ LS1012A Development System (LS1012AQDS) is a high-performance > >... > > +++ b/include/configs/ls1012a_common.h > >... > > +#define CONFIG_SYS_CLK_FREQ 1 > > +#define CONFIG_DDR_CLK_FREQ 12500 > > Hard-coded value? Are the clocks board-specfic? There is no separate DDR clock input, so the DDR frequency should be derived from SYS_CLK and it can only be 4x. > > + > > +/* Generic Timer Definitions */ > > +#define COUNTER_FREQUENCY2500/* 12MHz */ > > Does this timer has a dedicated clock source? This should be > CONFIG_SYS_CLK_FREQ/4, right? Isn't it also board-specific? The SOC RM section 7.1.1.5.2 says it always SYSCLK_FREQ/4, so doesn't this belong in arch-fsl-layerscape/config.h? > > +++ b/include/configs/ls1012aqds.h > > +#include "ls1012a_common.h" > > Shouldn't sysclk/ddrclk be put here? Yes. In addition, the SYS_CLK on the QDS can be controlled with a fine granularity and the actual frequency can be obtained from the QIXIS FPGA. Patch 5 in this series wasn't commented on, but it adds LS1012 specif hacks to the supposedly generic fsl_lsch2_speed function to compute freq_systembus and freq_ddrbus. For ls1012 there is no need to look at the RCW, the freq_systembus is always 2x SYS_CLK. Ed ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/2][V2] pci/layerscape: Add EP mode support
From: York Sun >On 07/09/2015 08:35 PM, Minghuan Lian wrote: >> The patch will initialize PCIe controller on EP mode 1. Setup bar: >>bar0 32bit 4K for specific configuration >>bar1 32bit 8K for MSIX >>bar2 64bit 4K for descriptor of memory >>bar4 64bit 1M for DMA memory test This usage is very board/application specific, why are they hard-coded in a general drivers c file? Ed ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] cfi_flash: don't hide write/erase errors
From: Baruch Siach > Partially revert commit 0d01f66d235118 (CFI: cfi_flash write fix for AMD > legacy). > > flash_full_status_check() used to skip status register parsing when > flash_status_check() returns OK. This is wrong since flash_status_check() > must return OK for other status bits to be valid. > Cc: Ed Swarthout > Signed-off-by: Baruch Siach I don't have access to the error case I thought I was fixing with this part and my change does look incorrect, so Acked-by: Ed Swarthout Ed ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] mpc85xx: configs: remove c=ffe from default environment
From: York Sun >On 05/14/2014 07:33 PM, Kim Phillips wrote: >> AFAICT, c=ffe does nothing and was a typo from the original commit >> d17123696c6180ac8b74fbd318bf14652623e982 "powerpc/p4080: Add support >> for the P4080DS board" and just kept on getting duplicated >> in subsequently added board config files. > > Thanks. I have been trying to get Kumar to respond but haven't heard from him. > It does look odd. I think we can delete them. ACK. It was a convenience variable to access ccsrbar space from scripts, but should have been changed to "c=fe" on p4080 and subsequent soc's. Ed ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
