Add support for Seagate BlackArmor NAS220
Signed-off-by: Evgeni Dobrev
---
arch/arm/cpu/arm926ejs/kirkwood/Kconfig |4 +
board/Seagate/nas220/Kconfig| 12 +++
board/Seagate/nas220/MAINTAINERS|6 ++
board/Seagate/nas220/Makefile |7 ++
board/Seagate/nas220/kwbimage.cfg | 151 +++
board/Seagate/nas220/nas220.c | 118 ++
configs/nas220_defconfig|3 +
include/configs/nas220.h| 168 +++
8 files changed, 469 insertions(+)
create mode 100644 board/Seagate/nas220/Kconfig
create mode 100644 board/Seagate/nas220/MAINTAINERS
create mode 100644 board/Seagate/nas220/Makefile
create mode 100644 board/Seagate/nas220/kwbimage.cfg
create mode 100644 board/Seagate/nas220/nas220.c
create mode 100644 configs/nas220_defconfig
create mode 100644 include/configs/nas220.h
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
index 6c037a1..45c6687 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
+++ b/arch/arm/cpu/arm926ejs/kirkwood/Kconfig
@@ -57,6 +57,9 @@ config TARGET_DOCKSTAR
config TARGET_GOFLEXHOME
bool "GoFlex Home Board"
+config TARGET_NAS220
+ bool "BlackArmor NAS220"
+
endchoice
config SYS_SOC
@@ -80,5 +83,6 @@ source "board/LaCie/wireless_space/Kconfig"
source "board/raidsonic/ib62x0/Kconfig"
source "board/Seagate/dockstar/Kconfig"
source "board/Seagate/goflexhome/Kconfig"
+source "board/Seagate/nas220/Kconfig"
endif
diff --git a/board/Seagate/nas220/Kconfig b/board/Seagate/nas220/Kconfig
new file mode 100644
index 000..0fa529c
--- /dev/null
+++ b/board/Seagate/nas220/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_NAS220
+
+config SYS_BOARD
+ default "nas220"
+
+config SYS_VENDOR
+ default "Seagate"
+
+config SYS_CONFIG_NAME
+ default "nas220"
+
+endif
diff --git a/board/Seagate/nas220/MAINTAINERS b/board/Seagate/nas220/MAINTAINERS
new file mode 100644
index 000..f2df7ea
--- /dev/null
+++ b/board/Seagate/nas220/MAINTAINERS
@@ -0,0 +1,6 @@
+NAS220 BOARD
+M: Evgeni Dobrev
+S: Maintained
+F: board/Seagate/nas220/
+F: include/configs/nas220.h
+F: configs/nas220_defconfig
diff --git a/board/Seagate/nas220/Makefile b/board/Seagate/nas220/Makefile
new file mode 100644
index 000..9de73e6
--- /dev/null
+++ b/board/Seagate/nas220/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright (C) 2014 Evgeni Dobrev
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y := nas220.o
diff --git a/board/Seagate/nas220/kwbimage.cfg
b/board/Seagate/nas220/kwbimage.cfg
new file mode 100644
index 000..dbbfb9c
--- /dev/null
+++ b/board/Seagate/nas220/kwbimage.cfg
@@ -0,0 +1,151 @@
+#
+# Copyright (C) 2014 Evgeni Dobrev
+#
+# Based on sheevaplug/kwbimage.cfg originally written by
+# Prafulla Wadaskar
+# (C) Copyright 2009
+# Marvell Semiconductor
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Refer doc/README.kwbimage for more details about how-to configure
+# and create kirkwood boot image
+#
+
+# Boot Media configurations
+BOOT_FROM nand
+NAND_ECC_MODE default
+NAND_PAGE_SIZE 0x0200
+
+# SOC registers configuration using bootrom header extension
+# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
+
+# Configure RGMII-0 interface pad voltage to 1.8V
+DATA 0xFFD100e0 0x1b1b1b9b
+
+#Dram initalization for SINGLE x16 CL=5 @ 400MHz
+DATA 0xFFD01400 0x43000618 # DDR Configuration register
+# bit13-0: 0xa00 (2560 DDR2 clks refresh rate)
+# bit23-14: zero
+# bit24: 1= enable exit self refresh mode on DDR access
+# bit25: 1 required
+# bit29-26: zero
+# bit31-30: 01
+
+DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
+# bit 4:0=addr/cmd in smame cycle
+# bit 5:0=clk is driven during self refresh, we don't care for APX
+# bit 6:0=use recommended falling edge of clk for addr/cmd
+# bit14:0=input buffer always powered up
+# bit18:1=cpu lock transaction enabled
+# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
+# bit27-24: 8= CL+3, STARTBURST sample stages, for freqs 400MHz, unbuffered
DIMM
+# bit30-28: 3 required
+# bit31:0=no additional STARTBURST delay
+
+DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
+# bit7-4: TRCD
+# bit11- 8: TRP
+# bit15-12: TWR
+# bit19-16: TWTR
+# bit20:TRAS msb
+# bit23-21: 0x0
+# bit27-24: TRRD
+# bit31-28: TRTP
+
+DATA 0xFFD0140C 0x0819 # DDR Timing (High)
+# bit6-0: TRFC
+# bit8-7: TR2R
+# bit10-9: TR2W
+# bit12-11: TW2W
+# bit31-13: zero required
+
+
+DATA 0xFFD01410 0x000d # DDR Address Control
+# bit1-0: 00, Cs0width=x8
+# bit3-2: 11, Cs0size=1Gb
+# bit5-4: 00, Cs1width=nonexistent
+# bit7-6: 00, Cs1size =nonexistent
+# bit9-8: 00, Cs2width=nonexistent
+# bit11-10: 00, Cs2siz