Re: [PATCH 1/2] ARM: at91: Enable SPL_SEPARATE_BSS by default
Hi Eugen, > On 05.06.2020 10:49, Gregory CLEMENT wrote: >> Hi Eugen, >> >>> On 10.01.2020 08:32, Stefan Roese wrote: >>> >>>> On 09.01.20 17:30, Gregory CLEMENT wrote: >>>>> According to the linker script for both armv7 and arm926ejs based SoC, >>>>> BSS section was all the time separated for SPL but this symbol was >>>>> only enabled on some boards. However, it is necessary to have it >>>>> enabled for OF_SEPARATE configuration where DTB is appended to u-boot >>>>> with DTB. >>>>> >>>>> Signed-off-by: Gregory CLEMENT >>>>> --- >>>>>arch/arm/Kconfig | 1 + >>>>>1 file changed, 1 insertion(+) >>>>> >>>>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >>>>> index f9dab073ea..e558024652 100644 >>>>> --- a/arch/arm/Kconfig >>>>> +++ b/arch/arm/Kconfig >>>>> @@ -492,6 +492,7 @@ choice >>>>>config ARCH_AT91 >>>>>bool "Atmel AT91" >>>>>select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB >>>>> + select SPL_SEPARATE_BSS if SPL >>>>> >>>>>config TARGET_EDB93XX >>>>>bool "Support edb93xx" >>>>> >>>> >>>> Reviewed-by: Stefan Roese >>>> >>>> Thanks, >>>> Stefan >>>> >>> >>> Hi, >>> >>> With these changes, for all the A5 boards , SEPARATE_BSS was already >>> enabled, but for the rest of the platforms, it was not. >>> As I see from the linker script, the BSS area is configured into DRAM area. >>> Is there any chance that we have accesses to this section before the >>> DRAM is initialized on these platforms ? Could cause the boards to >>> hang. >> >> It is explicitly stated that it BSS is not available before setting up >> the DRAM: it is forbidden to use global/static variables. So it should >> be OK. >> > > Thanks for the clarification. Will queue the patches for next merge > window. Thanks, actually I've just sent a v2 because in the meantime an other defconfig needed to be updated. Gregory > > Eugen > >> Gregory >> >>> >>> Eugen >> >> -- >> Gregory Clement, Bootlin >> Embedded Linux and Kernel engineering >> http://bootlin.com >> > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com
[PATCH v2 2/2] configs: atmel: cleanup CONFIG_SPL_SEPARATE_BSS
Now that CONFIG_SPL_SEPARATE_BSS is selected for all the AT91 based boards, cleanups the defconfigs by removing it. Reviewed-by: Stefan Roese Signed-off-by: Gregory CLEMENT --- configs/gardena-smart-gateway-at91sam_defconfig | 1 - configs/sama5d27_som1_ek_mmc1_defconfig | 1 - configs/sama5d27_som1_ek_mmc_defconfig | 1 - configs/sama5d27_som1_ek_qspiflash_defconfig| 1 - configs/sama5d27_wlsom1_ek_mmc_defconfig| 1 - configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 1 - configs/sama5d2_icp_mmc_defconfig | 1 - configs/sama5d2_xplained_emmc_defconfig | 1 - configs/sama5d2_xplained_mmc_defconfig | 1 - configs/sama5d2_xplained_qspiflash_defconfig| 1 - configs/sama5d3_xplained_mmc_defconfig | 1 - configs/sama5d3xek_mmc_defconfig| 1 - configs/sama5d4_xplained_mmc_defconfig | 1 - configs/sama5d4ek_mmc_defconfig | 1 - 14 files changed, 14 deletions(-) diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index 79d1cb9a96..8f536734e6 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -26,7 +26,6 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(boots CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index a750ec9e18..417a41980e 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -29,7 +29,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 3f22fde026..7aaf2a5c3c 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -30,7 +30,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 2c8ae8d004..726d884983 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -30,7 +30,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index a5fb4f514e..d19089c2e5 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -28,7 +28,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_AT91_MCK_BYPASS=y diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 92decb4b85..6edfdf5e0a 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -29,7 +29,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index dd15441798..0560f6ea19 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -26,7 +26,6 @@ CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_RAM_SUPPORT=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index 75d68a76e4..b75af59960 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -28,7 +28,6 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 r
[PATCH v2 1/2] ARM: at91: Enable SPL_SEPARATE_BSS by default
According to the linker script for both armv7 and arm926ejs based SoC, BSS section was all the time separated for SPL but this symbol was only enabled on some boards. However, it is necessary to have it enabled for OF_SEPARATE configuration where DTB is appended to u-boot with DTB. Reviewed-by: Stefan Roese Signed-off-by: Gregory CLEMENT --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 21df1c415f..3ba7e338b6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -532,6 +532,7 @@ choice config ARCH_AT91 bool "Atmel AT91" select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB + select SPL_SEPARATE_BSS if SPL config TARGET_EDB93XX bool "Support edb93xx" -- 2.26.2
[PATCH v2 0/2] ARM: at91: Allow running SPL with DTB append
Hello, a few months ago I submitted a small series allowing to run SPL with DTB append. Indeed according to the linker BSS section was all the time separated for SPL but the symbol SPL_SEPARATE_BSS was only enabled on some boards. In this v2 the changes are: - add reviewed-by Stefan Roese - modify a new defconfig sama5d3_xplained_nandflash_defconfig Thanks, Gregory Gregory CLEMENT (2): ARM: at91: Enable SPL_SEPARATE_BSS by default configs: atmel: cleanup CONFIG_SPL_SEPARATE_BSS arch/arm/Kconfig| 1 + configs/gardena-smart-gateway-at91sam_defconfig | 1 - configs/sama5d27_som1_ek_mmc1_defconfig | 1 - configs/sama5d27_som1_ek_mmc_defconfig | 1 - configs/sama5d27_som1_ek_qspiflash_defconfig| 1 - configs/sama5d27_wlsom1_ek_mmc_defconfig| 1 - configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 1 - configs/sama5d2_icp_mmc_defconfig | 1 - configs/sama5d2_xplained_emmc_defconfig | 1 - configs/sama5d2_xplained_mmc_defconfig | 1 - configs/sama5d2_xplained_qspiflash_defconfig| 1 - configs/sama5d3_xplained_mmc_defconfig | 1 - configs/sama5d3xek_mmc_defconfig| 1 - configs/sama5d4_xplained_mmc_defconfig | 1 - configs/sama5d4ek_mmc_defconfig | 1 - 15 files changed, 1 insertion(+), 14 deletions(-) -- 2.26.2
Re: [PATCH 1/2] ARM: at91: Enable SPL_SEPARATE_BSS by default
Hi Eugen, > On 10.01.2020 08:32, Stefan Roese wrote: > >> On 09.01.20 17:30, Gregory CLEMENT wrote: >>> According to the linker script for both armv7 and arm926ejs based SoC, >>> BSS section was all the time separated for SPL but this symbol was >>> only enabled on some boards. However, it is necessary to have it >>> enabled for OF_SEPARATE configuration where DTB is appended to u-boot >>> with DTB. >>> >>> Signed-off-by: Gregory CLEMENT >>> --- >>> arch/arm/Kconfig | 1 + >>> 1 file changed, 1 insertion(+) >>> >>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig >>> index f9dab073ea..e558024652 100644 >>> --- a/arch/arm/Kconfig >>> +++ b/arch/arm/Kconfig >>> @@ -492,6 +492,7 @@ choice >>> config ARCH_AT91 >>> bool "Atmel AT91" >>> select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB >>> + select SPL_SEPARATE_BSS if SPL >>> >>> config TARGET_EDB93XX >>> bool "Support edb93xx" >>> >> >> Reviewed-by: Stefan Roese >> >> Thanks, >> Stefan >> > > Hi, > > With these changes, for all the A5 boards , SEPARATE_BSS was already > enabled, but for the rest of the platforms, it was not. > As I see from the linker script, the BSS area is configured into DRAM area. > Is there any chance that we have accesses to this section before the > DRAM is initialized on these platforms ? Could cause the boards to > hang. It is explicitly stated that it BSS is not available before setting up the DRAM: it is forbidden to use global/static variables. So it should be OK. Gregory > > Eugen -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com
[PATCH 2/2] configs: atmel: cleanup CONFIG_SPL_SEPARATE_BSS
Now that CONFIG_SPL_SEPARATE_BSS is selected for all the AT91 based boards, cleanups the defconfigs by removing it. Signed-off-by: Gregory CLEMENT --- configs/gardena-smart-gateway-at91sam_defconfig | 1 - configs/sama5d27_som1_ek_mmc1_defconfig | 1 - configs/sama5d27_som1_ek_mmc_defconfig | 1 - configs/sama5d27_som1_ek_qspiflash_defconfig| 1 - configs/sama5d27_wlsom1_ek_mmc_defconfig| 1 - configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 1 - configs/sama5d2_icp_mmc_defconfig | 1 - configs/sama5d2_xplained_emmc_defconfig | 1 - configs/sama5d2_xplained_mmc_defconfig | 1 - configs/sama5d2_xplained_qspiflash_defconfig| 1 - configs/sama5d3_xplained_mmc_defconfig | 1 - configs/sama5d3xek_mmc_defconfig| 1 - configs/sama5d4_xplained_mmc_defconfig | 1 - configs/sama5d4ek_mmc_defconfig | 1 - 14 files changed, 14 deletions(-) diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index 455b41553a..891b301148 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -25,7 +25,6 @@ CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(boots CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y -CONFIG_SPL_SEPARATE_BSS=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_NAND_SUPPORT=y CONFIG_HUSH_PARSER=y diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index fd5c3da8ca..22b75eb6ed 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -28,7 +28,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw rootwait" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index eabdff31de..3cf7ef0ea1 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -29,7 +29,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index 56cb0c58e6..6dcb297123 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -29,7 +29,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_SEPARATE_BSS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 6b55e9585a..908b0942ff 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -27,7 +27,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_AT91_MCK_BYPASS=y diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 74fe6d42cb..9e54fbd583 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -27,7 +27,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index 316648ef70..0c2a774d61 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -25,7 +25,6 @@ CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y # CONFIG_DISPLAY_BOARDINFO is not set -CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_RAM_SUPPORT=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index 425ced92fe..b75a695cec 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -27,7 +27,6 @@ CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait
[PATCH 1/2] ARM: at91: Enable SPL_SEPARATE_BSS by default
According to the linker script for both armv7 and arm926ejs based SoC, BSS section was all the time separated for SPL but this symbol was only enabled on some boards. However, it is necessary to have it enabled for OF_SEPARATE configuration where DTB is appended to u-boot with DTB. Signed-off-by: Gregory CLEMENT --- arch/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index f9dab073ea..e558024652 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -492,6 +492,7 @@ choice config ARCH_AT91 bool "Atmel AT91" select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB + select SPL_SEPARATE_BSS if SPL config TARGET_EDB93XX bool "Support edb93xx" -- 2.24.1
[U-Boot] [PATCH] arm: lpc32xx: Fix timer initialization
The match controller register is not cleared during initialization. However, some bits of this register may reset the TC if tnMRx match it. As we can't make any assumption about how U-Boot is launched by the first stage bootloader (such as S1L) clearing this register ensure that the timers work as expected. Signed-off-by: Gregory CLEMENT --- arch/arm/cpu/arm926ejs/lpc32xx/timer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c index 404ccbb716..b3ca686040 100644 --- a/arch/arm/cpu/arm926ejs/lpc32xx/timer.c +++ b/arch/arm/cpu/arm926ejs/lpc32xx/timer.c @@ -33,6 +33,9 @@ static void lpc32xx_timer_reset(struct timer_regs *timer, u32 freq) /* Set prescale counter value */ writel((get_periph_clk_rate() / freq) - 1, >pr); + + /* Ensure that the counter is not reset when matching TC */ + writel(0, >mcr); } static void lpc32xx_timer_count(struct timer_regs *timer, int enable) -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH] net: lpc32xx: Use IRAM for transmit buffer
Since the introduction of the driver, some memory in IRAM is reserved for the TX buffers. However there are not used but instead of it, it is the buffer provided by the net stack which is used. As stated in the comment of the driver, not using the IRAM buffer could cause cache issue and lower the throughput. For the second argument it is less the case for transmitting buffers because the throughput gain in IRAM is mitigated by the time to copy the data from RAM to IRAM, but the first argument is still valid and indeed this patch fixes issue seen with Ethernet on some boards Signed-off-by: Gregory CLEMENT --- drivers/net/lpc32xx_eth.c | 8 +++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/net/lpc32xx_eth.c b/drivers/net/lpc32xx_eth.c index 2d15fc8db2..ec5184edf8 100644 --- a/drivers/net/lpc32xx_eth.c +++ b/drivers/net/lpc32xx_eth.c @@ -373,7 +373,8 @@ static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize) tx_index = readl(>txproduceindex); /* set up transmit packet */ - writel((u32)dataptr, >tx_desc[tx_index].packet); + memcpy((void *)>tx_buf[tx_index * PKTSIZE_ALIGN], + (void *)dataptr, datasize); writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE), >tx_desc[tx_index].control); writel(0, >tx_stat[tx_index].statusinfo); @@ -508,6 +509,11 @@ static int lpc32xx_eth_init(struct eth_device *dev) writel((u32)(>rx_stat), >rxstatus); writel(RX_BUF_COUNT-1, >rxdescriptornumber); + /* set up transmit buffers */ + for (index = 0; index < TX_BUF_COUNT; index++) + bufs->tx_desc[index].packet = + (u32)(bufs->tx_buf + index * PKTSIZE_ALIGN); + /* Enable broadcast and matching address packets */ writel(RXFILTERCTRL_ACCEPTBROADCAST | RXFILTERCTRL_ACCEPTPERFECT, >rxfilterctrl); -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH] mtd: nand: raw: Fix CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT behaviour
Miquel Raynal writes:
Hi Miquel,
> Hi Gregory,
>
> Gregory CLEMENT wrote on Wed, 17 Apr 2019
> 11:09:42 +0200:
>
>> The purpose of "mtd: nand: raw: allow to disable unneeded ECC layouts"
>> was to allow disabling the default ECC layouts if a driver is known to
>> provide its own ECC layout. However, this commit did the opposite and
>> disbaled the default layout whqant it was _not_ selectec.
>
> when selected
>
>>
>> It breaks all the driver nand that not providing their ecc layout, this
>
> What about "It breaks all the NAND drivers not providing their own ECC
> layout".
>
>> patch fix this sitution.
>
> situation
>
>>
>> It was tested with the lpc32xx_nand_slc driver.
>>
>> Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
>> Signed-off-by: Gregory CLEMENT
>> ---
>
> I missed that mistake in my original review. Thanks for fixing it.
>
> With above typos fixed:
>
> Reviewed-by: Miquel Raynal
Thanks I've just sent a v2 with the typo fixed and the new wording as
well as a another typo fix in the topic.
Thanks,
Gregory
>
>> drivers/mtd/nand/raw/nand_base.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/mtd/nand/raw/nand_base.c
>> b/drivers/mtd/nand/raw/nand_base.c
>> index 6d2ff58d86..dc4576a3a1 100644
>> --- a/drivers/mtd/nand/raw/nand_base.c
>> +++ b/drivers/mtd/nand/raw/nand_base.c
>> @@ -47,7 +47,7 @@
>> #include
>>
>> /* Define default oob placement schemes for large and small page devices */
>> -#ifdef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
>> +#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
>> static struct nand_ecclayout nand_oob_8 = {
>> .eccbytes = 3,
>> .eccpos = {0, 1, 2},
>> @@ -4341,7 +4341,7 @@ int nand_scan_tail(struct mtd_info *mtd)
>> */
>> if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
>> switch (mtd->oobsize) {
>> -#ifdef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
>> +#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
>> case 8:
>> ecc->layout = _oob_8;
>> break;
>
> Thanks,
> Miquèl
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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[U-Boot] [PATCH v2] mtd: nand: raw: Fix CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT behavior
The purpose of "mtd: nand: raw: allow to disable unneeded ECC layouts"
was to allow disabling the default ECC layouts if a driver is known to
provide its own ECC layout. However, this commit did the opposite and
disabled the default layout when it was _not_ selected.
It breaks all the NAND drivers not providing their own ECC layout this
patch fix this situation.
It was tested with the lpc32xx_nand_slc driver.
Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
Reviewed-by: Miquel Raynal
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2
- Fix typos in the commit log
- Improve wording as suggested by Miquel
- Add Reviewed-by tag from Miquel
drivers/mtd/nand/raw/nand_base.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 6d2ff58d86..dc4576a3a1 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -47,7 +47,7 @@
#include
/* Define default oob placement schemes for large and small page devices */
-#ifdef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
+#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
static struct nand_ecclayout nand_oob_8 = {
.eccbytes = 3,
.eccpos = {0, 1, 2},
@@ -4341,7 +4341,7 @@ int nand_scan_tail(struct mtd_info *mtd)
*/
if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
switch (mtd->oobsize) {
-#ifdef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
+#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
case 8:
ecc->layout = _oob_8;
break;
--
2.20.1
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[U-Boot] [PATCH] mtd: nand: raw: Fix CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT behaviour
The purpose of "mtd: nand: raw: allow to disable unneeded ECC layouts"
was to allow disabling the default ECC layouts if a driver is known to
provide its own ECC layout. However, this commit did the opposite and
disbaled the default layout whqant it was _not_ selectec.
It breaks all the driver nand that not providing their ecc layout, this
patch fix this sitution.
It was tested with the lpc32xx_nand_slc driver.
Fixes: a38c3af868 ("mtd: nand: raw: allow to disable unneeded ECC layouts")
Signed-off-by: Gregory CLEMENT
---
drivers/mtd/nand/raw/nand_base.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c
index 6d2ff58d86..dc4576a3a1 100644
--- a/drivers/mtd/nand/raw/nand_base.c
+++ b/drivers/mtd/nand/raw/nand_base.c
@@ -47,7 +47,7 @@
#include
/* Define default oob placement schemes for large and small page devices */
-#ifdef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
+#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
static struct nand_ecclayout nand_oob_8 = {
.eccbytes = 3,
.eccpos = {0, 1, 2},
@@ -4341,7 +4341,7 @@ int nand_scan_tail(struct mtd_info *mtd)
*/
if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
switch (mtd->oobsize) {
-#ifdef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
+#ifndef CONFIG_SYS_NAND_DRIVER_ECC_LAYOUT
case 8:
ecc->layout = _oob_8;
break;
--
2.20.1
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Re: [U-Boot] [PATCH 2/3] net: add MSCC Luton switch support
for (i = 0; i < IFH_LEN; i++)
> + readl(priv->regs[QS] + QS_XTR_RD(grp));
> +
> + while (!eof_flag) {
> + u32 val = readl(priv->regs[QS] + QS_XTR_RD(grp));
> +
> + switch (val) {
> + case XTR_NOT_READY:
> + debug("%d NOT_READY...?\n", byte_cnt);
> + break;
> + case XTR_ABORT:
> + /* really nedeed?? not done in linux */
> + *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
> + abort_flag = true;
> + eof_flag = true;
> + debug("XTR_ABORT\n");
> + break;
> + case XTR_EOF_0:
> + case XTR_EOF_1:
> + case XTR_EOF_2:
> + case XTR_EOF_3:
> + byte_cnt += XTR_VALID_BYTES(val);
> + *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
> + eof_flag = true;
> + debug("EOF\n");
> + break;
> + case XTR_PRUNED:
> + /* But get the last 4 bytes as well */
> + eof_flag = true;
> + pruned_flag = true;
> + debug("PRUNED\n");
> + /* fallthrough */
> + case XTR_ESCAPE:
> + *rxbuf = readl(priv->regs[QS] + QS_XTR_RD(grp));
> + byte_cnt += 4;
> + rxbuf++;
> + debug("ESCAPED\n");
> + break;
> + default:
> + *rxbuf = val;
> + byte_cnt += 4;
> + rxbuf++;
> + }
> + }
> +
> + if (abort_flag || pruned_flag || !eof_flag) {
> + debug("Discarded frame: abort:%d pruned:%d eof:%d\n",
> + abort_flag, pruned_flag, eof_flag);
> + return -EAGAIN;
> + }
> +
> + *packetp = net_rx_packets[0];
> +
> + return byte_cnt;
> +}
> +
> +static int luton_probe(struct udevice *dev)
> +{
> + struct luton_private *priv = dev_get_priv(dev);
> + int i;
> +
> + struct {
> + enum luton_target id;
> + char *name;
> + } reg[] = {
> + { PORT0, "port0" },
> + { PORT1, "port1" },
> + { PORT2, "port2" },
> + { PORT3, "port3" },
> + { PORT4, "port4" },
> + { PORT5, "port5" },
> + { PORT6, "port6" },
> + { PORT7, "port7" },
> + { PORT8, "port8" },
> + { PORT9, "port9" },
> + { PORT10, "port10" },
> + { PORT11, "port11" },
> + { PORT12, "port12" },
> + { PORT13, "port13" },
> + { PORT14, "port14" },
> + { PORT15, "port15" },
> + { PORT16, "port16" },
> + { PORT17, "port17" },
> + { PORT18, "port18" },
> + { PORT19, "port19" },
> + { PORT20, "port20" },
> + { PORT21, "port21" },
> + { PORT22, "port22" },
> + { PORT23, "port23" },
> + { SYS, "sys" },
> + { ANA, "ana" },
> + { REW, "rew" },
> + { GCB, "gcb" },
> + { QS, "qs" },
> + { HSIO, "hsio" },
> + };
> +
> + if (!priv)
> + return -EINVAL;
> +
> + for (i = 0; i < ARRAY_SIZE(reg); i++) {
> + priv->regs[reg[i].id] = dev_remap_addr_name(dev, reg[i].name);
> + if (!priv->regs[reg[i].id]) {
> + debug
> + ("Error can't get regs base addresses for %s\n",
> + reg[i].name);
> + return -ENOMEM;
> + }
> + }
> +
> + /* Release reset in the CU-PHY */
> + writel(0, priv->regs[GCB] + GCB_DEVCPU_RST_SOFT_CHIP_RST);
> +
> + /* Ports with ext phy don't need to reset clk */
> + for (i = PORT0; i < MAX_INT_PORT; i++) {
> + if (i < PORT10)
> + clrbits_le32(priv->regs[i] + DEV_GMII_PORT_MODE_CLK,
> + DEV_GMII_PORT_MODE_CLK_PHY_RST);
> + else
> + clrbits_le32(priv->regs[i] + DEV_PORT_MODE_CLK,
> + DEV_PORT_MODE_CLK_PHY_RST);
> + }
> +
> + /* Wait for internal PHY to be ready */
> + if (wait_for_bit_le32(priv->regs[GCB] + GCB_MISC_STAT,
> + GCB_MISC_STAT_PHY_READY, true, 500, false))
> + return -EACCES;
> +
> + priv->bus[INTERNAL] = luton_mdiobus_init(dev, INTERNAL);
> +
> + for (i = 0; i < MAX_INT_PORT; i++) {
> + phy_connect(priv->bus[INTERNAL], i, dev,
> + PHY_INTERFACE_MODE_NONE);
> + }
> +
> + /*
> + * coma_mode is need on only one phy, because all the other phys
> + * will be affected.
> + */
> + mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0x10);
> + mscc_miim_write(priv->bus[INTERNAL], 0, 0, 14, 0x800);
> + mscc_miim_write(priv->bus[INTERNAL], 0, 0, 31, 0);
> +
> + return 0;
> +}
> +
> +static int luton_remove(struct udevice *dev)
> +{
> + struct luton_private *priv = dev_get_priv(dev);
> + int i;
> +
> + for (i = 0; i < NUM_PHY; i++) {
> + mdio_unregister(priv->bus[i]);
> + mdio_free(priv->bus[i]);
> + }
> +
> + return 0;
> +}
> +
> +static const struct eth_ops luton_ops = {
> + .start= luton_start,
> + .stop = luton_stop,
> + .send = luton_send,
> + .recv = luton_recv,
> + .write_hwaddr = luton_write_hwaddr,
> +};
> +
> +static const struct udevice_id mscc_luton_ids[] = {
> + {.compatible = "mscc,vsc7527-switch", },
> + { /* Sentinel */ }
> +};
> +
> +U_BOOT_DRIVER(luton) = {
> + .name = "luton-switch",
> + .id = UCLASS_ETH,
> + .of_match = mscc_luton_ids,
> + .probe= luton_probe,
> + .remove = luton_remove,
> + .ops = _ops,
> + .priv_auto_alloc_size = sizeof(struct luton_private),
> + .platdata_auto_alloc_size = sizeof(struct eth_pdata),
> +};
> --
> 2.7.4
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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[U-Boot] [PATCH v3 2/4] net: add MSCC Ocelot switch support
This patch adds support for the Microsemi Ethernet switch present on Ocelot SoCs. Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 1 + drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/ocelot_switch.c | 765 4 files changed, 774 insertions(+) create mode 100644 drivers/net/ocelot_switch.c diff --git a/MAINTAINERS b/MAINTAINERS index 3fa5d3e96f..af44e19eae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -529,6 +529,7 @@ F: drivers/gpio/mscc_sgpio.c F: drivers/spi/mscc_bb_spi.c F: include/configs/vcoreiii.h F: drivers/pinctrl/mscc/ +F: drivers/net/ocelot_switch.c MIPS JZ4780 M: Ezequiel Garcia diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7044c6adf3..10ac15cc6c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -432,6 +432,13 @@ config SNI_AVE This driver implements support for the Socionext AVE Ethernet controller, as found on the Socionext UniPhier family. +config MSCC_OCELOT_SWITCH + bool "Ocelot switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Ocelot network switch device. + config ETHER_ON_FEC1 bool "FEC1" depends on MPC8XX_FEC diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 0dbfa03306..bd108c21d1 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -74,3 +74,4 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_SNI_AVE) += sni_ave.o obj-y += ti/ +obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o diff --git a/drivers/net/ocelot_switch.c b/drivers/net/ocelot_switch.c new file mode 100644 index 00..9fed26cd94 --- /dev/null +++ b/drivers/net/ocelot_switch.c @@ -0,0 +1,765 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MIIM_STATUS0x0 +#defineMIIM_STAT_BUSY BIT(3) +#define MIIM_CMD 0x8 +#defineMIIM_CMD_SCAN BIT(0) +#defineMIIM_CMD_OPR_WRITE BIT(1) +#defineMIIM_CMD_OPR_READ BIT(2) +#defineMIIM_CMD_SINGLE_SCANBIT(3) +#defineMIIM_CMD_WRDATA(x) ((x) << 4) +#defineMIIM_CMD_REGAD(x) ((x) << 20) +#defineMIIM_CMD_PHYAD(x) ((x) << 25) +#defineMIIM_CMD_VLDBIT(31) +#define MIIM_DATA 0xC +#defineMIIM_DATA_ERROR (0x2 << 16) + +#define PHY_CFG0x0 +#define PHY_CFG_ENA0xF +#define PHY_CFG_COMMON_RST BIT(4) +#define PHY_CFG_RST(0xF << 5) +#define PHY_STAT 0x4 +#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0) + +#define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x)) +#defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) +#defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18) +#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x)) +#defineANA_PORT_PORT_CFG_RECV_ENA BIT(6) +#defineANA_TABLES_MACHDATA 0x8b34 +#defineANA_TABLES_MACLDATA 0x8b38 +#define ANA_TABLES_MACACCESS 0x8b3c +#defineANA_TABLES_MACACCESS_VALID BIT(11) +#defineANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9) +#defineANA_TABLES_MACACCESS_DEST_IDX(x)((x) << 3) +#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x) +#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD_MGENMASK(2, 0) +#defineMACACCESS_CMD_IDLE 0 +#defineMACACCESS_CMD_LEARN1 +#defineMACACCESS_CMD_GET_NEXT 4 +#define ANA_PGID(x)(0x8c00 + 4 * (x)) + +#define SYS_FRM_AGING 0x574 +#defineSYS_FRM_AGING_ENA BIT(20) + +#define SYS_SYSTEM_RST_CFG 0x508 +#defineSYS_SYSTEM_RST_MEM_INIT BIT(0) +#defineSYS_SYSTEM_RST_MEM_ENA BIT(1) +#defineSYS_SYSTEM_RST_CORE_ENA BIT(2) +#define SYS_PORT_MODE(x) (0x514 + 0x4 * (x)) +#defineSYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 3) +#defineSYS_PORT_MODE_INCL_INJ_HDR_MGENMASK(4, 3) +#defineSYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 1) +#defineSYS_PORT_MODE_INCL_XTR_HDR_MGENMASK(2, 1) +#defineSYS_PAUSE_C
[U-Boot] [PATCH v3 3/4] MIPS: mscc: ocelot: add switch reset support
On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT
---
board/mscc/ocelot/ocelot.c | 24
1 file changed, 24 insertions(+)
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 0f7a532158..532d06f000 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -18,6 +19,29 @@ enum {
BOARD_TYPE_PCB123,
};
+void mscc_switch_reset(bool enter)
+{
+ /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
+ mscc_gpio_set_alternate(19, 2);
+
+ debug("applying SwC reset\n");
+
+ writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
+ PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
+ pr_err("Tiemout while waiting for switch reset\n");
+
+ /*
+* Reset GPIO19 mode back as regular GPIO, output, high (DDR
+* not reset) (Order is important)
+*/
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+ mscc_gpio_set_alternate(19, 0);
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
--
2.20.1
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[U-Boot] [PATCH v3 4/4] configs: mscc_ocelot: add network support
Now that network support is added for the ocelot platform, let's add it in the default configuration. Signed-off-by: Gregory CLEMENT --- configs/mscc_ocelot_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index fb6a5bdc31..792d00e646 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y +CONFIG_MSCC_OCELOT_SWITCH=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_SERIAL=y -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 1/4] MIPS: mscc: ocelot: Add ethernet nodes for Ocelot
Import Ethernet related nodes from Linux
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 97 +
arch/mips/dts/ocelot_pcb123.dts | 20 +++
2 files changed, 117 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 2592003103..4f3fe356c4 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -112,6 +112,98 @@
status = "disabled";
};
+ switch@101 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ compatible = "mscc,vsc7514-switch";
+ reg = <0x101 0x1>, /* VTSS_TO_SYS */
+ <0x103 0x1>, /* VTSS_TO_REW */
+ <0x108 0x100>, /* VTSS_TO_DEVCPU_QS */
+ <0x10d 0x1>, /* VTSS_TO_HSIO */
+ <0x11e 0x100>, /* VTSS_TO_DEV_0 */
+ <0x11f 0x100>, /* VTSS_TO_DEV_1 */
+ <0x120 0x100>, /* VTSS_TO_DEV_2 */
+ <0x121 0x100>, /* VTSS_TO_DEV_3 */
+ <0x122 0x100>, /* VTSS_TO_DEV_4 */
+ <0x123 0x100>, /* VTSS_TO_DEV_5 */
+ <0x124 0x100>, /* VTSS_TO_DEV_6 */
+ <0x125 0x100>, /* VTSS_TO_DEV_7 */
+ <0x126 0x100>, /* VTSS_TO_DEV_8 */
+ <0x127 0x100>, /* NA */
+ <0x128 0x100>, /* NA */
+ <0x180 0x8>, /* VTSS_TO_QSYS */
+ <0x188 0x1>; /* VTSS_TO_ANA */
+ reg-names = "sys", "rew", "qs", "hsio", "port0",
+ "port1", "port2", "port3", "port4", "port5",
+ "port6", "port7", "port8", "port9",
+ "port10", "qsys", "ana";
+ interrupts = <21 22>;
+ interrupt-names = "xtr", "inj";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ };
+ port8: port@8 {
+ reg = <8>;
+ };
+ port9: port@9 {
+ reg = <9>;
+ };
+ port10: port@10 {
+ reg = <10>;
+ };
+ };
+ };
+
+ mdio0: mdio@107009c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,ocelot-miim";
+ reg = <0x107009c 0x24>, <0x10700f0 0x8>;
+ interrupts = <14>;
+ status = "disabled";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+
[U-Boot] [PATCH v3 0/4] Add network support for Ocelots SoCs
Hello, this the third version of a series allowing to use the switch component of the Ocelots SoC as a network interface. The binding used is exactly the same of the one already used by Linux. There is also a patch adding a workaround needed on the Ocelot based boards: indeed the pin connected to the DDR reset is part of the switch subsystem. So we need ensure that the DDR is not reset during the switch reset. Gregory Changelog: v2 -> v3: - Use wait_for_bit_le32() whenever it is possible instead of timer_get_us() (Suggested by Daniel Schwierzeck) - Remove ocelot_ofdata_to_platdata() and get the resources directly from the probe function (Suggested by Daniel Schwierzeck) - Use dev_remap_addr_name() to simplify the address mapping (Suggested by Daniel Schwierzeck) - Simplify the mdio initialization by only manage the internal PHY for now v1 -> v2: - Use wait_for_bit_le32() (suggested by Stefan Roese) - Use debug() instead of printf() for the debug messages in mscc_switch_reset. Gregory CLEMENT (4): MIPS: mscc: ocelot: Add ethernet nodes for Ocelot net: add MSCC Ocelot switch support MIPS: mscc: ocelot: add switch reset support configs: mscc_ocelot: add network support MAINTAINERS | 1 + arch/mips/dts/mscc,ocelot.dtsi | 97 arch/mips/dts/ocelot_pcb123.dts | 20 + board/mscc/ocelot/ocelot.c | 24 + configs/mscc_ocelot_defconfig | 1 + drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/ocelot_switch.c | 765 8 files changed, 916 insertions(+) create mode 100644 drivers/net/ocelot_switch.c -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/4] MIPS: mscc: ocelot: add switch reset support
Hi Daniel,
On mer., janv. 16 2019, Daniel Schwierzeck
wrote:
> Am 16.01.19 um 14:07 schrieb Gregory CLEMENT:
>> On some ocelots platform a workaround is needed in order to be able to
>> reset the switch without resetting the DDR.
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> board/mscc/ocelot/ocelot.c | 26 ++
>> 1 file changed, 26 insertions(+)
>>
>> diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
>> index 0f7a532158..77ebe8ae26 100644
>> --- a/board/mscc/ocelot/ocelot.c
>> +++ b/board/mscc/ocelot/ocelot.c
>> @@ -10,6 +10,7 @@
>> #include
>> #include
>> #include
>> +#include
>>
>> DECLARE_GLOBAL_DATA_PTR;
>>
>> @@ -18,6 +19,31 @@ enum {
>> BOARD_TYPE_PCB123,
>> };
>>
>> +void mscc_switch_reset(bool enter)
>> +{
>> +u32 reg, count = 0;
>> +
>> +/* Nasty workaround to avoid GPIO19 (DDR!) being reset */
>> +mscc_gpio_set_alternate(19, 2);
>> +
>> +debug("applying SwC reset\n");
>> +
>> +writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
>> +writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
>> +
>> +if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
>> + PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
>> +pr_err("Tiemout while waiting for switch reset\n");
>> +
>> +/*
>> + * Reset GPIO19 mode back as regular GPIO, output, high (DDR
>> + * not reset) (Order is important)
>> + */
>> +setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
>> +writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
>> +mscc_gpio_set_alternate(19, 0);
>
> have you thought about or maybe planned a reset controller driver?
Actually, here it is not a reset driver, it is just the workaround part
of the stop() function in the network driver. It is not about resetting
the whole platform, for this feature a driver already has been submited.
Gregory
>
>> +}
>> +
>> void board_debug_uart_init(void)
>> {
>> /* too early for the pinctrl driver, so configure the UART pins here */
>>
>
> --
> - Daniel
--
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Re: [U-Boot] [PATCH v2 2/4] net: add MSCC Ocelot switch support
Hi Daniel,
On mer., janv. 16 2019, Daniel Schwierzeck
wrote:
>> +static int mscc_miim_wait_ready(struct mscc_miim_dev *miim)
>> +{
>> +unsigned long deadline;
>> +u32 val;
>> +
>> +deadline = timer_get_us() + 25;
>> +
>> +do {
>> +val = readl(miim->regs + MIIM_STATUS);
>> +} while (timer_get_us() <= deadline && (val & MIIM_STAT_BUSY));
>
> you use this multiple times, maybe it makes sense to add a generic
> wait_for_bit set with timer_get_us()
Sure I will do it.
>> +
>> +priv->data = (struct ocelot_soc_data *)dev_get_platdata(dev);
>> +if (!priv->data)
>> +return -EINVAL;
>> +
>
> actually you could avoid the overhead of allocating platdata and merge
> ocelot_ofdata_to_platdata() into ocelot_probe(). platdata is only needed
> if a driver want to support configuration without a device tree.
OK as we don't plan to support this driver without device tree, I will
do it.
>
>> +plat = priv->data;
>> +for (i = 0; i < ARRAY_SIZE(reg); i++) {
>> +ret = dev_read_resource_byname(dev, reg[i].name, );
>> +if (ret) {
>> +debug
>> +("Error %d: can't get regs base addresses for %s\n",
>> + ret, reg[i].name);
>> +return -ENOMEM;
>> +}
>> +
>> +faddr = cpu_to_fdt32(res.start);
>> +plat->base[reg[i].id] = dev_translate_address(dev, );
>> +if (plat->base[reg[i].id] == OF_BAD_ADDR)
>> +return -ENOMEM;
>> +plat->size[reg[i].id] = res.end - res.start;
>> +}
>
> have you tried with dev_read_addr_name()? If maybe address translation
> didn't work, a disabled CONFIG_OF_TRANSLATE could be the reason.
Indeed I have issue with adress translation, and if I remember well,
when I tried to activated CONFIG_OF_TRANSLATE I had build failure with
MIPS.
>
>> +
>> +/* gathered only the first mdio bus */
>> +eth_node = dev_read_first_subnode(dev);
>> +node = ofnode_first_subnode(eth_node);
>> +ofnode_parse_phandle_with_args(node, "phy-handle", NULL, 0, 0,
>> + );
>> +mdio_node = ofnode_get_parent(phandle.node);
>> +
>> +for (i = 0; i < TARGET_MDIO_MAX; i++) {
>> +if (ofnode_read_resource(mdio_node, i, ))
>> +return -ENOMEM;
>> +faddr = cpu_to_fdt32(res.start);
>> +plat->phy_base[INTERNAL][i] =
>> +ofnode_translate_address(mdio_node, );
>> +plat->phy_size[INTERNAL][i] = res.end - res.start;
>> +}
>> +
>> +return 0;
>> +}
>> +
>> +static int ocelot_probe(struct udevice *dev)
>> +{
>> +struct ocelot_private *priv = dev_get_priv(dev);
>> +int i;
>> +
>> +if (!priv)
>> +return -EINVAL;
>> +
>> +for (i = 0; i < TARGET_MAX; i++)
>> +priv->regs[i] = ioremap(priv->data->base[i],
>> +priv->data->size[i]);
>> +
>
> if dev_read_addr_name() works, you could also use dev_remap_addr_name()
> to implicitely do the ioremap
if dev_read_addr_name() works yes I can use it.
Gregory
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[U-Boot] [PATCH v2 2/4] net: add MSCC Ocelot switch support
This patch adds support for the Microsemi Ethernet switch present on Ocelot SoCs. Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 1 + drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/ocelot_switch.c | 837 4 files changed, 846 insertions(+) create mode 100644 drivers/net/ocelot_switch.c diff --git a/MAINTAINERS b/MAINTAINERS index 3fa5d3e96f..af44e19eae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -529,6 +529,7 @@ F: drivers/gpio/mscc_sgpio.c F: drivers/spi/mscc_bb_spi.c F: include/configs/vcoreiii.h F: drivers/pinctrl/mscc/ +F: drivers/net/ocelot_switch.c MIPS JZ4780 M: Ezequiel Garcia diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7044c6adf3..10ac15cc6c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -432,6 +432,13 @@ config SNI_AVE This driver implements support for the Socionext AVE Ethernet controller, as found on the Socionext UniPhier family. +config MSCC_OCELOT_SWITCH + bool "Ocelot switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Ocelot network switch device. + config ETHER_ON_FEC1 bool "FEC1" depends on MPC8XX_FEC diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 0dbfa03306..bd108c21d1 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -74,3 +74,4 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_SNI_AVE) += sni_ave.o obj-y += ti/ +obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o diff --git a/drivers/net/ocelot_switch.c b/drivers/net/ocelot_switch.c new file mode 100644 index 00..7ad0538b76 --- /dev/null +++ b/drivers/net/ocelot_switch.c @@ -0,0 +1,837 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MIIM_STATUS0x0 +#defineMIIM_STAT_BUSY BIT(3) +#define MIIM_CMD 0x8 +#defineMIIM_CMD_SCAN BIT(0) +#defineMIIM_CMD_OPR_WRITE BIT(1) +#defineMIIM_CMD_OPR_READ BIT(2) +#defineMIIM_CMD_SINGLE_SCANBIT(3) +#defineMIIM_CMD_WRDATA(x) ((x) << 4) +#defineMIIM_CMD_REGAD(x) ((x) << 20) +#defineMIIM_CMD_PHYAD(x) ((x) << 25) +#defineMIIM_CMD_VLDBIT(31) +#define MIIM_DATA 0xC +#defineMIIM_DATA_ERROR (0x2 << 16) + +#define PHY_CFG0x0 +#define PHY_CFG_ENA0xF +#define PHY_CFG_COMMON_RST BIT(4) +#define PHY_CFG_RST(0xF << 5) +#define PHY_STAT 0x4 +#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0) + +#define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x)) +#defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) +#defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18) +#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x)) +#defineANA_PORT_PORT_CFG_RECV_ENA BIT(6) +#defineANA_TABLES_MACHDATA 0x8b34 +#defineANA_TABLES_MACLDATA 0x8b38 +#define ANA_TABLES_MACACCESS 0x8b3c +#defineANA_TABLES_MACACCESS_VALID BIT(11) +#defineANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9) +#defineANA_TABLES_MACACCESS_DEST_IDX(x)((x) << 3) +#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x) +#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD_MGENMASK(2, 0) +#defineMACACCESS_CMD_IDLE 0 +#defineMACACCESS_CMD_LEARN1 +#defineMACACCESS_CMD_GET_NEXT 4 +#define ANA_PGID(x)(0x8c00 + 4 * (x)) + +#define SYS_FRM_AGING 0x574 +#defineSYS_FRM_AGING_ENA BIT(20) + +#define SYS_SYSTEM_RST_CFG 0x508 +#defineSYS_SYSTEM_RST_MEM_INIT BIT(0) +#defineSYS_SYSTEM_RST_MEM_ENA BIT(1) +#defineSYS_SYSTEM_RST_CORE_ENA BIT(2) +#define SYS_PORT_MODE(x) (0x514 + 0x4 * (x)) +#defineSYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 3) +#defineSYS_PORT_MODE_INCL_INJ_HDR_MGENMASK(4, 3) +#defineSYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 1) +#defineSYS_PORT_MODE_INCL_XTR_HDR_MGENMASK(2, 1) +#defineSYS_PAUSE_CFG(x)
[U-Boot] [PATCH v2 4/4] configs: mscc_ocelot: add network support
Now that network support is added for the ocelot platform, let's add it in the default configuration. Signed-off-by: Gregory CLEMENT --- configs/mscc_ocelot_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index fb6a5bdc31..792d00e646 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y +CONFIG_MSCC_OCELOT_SWITCH=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_SERIAL=y -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/4] MIPS: mscc: ocelot: add switch reset support
On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT
---
board/mscc/ocelot/ocelot.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 0f7a532158..77ebe8ae26 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -10,6 +10,7 @@
#include
#include
#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -18,6 +19,31 @@ enum {
BOARD_TYPE_PCB123,
};
+void mscc_switch_reset(bool enter)
+{
+ u32 reg, count = 0;
+
+ /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
+ mscc_gpio_set_alternate(19, 2);
+
+ debug("applying SwC reset\n");
+
+ writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ if (wait_for_bit_le32(BASE_DEVCPU_GCB + PERF_SOFT_RST,
+ PERF_SOFT_RST_SOFT_CHIP_RST, false, 5000, false))
+ pr_err("Tiemout while waiting for switch reset\n");
+
+ /*
+* Reset GPIO19 mode back as regular GPIO, output, high (DDR
+* not reset) (Order is important)
+*/
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+ mscc_gpio_set_alternate(19, 0);
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
--
2.20.1
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[U-Boot] [PATCH v2 1/4] MIPS: mscc: ocelot: Add ethernet nodes for Ocelot
Import Ethernet related nodes from Linux
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 97 +
arch/mips/dts/ocelot_pcb123.dts | 20 +++
2 files changed, 117 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 2592003103..4f3fe356c4 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -112,6 +112,98 @@
status = "disabled";
};
+ switch@101 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ compatible = "mscc,vsc7514-switch";
+ reg = <0x101 0x1>, /* VTSS_TO_SYS */
+ <0x103 0x1>, /* VTSS_TO_REW */
+ <0x108 0x100>, /* VTSS_TO_DEVCPU_QS */
+ <0x10d 0x1>, /* VTSS_TO_HSIO */
+ <0x11e 0x100>, /* VTSS_TO_DEV_0 */
+ <0x11f 0x100>, /* VTSS_TO_DEV_1 */
+ <0x120 0x100>, /* VTSS_TO_DEV_2 */
+ <0x121 0x100>, /* VTSS_TO_DEV_3 */
+ <0x122 0x100>, /* VTSS_TO_DEV_4 */
+ <0x123 0x100>, /* VTSS_TO_DEV_5 */
+ <0x124 0x100>, /* VTSS_TO_DEV_6 */
+ <0x125 0x100>, /* VTSS_TO_DEV_7 */
+ <0x126 0x100>, /* VTSS_TO_DEV_8 */
+ <0x127 0x100>, /* NA */
+ <0x128 0x100>, /* NA */
+ <0x180 0x8>, /* VTSS_TO_QSYS */
+ <0x188 0x1>; /* VTSS_TO_ANA */
+ reg-names = "sys", "rew", "qs", "hsio", "port0",
+ "port1", "port2", "port3", "port4", "port5",
+ "port6", "port7", "port8", "port9",
+ "port10", "qsys", "ana";
+ interrupts = <21 22>;
+ interrupt-names = "xtr", "inj";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ };
+ port8: port@8 {
+ reg = <8>;
+ };
+ port9: port@9 {
+ reg = <9>;
+ };
+ port10: port@10 {
+ reg = <10>;
+ };
+ };
+ };
+
+ mdio0: mdio@107009c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,ocelot-miim";
+ reg = <0x107009c 0x24>, <0x10700f0 0x8>;
+ interrupts = <14>;
+ status = "disabled";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+
[U-Boot] [PATCH v2 0/4] Add network support for Ocelots SoCs
Hello, this the second version of a series allowing to use the switch component of the Ocelots SoC as a network interface. The binding used is exactly the same of the one already used by Linux. There is also a patch adding a workaround needed on the Ocelot based boards: indeed the pin connected to the DDR reset is part of the switch subsystem. So we need ensure that the DDR is not reset during the switch reset. Gregory Changelog: v1 -> v2: - Use wait_for_bit_le32() (suggested by Stefan Roese) - Use debug() instead of printf() for the debug messages in mscc_switch_reset. Gregory CLEMENT (4): MIPS: mscc: ocelot: Add ethernet nodes for Ocelot net: add MSCC Ocelot switch support MIPS: mscc: ocelot: add switch reset support configs: mscc_ocelot: add network support MAINTAINERS | 1 + arch/mips/dts/mscc,ocelot.dtsi | 97 arch/mips/dts/ocelot_pcb123.dts | 20 + board/mscc/ocelot/ocelot.c | 26 + configs/mscc_ocelot_defconfig | 1 + drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/ocelot_switch.c | 837 8 files changed, 990 insertions(+) create mode 100644 drivers/net/ocelot_switch.c -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 1/4] MIPS: mscc: ocelot: Add ethernet nodes for Ocelot
Import Ethernet related nodes from Linux
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 97 +
arch/mips/dts/ocelot_pcb123.dts | 20 +++
2 files changed, 117 insertions(+)
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
index 2592003103..4f3fe356c4 100644
--- a/arch/mips/dts/mscc,ocelot.dtsi
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -112,6 +112,98 @@
status = "disabled";
};
+ switch@101 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ compatible = "mscc,vsc7514-switch";
+ reg = <0x101 0x1>, /* VTSS_TO_SYS */
+ <0x103 0x1>, /* VTSS_TO_REW */
+ <0x108 0x100>, /* VTSS_TO_DEVCPU_QS */
+ <0x10d 0x1>, /* VTSS_TO_HSIO */
+ <0x11e 0x100>, /* VTSS_TO_DEV_0 */
+ <0x11f 0x100>, /* VTSS_TO_DEV_1 */
+ <0x120 0x100>, /* VTSS_TO_DEV_2 */
+ <0x121 0x100>, /* VTSS_TO_DEV_3 */
+ <0x122 0x100>, /* VTSS_TO_DEV_4 */
+ <0x123 0x100>, /* VTSS_TO_DEV_5 */
+ <0x124 0x100>, /* VTSS_TO_DEV_6 */
+ <0x125 0x100>, /* VTSS_TO_DEV_7 */
+ <0x126 0x100>, /* VTSS_TO_DEV_8 */
+ <0x127 0x100>, /* NA */
+ <0x128 0x100>, /* NA */
+ <0x180 0x8>, /* VTSS_TO_QSYS */
+ <0x188 0x1>; /* VTSS_TO_ANA */
+ reg-names = "sys", "rew", "qs", "hsio", "port0",
+ "port1", "port2", "port3", "port4", "port5",
+ "port6", "port7", "port8", "port9",
+ "port10", "qsys", "ana";
+ interrupts = <21 22>;
+ interrupt-names = "xtr", "inj";
+ status = "okay";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port0: port@0 {
+ reg = <0>;
+ };
+ port1: port@1 {
+ reg = <1>;
+ };
+ port2: port@2 {
+ reg = <2>;
+ };
+ port3: port@3 {
+ reg = <3>;
+ };
+ port4: port@4 {
+ reg = <4>;
+ };
+ port5: port@5 {
+ reg = <5>;
+ };
+ port6: port@6 {
+ reg = <6>;
+ };
+ port7: port@7 {
+ reg = <7>;
+ };
+ port8: port@8 {
+ reg = <8>;
+ };
+ port9: port@9 {
+ reg = <9>;
+ };
+ port10: port@10 {
+ reg = <10>;
+ };
+ };
+ };
+
+ mdio0: mdio@107009c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "mscc,ocelot-miim";
+ reg = <0x107009c 0x24>, <0x10700f0 0x8>;
+ interrupts = <14>;
+ status = "disabled";
+
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+
[U-Boot] [PATCH 0/4] Add network support for Ocelots SoCs
Hello, this series allows to use the switch component of the Ocelots SoC as a network interface. The binding used is exactly the same of the one already used by Linux. There is also a patch adding a workaround needed on the Ocelot based boards: indeed the pin connected to the DDR reset is part of the switch subsystem. So we need ensure that the DDR is not reset during the switch reset. Gregory Gregory CLEMENT (4): MIPS: mscc: ocelot: Add ethernet nodes for Ocelot net: add MSCC Ocelot switch support MIPS: mscc: ocelot: add switch reset support configs: mscc_ocelot: add network support MAINTAINERS | 1 + arch/mips/dts/mscc,ocelot.dtsi | 97 arch/mips/dts/ocelot_pcb123.dts | 20 + board/mscc/ocelot/ocelot.c | 28 ++ configs/mscc_ocelot_defconfig | 1 + drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/ocelot_switch.c | 837 8 files changed, 992 insertions(+) create mode 100644 drivers/net/ocelot_switch.c -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/4] configs: mscc_ocelot: add network support
Now that network support is added for the ocelot platform, let's add it in the default configuration. Signed-off-by: Gregory CLEMENT --- configs/mscc_ocelot_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig index fb6a5bdc31..792d00e646 100644 --- a/configs/mscc_ocelot_defconfig +++ b/configs/mscc_ocelot_defconfig @@ -60,6 +60,7 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y CONFIG_DM_ETH=y +CONFIG_MSCC_OCELOT_SWITCH=y CONFIG_PINCTRL=y CONFIG_PINCONF=y CONFIG_DM_SERIAL=y -- 2.20.1 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/4] net: add MSCC Ocelot switch support
This patch adds support for the Microsemi Ethernet switch present on Ocelot SoCs. Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 1 + drivers/net/Kconfig | 7 + drivers/net/Makefile| 1 + drivers/net/ocelot_switch.c | 837 4 files changed, 846 insertions(+) create mode 100644 drivers/net/ocelot_switch.c diff --git a/MAINTAINERS b/MAINTAINERS index 3fa5d3e96f..af44e19eae 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -529,6 +529,7 @@ F: drivers/gpio/mscc_sgpio.c F: drivers/spi/mscc_bb_spi.c F: include/configs/vcoreiii.h F: drivers/pinctrl/mscc/ +F: drivers/net/ocelot_switch.c MIPS JZ4780 M: Ezequiel Garcia diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 7044c6adf3..10ac15cc6c 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -432,6 +432,13 @@ config SNI_AVE This driver implements support for the Socionext AVE Ethernet controller, as found on the Socionext UniPhier family. +config MSCC_OCELOT_SWITCH + bool "Ocelot switch driver" + depends on DM_ETH && ARCH_MSCC + select PHYLIB + help + This driver supports the Ocelot network switch device. + config ETHER_ON_FEC1 bool "FEC1" depends on MPC8XX_FEC diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 0dbfa03306..bd108c21d1 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -74,3 +74,4 @@ obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o obj-$(CONFIG_FSL_PFE) += pfe_eth/ obj-$(CONFIG_SNI_AVE) += sni_ave.o obj-y += ti/ +obj-$(CONFIG_MSCC_OCELOT_SWITCH) += ocelot_switch.o diff --git a/drivers/net/ocelot_switch.c b/drivers/net/ocelot_switch.c new file mode 100644 index 00..7ad0538b76 --- /dev/null +++ b/drivers/net/ocelot_switch.c @@ -0,0 +1,837 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2018 Microsemi Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MIIM_STATUS0x0 +#defineMIIM_STAT_BUSY BIT(3) +#define MIIM_CMD 0x8 +#defineMIIM_CMD_SCAN BIT(0) +#defineMIIM_CMD_OPR_WRITE BIT(1) +#defineMIIM_CMD_OPR_READ BIT(2) +#defineMIIM_CMD_SINGLE_SCANBIT(3) +#defineMIIM_CMD_WRDATA(x) ((x) << 4) +#defineMIIM_CMD_REGAD(x) ((x) << 20) +#defineMIIM_CMD_PHYAD(x) ((x) << 25) +#defineMIIM_CMD_VLDBIT(31) +#define MIIM_DATA 0xC +#defineMIIM_DATA_ERROR (0x2 << 16) + +#define PHY_CFG0x0 +#define PHY_CFG_ENA0xF +#define PHY_CFG_COMMON_RST BIT(4) +#define PHY_CFG_RST(0xF << 5) +#define PHY_STAT 0x4 +#define PHY_STAT_SUPERVISOR_COMPLETE BIT(0) + +#define ANA_PORT_VLAN_CFG(x) (0x7000 + 0x100 * (x)) +#defineANA_PORT_VLAN_CFG_AWARE_ENA BIT(20) +#defineANA_PORT_VLAN_CFG_POP_CNT(x)((x) << 18) +#define ANA_PORT_PORT_CFG(x) (0x7070 + 0x100 * (x)) +#defineANA_PORT_PORT_CFG_RECV_ENA BIT(6) +#defineANA_TABLES_MACHDATA 0x8b34 +#defineANA_TABLES_MACLDATA 0x8b38 +#define ANA_TABLES_MACACCESS 0x8b3c +#defineANA_TABLES_MACACCESS_VALID BIT(11) +#defineANA_TABLES_MACACCESS_ENTRYTYPE(x) ((x) << 9) +#defineANA_TABLES_MACACCESS_DEST_IDX(x)((x) << 3) +#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD(x) (x) +#defineANA_TABLES_MACACCESS_MAC_TABLE_CMD_MGENMASK(2, 0) +#defineMACACCESS_CMD_IDLE 0 +#defineMACACCESS_CMD_LEARN1 +#defineMACACCESS_CMD_GET_NEXT 4 +#define ANA_PGID(x)(0x8c00 + 4 * (x)) + +#define SYS_FRM_AGING 0x574 +#defineSYS_FRM_AGING_ENA BIT(20) + +#define SYS_SYSTEM_RST_CFG 0x508 +#defineSYS_SYSTEM_RST_MEM_INIT BIT(0) +#defineSYS_SYSTEM_RST_MEM_ENA BIT(1) +#defineSYS_SYSTEM_RST_CORE_ENA BIT(2) +#define SYS_PORT_MODE(x) (0x514 + 0x4 * (x)) +#defineSYS_PORT_MODE_INCL_INJ_HDR(x) ((x) << 3) +#defineSYS_PORT_MODE_INCL_INJ_HDR_MGENMASK(4, 3) +#defineSYS_PORT_MODE_INCL_XTR_HDR(x) ((x) << 1) +#defineSYS_PORT_MODE_INCL_XTR_HDR_MGENMASK(2, 1) +#defineSYS_PAUSE_CFG(x)
[U-Boot] [PATCH 3/4] MIPS: mscc: ocelot: add switch reset support
On some ocelots platform a workaround is needed in order to be able to
reset the switch without resetting the DDR.
Signed-off-by: Gregory CLEMENT
---
board/mscc/ocelot/ocelot.c | 28
1 file changed, 28 insertions(+)
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
index 0f7a532158..88f59e8044 100644
--- a/board/mscc/ocelot/ocelot.c
+++ b/board/mscc/ocelot/ocelot.c
@@ -18,6 +18,34 @@ enum {
BOARD_TYPE_PCB123,
};
+void mscc_switch_reset(bool enter)
+{
+ u32 reg, count = 0;
+
+ /* Nasty workaround to avoid GPIO19 (DDR!) being reset */
+ mscc_gpio_set_alternate(19, 2);
+
+ printf("applying SwC reset\n");
+
+ writel(ICPU_RESET_CORE_RST_PROTECT, BASE_CFG + ICPU_RESET);
+ writel(PERF_SOFT_RST_SOFT_CHIP_RST, BASE_DEVCPU_GCB + PERF_SOFT_RST);
+
+ do {
+ reg = readl(BASE_DEVCPU_GCB + PERF_SOFT_RST);
+ count++;
+ } while (reg & PERF_SOFT_RST_SOFT_CHIP_RST);
+
+ printf("SwC reset done - reg = 0x%08x, count %u\n", reg, count);
+
+ /*
+* Reset GPIO19 mode back as regular GPIO, output, high (DDR
+* not reset) (Order is important)
+*/
+ setbits_le32(BASE_DEVCPU_GCB + PERF_GPIO_OE, BIT(19));
+ writel(BIT(19), BASE_DEVCPU_GCB + PERF_GPIO_OUT_SET);
+ mscc_gpio_set_alternate(19, 0);
+}
+
void board_debug_uart_init(void)
{
/* too early for the pinctrl driver, so configure the UART pins here */
--
2.20.1
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Re: [U-Boot] [PATCH v4 1/6] pinctrl: mscc: Add gpio and pinctrl for Jaguar2 SOC family
IN(36),
> + JR2_PIN(37),
> + JR2_PIN(38),
> + JR2_PIN(39),
> + JR2_PIN(40),
> + JR2_PIN(41),
> + JR2_PIN(42),
> + JR2_PIN(43),
> + JR2_PIN(44),
> + JR2_PIN(45),
> + JR2_PIN(46),
> + JR2_PIN(47),
> + JR2_PIN(48),
> + JR2_PIN(49),
> + JR2_PIN(50),
> + JR2_PIN(51),
> + JR2_PIN(52),
> + JR2_PIN(53),
> + JR2_PIN(54),
> + JR2_PIN(55),
> + JR2_PIN(56),
> + JR2_PIN(57),
> + JR2_PIN(58),
> + JR2_PIN(59),
> + JR2_PIN(60),
> + JR2_PIN(61),
> + JR2_PIN(62),
> + JR2_PIN(63),
> +};
> +
> +const unsigned long jr2_gpios[] = {
> + [MSCC_GPIO_OUT_SET] = 0x00,
> + [MSCC_GPIO_OUT_CLR] = 0x08,
> + [MSCC_GPIO_OUT] = 0x10,
> + [MSCC_GPIO_IN] = 0x18,
> + [MSCC_GPIO_OE] = 0x20,
> + [MSCC_GPIO_INTR] = 0x28,
> + [MSCC_GPIO_INTR_ENA] = 0x30,
> + [MSCC_GPIO_INTR_IDENT] = 0x38,
> + [MSCC_GPIO_ALT0] = 0x40,
> + [MSCC_GPIO_ALT1] = 0x48,
> +};
> +
> +static int jr2_gpio_probe(struct udevice *dev)
> +{
> + struct gpio_dev_priv *uc_priv;
> +
> + uc_priv = dev_get_uclass_priv(dev);
> + uc_priv->bank_name = "jr2-gpio";
> + uc_priv->gpio_count = ARRAY_SIZE(jr2_pins);
> +
> + return 0;
> +}
> +
> +static struct driver jr2_gpio_driver = {
> + .name = "jr2-gpio",
> + .id = UCLASS_GPIO,
> + .probe = jr2_gpio_probe,
> + .ops= _gpio_ops,
> +};
> +
> +int jr2_pinctrl_probe(struct udevice *dev)
> +{
> + int ret;
> +
> + ret = mscc_pinctrl_probe(dev, FUNC_MAX, jr2_pins,
> + ARRAY_SIZE(jr2_pins),
> + jr2_function_names,
> + jr2_gpios);
> +
> + if (ret)
> + return ret;
> +
> + ret = device_bind(dev, _gpio_driver, "jr2-gpio", NULL,
> + dev_of_offset(dev), NULL);
> +
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static const struct udevice_id jr2_pinctrl_of_match[] = {
> + { .compatible = "mscc,jr2-pinctrl" },
I still think that it is important to use the same compatible string
used in Linux ""mscc,jaguar2-pinctrl"
https://elixir.bootlin.com/linux/v5.0-rc1/source/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt#L6
> + {},
> +};
> +
> +U_BOOT_DRIVER(jr2_pinctrl) = {
> + .name = "jr2-pinctrl",
> + .id = UCLASS_PINCTRL,
> + .of_match = of_match_ptr(jr2_pinctrl_of_match),
> + .probe = jr2_pinctrl_probe,
> + .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
> + .ops = _pinctrl_ops,
> +};
> diff --git a/drivers/pinctrl/mscc/pinctrl-luton.c
> b/drivers/pinctrl/mscc/pinctrl-luton.c
> index 7166588..8c636ff 100644
> --- a/drivers/pinctrl/mscc/pinctrl-luton.c
> +++ b/drivers/pinctrl/mscc/pinctrl-luton.c
> @@ -123,6 +123,19 @@ static const struct mscc_pin_data luton_pins[] = {
> LUTON_PIN(31),
> };
>
> +const unsigned long luton_gpios[] = {
> + [MSCC_GPIO_OUT_SET] = 0x00,
> + [MSCC_GPIO_OUT_CLR] = 0x04,
> + [MSCC_GPIO_OUT] = 0x08,
> + [MSCC_GPIO_IN] = 0x0c,
> + [MSCC_GPIO_OE] = 0x10,
> + [MSCC_GPIO_INTR] = 0x14,
> + [MSCC_GPIO_INTR_ENA] = 0x18,
> + [MSCC_GPIO_INTR_IDENT] = 0x1c,
> + [MSCC_GPIO_ALT0] = 0x20,
> + [MSCC_GPIO_ALT1] = 0x24,
> +};
> +
> static int luton_gpio_probe(struct udevice *dev)
> {
> struct gpio_dev_priv *uc_priv;
> @@ -146,7 +159,8 @@ int luton_pinctrl_probe(struct udevice *dev)
> int ret;
>
> ret = mscc_pinctrl_probe(dev, FUNC_MAX, luton_pins,
> - ARRAY_SIZE(luton_pins), luton_function_names);
> + ARRAY_SIZE(luton_pins), luton_function_names,
> + luton_gpios);
>
> if (ret)
> return ret;
> diff --git a/drivers/pinctrl/mscc/pinctrl-ocelot.c
> b/drivers/pinctrl/mscc/pinctrl-ocelot.c
> index 10f9b90..fb02061 100644
> --- a/drivers/pinctrl/mscc/pinctrl-ocelot.c
> +++ b/drivers/pinctrl/mscc/pinctrl-ocelot.c
> @@ -138,6 +138,19 @@ static const struct mscc_pin_data ocelot_pins[] = {
> OCELOT_PIN(21),
> };
>
> +const unsigned long ocelot_gpios[] = {
> + [MSCC_GPIO_OUT_SET] = 0x00,
> + [MSCC_GPIO_OUT_CLR] = 0x04,
> + [MSCC_GPIO_OUT] = 0x08,
> + [MSCC_GPIO_IN] = 0x0c,
> + [MSCC_GPIO_OE] = 0x10,
> + [MSCC_GPIO_INTR] = 0x14,
> + [MSCC_GPIO_INTR_ENA] = 0x18,
> + [MSCC_GPIO_INTR_IDENT] = 0x1c,
> + [MSCC_GPIO_ALT0] = 0x20,
> + [MSCC_GPIO_ALT1] = 0x24,
> +};
> +
> static int ocelot_gpio_probe(struct udevice *dev)
> {
> struct gpio_dev_priv *uc_priv;
> @@ -162,7 +175,8 @@ int ocelot_pinctrl_probe(struct udevice *dev)
>
> ret = mscc_pinctrl_probe(dev, FUNC_MAX, ocelot_pins,
>ARRAY_SIZE(ocelot_pins),
> - ocelot_function_names);
> + ocelot_function_names,
> + ocelot_gpios);
>
> if (ret)
> return ret;
> --
> 2.7.4
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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Re: [U-Boot] [PATCH v3 3/7] MSCC: Add device tree for Jaguar2 board
#size-cells = <1>;
> + ranges = <0 0x7000 0x200>;
> +
> + interrupt-parent = <>;
> +
> + cpu_ctrl: syscon@0 {
> + compatible = "mscc,jr2-cpu-syscon", "syscon";
> + reg = <0x0 0x2c>;
> + };
> +
> + intc: interrupt-controller@70 {
> + compatible = "mscc,jr2-icpu-intr";
> + reg = <0x70 0x94>;
> + #interrupt-cells = <1>;
> + interrupt-controller;
> + interrupt-parent = <>;
> + interrupts = <2>;
> + };
> +
> + uart0: serial@10 {
> + pinctrl-0 = <_pins>;
> + pinctrl-names = "default";
> + compatible = "ns16550a";
> + reg = <0x10 0x20>;
> + interrupts = <6>;
> + clocks = <_clk>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> +
> + status = "disabled";
> + };
> +
> + uart2: serial@100800 {
> + pinctrl-0 = <_pins>;
> + pinctrl-names = "default";
> + compatible = "ns16550a";
> + reg = <0x100800 0x20>;
> + interrupts = <7>;
> + clocks = <_clk>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> +
> + status = "disabled";
> + };
> +
> + spi0: spi-master@101000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + compatible = "snps,dw-apb-ssi";
> + reg = <0x101000 0x40>;
> + num-chipselect = <4>;
> + bus-num = <0>;
> + reg-io-width = <4>;
> + reg-shift = <2>;
> + spi-max-frequency = <1800>; /* input clock */
> + clocks = <_clk>;
> +
> + status = "disabled";
> + };
> +
> + reset@1010008 {
> + compatible = "mscc,jr2-chip-reset";
> + reg = <0x1010008 0x4>;
> + };
> +
> + gpio: pinctrl@1070034 {
> + compatible = "mscc,jr2-pinctrl";
Actually the binding for the pin controller of the Jaguar 2 had already
been posted for the Linux kernel. So in order to be able to use the same
dts between Linux and U-Boot and should be good to use the same binding:
https://elixir.bootlin.com/linux/v5.0-rc1/source/Documentation/devicetree/bindings/pinctrl/mscc,ocelot-pinctrl.txt#L6
Gregory
> + reg = <0x1010038 0x90>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + gpio-ranges = < 0 0 64>;
> +
> + sgpio_pins: sgpio-pins {
> + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3";
> + function = "sio";
> + };
> +
> + sgpio1_pins: sgpio1-pins {
> + pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13";
> + function = "sio1";
> + };
> +
> + sgpio2_pins: sgpio2-pins {
> + pins = "GPIO_30", "GPIO_31",
> +"GPIO_32", "GPIO_33";
> + function = "sio2";
> + };
> +
> + uart_pins: uart-pins {
> + pins = "GPIO_10", "GPIO_11";
> + function = "uart";
> + };
> +
> + uart2_pins: uart2-pins {
> + pins = "GPIO_24", "GPIO_25";
> + function = "uart2";
> + };
> + };
> +
> + sgpio: gpio@1010150 {
> + compatible = "mscc,ocelot-sgpio";
>
Re: [U-Boot] [PATCH] spi: soft_spi: Fix null ptr when probing soft_spi.
Hi Horatiu,
I am adding Daniel because actually this patch is needed to be able to
boot the Luton MIPS based platform. It is on this platform that we find
this issue.
Gregory
On mer., déc. 19 2018, Horatiu Vultur wrote:
> When probing soft_spi the result of dev_get_parent_priv(dev) in probe
> function is null ptr because the spi is on the ahb bus which has
> per_child_auto_alloc_size set to 0. Therefore it would generate an Ooops
> messages when accessing spi_slave structure.
>
> The fix consist of delaying the read of dm_spi_slave_platdata until a
> child under the spi is probed, to be able to read SPI mode. Therefore
> implement .child_pre_probe in which updates soft_spi_platdata based on
> child dm_spi_slave_platdata.
>
> Signed-off-by: Horatiu Vultur
> ---
> drivers/spi/soft_spi.c | 24 +---
> 1 file changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/spi/soft_spi.c b/drivers/spi/soft_spi.c
> index b06883f..e28591b 100644
> --- a/drivers/spi/soft_spi.c
> +++ b/drivers/spi/soft_spi.c
> @@ -210,18 +210,13 @@ static int soft_spi_ofdata_to_platdata(struct udevice
> *dev)
>
> static int soft_spi_probe(struct udevice *dev)
> {
> - struct spi_slave *slave = dev_get_parent_priv(dev);
> struct soft_spi_platdata *plat = dev->platdata;
> - int cs_flags, clk_flags;
> int ret;
>
> - cs_flags = (slave->mode & SPI_CS_HIGH) ? 0 : GPIOD_ACTIVE_LOW;
> - clk_flags = (slave->mode & SPI_CPOL) ? GPIOD_ACTIVE_LOW : 0;
> -
> if (gpio_request_by_name(dev, "cs-gpios", 0, >cs,
> - GPIOD_IS_OUT | cs_flags) ||
> + GPIOD_IS_OUT) ||
> gpio_request_by_name(dev, "gpio-sck", 0, >sclk,
> - GPIOD_IS_OUT | clk_flags))
> + GPIOD_IS_OUT))
> return -EINVAL;
>
> ret = gpio_request_by_name(dev, "gpio-mosi", 0, >mosi,
> @@ -241,6 +236,20 @@ static int soft_spi_probe(struct udevice *dev)
> return 0;
> }
>
> +static int soft_spi_child_pre_probe(struct udevice *dev)
> +{
> + struct udevice *bus = dev_get_parent(dev);
> + struct dm_spi_slave_platdata *slave = dev_get_parent_platdata(dev);
> + struct soft_spi_platdata *plat = bus->platdata;
> +
> + if (!(slave->mode & SPI_CS_HIGH))
> + plat->cs.flags |= GPIOD_ACTIVE_LOW;
> + if (slave->mode & SPI_CPOL)
> + plat->sclk.flags |= GPIOD_ACTIVE_LOW;
> +
> + return 0;
> +}
> +
> static const struct udevice_id soft_spi_ids[] = {
> { .compatible = "spi-gpio" },
> { }
> @@ -254,5 +263,6 @@ U_BOOT_DRIVER(soft_spi) = {
> .ofdata_to_platdata = soft_spi_ofdata_to_platdata,
> .platdata_auto_alloc_size = sizeof(struct soft_spi_platdata),
> .priv_auto_alloc_size = sizeof(struct soft_spi_priv),
> + .child_pre_probe = soft_spi_child_pre_probe,
> .probe = soft_spi_probe,
> };
> --
> 2.7.4
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
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Re: [U-Boot] [PATCH v4 6/7] MSCC: add board support for the Luton based evaluation board
Hi Daniel, On lun., déc. 17 2018, Daniel Schwierzeck wrote: > Am 17.12.18 um 10:55 schrieb Gregory CLEMENT: >> Hi Daniel, >> >> On dim., déc. 16 2018, Gregory CLEMENT wrote: >> >>> Hi Daniel, >>> >>> On sam., déc. 15 2018, Daniel Schwierzeck >>> wrote: >>> >>>> Am 14.12.18 um 16:16 schrieb Gregory CLEMENT: >>>>> Adding the support for the Luton boards PCB91 which share common code with >>>>> the Ocelots boards, including board code, device tree and configuration. >>>>> >>>>> Signed-off-by: Gregory CLEMENT >>>>> --- >>>>> MAINTAINERS| 1 + >>>>> arch/mips/dts/luton_pcb091.dts | 36 ++ >>>>> arch/mips/dts/mscc,luton.dtsi | 87 ++ >>>>> arch/mips/mach-mscc/Kconfig| 2 + >>>>> board/mscc/luton/Kconfig | 14 ++ >>>>> board/mscc/luton/Makefile | 3 ++ >>>>> board/mscc/luton/luton.c | 28 +++ >>>>> configs/mscc_luton_defconfig | 66 ++ >>>>> 8 files changed, 237 insertions(+) >>>>> create mode 100644 arch/mips/dts/luton_pcb091.dts >>>>> create mode 100644 arch/mips/dts/mscc,luton.dtsi >>>>> create mode 100644 board/mscc/luton/Kconfig >>>>> create mode 100644 board/mscc/luton/Makefile >>>>> create mode 100644 board/mscc/luton/luton.c >>>>> create mode 100644 configs/mscc_luton_defconfig >>>>> >>>> >>>>> diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig >>>>> new file mode 100644 >>>>> index 00..47fe12b6ee >>>>> --- /dev/null >>>>> +++ b/configs/mscc_luton_defconfig >>>>> @@ -0,0 +1,66 @@ >>>>> +CONFIG_MIPS=y >>>>> +CONFIG_SYS_TEXT_BASE=0x4000 >>>>> +CONFIG_SYS_MALLOC_F_LEN=0x2000 >>>>> +CONFIG_DEBUG_UART_BOARD_INIT=y >>>>> +CONFIG_DEBUG_UART_BASE=0x7010 >>>>> +CONFIG_DEBUG_UART_CLOCK=20833 >>>>> +CONFIG_ARCH_MSCC=y >>>>> +CONFIG_TARGET_LUTON_PCB091=y >>>>> +CONFIG_DDRTYPE_MT47H128M8HQ=y >>>>> +CONFIG_SYS_LITTLE_ENDIAN=y >>>>> +CONFIG_MIPS_BOOT_FDT=y >>>>> +CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" >>>>> +CONFIG_DEBUG_UART=y >>>>> +CONFIG_FIT=y >>>>> +CONFIG_BOOTDELAY=3 >>>>> +CONFIG_USE_BOOTARGS=y >>>>> +CONFIG_BOOTARGS="console=ttyS0,115200" >>>>> +CONFIG_LOGLEVEL=7 >>>>> +CONFIG_DISPLAY_CPUINFO=y >>>>> +CONFIG_SYS_PROMPT="pcb091 # " >>>>> +# CONFIG_CMD_BDI is not set >>>>> +# CONFIG_CMD_CONSOLE is not set >>>>> +# CONFIG_CMD_ELF is not set >>>>> +# CONFIG_CMD_EXPORTENV is not set >>>>> +# CONFIG_CMD_IMPORTENV is not set >>>>> +# CONFIG_CMD_CRC32 is not set >>>>> +CONFIG_CMD_MD5SUM=y >>>>> +CONFIG_CMD_MEMINFO=y >>>>> +CONFIG_CMD_MEMTEST=y >>>>> +# CONFIG_CMD_FLASH is not set >>>>> +CONFIG_CMD_GPIO=y >>>>> +CONFIG_CMD_SF=y >>>>> +CONFIG_CMD_SPI=y >>>>> +CONFIG_CMD_DHCP=y >>>>> +# CONFIG_NET_TFTP_VARS is not set >>>>> +# CONFIG_CMD_NFS is not set >>>>> +CONFIG_CMD_PING=y >>>>> +CONFIG_CMD_MTDPARTS=y >>>>> +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" >>>>> +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)" >>>>> +# CONFIG_ISO_PARTITION is not set >>>>> +CONFIG_OF_EMBED=y >>>> >>>> this gives now a build warning >>>> >>>> = WARNING == >>>> CONFIG_OF_EMBED is enabled. This option should only >>>> be used for debugging purposes. Please use >>>> CONFIG_OF_SEPARATE for boards in mainline. >>>> See doc/README.fdt-control for more info. >>>> >>> >>> I did not get this warning. For now I base my series on v2018.11, >>> should I base it on v2019.01-rc1 (i didn't realized it was already >>> released) ? >>> >>>> >>>> >>>> Shall I change it when applying or do you want to test it first and send >>>> a follow-up patch? >>> >>> I'd like to test it to be sure it continue to work. >> >> I had a closer look on this issue and actually we have already a patch >> series to apply which it is planned to be sent very soon. With this new >> series we will be able to support multiple boards with this series >> CONFIG_OF_SEPARATE will be used instead of CONFIG_OF_EMBED. >> >> Would it be possible to keep this series as is ? >> > > I asked because I had to fix some minor merge conflicts when applying > and I had to re-sync the defconfig files due to various changes in > mainline. Thus I need to update your patches anyway and a simply > removing CONFIG_OF_EMBED=y would be a trivial fix. > > You can review the current patch queue at u-boot-mips/microsemi which is > based on u-boot-mips/next. I tested you branch and it worked on both Ocelot and Luton. So I'm fine with your changes. Thanks ! Gregory > > -- > - Daniel -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 6/7] MSCC: add board support for the Luton based evaluation board
Hi Daniel, On dim., déc. 16 2018, Gregory CLEMENT wrote: > Hi Daniel, > > On sam., déc. 15 2018, Daniel Schwierzeck > wrote: > >> Am 14.12.18 um 16:16 schrieb Gregory CLEMENT: >>> Adding the support for the Luton boards PCB91 which share common code with >>> the Ocelots boards, including board code, device tree and configuration. >>> >>> Signed-off-by: Gregory CLEMENT >>> --- >>> MAINTAINERS| 1 + >>> arch/mips/dts/luton_pcb091.dts | 36 ++ >>> arch/mips/dts/mscc,luton.dtsi | 87 ++ >>> arch/mips/mach-mscc/Kconfig| 2 + >>> board/mscc/luton/Kconfig | 14 ++ >>> board/mscc/luton/Makefile | 3 ++ >>> board/mscc/luton/luton.c | 28 +++ >>> configs/mscc_luton_defconfig | 66 ++ >>> 8 files changed, 237 insertions(+) >>> create mode 100644 arch/mips/dts/luton_pcb091.dts >>> create mode 100644 arch/mips/dts/mscc,luton.dtsi >>> create mode 100644 board/mscc/luton/Kconfig >>> create mode 100644 board/mscc/luton/Makefile >>> create mode 100644 board/mscc/luton/luton.c >>> create mode 100644 configs/mscc_luton_defconfig >>> >> >>> diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig >>> new file mode 100644 >>> index 00..47fe12b6ee >>> --- /dev/null >>> +++ b/configs/mscc_luton_defconfig >>> @@ -0,0 +1,66 @@ >>> +CONFIG_MIPS=y >>> +CONFIG_SYS_TEXT_BASE=0x4000 >>> +CONFIG_SYS_MALLOC_F_LEN=0x2000 >>> +CONFIG_DEBUG_UART_BOARD_INIT=y >>> +CONFIG_DEBUG_UART_BASE=0x7010 >>> +CONFIG_DEBUG_UART_CLOCK=20833 >>> +CONFIG_ARCH_MSCC=y >>> +CONFIG_TARGET_LUTON_PCB091=y >>> +CONFIG_DDRTYPE_MT47H128M8HQ=y >>> +CONFIG_SYS_LITTLE_ENDIAN=y >>> +CONFIG_MIPS_BOOT_FDT=y >>> +CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" >>> +CONFIG_DEBUG_UART=y >>> +CONFIG_FIT=y >>> +CONFIG_BOOTDELAY=3 >>> +CONFIG_USE_BOOTARGS=y >>> +CONFIG_BOOTARGS="console=ttyS0,115200" >>> +CONFIG_LOGLEVEL=7 >>> +CONFIG_DISPLAY_CPUINFO=y >>> +CONFIG_SYS_PROMPT="pcb091 # " >>> +# CONFIG_CMD_BDI is not set >>> +# CONFIG_CMD_CONSOLE is not set >>> +# CONFIG_CMD_ELF is not set >>> +# CONFIG_CMD_EXPORTENV is not set >>> +# CONFIG_CMD_IMPORTENV is not set >>> +# CONFIG_CMD_CRC32 is not set >>> +CONFIG_CMD_MD5SUM=y >>> +CONFIG_CMD_MEMINFO=y >>> +CONFIG_CMD_MEMTEST=y >>> +# CONFIG_CMD_FLASH is not set >>> +CONFIG_CMD_GPIO=y >>> +CONFIG_CMD_SF=y >>> +CONFIG_CMD_SPI=y >>> +CONFIG_CMD_DHCP=y >>> +# CONFIG_NET_TFTP_VARS is not set >>> +# CONFIG_CMD_NFS is not set >>> +CONFIG_CMD_PING=y >>> +CONFIG_CMD_MTDPARTS=y >>> +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" >>> +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)" >>> +# CONFIG_ISO_PARTITION is not set >>> +CONFIG_OF_EMBED=y >> >> this gives now a build warning >> >> = WARNING == >> CONFIG_OF_EMBED is enabled. This option should only >> be used for debugging purposes. Please use >> CONFIG_OF_SEPARATE for boards in mainline. >> See doc/README.fdt-control for more info. >> > > I did not get this warning. For now I base my series on v2018.11, > should I base it on v2019.01-rc1 (i didn't realized it was already > released) ? > >> >> >> Shall I change it when applying or do you want to test it first and send >> a follow-up patch? > > I'd like to test it to be sure it continue to work. I had a closer look on this issue and actually we have already a patch series to apply which it is planned to be sent very soon. With this new series we will be able to support multiple boards with this series CONFIG_OF_SEPARATE will be used instead of CONFIG_OF_EMBED. Would it be possible to keep this series as is ? Thanks, Gregory > > Thanks, > > Gregory > >> >>> +CONFIG_ENV_IS_IN_SPI_FLASH=y >>> +CONFIG_NET_RANDOM_ETHADDR=y >>> +CONFIG_CLK=y >>> +CONFIG_DM_GPIO=y >>> +CONFIG_DM_SPI_FLASH=y >>> +CONFIG_SPI_FLASH=y >>> +CONFIG_SPI_FLASH_BAR=y >>> +CONFIG_SPI_FLASH_GIGADEVICE=y >>> +CONFIG_SPI_FLASH_MACRONIX=y >>> +CONFIG_SPI_FLASH_SPANSION=y >>> +CONFIG_SPI_FLASH_STMICRO=y >>> +CONFIG_SPI_FLASH_WINBOND=y >>> +CONFIG_SPI_FLASH_MTD=y >>> +CONFIG_DM_ETH=y >>> +CONFIG_PINCTRL=y >>> +CONFIG_PINCONF=y >>> +CONFIG_DM_SERIAL=y >>> +CONFIG_DEBUG_UART_SHIFT=2 >>> +CONFIG_SYS_NS16550=y >>> +CONFIG_SPI=y >>> +CONFIG_DM_SPI=y >>> +CONFIG_SOFT_SPI=y >>> +CONFIG_LZMA=y >>> +CONFIG_XZ=y >>> >> >> -- >> - Daniel > > -- > Gregory Clement, Bootlin > Embedded Linux and Kernel engineering > http://bootlin.com > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 6/7] MSCC: add board support for the Luton based evaluation board
Hi Daniel, On sam., déc. 15 2018, Daniel Schwierzeck wrote: > Am 14.12.18 um 16:16 schrieb Gregory CLEMENT: >> Adding the support for the Luton boards PCB91 which share common code with >> the Ocelots boards, including board code, device tree and configuration. >> >> Signed-off-by: Gregory CLEMENT >> --- >> MAINTAINERS| 1 + >> arch/mips/dts/luton_pcb091.dts | 36 ++ >> arch/mips/dts/mscc,luton.dtsi | 87 ++ >> arch/mips/mach-mscc/Kconfig| 2 + >> board/mscc/luton/Kconfig | 14 ++ >> board/mscc/luton/Makefile | 3 ++ >> board/mscc/luton/luton.c | 28 +++ >> configs/mscc_luton_defconfig | 66 ++ >> 8 files changed, 237 insertions(+) >> create mode 100644 arch/mips/dts/luton_pcb091.dts >> create mode 100644 arch/mips/dts/mscc,luton.dtsi >> create mode 100644 board/mscc/luton/Kconfig >> create mode 100644 board/mscc/luton/Makefile >> create mode 100644 board/mscc/luton/luton.c >> create mode 100644 configs/mscc_luton_defconfig >> > >> diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig >> new file mode 100644 >> index 00..47fe12b6ee >> --- /dev/null >> +++ b/configs/mscc_luton_defconfig >> @@ -0,0 +1,66 @@ >> +CONFIG_MIPS=y >> +CONFIG_SYS_TEXT_BASE=0x4000 >> +CONFIG_SYS_MALLOC_F_LEN=0x2000 >> +CONFIG_DEBUG_UART_BOARD_INIT=y >> +CONFIG_DEBUG_UART_BASE=0x7010 >> +CONFIG_DEBUG_UART_CLOCK=20833 >> +CONFIG_ARCH_MSCC=y >> +CONFIG_TARGET_LUTON_PCB091=y >> +CONFIG_DDRTYPE_MT47H128M8HQ=y >> +CONFIG_SYS_LITTLE_ENDIAN=y >> +CONFIG_MIPS_BOOT_FDT=y >> +CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" >> +CONFIG_DEBUG_UART=y >> +CONFIG_FIT=y >> +CONFIG_BOOTDELAY=3 >> +CONFIG_USE_BOOTARGS=y >> +CONFIG_BOOTARGS="console=ttyS0,115200" >> +CONFIG_LOGLEVEL=7 >> +CONFIG_DISPLAY_CPUINFO=y >> +CONFIG_SYS_PROMPT="pcb091 # " >> +# CONFIG_CMD_BDI is not set >> +# CONFIG_CMD_CONSOLE is not set >> +# CONFIG_CMD_ELF is not set >> +# CONFIG_CMD_EXPORTENV is not set >> +# CONFIG_CMD_IMPORTENV is not set >> +# CONFIG_CMD_CRC32 is not set >> +CONFIG_CMD_MD5SUM=y >> +CONFIG_CMD_MEMINFO=y >> +CONFIG_CMD_MEMTEST=y >> +# CONFIG_CMD_FLASH is not set >> +CONFIG_CMD_GPIO=y >> +CONFIG_CMD_SF=y >> +CONFIG_CMD_SPI=y >> +CONFIG_CMD_DHCP=y >> +# CONFIG_NET_TFTP_VARS is not set >> +# CONFIG_CMD_NFS is not set >> +CONFIG_CMD_PING=y >> +CONFIG_CMD_MTDPARTS=y >> +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" >> +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)" >> +# CONFIG_ISO_PARTITION is not set >> +CONFIG_OF_EMBED=y > > this gives now a build warning > > = WARNING == > CONFIG_OF_EMBED is enabled. This option should only > be used for debugging purposes. Please use > CONFIG_OF_SEPARATE for boards in mainline. > See doc/README.fdt-control for more info. > I did not get this warning. For now I base my series on v2018.11, should I base it on v2019.01-rc1 (i didn't realized it was already released) ? > > > Shall I change it when applying or do you want to test it first and send > a follow-up patch? I'd like to test it to be sure it continue to work. Thanks, Gregory > >> +CONFIG_ENV_IS_IN_SPI_FLASH=y >> +CONFIG_NET_RANDOM_ETHADDR=y >> +CONFIG_CLK=y >> +CONFIG_DM_GPIO=y >> +CONFIG_DM_SPI_FLASH=y >> +CONFIG_SPI_FLASH=y >> +CONFIG_SPI_FLASH_BAR=y >> +CONFIG_SPI_FLASH_GIGADEVICE=y >> +CONFIG_SPI_FLASH_MACRONIX=y >> +CONFIG_SPI_FLASH_SPANSION=y >> +CONFIG_SPI_FLASH_STMICRO=y >> +CONFIG_SPI_FLASH_WINBOND=y >> +CONFIG_SPI_FLASH_MTD=y >> +CONFIG_DM_ETH=y >> +CONFIG_PINCTRL=y >> +CONFIG_PINCONF=y >> +CONFIG_DM_SERIAL=y >> +CONFIG_DEBUG_UART_SHIFT=2 >> +CONFIG_SYS_NS16550=y >> +CONFIG_SPI=y >> +CONFIG_DM_SPI=y >> +CONFIG_SOFT_SPI=y >> +CONFIG_LZMA=y >> +CONFIG_XZ=y >> > > -- > - Daniel -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 7/7] MIPS: bootm: Add support for compatibility with redboot
The kernels built to be launch by redboot (such as the Vcore III) have
different expectation in the way the data were passed.
Unlike with yamon, the command line is expected to be a single string
passed in argv[1]. An other expectation is that the arguments are located
in the cached address space.
However, like yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel.
Signed-off-by: Gregory CLEMENT
---
arch/mips/Kconfig | 4 +++
arch/mips/lib/bootm.c | 76 +++
2 files changed, 60 insertions(+), 20 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bfe9c11069..eae5cb0f99 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -63,6 +63,7 @@ config ARCH_MSCC
bool "Support MSCC VCore-III"
select OF_CONTROL
select DM
+ select MIPS_BOOT_CMDLINE_SINGLESTRING
config ARCH_BMIPS
bool "Support BMIPS SoCs"
@@ -466,6 +467,9 @@ config MIPS_BOOT_CONFIG_WORD1
help
Value which is inserted as boot config word 1.
+config MIPS_BOOT_CMDLINE_SINGLESTRING
+ bool
+
endif
endmenu
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index deca5189e3..38243cfa92 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
#defineLINUX_MAX_ENVS 256
#defineLINUX_MAX_ARGS 256
+enum legacy_boot_type {
+ LEGACY_BOOT_YAML,
+ LEGACY_BOOT_CMDLINE_SINGLESTRING,
+};
+
static int linux_argc;
static char **linux_argv;
static char *linux_argp;
@@ -44,22 +49,47 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, sp, gd->ram_top - sp);
}
-static void linux_cmdline_init(void)
+static void linux_cmdline_init(enum legacy_boot_type boot_type)
{
+ switch (boot_type) {
+ /*
+* Vcore III linux kernels expect arguments in the cached
+* address space. They also expect the command line being a
+* single string in the first argument
+*/
+ case LEGACY_BOOT_CMDLINE_SINGLESTRING:
+ linux_argv = (char **)(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ linux_argv[1] = linux_argp;
+ break;
+ case LEGACY_BOOT_YAML:
+ /* fall-through */
+ default:
+ linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ }
linux_argc = 1;
- linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
linux_argv[0] = 0;
- linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
}
-static void linux_cmdline_set(const char *value, size_t len)
+static void linux_cmdline_set(const char *value, size_t len,
+ enum legacy_boot_type boot_type)
{
- linux_argv[linux_argc] = linux_argp;
memcpy(linux_argp, value, len);
- linux_argp[len] = 0;
-
+ switch (boot_type) {
+ case LEGACY_BOOT_CMDLINE_SINGLESTRING:
+ linux_argv[linux_argc] = linux_argp;
+ linux_argp[len] = 0;
+ linux_argc++;
+ break;
+ case LEGACY_BOOT_YAML:
+ /* fall-through */
+ default:
+ linux_argp[len] = ' ';
+ linux_argp[len + 1] = 0;
+ linux_argc = 2;
+ }
linux_argp += len + 1;
- linux_argc++;
}
static void linux_cmdline_dump(void)
@@ -73,12 +103,11 @@ static void linux_cmdline_dump(void)
debug(" arg %03d: %s\n", i, linux_argv[i]);
}
-static void linux_cmdline_legacy(bootm_headers_t *images)
+static void linux_cmdline_legacy(bootm_headers_t *images,
+enum legacy_boot_type boot_type)
{
const char *bootargs, *next, *quote;
-
- linux_cmdline_init();
-
+ linux_cmdline_init(boot_type);
bootargs = env_get("bootargs");
if (!bootargs)
return;
@@ -104,7 +133,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
if (!next)
next = bootargs + strlen(bootargs);
- linux_cmdline_set(bootargs, next - bootargs);
+ linux_cmdline_set(bootargs, next - bootargs, boot_type);
if (*next)
next++;
@@ -113,7 +142,8 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
}
}
-static void linux_cmdline_append(bootm_headers_t *images)
+static void linux_cmdline_append(bootm_headers_t *images,
+enum legacy_boot_type boot_type)
{
char buf[24];
ulong mem, rd_start, rd_size;
@@ -121,7 +151,7 @@ static void linux_cmdline_append(bootm_headers_t *images)
/* append mem *
[U-Boot] [PATCH v4 3/7] MSCC: add support for Ocelot SoCs
This family of SoCs are found in the Microsemi Switches solution and have already a support in the linux kernel. Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 7 + arch/mips/Kconfig | 6 + arch/mips/Makefile| 1 + arch/mips/mach-mscc/Kconfig | 69 ++ arch/mips/mach-mscc/Makefile | 5 + arch/mips/mach-mscc/cpu.c | 90 +++ arch/mips/mach-mscc/dram.c| 71 ++ arch/mips/mach-mscc/include/ioremap.h | 49 ++ arch/mips/mach-mscc/include/mach/common.h | 24 + arch/mips/mach-mscc/include/mach/ddr.h| 708 ++ .../mach-mscc/include/mach/ocelot/ocelot.h| 24 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 + .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 +++ arch/mips/mach-mscc/include/mach/tlb.h| 55 ++ arch/mips/mach-mscc/lowlevel_init.S | 23 + arch/mips/mach-mscc/reset.c | 30 + 16 files changed, 1457 insertions(+) create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/reset.c diff --git a/MAINTAINERS b/MAINTAINERS index abdb6dcdb5..53a3c5bec6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -484,6 +484,13 @@ S: Maintained T: git git://git.denx.de/u-boot-mips.git F: arch/mips/ +MIPS MSCC +M: Gregory CLEMENT +M: Lars Povlsen +M: Horatiu Vultur +S: Maintained +F: arch/mips/mach-mscc/ + MMC M: Jaehoon Chung S: Maintained diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6d646ef999..bfe9c11069 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -59,6 +59,11 @@ config ARCH_ATH79 select OF_CONTROL imply CMD_DM +config ARCH_MSCC + bool "Support MSCC VCore-III" + select OF_CONTROL + select DM + config ARCH_BMIPS bool "Support BMIPS SoCs" select CLK @@ -135,6 +140,7 @@ source "board/imgtec/xilfpga/Kconfig" source "board/micronas/vct/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-mscc/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mt7620/Kconfig" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 802244a06e..124e93fa26 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,6 +15,7 @@ machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 machine-$(CONFIG_ARCH_MT7620) += mt7620 +machine-$(CONFIG_ARCH_MSCC) += mscc machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig new file mode 100644 index 00..7f1b270207 --- /dev/null +++ b/arch/mips/mach-mscc/Kconfig @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +menu "MSCC VCore-III platforms" + depends on ARCH_MSCC + +config SOC_VCOREIII + select MIPS_TUNE_24KC + select ROM_EXCEPTION_VECTORS + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + bool + +config SYS_SOC + default "mscc" + +config SOC_OCELOT + bool + select SOC_VCOREIII + help + This supports MSCC Ocelot family of SOCs. + +config SYS_CONFIG_NAME + default "vcoreiii" + +choice + prompt "Board select" + +config TARGET_OCELOT_PCB120 + bool "MSCC PCB120 Reference Board (aka VSC5635EV)" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb120 + +config TARGET_OCELOT_PCB123 + bool "MSCC PCB123 Reference Board (aka VSC7514EV))" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb123 + +endchoice + +choice + prompt "DDR type" + +config DDRTYPE_H5TQ4G63MFR + bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)" + +co
[U-Boot] [PATCH v4 5/7] MSCC: add board support for the Ocelots based evaluation boards
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 5 +
arch/mips/dts/mscc,ocelot.dtsi | 152 +++
arch/mips/dts/mscc,ocelot_pcb.dtsi | 42
arch/mips/dts/ocelot_pcb120.dts | 12 +++
arch/mips/dts/ocelot_pcb123.dts | 12 +++
arch/mips/mach-mscc/Kconfig | 2 +
board/mscc/ocelot/Kconfig| 14 +++
board/mscc/ocelot/Makefile | 4 +
board/mscc/ocelot/ocelot.c | 58 ++
configs/mscc_ocelot_defconfig| 73 +
configs/mscc_ocelot_pcb120_defconfig | 66
include/configs/vcoreiii.h | 82 +++
12 files changed, 522 insertions(+)
create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
create mode 100644 arch/mips/dts/ocelot_pcb120.dts
create mode 100644 arch/mips/dts/ocelot_pcb123.dts
create mode 100644 board/mscc/ocelot/Kconfig
create mode 100644 board/mscc/ocelot/Makefile
create mode 100644 board/mscc/ocelot/ocelot.c
create mode 100644 configs/mscc_ocelot_defconfig
create mode 100644 configs/mscc_ocelot_pcb120_defconfig
create mode 100644 include/configs/vcoreiii.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 53a3c5bec6..c906ca006b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -490,6 +490,11 @@ M: Lars Povlsen
M: Horatiu Vultur
S: Maintained
F: arch/mips/mach-mscc/
+F: arch/mips/dts/mscc*
+F: arch/mips/dts/ocelot*
+F: board/mscc/
+F: configs/mscc*
+F: include/configs/vcoreiii.h
MMC
M: Jaehoon Chung
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
new file mode 100644
index 00..87b4736285
--- /dev/null
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,ocelot";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 =
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x7000 0x200>;
+
+ interrupt-parent = <>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@10 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x10 0x20>;
+ interrupts = <6>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <
[U-Boot] [PATCH v4 6/7] MSCC: add board support for the Luton based evaluation board
Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS| 1 +
arch/mips/dts/luton_pcb091.dts | 36 ++
arch/mips/dts/mscc,luton.dtsi | 87 ++
arch/mips/mach-mscc/Kconfig| 2 +
board/mscc/luton/Kconfig | 14 ++
board/mscc/luton/Makefile | 3 ++
board/mscc/luton/luton.c | 28 +++
configs/mscc_luton_defconfig | 66 ++
8 files changed, 237 insertions(+)
create mode 100644 arch/mips/dts/luton_pcb091.dts
create mode 100644 arch/mips/dts/mscc,luton.dtsi
create mode 100644 board/mscc/luton/Kconfig
create mode 100644 board/mscc/luton/Makefile
create mode 100644 board/mscc/luton/luton.c
create mode 100644 configs/mscc_luton_defconfig
diff --git a/MAINTAINERS b/MAINTAINERS
index c906ca006b..4ce19aef11 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -490,6 +490,7 @@ M: Lars Povlsen
M: Horatiu Vultur
S: Maintained
F: arch/mips/mach-mscc/
+F: arch/mips/dts/luton*
F: arch/mips/dts/mscc*
F: arch/mips/dts/ocelot*
F: board/mscc/
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
new file mode 100644
index 00..74f9274c21
--- /dev/null
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+ model = "Luton10 PCB091 Reference Board";
+ compatible = "mscc,luton-pcb091", "mscc,luton";
+
+ aliases {
+ serial0 =
+ spi0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <1800>; /* input clock */
+ reg = <0>; /* CS0 */
+ spi-cs-high;
+ };
+};
+
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
new file mode 100644
index 00..6a4ad2a5be
--- /dev/null
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,luton";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 =
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20833>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x1020>;
+
+ uart0: serial@1010 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ compatible = "ns16550a";
+ reg = <0x1010 0x20>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@70068 {
+ compatible = "mscc,luton-pinctrl";
+ reg = <0x70068 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 32>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_30", "GPIO_31";
+ function = "uart";
+ };
+
+ };
+
+ gpio_spi_bitbang: gpio@1064 {
+ compatible = "mscc,spi-bitbang-gpio";
+ reg = <0x1064 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ };
+
+ spi0: spi-bitbang {
+ compatible = "spi-gpio";
+ status = "okay";
+ gpio-sck = <_spi_bitbang 6 0>;
+ gpio-mi
[U-Boot] [PATCH v4 4/7] MSCC: add support for Luton SoCs
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT
---
arch/mips/mach-mscc/Kconfig | 13 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 14 +-
arch/mips/mach-mscc/dram.c| 2 +
arch/mips/mach-mscc/include/mach/common.h | 4 +
arch/mips/mach-mscc/include/mach/ddr.h| 112 +++-
.../mips/mach-mscc/include/mach/luton/luton.h | 24 ++
.../include/mach/luton/luton_devcpu_gcb.h | 14 +
.../include/mach/luton/luton_icpu_cfg.h | 245 ++
arch/mips/mach-mscc/lowlevel_init.S | 7 +
arch/mips/mach-mscc/lowlevel_init_luton.S | 62 +
11 files changed, 494 insertions(+), 4 deletions(-)
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 7f1b270207..a8cace0e79 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -21,6 +21,12 @@ config SOC_OCELOT
help
This supports MSCC Ocelot family of SOCs.
+config SOC_LUTON
+ bool
+ select SOC_VCOREIII
+ help
+ This supports MSCC Luton family of SOCs.
+
config SYS_CONFIG_NAME
default "vcoreiii"
@@ -41,6 +47,13 @@ config TARGET_OCELOT_PCB123
When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
ocelot_pcb123
+config TARGET_LUTON_PCB091
+ bool "MSCC PCB091 Reference Board"
+ select SOC_LUTON
+ select MSCC_BITBANG_SPI_GPIO
+ help
+ When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
+ luton_pcb091
endchoice
choice
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index d14ec33838..6c60f26ca4 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -3,3 +3,4 @@
CFLAGS_cpu.o += -finline-limit=64000
obj-y += cpu.o dram.o reset.o lowlevel_init.o
+obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index b503e1407b..5be8ff69d5 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -48,6 +48,10 @@ void vcoreiii_tlb_init(void)
*/
create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
MMU_REGIO_RW);
+#ifdef CONFIG_SOC_LUTON
+ create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
+ MMU_REGIO_RW);
+#endif
#if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO
/*
@@ -75,6 +79,14 @@ void vcoreiii_tlb_init(void)
int mach_cpu_init(void)
{
/* Speed up NOR flash access */
+#ifdef CONFIG_SOC_LUTON
+ writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
+ ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG);
+
+ writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
+ ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
+ ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
+#else
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
/*
@@ -85,6 +97,6 @@ int mach_cpu_init(void)
writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1));
writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2));
writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3));
-
+#endif
return 0;
}
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index 5acee6f918..309007c14e 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -19,9 +19,11 @@ static inline int vcoreiii_train_bytelane(void)
ret = hal_vcoreiii_train_bytelane(0);
+#ifdef CONFIG_SOC_OCELOT
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
+#endif
return ret;
}
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index 842462aeed..931ecd7985 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -10,6 +10,10 @@
#include
#include
#include
+#elif defined(CONFIG_SOC_LUTON)
+#include
+#include
+#include
#else
#error Unsupported platform
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h
b/arch/mips/mach-mscc/include/mach/ddr.h
index 262985c8c9..f445e63a35 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -614,6 +614,98 @@ static inline int dram_check(void)
}
return 0;
}
+#else /* Luton */
+
+static inline void sleep_100ns(u32 val)
+{
+}
+
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+ setbits_le32(BASE_C
[U-Boot] [PATCH v4 2/7] MIPS: Allow to prefetch and lock instructions into cache
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT
---
arch/mips/include/asm/cacheops.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 3161875441..98b67ccc8e 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void
*addr)
#endif
}
+#define MIPS32_WHICH_ICACHE0x0
+#define MIPS32_FETCH_AND_LOCK 0x7
+
+#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
+
+/* Prefetch and lock instructions into cache */
+static inline void icache_lock(void *func, size_t len)
+{
+ int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
+
+ for (i = 0; i < lines; i++) {
+ asm volatile (" cache %0, %1(%2)"
+ : /* No Output */
+ : "I" ICACHE_LOAD_LOCK,
+ "n" (i * ARCH_DMA_MINALIGN),
+ "r" (func)
+ : /* No Clobbers */);
+ }
+}
#endif /* !__ASSEMBLY__ */
/*
--
2.19.2
___
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U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v4 1/7] MIPS: move create_tlb() in an proper header: mipsregs.h
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c | 10 --
arch/mips/include/asm/mipsregs.h | 11 +++
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 5c56ab0289..a403ff729b 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
}
#endif
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
- write_c0_entrylo0(low0);
- write_c0_pagemask(pagemask);
- write_c0_entrylo1(low1);
- write_c0_entryhi(hi);
- write_c0_index(index);
- tlb_write_indexed();
-}
-
int arch_cpu_init(void)
{
mips_cache_probe();
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 48fa1f1f7f..930562ebb2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2005,6 +2005,17 @@ static inline unsigned int get_ebase_cpunum(void)
return read_c0_ebase() & 0x3ff;
}
+static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
+u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
--
2.19.2
___
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[U-Boot] [PATCH v4 0/7] Add support for the SoCs found in Microsemi switches
Hello,
For the record this the fourth version of the series adding the
support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them
belongs to the same family Vcore III.
We found them on various advanced switches product.
The support for Ocelot already have been submit to Linux, but not yet
the Luton support.
The comments on v3 were fewer and quite easy to address, so I am able
to send a new version right one (hopping it will be the final one :)
).
Gregory
Changelog:
v3 -> v4:
- add the support for the legacy kernel more generic and more related
to the old bootloader: redboot
- removed useless test on CONFIG_ARCH_MSCC in
arch/mips/mach-mscc/include/ioremap.h
- add an explanation about the cache instruction lock in
hal_vcoreiii_ddr_failed()
- use __raw_read/write instead of directly use pointer dereferencing
- use rmb instead of asm volatile("" : : : "memory");
- remove remaining C++ style comment
- use __maybe_unused instead of __attribute__ ((unused))
- indent by an extra space the instructions in the delay slot
v2 -> v3:
- Added n entry in the MAINTAINER file for the SoCs
- Fixup the last errors from checkpatch, the remaining ones are only
about volatile, long line and Kconfig, but each ones have good
reason to be here.
- Add SPI NAND flash support in device tree and configuration files,
the driver are already be merged in U-Boot.
- In order to improve boot time, setup the TLB to allow using cache
in the memory mapped to the SPI NOR.
- Removed all the macro REG_CFG to only keep direct access to memory.
- Put back the setting of the interrupt map as it is needed by
mainline kernel (without it the kernel doesn't finish to boot)
- During DDR training, prevent the compiler reordering the
instruction.
- Add early debug support to Ocelot (it was already done for Luton)
v1 -> v2:
- a big clean-up for indentation and some style issue
- usage of the clrsetbits family functions where it was possible
- split the patches for Ocelot and Luton
- add a new patch to introduce the icache_lock function which was in
the mscc directory in the first version
- remove more unused define in the platform header files
- use the automatic cache size detection instead of hard coding it
- reduce the tlb init to only two entries for the IO as needed by the
kernel
- remove the interrupt disabling
- fix the ddr init for luton
Gregory CLEMENT (7):
MIPS: move create_tlb() in an proper header: mipsregs.h
MIPS: Allow to prefetch and lock instructions into cache
MSCC: add support for Ocelot SoCs
MSCC: add support for Luton SoCs
MSCC: add board support for the Ocelots based evaluation boards
MSCC: add board support for the Luton based evaluation board
MIPS: bootm: Add support for compatibility with redboot
MAINTAINERS | 13 +
arch/mips/Kconfig | 10 +
arch/mips/Makefile| 1 +
arch/mips/cpu/cpu.c | 10 -
arch/mips/dts/luton_pcb091.dts| 36 +
arch/mips/dts/mscc,luton.dtsi | 87 ++
arch/mips/dts/mscc,ocelot.dtsi| 152
arch/mips/dts/mscc,ocelot_pcb.dtsi| 42 +
arch/mips/dts/ocelot_pcb120.dts | 12 +
arch/mips/dts/ocelot_pcb123.dts | 12 +
arch/mips/include/asm/cacheops.h | 19 +
arch/mips/include/asm/mipsregs.h | 11 +
arch/mips/lib/bootm.c | 76 +-
arch/mips/mach-mscc/Kconfig | 86 ++
arch/mips/mach-mscc/Makefile | 6 +
arch/mips/mach-mscc/cpu.c | 102 +++
arch/mips/mach-mscc/dram.c| 73 ++
arch/mips/mach-mscc/include/ioremap.h | 49 ++
arch/mips/mach-mscc/include/mach/common.h | 28 +
arch/mips/mach-mscc/include/mach/ddr.h| 814 ++
.../mips/mach-mscc/include/mach/luton/luton.h | 24 +
.../include/mach/luton/luton_devcpu_gcb.h | 14 +
.../include/mach/luton/luton_icpu_cfg.h | 245 ++
.../mach-mscc/include/mach/ocelot/ocelot.h| 24 +
.../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 +
.../include/mach/ocelot/ocelot_icpu_cfg.h | 274 ++
arch/mips/mach-mscc/include/mach/tlb.h| 55 ++
arch/mips/mach-mscc/lowlevel_init.S | 30 +
arch/mips/mach-mscc/lowlevel_init_luton.S | 62 ++
arch/mips/mach-mscc/reset.c | 30 +
board/mscc/luton/Kconfig | 14 +
board/mscc/luton/Makefile | 3 +
board/mscc/luton/luton.c | 28 +
board/mscc/ocelot/Kconfig | 14 +
board/mscc/ocelot/Makefile| 4 +
board/mscc/ocelot/ocelot.c| 58 ++
configs/mscc_luton_defconfig | 66 ++
configs/mscc_ocelot_defconfig | 73 ++
configs/mscc_ocelot_pc
Re: [U-Boot] [PATCH v3 7/7] MIPS: bootm: Add support for Vcore III linux kernel
Hi Daniel,
On lun., déc. 10 2018, Daniel Schwierzeck wrote:
> Am 05.12.18 um 18:10 schrieb Gregory CLEMENT:
>> The kernels built for the Vcore III linux kernel have different
>> expectation in the way the data were passed.
>>
>> Unlike with yamon, the command line is expected to be a single string
>> passed in argv[1]. An other expectation is that the arguments are located
>> in the cached address space.
>>
>> However, like yamon, they expect that rd_start and rd_size was passed by
>> the bootloader in the command line of the kernel, and besides that it
>> also wait for the root=/dev/ram0.
>
>
>
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> arch/mips/lib/bootm.c | 78 ---
>> 1 file changed, 58 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
>> index deca5189e3..a3831c28a4 100644
>> --- a/arch/mips/lib/bootm.c
>> +++ b/arch/mips/lib/bootm.c
>> @@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
>> #define LINUX_MAX_ENVS 256
>> #define LINUX_MAX_ARGS 256
>>
>> +enum legacy_boot_type {
>> +LEGACY_BOOT_YAML,
>> +LEGACY_BOOT_VCORE,
>> +};
>> +
>> static int linux_argc;
>> static char **linux_argv;
>> static char *linux_argp;
>> @@ -44,22 +49,47 @@ void arch_lmb_reserve(struct lmb *lmb)
>> lmb_reserve(lmb, sp, gd->ram_top - sp);
>> }
>>
>> -static void linux_cmdline_init(void)
>> +static void linux_cmdline_init(enum legacy_boot_type boot_type)
>> {
>> +switch (boot_type) {
>> +/*
>> + * Vcore III linux kernels expect arguments in the cached
>> + * address space. They also expect the command line being a
>> + * single string in the first argument
>> + */
>> +case LEGACY_BOOT_VCORE:
>> +linux_argv = (char **)(gd->bd->bi_boot_params);
>> +linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> +linux_argv[1] = linux_argp;
>> +break;
>> +case LEGACY_BOOT_YAML:
>> +/* fall-through */
>> +default:
>> +linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> +linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> +}
>> linux_argc = 1;
>> -linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> linux_argv[0] = 0;
>> -linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> }
>>
>> -static void linux_cmdline_set(const char *value, size_t len)
>> +static void linux_cmdline_set(const char *value, size_t len,
>> + enum legacy_boot_type boot_type)
>> {
>> -linux_argv[linux_argc] = linux_argp;
>> memcpy(linux_argp, value, len);
>> -linux_argp[len] = 0;
>> -
>> +switch (boot_type) {
>> +case LEGACY_BOOT_VCORE:
>> +linux_argv[linux_argc] = linux_argp;
>> +linux_argp[len] = 0;
>> +linux_argc++;
>> +break;
>> +case LEGACY_BOOT_YAML:
>> +/* fall-through */
>> +default:
>> +linux_argp[len] = ' ';
>> +linux_argp[len + 1] = 0;
>> +linux_argc = 2;
>> +}
>> linux_argp += len + 1;
>> -linux_argc++;
>> }
>>
>> static void linux_cmdline_dump(void)
>> @@ -73,12 +103,11 @@ static void linux_cmdline_dump(void)
>> debug(" arg %03d: %s\n", i, linux_argv[i]);
>> }
>>
>> -static void linux_cmdline_legacy(bootm_headers_t *images)
>> +static void linux_cmdline_legacy(bootm_headers_t *images,
>> + enum legacy_boot_type boot_type)
>> {
>> const char *bootargs, *next, *quote;
>> -
>> -linux_cmdline_init();
>> -
>> +linux_cmdline_init(boot_type);
>> bootargs = env_get("bootargs");
>> if (!bootargs)
>> return;
>> @@ -104,7 +133,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
>> if (!next)
>> next = bootargs + strlen(bootargs);
>>
>> -linux_cmdline_set(bootargs, next - bootargs);
>> +linux_cmdline_set(bootargs, next - bootargs, boot_type);
>>
>> if (*next)
>> next++;
>> @@ -113,7 +142,8 @@ static void linux_cmdline_legacy(bootm_headers_t *
Re: [U-Boot] [PATCH v3 5/7] MSCC: add board support for the Ocelots based evaluation boards
Hi Daniel, On lun., déc. 10 2018, Daniel Schwierzeck wrote: >> +CONFIG_CMD_PING=y >> +CONFIG_CMD_MTDPARTS=y >> +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" >> +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)" > > you should recheck all MTD related options due to some recent changes in > mainline It's OK all the MTD related option of this file are aligned with the changes merged in mainline. Thanks, Gregory -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/7] MSCC: add support for Luton SoCs
Hi Daniel,
On lun., déc. 10 2018, Daniel Schwierzeck wrote:
>> +static inline int hal_vcoreiii_train_bytelane(u32 bytelane)
>> +{
>> +register int res;
>> +
>> +set_dly(bytelane, 0); // Start training at DQS=0
>
> no C++ style comments
>
OK
[...]
>> +for (i = 0; i < 8; i++) {
>> +DDR[i] = ~i;
>> +if (DDR[i] != ~i)
>
> __raw_readl(), __raw_writel() ?
OK
[...]
>> +++ b/arch/mips/mach-mscc/include/mach/luton/luton.h
>> @@ -0,0 +1,24 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>
> this line should begin with a //. Please fix all files in this patch.
As explained in the previous patch /* */ is the correct comment style for
SPDX in C header file
[...]
>> +/* Wait for lock */
>> +2: lw v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0
>> +andiv1, v0, MACRO_CTRL_PLL5G_STATUS_PLL5G_STATUS0_LOCK_STATUS
>> +# Keep looping if zero (no lock bit yet)
>
> should be a C style comment
OK
Thanks,
Gregory
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
___
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U-Boot@lists.denx.de
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Re: [U-Boot] [PATCH v3 3/7] MSCC: add support for Ocelot SoCs
> +#define MSCC_IO_ORIGIN1_OFFSET 0x7000
>> +#define MSCC_IO_ORIGIN1_SIZE 0x0020
>> +#define MSCC_IO_ORIGIN2_OFFSET 0x7100
>> +#define MSCC_IO_ORIGIN2_SIZE 0x0100
>> +#define BASE_CFG((void __iomem *)0x7000)
>> +#define BASE_DEVCPU_GCB ((void __iomem *)0x7107)
>
> Would it be possible on that SoC to define those register offsets as
> simple physical address and create the mapping when needed?
> For example:
>
> void foo()
> {
> void __iomem *base_cfg = ioremap(BASE_CFG, ...);
> writel(base_cfg + XXX, 0);
> }
Actually creating the mapping is just casting the physical address in an
(void __iomem *), see our plat_ioremap.
Calling ioremap in every function will just grow them with little
benefit.
If you really want it, what I could is sharing void __iomem *base_cfg
and void __iomem *base_devcpu_gcb at platform level, and initialize them
only once very early during the boot.
>> +LEAF(lowlevel_init)
>> +/*
>> + * As we have no stack yet, we can assume the restricted
>> + * luxury of the sX-registers without saving them
>> + */
>> +moves0,ra
>> +
>> +jal vcoreiii_tlb_init
>> +nop
>
> we use the same style as Linux MIPS where instructions in the delay slot
> should be indented by an extra space.
OK
Thanks,
Gregory
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
___
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Re: [U-Boot] [PATCH v2] gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi
Hi,
On mar., oct. 09 2018, Gregory CLEMENT wrote:
> The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
> flash directly in memory. However, for writing in the flash the
> communication has to be done by software.
>
> Each of the signal used for the SPI are exposed in a single register. In
> order to be able to use the soft-spi driver, the management of this pin
> is done through this simple gpio driver.
>
> Even if the main purpose of this driver is to be used by soft-spi, it can
> still be used as a normal gpio driver but with limitation: for example
> the first pin can't be used as output.
>
> Signed-off-by: Gregory CLEMENT
> ---
> Changelog:
> v1 -> v2:
> - use const and static when needed
> - fix style
> - use dev_remap_addr
I sent this version 2 months ago and addressed all the comments, how
could we going further ?
Thanks,
Gregory
>
> drivers/gpio/Kconfig | 7 ++
> drivers/gpio/Makefile| 1 +
> drivers/gpio/gpio-mscc-bitbang-spi.c | 122 +++
> 3 files changed, 130 insertions(+)
> create mode 100644 drivers/gpio/gpio-mscc-bitbang-spi.c
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 5cd8b34400..947a59cce3 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -99,6 +99,13 @@ config LPC32XX_GPIO
> help
> Support for the LPC32XX GPIO driver.
>
> +config MSCC_BITBANG_SPI_GPIO
> + bool "Microsemi bitbang spi GPIO driver"
> + depends on DM_GPIO && SOC_VCOREIII
> + help
> + Support controlling the GPIO used for SPI bitbang by software. Can
> + be used by the VCoreIII SoCs, but it was mainly useful for Luton.
> +
> config MSM_GPIO
> bool "Qualcomm GPIO driver"
> depends on DM_GPIO
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index f186120684..2085dd3cba 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -58,3 +58,4 @@ obj-$(CONFIG_MVEBU_GPIO)+= mvebu_gpio.o
> obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
> obj-$(CONFIG_$(SPL_)PCF8575_GPIO)+= pcf8575_gpio.o
> obj-$(CONFIG_PM8916_GPIO)+= pm8916_gpio.o
> +obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO) += gpio-mscc-bitbang-spi.o
> diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c
> b/drivers/gpio/gpio-mscc-bitbang-spi.c
> new file mode 100644
> index 00..b675f9052c
> --- /dev/null
> +++ b/drivers/gpio/gpio-mscc-bitbang-spi.c
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Microsemi SoCs pinctrl driver
> + *
> + * Author:
> + * License: Dual MIT/GPL
> + * Copyright (c) 2018 Microsemi Corporation
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +enum {
> + SDI,
> + CS0,
> + CS1,
> + CS2,
> + CS3,
> + SDO,
> + SCK
> +};
> +
> +static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
> +
> +#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
> +#define SW_SPI_CS0_OE BIT(1)
> +#define SW_SPI_SDO_OE BIT(9)
> +#define SW_SPI_SCK_OE BIT(11)
> +#define SW_PIN_CTRL_MODE BIT(13)
> +
> +struct mscc_bb_spi_gpio {
> + void __iomem *regs;
> + u32 cache_val;
> +};
> +
> +static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
> +{
> + struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
> +
> + if (val)
> + gpio->cache_val |= BIT(pinmap[oft]);
> + else
> + gpio->cache_val &= ~BIT(pinmap[oft]);
> +
> + writel(gpio->cache_val, gpio->regs);
> +
> + return 0;
> +}
> +
> +static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned
> oft,
> + int val)
> +{
> + if (oft == 0) {
> + pr_err("SW_SPI_DSI can't be used as output\n");
> + return -ENOTSUPP;
> + }
> +
> + mscc_bb_spi_gpio_set(dev, oft, val);
> +
> + return 0;
> +}
> +
> +static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned
> oft)
> +{
> + return 0;
> +}
> +
> +static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
> +{
> + struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
> + u32 val = readl(gpio->regs);
> +
> + return !!(val & BIT(pinmap[oft]));
> +}
> +
> +static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
> + .direction_output = mscc_bb_spi_gpio_direction_output,
> + .direction_input= mscc_bb_spi_gpio_direction_input,
> +
[U-Boot] [PATCH v3] pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.
The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).
For Ocelot and Luton the controller is the same, only the pins to program
differ.
Signed-off-by: Gregory CLEMENT
---
Hi,
I sent the second version _2_ months ago and did not get
anyfeedback. I hope this patch could be merge soon.
Thanks!
Changelog:
v2 -> v3:
- fix the return value of mscc_gpio_get_direction (reported by Lars
Povlsen)
v1 -> v2:
- use clrbits and setbits from MIPS
- use const and static when needed
- fix style
- use dev_remap_addr
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mscc/Kconfig | 22 +++
drivers/pinctrl/mscc/Makefile | 5 +
drivers/pinctrl/mscc/mscc-common.c| 236 ++
drivers/pinctrl/mscc/mscc-common.h| 51 ++
drivers/pinctrl/mscc/pinctrl-luton.c | 172 +++
drivers/pinctrl/mscc/pinctrl-ocelot.c | 188
8 files changed, 676 insertions(+)
create mode 100644 drivers/pinctrl/mscc/Kconfig
create mode 100644 drivers/pinctrl/mscc/Makefile
create mode 100644 drivers/pinctrl/mscc/mscc-common.c
create mode 100644 drivers/pinctrl/mscc/mscc-common.h
create mode 100644 drivers/pinctrl/mscc/pinctrl-luton.c
create mode 100644 drivers/pinctrl/mscc/pinctrl-ocelot.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ad0b8daba6..cc82f91579 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -305,6 +305,7 @@ source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
+source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/broadcom/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3a6c6d163..2461dba293 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_UNIPHIER)+= uniphier/
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-y += mscc/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
new file mode 100644
index 00..cfc6c06076
--- /dev/null
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config PINCTRL_MSCC
+ bool
+
+config PINCTRL_MSCC_OCELOT
+ depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi ocelot family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi ocelot SoCs.
+
+config PINCTRL_MSCC_LUTON
+ depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi luton family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi luton SoCs.
diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
new file mode 100644
index 00..941f418ff9
--- /dev/null
+++ b/drivers/pinctrl/mscc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_PINCTRL_MSCC) += mscc-common.o
+obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
+obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
diff --git a/drivers/pinctrl/mscc/mscc-common.c
b/drivers/pinctrl/mscc/mscc-common.c
new file mode 100644
index 00..d74b8a6649
--- /dev/null
+++ b/drivers/pinctrl/mscc/mscc-common.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author:
+ * Author:
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mscc-common.h"
+
+#define MSCC_GPIO_OUT_SET 0x0
+#define MSCC_GPIO_OUT_CLR 0x4
+#define MSCC_GPIO_OUT 0x8
+#define MSCC_GPIO_IN 0xc
+#define MSCC_GPIO_OE 0x10
+#define MSCC_GPIO_INTR 0x14
+#define MSCC_GPIO_INTR_ENA 0x18
+#define MSCC_GPIO_INTR_IDENT 0x1c
+#define MSCC_GPIO_ALT0 0x20
+#define MSCC_GPIO_ALT1 0x24
+
+static int mscc_get_functions_count(struct udevice *dev)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return i
[U-Boot] [PATCH v3 7/7] MIPS: bootm: Add support for Vcore III linux kernel
The kernels built for the Vcore III linux kernel have different
expectation in the way the data were passed.
Unlike with yamon, the command line is expected to be a single string
passed in argv[1]. An other expectation is that the arguments are located
in the cached address space.
However, like yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel, and besides that it
also wait for the root=/dev/ram0.
Signed-off-by: Gregory CLEMENT
---
arch/mips/lib/bootm.c | 78 ---
1 file changed, 58 insertions(+), 20 deletions(-)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index deca5189e3..a3831c28a4 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
#defineLINUX_MAX_ENVS 256
#defineLINUX_MAX_ARGS 256
+enum legacy_boot_type {
+ LEGACY_BOOT_YAML,
+ LEGACY_BOOT_VCORE,
+};
+
static int linux_argc;
static char **linux_argv;
static char *linux_argp;
@@ -44,22 +49,47 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, sp, gd->ram_top - sp);
}
-static void linux_cmdline_init(void)
+static void linux_cmdline_init(enum legacy_boot_type boot_type)
{
+ switch (boot_type) {
+ /*
+* Vcore III linux kernels expect arguments in the cached
+* address space. They also expect the command line being a
+* single string in the first argument
+*/
+ case LEGACY_BOOT_VCORE:
+ linux_argv = (char **)(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ linux_argv[1] = linux_argp;
+ break;
+ case LEGACY_BOOT_YAML:
+ /* fall-through */
+ default:
+ linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ }
linux_argc = 1;
- linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
linux_argv[0] = 0;
- linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
}
-static void linux_cmdline_set(const char *value, size_t len)
+static void linux_cmdline_set(const char *value, size_t len,
+ enum legacy_boot_type boot_type)
{
- linux_argv[linux_argc] = linux_argp;
memcpy(linux_argp, value, len);
- linux_argp[len] = 0;
-
+ switch (boot_type) {
+ case LEGACY_BOOT_VCORE:
+ linux_argv[linux_argc] = linux_argp;
+ linux_argp[len] = 0;
+ linux_argc++;
+ break;
+ case LEGACY_BOOT_YAML:
+ /* fall-through */
+ default:
+ linux_argp[len] = ' ';
+ linux_argp[len + 1] = 0;
+ linux_argc = 2;
+ }
linux_argp += len + 1;
- linux_argc++;
}
static void linux_cmdline_dump(void)
@@ -73,12 +103,11 @@ static void linux_cmdline_dump(void)
debug(" arg %03d: %s\n", i, linux_argv[i]);
}
-static void linux_cmdline_legacy(bootm_headers_t *images)
+static void linux_cmdline_legacy(bootm_headers_t *images,
+enum legacy_boot_type boot_type)
{
const char *bootargs, *next, *quote;
-
- linux_cmdline_init();
-
+ linux_cmdline_init(boot_type);
bootargs = env_get("bootargs");
if (!bootargs)
return;
@@ -104,7 +133,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
if (!next)
next = bootargs + strlen(bootargs);
- linux_cmdline_set(bootargs, next - bootargs);
+ linux_cmdline_set(bootargs, next - bootargs, boot_type);
if (*next)
next++;
@@ -113,7 +142,8 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
}
}
-static void linux_cmdline_append(bootm_headers_t *images)
+static void linux_cmdline_append(bootm_headers_t *images,
+enum legacy_boot_type boot_type)
{
char buf[24];
ulong mem, rd_start, rd_size;
@@ -121,7 +151,7 @@ static void linux_cmdline_append(bootm_headers_t *images)
/* append mem */
mem = gd->ram_size >> 20;
sprintf(buf, "mem=%luM", mem);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), boot_type);
/* append rd_start and rd_size */
rd_start = images->initrd_start;
@@ -129,9 +159,13 @@ static void linux_cmdline_append(bootm_headers_t *images)
if (rd_size) {
sprintf(buf, "rd_start=0x%08lX", rd_start);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), boot_type);
sprintf(buf, &qu
[U-Boot] [PATCH v3 6/7] MSCC: add board support for the Luton based evaluation board
Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS| 1 +
arch/mips/dts/luton_pcb091.dts | 35 ++
arch/mips/dts/mscc,luton.dtsi | 87 ++
arch/mips/mach-mscc/Kconfig| 2 +
board/mscc/luton/Kconfig | 14 ++
board/mscc/luton/Makefile | 3 ++
board/mscc/luton/luton.c | 28 +++
configs/mscc_luton_defconfig | 66 ++
8 files changed, 236 insertions(+)
create mode 100644 arch/mips/dts/luton_pcb091.dts
create mode 100644 arch/mips/dts/mscc,luton.dtsi
create mode 100644 board/mscc/luton/Kconfig
create mode 100644 board/mscc/luton/Makefile
create mode 100644 board/mscc/luton/luton.c
create mode 100644 configs/mscc_luton_defconfig
diff --git a/MAINTAINERS b/MAINTAINERS
index c906ca006b..4ce19aef11 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -490,6 +490,7 @@ M: Lars Povlsen
M: Horatiu Vultur
S: Maintained
F: arch/mips/mach-mscc/
+F: arch/mips/dts/luton*
F: arch/mips/dts/mscc*
F: arch/mips/dts/ocelot*
F: board/mscc/
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
new file mode 100644
index 00..3a2bc42294
--- /dev/null
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+ model = "Luton10 PCB091 Reference Board";
+ compatible = "mscc,luton-pcb091", "mscc,luton";
+
+ aliases {
+ serial0 =
+ spi0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+ spi-max-frequency = <1800>; /* input clock */
+ reg = <0>; /* CS0 */
+ };
+};
+
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
new file mode 100644
index 00..6a4ad2a5be
--- /dev/null
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,luton";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 =
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20833>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x1020>;
+
+ uart0: serial@1010 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ compatible = "ns16550a";
+ reg = <0x1010 0x20>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@70068 {
+ compatible = "mscc,luton-pinctrl";
+ reg = <0x70068 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 32>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_30", "GPIO_31";
+ function = "uart";
+ };
+
+ };
+
+ gpio_spi_bitbang: gpio@1064 {
+ compatible = "mscc,spi-bitbang-gpio";
+ reg = <0x1064 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ };
+
+ spi0: spi-bitbang {
+ compatible = "spi-gpio";
+ status = "okay";
+ gpio-sck = <_spi_bitbang 6 0>;
+ gpio-miso = <_spi_bitbang 0 0
[U-Boot] [PATCH v3 5/7] MSCC: add board support for the Ocelots based evaluation boards
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT
---
MAINTAINERS | 5 +
arch/mips/dts/mscc,ocelot.dtsi | 152 +++
arch/mips/dts/mscc,ocelot_pcb.dtsi | 42
arch/mips/dts/ocelot_pcb120.dts | 12 +++
arch/mips/dts/ocelot_pcb123.dts | 12 +++
arch/mips/mach-mscc/Kconfig | 2 +
board/mscc/ocelot/Kconfig| 14 +++
board/mscc/ocelot/Makefile | 4 +
board/mscc/ocelot/ocelot.c | 58 ++
configs/mscc_ocelot_defconfig| 73 +
configs/mscc_ocelot_pcb120_defconfig | 66
include/configs/vcoreiii.h | 82 +++
12 files changed, 522 insertions(+)
create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
create mode 100644 arch/mips/dts/ocelot_pcb120.dts
create mode 100644 arch/mips/dts/ocelot_pcb123.dts
create mode 100644 board/mscc/ocelot/Kconfig
create mode 100644 board/mscc/ocelot/Makefile
create mode 100644 board/mscc/ocelot/ocelot.c
create mode 100644 configs/mscc_ocelot_defconfig
create mode 100644 configs/mscc_ocelot_pcb120_defconfig
create mode 100644 include/configs/vcoreiii.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 53a3c5bec6..c906ca006b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -490,6 +490,11 @@ M: Lars Povlsen
M: Horatiu Vultur
S: Maintained
F: arch/mips/mach-mscc/
+F: arch/mips/dts/mscc*
+F: arch/mips/dts/ocelot*
+F: board/mscc/
+F: configs/mscc*
+F: include/configs/vcoreiii.h
MMC
M: Jaehoon Chung
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
new file mode 100644
index 00..87b4736285
--- /dev/null
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -0,0 +1,152 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,ocelot";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 =
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x7000 0x200>;
+
+ interrupt-parent = <>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@10 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x10 0x20>;
+ interrupts = <6>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <
[U-Boot] [PATCH v3 3/7] MSCC: add support for Ocelot SoCs
This family of SoCs are found in the Microsemi Switches solution and have already a support in the linux kernel. Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 7 + arch/mips/Kconfig | 6 + arch/mips/Makefile| 1 + arch/mips/mach-mscc/Kconfig | 69 ++ arch/mips/mach-mscc/Makefile | 5 + arch/mips/mach-mscc/cpu.c | 90 +++ arch/mips/mach-mscc/dram.c| 71 ++ arch/mips/mach-mscc/include/ioremap.h | 51 ++ arch/mips/mach-mscc/include/mach/common.h | 24 + arch/mips/mach-mscc/include/mach/ddr.h| 692 ++ .../mach-mscc/include/mach/ocelot/ocelot.h| 24 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 + .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 +++ arch/mips/mach-mscc/include/mach/tlb.h| 55 ++ arch/mips/mach-mscc/lowlevel_init.S | 23 + arch/mips/mach-mscc/reset.c | 36 + 16 files changed, 1449 insertions(+) create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/reset.c diff --git a/MAINTAINERS b/MAINTAINERS index abdb6dcdb5..53a3c5bec6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -484,6 +484,13 @@ S: Maintained T: git git://git.denx.de/u-boot-mips.git F: arch/mips/ +MIPS MSCC +M: Gregory CLEMENT +M: Lars Povlsen +M: Horatiu Vultur +S: Maintained +F: arch/mips/mach-mscc/ + MMC M: Jaehoon Chung S: Maintained diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6d646ef999..bfe9c11069 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -59,6 +59,11 @@ config ARCH_ATH79 select OF_CONTROL imply CMD_DM +config ARCH_MSCC + bool "Support MSCC VCore-III" + select OF_CONTROL + select DM + config ARCH_BMIPS bool "Support BMIPS SoCs" select CLK @@ -135,6 +140,7 @@ source "board/imgtec/xilfpga/Kconfig" source "board/micronas/vct/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-mscc/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mt7620/Kconfig" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 802244a06e..124e93fa26 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,6 +15,7 @@ machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 machine-$(CONFIG_ARCH_MT7620) += mt7620 +machine-$(CONFIG_ARCH_MSCC) += mscc machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig new file mode 100644 index 00..7f1b270207 --- /dev/null +++ b/arch/mips/mach-mscc/Kconfig @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +menu "MSCC VCore-III platforms" + depends on ARCH_MSCC + +config SOC_VCOREIII + select MIPS_TUNE_24KC + select ROM_EXCEPTION_VECTORS + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + bool + +config SYS_SOC + default "mscc" + +config SOC_OCELOT + bool + select SOC_VCOREIII + help + This supports MSCC Ocelot family of SOCs. + +config SYS_CONFIG_NAME + default "vcoreiii" + +choice + prompt "Board select" + +config TARGET_OCELOT_PCB120 + bool "MSCC PCB120 Reference Board (aka VSC5635EV)" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb120 + +config TARGET_OCELOT_PCB123 + bool "MSCC PCB123 Reference Board (aka VSC7514EV))" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb123 + +endchoice + +choice + prompt "DDR type" + +config DDRTYPE_H5TQ4G63MFR + bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)" + +co
[U-Boot] [PATCH v3 4/7] MSCC: add support for Luton SoCs
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT
---
arch/mips/mach-mscc/Kconfig | 13 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 14 +-
arch/mips/mach-mscc/dram.c| 2 +
arch/mips/mach-mscc/include/mach/common.h | 4 +
arch/mips/mach-mscc/include/mach/ddr.h| 112 +++-
.../mips/mach-mscc/include/mach/luton/luton.h | 24 ++
.../include/mach/luton/luton_devcpu_gcb.h | 14 +
.../include/mach/luton/luton_icpu_cfg.h | 245 ++
arch/mips/mach-mscc/lowlevel_init.S | 7 +
arch/mips/mach-mscc/lowlevel_init_luton.S | 62 +
11 files changed, 494 insertions(+), 4 deletions(-)
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 7f1b270207..a8cace0e79 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -21,6 +21,12 @@ config SOC_OCELOT
help
This supports MSCC Ocelot family of SOCs.
+config SOC_LUTON
+ bool
+ select SOC_VCOREIII
+ help
+ This supports MSCC Luton family of SOCs.
+
config SYS_CONFIG_NAME
default "vcoreiii"
@@ -41,6 +47,13 @@ config TARGET_OCELOT_PCB123
When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
ocelot_pcb123
+config TARGET_LUTON_PCB091
+ bool "MSCC PCB091 Reference Board"
+ select SOC_LUTON
+ select MSCC_BITBANG_SPI_GPIO
+ help
+ When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
+ luton_pcb091
endchoice
choice
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index d14ec33838..6c60f26ca4 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -3,3 +3,4 @@
CFLAGS_cpu.o += -finline-limit=64000
obj-y += cpu.o dram.o reset.o lowlevel_init.o
+obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index b503e1407b..5be8ff69d5 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -48,6 +48,10 @@ void vcoreiii_tlb_init(void)
*/
create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
MMU_REGIO_RW);
+#ifdef CONFIG_SOC_LUTON
+ create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
+ MMU_REGIO_RW);
+#endif
#if CONFIG_SYS_TEXT_BASE == MSCC_FLASH_TO
/*
@@ -75,6 +79,14 @@ void vcoreiii_tlb_init(void)
int mach_cpu_init(void)
{
/* Speed up NOR flash access */
+#ifdef CONFIG_SOC_LUTON
+ writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
+ ICPU_PI_MST_CFG_CLK_DIV(4), BASE_CFG + ICPU_PI_MST_CFG);
+
+ writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
+ ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
+ ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
+#else
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), BASE_CFG + ICPU_SPI_MST_CFG);
/*
@@ -85,6 +97,6 @@ int mach_cpu_init(void)
writel(0, BASE_CFG + ICPU_DST_INTR_MAP(1));
writel(0, BASE_CFG + ICPU_DST_INTR_MAP(2));
writel(0, BASE_CFG + ICPU_DST_INTR_MAP(3));
-
+#endif
return 0;
}
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index 5acee6f918..309007c14e 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -19,9 +19,11 @@ static inline int vcoreiii_train_bytelane(void)
ret = hal_vcoreiii_train_bytelane(0);
+#ifdef CONFIG_SOC_OCELOT
if (ret)
return ret;
ret = hal_vcoreiii_train_bytelane(1);
+#endif
return ret;
}
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index 842462aeed..931ecd7985 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -10,6 +10,10 @@
#include
#include
#include
+#elif defined(CONFIG_SOC_LUTON)
+#include
+#include
+#include
#else
#error Unsupported platform
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h
b/arch/mips/mach-mscc/include/mach/ddr.h
index 4bdea90506..97eff2a196 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -598,6 +598,98 @@ static inline int dram_check(void)
}
return 0;
}
+#else /* Luton */
+
+static inline void sleep_100ns(u32 val)
+{
+}
+
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+ setbits_le32(BASE_C
[U-Boot] [PATCH v3 0/7] ] Add support for the SoCs found in Microsemi switches
Hello, For the record this the third version of the series adding the support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them belongs to the same family Vcore III. We found them on various advanced switches product. The support for Ocelot already have been submit to Linux, but not yet the Luton support. Since the v2, U-boot was continued to be tested internally and besides the changes asked by Daniel, we also made several fixes and improvements. Most of them come from Lars Povlsen and Horatiu Vultur. I tried to address all the comment from Daniel and for the part I kept more or less as is, I added comment explaining the rational for this choice inside the code itself. Gregory Changelog: v2 -> v3: - Added n entry in the MAINTAINER file for the SoCs - Fixup the last errors from checkpatch, the remaining ones are only about volatile, long line and Kconfig, but each ones have good reason to be here. - Add SPI NAND flash support in device tree and configuration files, the driver are already be merged in U-Boot. - In order to improve boot time, setup the TLB to allow using cache in the memory mapped to the SPI NOR. - Removed all the macro REG_CFG to only keep direct access to memory. - Put back the setting of the interrupt map as it is needed by mainline kernel (without it the kernel doesn't finish to boot) - During DDR training, prevent the compiler reordering the instruction. - Add early debug support to Ocelot (it was already done for Luton) v1 -> v2: - a big clean-up for indentation and some style issue - usage of the clrsetbits family functions where it was possible - split the patches for Ocelot and Luton - add a new patch to introduce the icache_lock function which was in the mscc directory in the first version - remove more unused define in the platform header files - use the automatic cache size detection instead of hard coding it - reduce the tlb init to only two entries for the IO as needed by the kernel - remove the interrupt disabling - fix the ddr init for luton Gregory CLEMENT (7): MIPS: move create_tlb() in an proper header: mipsregs.h MIPS: Allow to prefetch and lock instructions into cache MSCC: add support for Ocelot SoCs MSCC: add support for Luton SoCs MSCC: add board support for the Ocelots based evaluation boards MSCC: add board support for the Luton based evaluation board MIPS: bootm: Add support for Vcore III linux kernel MAINTAINERS | 13 + arch/mips/Kconfig | 6 + arch/mips/Makefile| 1 + arch/mips/cpu/cpu.c | 10 - arch/mips/dts/luton_pcb091.dts| 35 + arch/mips/dts/mscc,luton.dtsi | 87 ++ arch/mips/dts/mscc,ocelot.dtsi| 152 arch/mips/dts/mscc,ocelot_pcb.dtsi| 42 + arch/mips/dts/ocelot_pcb120.dts | 12 + arch/mips/dts/ocelot_pcb123.dts | 12 + arch/mips/include/asm/cacheops.h | 19 + arch/mips/include/asm/mipsregs.h | 11 + arch/mips/lib/bootm.c | 78 +- arch/mips/mach-mscc/Kconfig | 86 ++ arch/mips/mach-mscc/Makefile | 6 + arch/mips/mach-mscc/cpu.c | 102 +++ arch/mips/mach-mscc/dram.c| 73 ++ arch/mips/mach-mscc/include/ioremap.h | 51 ++ arch/mips/mach-mscc/include/mach/common.h | 28 + arch/mips/mach-mscc/include/mach/ddr.h| 798 ++ .../mips/mach-mscc/include/mach/luton/luton.h | 24 + .../include/mach/luton/luton_devcpu_gcb.h | 14 + .../include/mach/luton/luton_icpu_cfg.h | 245 ++ .../mach-mscc/include/mach/ocelot/ocelot.h| 24 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 + .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 ++ arch/mips/mach-mscc/include/mach/tlb.h| 55 ++ arch/mips/mach-mscc/lowlevel_init.S | 30 + arch/mips/mach-mscc/lowlevel_init_luton.S | 62 ++ arch/mips/mach-mscc/reset.c | 36 + board/mscc/luton/Kconfig | 14 + board/mscc/luton/Makefile | 3 + board/mscc/luton/luton.c | 28 + board/mscc/ocelot/Kconfig | 14 + board/mscc/ocelot/Makefile| 4 + board/mscc/ocelot/ocelot.c| 58 ++ configs/mscc_luton_defconfig | 66 ++ configs/mscc_ocelot_defconfig | 73 ++ configs/mscc_ocelot_pcb120_defconfig | 66 ++ include/configs/vcoreiii.h| 82 ++ 40 files changed, 2785 insertions(+), 30 deletions(-) create mode 100644 arch/mips/dts/luton_pcb091.dts create mode 100644 arch/mips/dts/mscc,luton.dtsi create mode 100644 arch/mips/dts/mscc,ocelot.dtsi create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi create mode 100644 arch/mi
[U-Boot] [PATCH v3 2/7] MIPS: Allow to prefetch and lock instructions into cache
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT
---
arch/mips/include/asm/cacheops.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 3161875441..98b67ccc8e 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void
*addr)
#endif
}
+#define MIPS32_WHICH_ICACHE0x0
+#define MIPS32_FETCH_AND_LOCK 0x7
+
+#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
+
+/* Prefetch and lock instructions into cache */
+static inline void icache_lock(void *func, size_t len)
+{
+ int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
+
+ for (i = 0; i < lines; i++) {
+ asm volatile (" cache %0, %1(%2)"
+ : /* No Output */
+ : "I" ICACHE_LOAD_LOCK,
+ "n" (i * ARCH_DMA_MINALIGN),
+ "r" (func)
+ : /* No Clobbers */);
+ }
+}
#endif /* !__ASSEMBLY__ */
/*
--
2.19.2
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[U-Boot] [PATCH v3 1/7] MIPS: move create_tlb() in an proper header: mipsregs.h
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c | 10 --
arch/mips/include/asm/mipsregs.h | 11 +++
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 5c56ab0289..a403ff729b 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
}
#endif
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
- write_c0_entrylo0(low0);
- write_c0_pagemask(pagemask);
- write_c0_entrylo1(low1);
- write_c0_entryhi(hi);
- write_c0_index(index);
- tlb_write_indexed();
-}
-
int arch_cpu_init(void)
{
mips_cache_probe();
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 48fa1f1f7f..930562ebb2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2005,6 +2005,17 @@ static inline unsigned int get_ebase_cpunum(void)
return read_c0_ebase() & 0x3ff;
}
+static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
+u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
--
2.19.2
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Re: [U-Boot] [PATCH v2 3/7] MSCC: add support for Ocelot SoCs
Hi Daniel,
On dim., oct. 28 2018, Daniel Schwierzeck wrote:
> Am 09.10.18 um 13:58 schrieb Gregory CLEMENT:
>> This family of SoCs are found in the Microsemi Switches solution and have
>> already a support in the linux kernel.
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> arch/mips/Kconfig | 6 +
>> arch/mips/Makefile| 1 +
>> arch/mips/mach-mscc/Kconfig | 69 ++
>> arch/mips/mach-mscc/Makefile | 5 +
>> arch/mips/mach-mscc/cpu.c | 42 ++
>> arch/mips/mach-mscc/dram.c| 61 ++
>> arch/mips/mach-mscc/include/ioremap.h | 51 ++
>> arch/mips/mach-mscc/include/mach/common.h | 27 +
>> arch/mips/mach-mscc/include/mach/ddr.h| 680 ++
>> .../mach-mscc/include/mach/ocelot/ocelot.h| 35 +
>> .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 +
>> .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 +++
>> arch/mips/mach-mscc/include/mach/tlb.h| 55 ++
>> arch/mips/mach-mscc/lowlevel_init.S | 23 +
>> arch/mips/mach-mscc/reset.c | 36 +
>> 15 files changed, 1386 insertions(+)
>> create mode 100644 arch/mips/mach-mscc/Kconfig
>> create mode 100644 arch/mips/mach-mscc/Makefile
>> create mode 100644 arch/mips/mach-mscc/cpu.c
>> create mode 100644 arch/mips/mach-mscc/dram.c
>> create mode 100644 arch/mips/mach-mscc/include/ioremap.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/common.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h
>> create mode 100644
>> arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h
>> create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h
>> create mode 100644 arch/mips/mach-mscc/lowlevel_init.S
>> create mode 100644 arch/mips/mach-mscc/reset.c
>
> there are still some style issues and checkpatch.pl warnings in all
> patches. Please fix.
Actually there was a lot of warning no relevant such as:
- the ones about the "line over 80 character" in the headers, but
splitting the register definition in multiple line woul just make the
file less readbale
- the ones about "please write a paragraph that describes the config
symbol fully" fro the RAM choice, but the title give engough
information.
- the ones about "Use of volatile is usually wrong", but here we really
want to be sure that value will be really read from the memory that
we are testing.
- the one about "Avoid CamelCase", here the rational is to use a small
"t" in the naem of a register, as it make prefectly sens to use it to
indicate time: VC3_MPAR_tXSRD
And in the middle of them there were a few real issues that I indeed
missed and that I fixed now.
>
>> +/*
>> + * DDR memory sanity checking failed, tally and do hard reset
>> + *
>> + * NB: Assumes inlining as no stack is available!
>> + */
>> +static inline void hal_vcoreiii_ddr_failed(void)
>> +{
>> +register u32 reset;
>> +
>> +writel(readl(REG_CFG(ICPU_GPR(6))) + 1, REG_CFG(ICPU_GPR(6)));
>> +
>> +clrbits_le32(REG_GCB(PERF_GPIO_OE), BIT(19));
>> +
>> +/* Jump to reset - does not return */
>> +reset = KSEG0ADDR(_machine_restart);
>> +/* Reset while running from cache */
>> +icache_lock((void *)reset, 128);
>> +asm volatile ("jr %0"::"r" (reset));
>
> why do you need to move to KSEG0 and to lock the cache line? Do you run
> the whole lowlevel code in KSEG1 space?
Yes the vector code of this platform is not located in KSEG0 actually it
started at address 0x4000 so in KUSEG.
Gregory
>
> I guess the SoC maps the SPI flash to some executable buffer from where
> U-Boot is started. If the I-Cache works on this buffer, you could move
> your text base to KSEG0 space and run fully cached after I-Caches have
> been initialised.
--
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Re: [U-Boot] [PATCH v2 7/7] MIPS: bootm: Add support for Vcore III linux kernel
Hi Daniel,
On dim., oct. 28 2018, Daniel Schwierzeck wrote:
> Hi Gregory,
>
> sorry for the late response.
>
> Am 09.10.18 um 13:58 schrieb Gregory CLEMENT:
>> The kernels built for the Vcore III linux kernel have different
>> expectation in the way the data were passed.
>>
>> Unlike with yamon, the command line is expected to be a single string
>> passed in argv[1]. An other expectation is that the arguments are located
>> in the cached address space.
>
> I'm still not convinced whether this patch is necessary. As far as I
> understand, you can boot a mainline kernel with the device-tree blob way
> or with the legacy way. The latter makes sense when booting a mainline
> kernel with Redboot. But what's the use case for booting a mainline
> kernel in mainline U-Boot in the legacy way? Do you still want to boot
> out-of-tree legacy kernels with mainline U-Boot?
Currently there is only redboot which is used , but there is already
mainline kernel in legacy format. The purpose of it, is to be able to
switch from reboot to u-Boot but still being able to boot the mainline
kernel currently used.
As a bonus it could also allow to boot old out of tree kernel, but I
don't think it is something planed.
>
> Apart from this is this single cmdline string specific to Redboot or
> only to Microsemi? The former would be acceptable for a generic patch to
Actually I don't know.
> emulate a Redboot interface (similar to the YAMON one). But this should
> be configurable for the user via Kconfig. You could enable this by
> default with an "imply MIPS_BOOT_CMDLINE_REDBOOT" in your SoC/board
> specific Kconfig part.
>
>>
>> However, like yamon, they expect that rd_start and rd_size was passed by
>> the bootloader in the command line of the kernel, and besides that it
>> also wait for the root=/dev/ram0.
>
> Who exactly needs "root=/dev/ram0"? Normally the generic MIPS setup code
> only needs "rd_start" and "rd_size" from cmdline respectively
> "linux,initrd-start" and "linux,initrd-end" from the device-tree blob.
If it is a problem I think that we can use a U-boot script to take care
of this value.
Gregory
>
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> arch/mips/lib/bootm.c | 77 ---
>> 1 file changed, 57 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
>> index deca5189e3..803d5e1de3 100644
>> --- a/arch/mips/lib/bootm.c
>> +++ b/arch/mips/lib/bootm.c
>> @@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
>> #define LINUX_MAX_ENVS 256
>> #define LINUX_MAX_ARGS 256
>>
>> +enum legacy_boot_type {
>> +LEGACY_BOOT_YAML,
>> +LEGACY_BOOT_VCORE,
>> +};
>> +
>> static int linux_argc;
>> static char **linux_argv;
>> static char *linux_argp;
>> @@ -44,22 +49,46 @@ void arch_lmb_reserve(struct lmb *lmb)
>> lmb_reserve(lmb, sp, gd->ram_top - sp);
>> }
>>
>> -static void linux_cmdline_init(void)
>> +static void linux_cmdline_init(enum legacy_boot_type boot_type)
>> {
>> +switch (boot_type) {
>> +/*
>> + * Vcore III linux kernels expect arguments in the cached
>> + * address space. They also expect the command line being a
>> + * single string in the first argument
>> + */
>> +case LEGACY_BOOT_VCORE:
>> +linux_argv = (char **)(gd->bd->bi_boot_params);
>> +linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> +linux_argv[1] = linux_argp;
>> +break;
>> +case LEGACY_BOOT_YAML:
>> +/* fallthrough */
>> +default:
>> +linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> +linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> +}
>> linux_argc = 1;
>> -linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> linux_argv[0] = 0;
>> -linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> }
>>
>> -static void linux_cmdline_set(const char *value, size_t len)
>> +static void linux_cmdline_set(const char *value, size_t len,
>> + enum legacy_boot_type boot_type)
>> {
>> -linux_argv[linux_argc] = linux_argp;
>> memcpy(linux_argp, value, len);
>> -linux_argp[len] = 0;
>> -
>> +switch (boot_type) {
>> +case LEGACY_BOOT_VCORE:
>> +linux_argv[linux_argc] = linux
Re: [U-Boot] [PATCH v2] DW SPI: Allow to overload the management of the external CS
Hi Jagan,
On mar., oct. 09 2018, Gregory CLEMENT wrote:
> On some platforms, as the Ocelot ones, when wanting to control the CS
> through software, it is not possible to do it through the GPIO
> controller. Indeed, this signal is managed through a dedicated range of
> registers inside the SoC..
>
> By declaring the external_cs_manage function as weak, it is possible to
> manage the CS at platform level and then using the appropriate registers.
>
I sent this v2 nearly 2 months ago and didn't have any objection about
it. So, Could you merge this patch please?
Thanks!
> Signed-off-by: Gregory CLEMENT
> ---
> Changelog:
> v1 -> v2
> - Fix ocelot name
>
> drivers/spi/designware_spi.c | 8 +++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
> index d8b73ea326..1f47ea24c8 100644
> --- a/drivers/spi/designware_spi.c
> +++ b/drivers/spi/designware_spi.c
> @@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
> return 0;
> }
>
> -static void external_cs_manage(struct udevice *dev, bool on)
> +/*
> + * We define external_cs_manage function as 'weak' as some targets
> + * (like MSCC Ocelot) don't control the external CS pin using a GPIO
> + * controller. These SoCs use specific registers to control by
> + * software the SPI pins (and especially the CS).
> + */
> +__weak void external_cs_manage(struct udevice *dev, bool on)
> {
> #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
> struct dw_spi_priv *priv = dev_get_priv(dev->parent);
> --
> 2.19.1
>
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[U-Boot] [PATCH v2] DW SPI: Allow to overload the management of the external CS
On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..
By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2
- Fix ocelot name
drivers/spi/designware_spi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index d8b73ea326..1f47ea24c8 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
return 0;
}
-static void external_cs_manage(struct udevice *dev, bool on)
+/*
+ * We define external_cs_manage function as 'weak' as some targets
+ * (like MSCC Ocelot) don't control the external CS pin using a GPIO
+ * controller. These SoCs use specific registers to control by
+ * software the SPI pins (and especially the CS).
+ */
+__weak void external_cs_manage(struct udevice *dev, bool on)
{
#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
struct dw_spi_priv *priv = dev_get_priv(dev->parent);
--
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Re: [U-Boot] [PATCH] DW SPI: Allow to overload the management of the external CS
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:17, Gregory CLEMENT wrote:
>> On some platforms, as the Ocelot ones, when wanting to control the CS
>> through software, it is not possible to do it through the GPIO
>> controller. Indeed, this signal is managed through a dedicated range of
>> registers inside the SoC..
>
> and why did you add a spi-bitbang-gpio driver?
Because the DW SPI is not available on Luton, so for Luton we can only
use a spi-bitbang-gpio driver which is very slow.
Gregory
>
>>
>> By declaring the external_cs_manage function as weak, it is possible to
>> manage the CS at platform level and then using the appropriate registers.
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> drivers/spi/designware_spi.c | 8 +++-
>> 1 file changed, 7 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
>> index d8b73ea326..fe6e753bff 100644
>> --- a/drivers/spi/designware_spi.c
>> +++ b/drivers/spi/designware_spi.c
>> @@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
>> return 0;
>> }
>>
>> -static void external_cs_manage(struct udevice *dev, bool on)
>> +/*
>> + * We define external_cs_manage function as 'weak' as some targets
>> + * (like OCELOT) don't control the external CS pin using a GPIO
>> + * controller. These SoCs use specific registers to controll by
>> + * software the SPI pins (and especially the CS).
>> + */
>> +__weak void external_cs_manage(struct udevice *dev, bool on)
>> {
>> #if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
>> struct dw_spi_priv *priv = dev_get_priv(dev->parent);
>>
>
> --
> - Daniel
>
--
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[U-Boot] [PATCH v2] gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.
Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.
Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2:
- use const and static when needed
- fix style
- use dev_remap_addr
drivers/gpio/Kconfig | 7 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/gpio-mscc-bitbang-spi.c | 122 +++
3 files changed, 130 insertions(+)
create mode 100644 drivers/gpio/gpio-mscc-bitbang-spi.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 5cd8b34400..947a59cce3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -99,6 +99,13 @@ config LPC32XX_GPIO
help
Support for the LPC32XX GPIO driver.
+config MSCC_BITBANG_SPI_GPIO
+ bool "Microsemi bitbang spi GPIO driver"
+ depends on DM_GPIO && SOC_VCOREIII
+ help
+ Support controlling the GPIO used for SPI bitbang by software. Can
+ be used by the VCoreIII SoCs, but it was mainly useful for Luton.
+
config MSM_GPIO
bool "Qualcomm GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index f186120684..2085dd3cba 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -58,3 +58,4 @@ obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
+obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)+= gpio-mscc-bitbang-spi.o
diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c
b/drivers/gpio/gpio-mscc-bitbang-spi.c
new file mode 100644
index 00..b675f9052c
--- /dev/null
+++ b/drivers/gpio/gpio-mscc-bitbang-spi.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author:
+ * License: Dual MIT/GPL
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+enum {
+ SDI,
+ CS0,
+ CS1,
+ CS2,
+ CS3,
+ SDO,
+ SCK
+};
+
+static const int pinmap[] = { 0, 5, 6, 7, 8, 10, 12 };
+
+#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
+#define SW_SPI_CS0_OE BIT(1)
+#define SW_SPI_SDO_OE BIT(9)
+#define SW_SPI_SCK_OE BIT(11)
+#define SW_PIN_CTRL_MODE BIT(13)
+
+struct mscc_bb_spi_gpio {
+ void __iomem *regs;
+ u32 cache_val;
+};
+
+static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
+{
+ struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
+
+ if (val)
+ gpio->cache_val |= BIT(pinmap[oft]);
+ else
+ gpio->cache_val &= ~BIT(pinmap[oft]);
+
+ writel(gpio->cache_val, gpio->regs);
+
+ return 0;
+}
+
+static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
+int val)
+{
+ if (oft == 0) {
+ pr_err("SW_SPI_DSI can't be used as output\n");
+ return -ENOTSUPP;
+ }
+
+ mscc_bb_spi_gpio_set(dev, oft, val);
+
+ return 0;
+}
+
+static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
+{
+ return 0;
+}
+
+static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
+{
+ struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
+ u32 val = readl(gpio->regs);
+
+ return !!(val & BIT(pinmap[oft]));
+}
+
+static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
+ .direction_output = mscc_bb_spi_gpio_direction_output,
+ .direction_input= mscc_bb_spi_gpio_direction_input,
+ .set_value = mscc_bb_spi_gpio_set,
+ .get_value = mscc_bb_spi_gpio_get,
+};
+
+static int mscc_bb_spi_gpio_probe(struct udevice *dev)
+{
+ struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+
+ gpio->regs = dev_remap_addr(dev);
+ if (!gpio->regs)
+ return -EINVAL;
+
+ uc_priv->bank_name = dev->name;
+ uc_priv->gpio_count = ARRAY_SIZE(pinmap);
+ /*
+* Enable software mode to control the SPI pin, enables the
+* output mode for most of the pin and initialize the cache
+* value in the same time
+*/
+
+ gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
+ SW_SPI_CS0_OE;
+ writel(gpio
[U-Boot] [PATCH v2] pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.
The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).
For Ocelot and Luton the controller is the same, only the pins to program
differ.
Signed-off-by: Gregory CLEMENT
---
Changelog:
v1 -> v2:
- use clrbits and setbits from MIPS
- use const and static when needed
- fix style
- use dev_remap_addr
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mscc/Kconfig | 22 +++
drivers/pinctrl/mscc/Makefile | 5 +
drivers/pinctrl/mscc/mscc-common.c| 236 ++
drivers/pinctrl/mscc/mscc-common.h| 51 ++
drivers/pinctrl/mscc/pinctrl-luton.c | 172 +++
drivers/pinctrl/mscc/pinctrl-ocelot.c | 188
8 files changed, 676 insertions(+)
create mode 100644 drivers/pinctrl/mscc/Kconfig
create mode 100644 drivers/pinctrl/mscc/Makefile
create mode 100644 drivers/pinctrl/mscc/mscc-common.c
create mode 100644 drivers/pinctrl/mscc/mscc-common.h
create mode 100644 drivers/pinctrl/mscc/pinctrl-luton.c
create mode 100644 drivers/pinctrl/mscc/pinctrl-ocelot.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ad0b8daba6..cc82f91579 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -305,6 +305,7 @@ source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
+source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/broadcom/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3a6c6d163..2461dba293 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_UNIPHIER)+= uniphier/
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-y += mscc/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
new file mode 100644
index 00..cfc6c06076
--- /dev/null
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config PINCTRL_MSCC
+ bool
+
+config PINCTRL_MSCC_OCELOT
+ depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi ocelot family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi ocelot SoCs.
+
+config PINCTRL_MSCC_LUTON
+ depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi luton family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi luton SoCs.
diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
new file mode 100644
index 00..941f418ff9
--- /dev/null
+++ b/drivers/pinctrl/mscc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_PINCTRL_MSCC) += mscc-common.o
+obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
+obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
diff --git a/drivers/pinctrl/mscc/mscc-common.c
b/drivers/pinctrl/mscc/mscc-common.c
new file mode 100644
index 00..db98fc30f3
--- /dev/null
+++ b/drivers/pinctrl/mscc/mscc-common.c
@@ -0,0 +1,236 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author:
+ * Author:
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mscc-common.h"
+
+#define MSCC_GPIO_OUT_SET 0x0
+#define MSCC_GPIO_OUT_CLR 0x4
+#define MSCC_GPIO_OUT 0x8
+#define MSCC_GPIO_IN 0xc
+#define MSCC_GPIO_OE 0x10
+#define MSCC_GPIO_INTR 0x14
+#define MSCC_GPIO_INTR_ENA 0x18
+#define MSCC_GPIO_INTR_IDENT 0x1c
+#define MSCC_GPIO_ALT0 0x20
+#define MSCC_GPIO_ALT1 0x24
+
+static int mscc_get_functions_count(struct udevice *dev)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->num_func;
+}
+
+static const char *mscc_get_function_name(struct udevice *dev,
+ unsigned int function)
+{
+ struct mscc_pinctrl *info = dev_get_
[U-Boot] [PATCH v2 7/7] MIPS: bootm: Add support for Vcore III linux kernel
The kernels built for the Vcore III linux kernel have different
expectation in the way the data were passed.
Unlike with yamon, the command line is expected to be a single string
passed in argv[1]. An other expectation is that the arguments are located
in the cached address space.
However, like yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel, and besides that it
also wait for the root=/dev/ram0.
Signed-off-by: Gregory CLEMENT
---
arch/mips/lib/bootm.c | 77 ---
1 file changed, 57 insertions(+), 20 deletions(-)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index deca5189e3..803d5e1de3 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -15,6 +15,11 @@ DECLARE_GLOBAL_DATA_PTR;
#defineLINUX_MAX_ENVS 256
#defineLINUX_MAX_ARGS 256
+enum legacy_boot_type {
+ LEGACY_BOOT_YAML,
+ LEGACY_BOOT_VCORE,
+};
+
static int linux_argc;
static char **linux_argv;
static char *linux_argp;
@@ -44,22 +49,46 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, sp, gd->ram_top - sp);
}
-static void linux_cmdline_init(void)
+static void linux_cmdline_init(enum legacy_boot_type boot_type)
{
+ switch (boot_type) {
+ /*
+* Vcore III linux kernels expect arguments in the cached
+* address space. They also expect the command line being a
+* single string in the first argument
+*/
+ case LEGACY_BOOT_VCORE:
+ linux_argv = (char **)(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ linux_argv[1] = linux_argp;
+ break;
+ case LEGACY_BOOT_YAML:
+ /* fallthrough */
+ default:
+ linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ }
linux_argc = 1;
- linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
linux_argv[0] = 0;
- linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
}
-static void linux_cmdline_set(const char *value, size_t len)
+static void linux_cmdline_set(const char *value, size_t len,
+ enum legacy_boot_type boot_type)
{
- linux_argv[linux_argc] = linux_argp;
memcpy(linux_argp, value, len);
- linux_argp[len] = 0;
-
+ switch (boot_type) {
+ case LEGACY_BOOT_VCORE:
+ linux_argv[linux_argc] = linux_argp;
+ linux_argp[len] = 0;
+ linux_argc++;
+ case LEGACY_BOOT_YAML:
+ /* fallthrough */
+ default:
+ linux_argp[len] = ' ';
+ linux_argp[len + 1] = 0;
+ linux_argc = 2;
+ }
linux_argp += len + 1;
- linux_argc++;
}
static void linux_cmdline_dump(void)
@@ -73,12 +102,11 @@ static void linux_cmdline_dump(void)
debug(" arg %03d: %s\n", i, linux_argv[i]);
}
-static void linux_cmdline_legacy(bootm_headers_t *images)
+static void linux_cmdline_legacy(bootm_headers_t *images,
+enum legacy_boot_type boot_type)
{
const char *bootargs, *next, *quote;
-
- linux_cmdline_init();
-
+ linux_cmdline_init(boot_type);
bootargs = env_get("bootargs");
if (!bootargs)
return;
@@ -104,7 +132,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
if (!next)
next = bootargs + strlen(bootargs);
- linux_cmdline_set(bootargs, next - bootargs);
+ linux_cmdline_set(bootargs, next - bootargs, boot_type);
if (*next)
next++;
@@ -113,7 +141,8 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
}
}
-static void linux_cmdline_append(bootm_headers_t *images)
+static void linux_cmdline_append(bootm_headers_t *images,
+enum legacy_boot_type boot_type)
{
char buf[24];
ulong mem, rd_start, rd_size;
@@ -121,7 +150,7 @@ static void linux_cmdline_append(bootm_headers_t *images)
/* append mem */
mem = gd->ram_size >> 20;
sprintf(buf, "mem=%luM", mem);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), boot_type);
/* append rd_start and rd_size */
rd_start = images->initrd_start;
@@ -129,9 +158,13 @@ static void linux_cmdline_append(bootm_headers_t *images)
if (rd_size) {
sprintf(buf, "rd_start=0x%08lX", rd_start);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), boot_type);
sprintf(buf, "rd_size=0x%lX", rd_size);
-
[U-Boot] [PATCH v2 5/7] MSCC: add board support for the Ocelots based evaluation boards
Adding the support for 2 boards sharing common code for Ocelot chip:
PCB120 and PCB123
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/mscc,ocelot.dtsi | 132 +++
arch/mips/dts/mscc,ocelot_pcb.dtsi | 33 +++
arch/mips/dts/ocelot_pcb120.dts | 12 +++
arch/mips/dts/ocelot_pcb123.dts | 12 +++
arch/mips/mach-mscc/Kconfig | 2 +
board/mscc/ocelot/Kconfig| 14 +++
board/mscc/ocelot/Makefile | 4 +
board/mscc/ocelot/ocelot.c | 48 ++
configs/mscc_ocelot_defconfig| 57
configs/mscc_ocelot_pcb120_defconfig | 56
include/configs/vcoreiii.h | 77
11 files changed, 447 insertions(+)
create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
create mode 100644 arch/mips/dts/ocelot_pcb120.dts
create mode 100644 arch/mips/dts/ocelot_pcb123.dts
create mode 100644 board/mscc/ocelot/Kconfig
create mode 100644 board/mscc/ocelot/Makefile
create mode 100644 board/mscc/ocelot/ocelot.c
create mode 100644 configs/mscc_ocelot_defconfig
create mode 100644 configs/mscc_ocelot_pcb120_defconfig
create mode 100644 include/configs/vcoreiii.h
diff --git a/arch/mips/dts/mscc,ocelot.dtsi b/arch/mips/dts/mscc,ocelot.dtsi
new file mode 100644
index 00..81afdffd4b
--- /dev/null
+++ b/arch/mips/dts/mscc,ocelot.dtsi
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,ocelot";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ clocks = <_clk>;
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 =
+ };
+
+ cpuintc: interrupt-controller@0 {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ compatible = "mti,cpu-interrupt-controller";
+ };
+
+ cpu_clk: cpu-clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <5>;
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x7000 0x200>;
+
+ interrupt-parent = <>;
+
+ cpu_ctrl: syscon@0 {
+ compatible = "mscc,ocelot-cpu-syscon", "syscon";
+ reg = <0x0 0x2c>;
+ };
+
+ intc: interrupt-controller@70 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70 0x70>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ interrupt-parent = <>;
+ interrupts = <2>;
+ };
+
+ uart0: serial@10 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x10 0x20>;
+ interrupts = <6>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@100800 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+ compatible = "ns16550a";
+ reg = <0x100800 0x20>;
+ interrupts = <7>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ spi0: spi-master@101000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-ssi";
+ reg = <0x101000 0x40>;
+ num-chipselect = <4>;
+
[U-Boot] [PATCH v2 6/7] MSCC: add board support for the Luton based evaluation board
Adding the support for the Luton boards PCB91 which share common code with
the Ocelots boards, including board code, device tree and configuration.
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/luton_pcb091.dts | 36 ++
arch/mips/dts/mscc,luton.dtsi | 87 ++
arch/mips/mach-mscc/Kconfig| 2 +
board/mscc/luton/Kconfig | 14 ++
board/mscc/luton/Makefile | 3 ++
board/mscc/luton/luton.c | 28 +++
configs/mscc_luton_defconfig | 66 ++
7 files changed, 236 insertions(+)
create mode 100644 arch/mips/dts/luton_pcb091.dts
create mode 100644 arch/mips/dts/mscc,luton.dtsi
create mode 100644 board/mscc/luton/Kconfig
create mode 100644 board/mscc/luton/Makefile
create mode 100644 board/mscc/luton/luton.c
create mode 100644 configs/mscc_luton_defconfig
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
new file mode 100644
index 00..b5e0df8d04
--- /dev/null
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+ model = "Luton PCB091 Reference Board";
+ compatible = "mscc,luton-pcb091", "mscc,luton";
+
+ aliases {
+ serial0 =
+ spi0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+spi-max-frequency = <1800>; /* input clock */
+reg = <0>; /* CS0 */
+ };
+};
+
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
new file mode 100644
index 00..6a4ad2a5be
--- /dev/null
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,luton";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 =
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20833>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x1020>;
+
+ uart0: serial@1010 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ compatible = "ns16550a";
+ reg = <0x1010 0x20>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@70068 {
+ compatible = "mscc,luton-pinctrl";
+ reg = <0x70068 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 32>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_30", "GPIO_31";
+ function = "uart";
+ };
+
+ };
+
+ gpio_spi_bitbang: gpio@1064 {
+ compatible = "mscc,spi-bitbang-gpio";
+ reg = <0x1064 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ };
+
+ spi0: spi-bitbang {
+ compatible = "spi-gpio";
+ status = "okay";
+ gpio-sck = <_spi_bitbang 6 0>;
+ gpio-miso = <_spi_bitbang 0 0>;
+ gpio-mosi = <_spi_bitbang 5 0>;
+ cs-gpios = <_spi_bitbang 1 0>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-
[U-Boot] [PATCH v2 3/7] MSCC: add support for Ocelot SoCs
This family of SoCs are found in the Microsemi Switches solution and have already a support in the linux kernel. Signed-off-by: Gregory CLEMENT --- arch/mips/Kconfig | 6 + arch/mips/Makefile| 1 + arch/mips/mach-mscc/Kconfig | 69 ++ arch/mips/mach-mscc/Makefile | 5 + arch/mips/mach-mscc/cpu.c | 42 ++ arch/mips/mach-mscc/dram.c| 61 ++ arch/mips/mach-mscc/include/ioremap.h | 51 ++ arch/mips/mach-mscc/include/mach/common.h | 27 + arch/mips/mach-mscc/include/mach/ddr.h| 680 ++ .../mach-mscc/include/mach/ocelot/ocelot.h| 35 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 + .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 +++ arch/mips/mach-mscc/include/mach/tlb.h| 55 ++ arch/mips/mach-mscc/lowlevel_init.S | 23 + arch/mips/mach-mscc/reset.c | 36 + 15 files changed, 1386 insertions(+) create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/reset.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 071dea04ec..da479f2172 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -59,6 +59,11 @@ config ARCH_ATH79 select OF_CONTROL imply CMD_DM +config ARCH_MSCC + bool "Support MSCC VCore-III" + select OF_CONTROL + select DM + config ARCH_BMIPS bool "Support BMIPS SoCs" select CLK @@ -135,6 +140,7 @@ source "board/imgtec/xilfpga/Kconfig" source "board/micronas/vct/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-mscc/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" source "arch/mips/mach-mt7620/Kconfig" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 802244a06e..124e93fa26 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -15,6 +15,7 @@ machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 machine-$(CONFIG_ARCH_MT7620) += mt7620 +machine-$(CONFIG_ARCH_MSCC) += mscc machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig new file mode 100644 index 00..7f1b270207 --- /dev/null +++ b/arch/mips/mach-mscc/Kconfig @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +menu "MSCC VCore-III platforms" + depends on ARCH_MSCC + +config SOC_VCOREIII + select MIPS_TUNE_24KC + select ROM_EXCEPTION_VECTORS + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_LITTLE_ENDIAN + bool + +config SYS_SOC + default "mscc" + +config SOC_OCELOT + bool + select SOC_VCOREIII + help + This supports MSCC Ocelot family of SOCs. + +config SYS_CONFIG_NAME + default "vcoreiii" + +choice + prompt "Board select" + +config TARGET_OCELOT_PCB120 + bool "MSCC PCB120 Reference Board (aka VSC5635EV)" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb120 + +config TARGET_OCELOT_PCB123 + bool "MSCC PCB123 Reference Board (aka VSC7514EV))" + select SOC_OCELOT + help + When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to + ocelot_pcb123 + +endchoice + +choice + prompt "DDR type" + +config DDRTYPE_H5TQ4G63MFR + bool "Hynix H5TQ4G63MFR-PBC (4Gbit, DDR3-800, 256Mbitx16)" + +config DDRTYPE_MT41K256M16 + bool "Micron MT41K256M16 (4Gbit, DDR3L-800, 256Mbitx16)" + +config DDRTYPE_H5TQ1G63BFA + bool "Hynix H5TQ1G63BFA (1Gbit DDR3, x16)" + +config DDRTYPE_MT41J128M16HA + bool "Micron MT41J128M16HA-15E:D (2Gbit DDR3, x16)" + +config DDRTYPE_MT41K128M16JT + bool "Micron MT41K128M16JT-125 (2Gbit DDR3L, 128Mbitx16)" + +config DDRTYPE_MT47H128M8HQ + bool "Micron M
[U-Boot] [PATCH v2 4/7] MSCC: add support for Luton SoCs
As the Ocelots SoCs, this family of SoCs are found in the Microsemi
Switches solution.
Signed-off-by: Gregory CLEMENT
---
arch/mips/mach-mscc/Kconfig | 13 +
arch/mips/mach-mscc/Makefile | 1 +
arch/mips/mach-mscc/cpu.c | 13 +
arch/mips/mach-mscc/dram.c| 2 +
arch/mips/mach-mscc/include/mach/common.h | 4 +
arch/mips/mach-mscc/include/mach/ddr.h| 114 +++-
.../mips/mach-mscc/include/mach/luton/luton.h | 37 +++
.../include/mach/luton/luton_devcpu_gcb.h | 14 +
.../include/mach/luton/luton_icpu_cfg.h | 245 ++
arch/mips/mach-mscc/lowlevel_init.S | 7 +
arch/mips/mach-mscc/lowlevel_init_luton.S | 62 +
11 files changed, 508 insertions(+), 4 deletions(-)
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h
create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h
create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 7f1b270207..a8cace0e79 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -21,6 +21,12 @@ config SOC_OCELOT
help
This supports MSCC Ocelot family of SOCs.
+config SOC_LUTON
+ bool
+ select SOC_VCOREIII
+ help
+ This supports MSCC Luton family of SOCs.
+
config SYS_CONFIG_NAME
default "vcoreiii"
@@ -41,6 +47,13 @@ config TARGET_OCELOT_PCB123
When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
ocelot_pcb123
+config TARGET_LUTON_PCB091
+ bool "MSCC PCB091 Reference Board"
+ select SOC_LUTON
+ select MSCC_BITBANG_SPI_GPIO
+ help
+ When selected, CONFIG_DEFAULT_DEVICE_TREE should be set to
+ luton_pcb091
endchoice
choice
diff --git a/arch/mips/mach-mscc/Makefile b/arch/mips/mach-mscc/Makefile
index d14ec33838..6c60f26ca4 100644
--- a/arch/mips/mach-mscc/Makefile
+++ b/arch/mips/mach-mscc/Makefile
@@ -3,3 +3,4 @@
CFLAGS_cpu.o += -finline-limit=64000
obj-y += cpu.o dram.o reset.o lowlevel_init.o
+obj-$(CONFIG_SOC_LUTON) += lowlevel_init_luton.o
diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c
index 0c8f7933cd..562b2cf5f9 100644
--- a/arch/mips/mach-mscc/cpu.c
+++ b/arch/mips/mach-mscc/cpu.c
@@ -31,12 +31,25 @@ void vcoreiii_tlb_init(void)
*/
create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
MMU_REGIO_RW);
+#ifdef CONFIG_SOC_LUTON
+ create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
+ MMU_REGIO_RW);
+#endif
}
int mach_cpu_init(void)
{
/* Speed up NOR flash access */
+#ifdef CONFIG_SOC_LUTON
+ writel(ICPU_PI_MST_CFG_TRISTATE_CTRL +
+ ICPU_PI_MST_CFG_CLK_DIV(4), REG_CFG(ICPU_PI_MST_CFG));
+
+ writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
+ ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
+ ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
+#else
writel(ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
+#endif
return 0;
}
diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
index b82961f773..5ee141ab77 100644
--- a/arch/mips/mach-mscc/dram.c
+++ b/arch/mips/mach-mscc/dram.c
@@ -23,7 +23,9 @@ int vcoreiii_ddr_init(void)
hal_vcoreiii_wait_memctl();
if (hal_vcoreiii_init_dqs() != 0 ||
hal_vcoreiii_train_bytelane(0) != 0
+#ifdef CONFIG_SOC_OCELOT
|| hal_vcoreiii_train_bytelane(1) != 0
+#endif
)
hal_vcoreiii_ddr_failed();
}
diff --git a/arch/mips/mach-mscc/include/mach/common.h
b/arch/mips/mach-mscc/include/mach/common.h
index 41887097f9..4ba1f7974c 100644
--- a/arch/mips/mach-mscc/include/mach/common.h
+++ b/arch/mips/mach-mscc/include/mach/common.h
@@ -13,6 +13,10 @@
#include
#include
#include
+#elif defined(CONFIG_SOC_LUTON)
+#include
+#include
+#include
#else
#error Unsupported platform
#endif
diff --git a/arch/mips/mach-mscc/include/mach/ddr.h
b/arch/mips/mach-mscc/include/mach/ddr.h
index c089af8e33..51ea65b573 100644
--- a/arch/mips/mach-mscc/include/mach/ddr.h
+++ b/arch/mips/mach-mscc/include/mach/ddr.h
@@ -586,6 +586,99 @@ static inline int dram_check(void)
}
return 0;
}
+#else /* Luton */
+
+static inline void sleep_100ns(u32 val)
+{
+}
+
+static inline void hal_vcoreiii_ddr_reset_assert(void)
+{
+ setbits_le32(REG_CFG(ICPU_MEMPHY_CFG), ICPU_MEMPHY_CFG_PHY_RST);
+ setbits_le32(REG_CFG(ICPU_RESET), ICPU_RESET_MEM_RST_FORCE);
+}
+
+static inline void hal_vcoreiii_ddr_reset_release(void)
+{
+}
+
+static inline void hal_vcor
[U-Boot] [PATCH v2 0/7] Add support for the SoCs found in Microsemi switches
Hello, For the record this the second version of the series adding the support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them belongs to the same family Vcore III. We found them on various advanced switches product. The support for Ocelot already have been submit to Linux, but not yet the Luton support. Since the v1 many changes had been done: - a big clean-up for indentation and some style issue - usage of the clrsetbits family functions where it was possible - split the patches for Ocelot and Luton - add a new patch to introduce the icache_lock function which was in the mscc directory in the first version - remove more unused define in the platform header files - use the automatic cache size detection instead of hard coding it - reduce the tlb init to only two entries for the IO as needed by the kernel - remove the interrupt disabling - fix the ddr init for luton Gregory CLEMENT (7): MIPS: move create_tlb() in an proper header: mipsregs.h MIPS: Allow to prefetch and lock instructions into cache MSCC: add support for Ocelot SoCs MSCC: add support for Luton SoCs MSCC: add board support for the Ocelots based evaluation boards MSCC: add board support for the Luton based evaluation board MIPS: bootm: Add support for Vcore III linux kernel arch/mips/Kconfig | 6 + arch/mips/Makefile| 1 + arch/mips/cpu/cpu.c | 10 - arch/mips/dts/luton_pcb091.dts| 36 + arch/mips/dts/mscc,luton.dtsi | 87 ++ arch/mips/dts/mscc,ocelot.dtsi| 132 +++ arch/mips/dts/mscc,ocelot_pcb.dtsi| 33 + arch/mips/dts/ocelot_pcb120.dts | 12 + arch/mips/dts/ocelot_pcb123.dts | 12 + arch/mips/include/asm/cacheops.h | 19 + arch/mips/include/asm/mipsregs.h | 11 + arch/mips/lib/bootm.c | 77 +- arch/mips/mach-mscc/Kconfig | 86 ++ arch/mips/mach-mscc/Makefile | 6 + arch/mips/mach-mscc/cpu.c | 55 ++ arch/mips/mach-mscc/dram.c| 63 ++ arch/mips/mach-mscc/include/ioremap.h | 51 ++ arch/mips/mach-mscc/include/mach/common.h | 31 + arch/mips/mach-mscc/include/mach/ddr.h| 786 ++ .../mips/mach-mscc/include/mach/luton/luton.h | 37 + .../include/mach/luton/luton_devcpu_gcb.h | 14 + .../include/mach/luton/luton_icpu_cfg.h | 245 ++ .../mach-mscc/include/mach/ocelot/ocelot.h| 35 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 21 + .../include/mach/ocelot/ocelot_icpu_cfg.h | 274 ++ arch/mips/mach-mscc/include/mach/tlb.h| 55 ++ arch/mips/mach-mscc/lowlevel_init.S | 30 + arch/mips/mach-mscc/lowlevel_init_luton.S | 62 ++ arch/mips/mach-mscc/reset.c | 36 + board/mscc/luton/Kconfig | 14 + board/mscc/luton/Makefile | 3 + board/mscc/luton/luton.c | 28 + board/mscc/ocelot/Kconfig | 14 + board/mscc/ocelot/Makefile| 4 + board/mscc/ocelot/ocelot.c| 48 ++ configs/mscc_luton_defconfig | 66 ++ configs/mscc_ocelot_defconfig | 57 ++ configs/mscc_ocelot_pcb120_defconfig | 56 ++ include/configs/vcoreiii.h| 77 ++ 39 files changed, 2660 insertions(+), 30 deletions(-) create mode 100644 arch/mips/dts/luton_pcb091.dts create mode 100644 arch/mips/dts/mscc,luton.dtsi create mode 100644 arch/mips/dts/mscc,ocelot.dtsi create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi create mode 100644 arch/mips/dts/ocelot_pcb120.dts create mode 100644 arch/mips/dts/ocelot_pcb123.dts create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S create mode 100644 arch/mips/mach-mscc/reset.c create mode 100644 board/mscc/luton/Kconfig create mode 100644 board/mscc/luton/Makefile create
[U-Boot] [PATCH v2 2/7] MIPS: Allow to prefetch and lock instructions into cache
This path add a new helper allowing to prefetch and lock instructions
into cache. This is useful very early in the boot when no RAM is
available yet.
Signed-off-by: Gregory CLEMENT
---
arch/mips/include/asm/cacheops.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/mips/include/asm/cacheops.h b/arch/mips/include/asm/cacheops.h
index 3161875441..98b67ccc8e 100644
--- a/arch/mips/include/asm/cacheops.h
+++ b/arch/mips/include/asm/cacheops.h
@@ -19,6 +19,25 @@ static inline void mips_cache(int op, const volatile void
*addr)
#endif
}
+#define MIPS32_WHICH_ICACHE0x0
+#define MIPS32_FETCH_AND_LOCK 0x7
+
+#define ICACHE_LOAD_LOCK (MIPS32_WHICH_ICACHE | (MIPS32_FETCH_AND_LOCK << 2))
+
+/* Prefetch and lock instructions into cache */
+static inline void icache_lock(void *func, size_t len)
+{
+ int i, lines = ((len - 1) / ARCH_DMA_MINALIGN) + 1;
+
+ for (i = 0; i < lines; i++) {
+ asm volatile (" cache %0, %1(%2)"
+ : /* No Output */
+ : "I" ICACHE_LOAD_LOCK,
+ "n" (i * ARCH_DMA_MINALIGN),
+ "r" (func)
+ : /* No Clobbers */);
+ }
+}
#endif /* !__ASSEMBLY__ */
/*
--
2.19.1
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[U-Boot] [PATCH v2 1/7] MIPS: move create_tlb() in an proper header: mipsregs.h
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c | 10 --
arch/mips/include/asm/mipsregs.h | 11 +++
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 5c56ab0289..a403ff729b 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
}
#endif
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
- write_c0_entrylo0(low0);
- write_c0_pagemask(pagemask);
- write_c0_entrylo1(low1);
- write_c0_entryhi(hi);
- write_c0_index(index);
- tlb_write_indexed();
-}
-
int arch_cpu_init(void)
{
mips_cache_probe();
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 48fa1f1f7f..930562ebb2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2005,6 +2005,17 @@ static inline unsigned int get_ebase_cpunum(void)
return read_c0_ebase() & 0x3ff;
}
+static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
+u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
--
2.19.1
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Re: [U-Boot] [PATCH 6/6] MIPS: bootm: Add support for Vcore III linux kernel
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> The kernels built for the Vcore III linux kernel have different
>> expectation in the way the data were passed.
>>
>> Unlike with yamon, the command line is expected to be a single string
>> passed in argv[1]. An other expectation is that the arguments are located
>> in the cached address space.
>>
>> However, like yamon, they expect that rd_start and rd_size was passed by
>> the bootloader in the command line of the kernel, and besides that it
>> also wait for the root=/dev/ram0.
>
> Can't you use existing boot interfaces? The preferred way would be to
> pass a device-tree blob to the kernel and let U-Boot fill the bootargs
> in that DTB. I wonder why the linux-mips guys let you add another boot
> interface. Or do you simply want to boot some legacy or propietary
> kernels?
Actually we support the dtb way, but the legacy kernel still neeeds this
see:
https://elixir.bootlin.com/linux/v4.19-rc7/source/arch/mips/generic/board-ocelot.c#L38
Gregory
>
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> arch/mips/lib/bootm.c | 62 +--
>> 1 file changed, 42 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
>> index deca5189e3..417f5ce452 100644
>> --- a/arch/mips/lib/bootm.c
>> +++ b/arch/mips/lib/bootm.c
>> @@ -44,22 +44,38 @@ void arch_lmb_reserve(struct lmb *lmb)
>> lmb_reserve(lmb, sp, gd->ram_top - sp);
>> }
>>
>> -static void linux_cmdline_init(void)
>> +static void linux_cmdline_init(int vcoreiii)
>> {
>> +if (!vcoreiii) {
>> +linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> +linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> +} else {
>> +/*
>> + * Vcore III linux kernels expect arguments in the cached
>> + * address space. They also expect the command line being a
>> + * single string in the first argument
>> + */
>> +linux_argv = (char **)(gd->bd->bi_boot_params);
>> +linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> +linux_argv[1] = linux_argp;
>> +}
>> linux_argc = 1;
>> -linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
>> linux_argv[0] = 0;
>> -linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
>> }
>>
>> -static void linux_cmdline_set(const char *value, size_t len)
>> +static void linux_cmdline_set(const char *value, size_t len, int vcoreiii)
>> {
>> -linux_argv[linux_argc] = linux_argp;
>> memcpy(linux_argp, value, len);
>> -linux_argp[len] = 0;
>> -
>> +if (!vcoreiii) {
>> +linux_argv[linux_argc] = linux_argp;
>> +linux_argp[len] = 0;
>> +linux_argc++;
>> +} else {
>> +linux_argp[len] = ' ';
>> +linux_argp[len + 1] = 0;
>> +linux_argc = 2;
>> +}
>> linux_argp += len + 1;
>> -linux_argc++;
>> }
>>
>> static void linux_cmdline_dump(void)
>> @@ -73,12 +89,10 @@ static void linux_cmdline_dump(void)
>> debug(" arg %03d: %s\n", i, linux_argv[i]);
>> }
>>
>> -static void linux_cmdline_legacy(bootm_headers_t *images)
>> +static void linux_cmdline_legacy(bootm_headers_t *images, int vcoreiii)
>> {
>> const char *bootargs, *next, *quote;
>> -
>> -linux_cmdline_init();
>> -
>> +linux_cmdline_init(vcoreiii);
>> bootargs = env_get("bootargs");
>> if (!bootargs)
>> return;
>> @@ -104,7 +118,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
>> if (!next)
>> next = bootargs + strlen(bootargs);
>>
>> -linux_cmdline_set(bootargs, next - bootargs);
>> +linux_cmdline_set(bootargs, next - bootargs, vcoreiii);
>>
>> if (*next)
>> next++;
>> @@ -113,7 +127,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
>> }
>> }
>>
>> -static void linux_cmdline_append(bootm_headers_t *images)
>> +static void linux_cmdline_append(bootm_headers_t *images, int vcoreiii)
>> {
>> char buf[24];
>> ulong mem, rd_start, rd_size;
>> @@ -121,7 +135,7 @@ static void linu
Re: [U-Boot] [PATCH 5/6] MSCC: add configuration for Ocelot and Luton based boards
Hi Daniel, On mer., sept. 26 2018, Daniel Schwierzeck wrote: > On 25.09.2018 15:01, Gregory CLEMENT wrote: >> Add common configuration header for the VCore III SoCs (currently Ocelot >> and Luton), but also the defconfig for the evaluation boards of these >> SoCs. >> >> Signed-off-by: Gregory CLEMENT >> --- >> configs/mscc_luton_defconfig | 66 + >> configs/mscc_ocelot_defconfig| 57 ++ >> configs/mscc_ocelot_pcb120_defconfig | 56 ++ >> include/configs/vcoreiii.h | 72 >> 4 files changed, 251 insertions(+) >> create mode 100644 configs/mscc_luton_defconfig >> create mode 100644 configs/mscc_ocelot_defconfig >> create mode 100644 configs/mscc_ocelot_pcb120_defconfig >> create mode 100644 include/configs/vcoreiii.h > > should also be added along with the board code Done too Gregory -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] MSCC: add device tree for Ocelot and Luton (boards and SoCs)
Hi Daniel, On mer., sept. 26 2018, Daniel Schwierzeck wrote: > On 25.09.2018 15:01, Gregory CLEMENT wrote: >> Adding device tree for Ocelot SoC (extract from Linux) and the 2 >> evaluation boards using this SoC: PCB120 and PCB132. >> >> Adding device tree for Luton SoC (not yet in Linux) and the evaluation >> boards using this SoC: PCB91. >> >> Signed-off-by: Gregory CLEMENT >> --- >> arch/mips/dts/luton_pcb091.dts | 36 >> arch/mips/dts/mscc,luton.dtsi | 87 +++ >> arch/mips/dts/mscc,ocelot.dtsi | 132 + >> arch/mips/dts/mscc,ocelot_pcb.dtsi | 37 >> arch/mips/dts/ocelot_pcb120.dts| 12 +++ >> arch/mips/dts/ocelot_pcb123.dts| 12 +++ >> 6 files changed, 316 insertions(+) >> create mode 100644 arch/mips/dts/luton_pcb091.dts >> create mode 100644 arch/mips/dts/mscc,luton.dtsi >> create mode 100644 arch/mips/dts/mscc,ocelot.dtsi >> create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi >> create mode 100644 arch/mips/dts/ocelot_pcb120.dts >> create mode 100644 arch/mips/dts/ocelot_pcb123.dts > > should be added along with the board code. Also please try to add Ocelot > and Luton boards in separate patches. Done Gregory -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 3/6] MSCC: add board support for the VCoreIII based evaluation boards
Hi Marek,
On jeu., sept. 27 2018, Marek Vasut wrote:
> On 09/25/2018 03:01 PM, Gregory CLEMENT wrote:
>> Adding the support for 3 boards sharing common code:
>> - PCB120 and PCB 123 for Ocelot chip
>> - PCB 91 for Luton chip
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
>> board/mscc/common/board.c | 29 +
>> board/mscc/luton/Kconfig | 14 ++
>> board/mscc/luton/Makefile | 4
>> board/mscc/luton/luton.c | 14 ++
>> board/mscc/ocelot/Kconfig | 24
>> board/mscc/ocelot/Makefile | 5 +
>> board/mscc/ocelot/ocelot.c | 38 ++
>> 7 files changed, 128 insertions(+)
>> create mode 100644 board/mscc/common/board.c
>> create mode 100644 board/mscc/luton/Kconfig
>> create mode 100644 board/mscc/luton/Makefile
>> create mode 100644 board/mscc/luton/luton.c
>> create mode 100644 board/mscc/ocelot/Kconfig
>> create mode 100644 board/mscc/ocelot/Makefile
>> create mode 100644 board/mscc/ocelot/ocelot.c
>>
>> diff --git a/board/mscc/common/board.c b/board/mscc/common/board.c
>> new file mode 100644
>> index 00..86e7bf3353
>> --- /dev/null
>> +++ b/board/mscc/common/board.c
>> @@ -0,0 +1,29 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Microsemi Corporation
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +int board_early_init_r(void)
>> +{
>> +u32 ctrl;
>> +
>> +/* Prepare SPI controller to be used in master mode */
>> +writel(0, REG_CFG(ICPU_SW_MODE));
>> +ctrl = readl(REG_CFG(ICPU_GENERAL_CTRL));
>> +
>> +writel((ctrl & ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M) |
>> + ICPU_GENERAL_CTRL_IF_SI_OWNER(2),
>> + REG_CFG(ICPU_GENERAL_CTRL));
>
> This can be replaced by one of the clrsetbits stuff.
I used the clrsetbits family everywhere it was possible now.
>
> [...]
>
>> +++ b/board/mscc/luton/luton.c
>> @@ -0,0 +1,14 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Microsemi Corporation
>> + */
>> +
>> +#include
>> +#include
>> +
>> +void board_debug_uart_init(void)
>> +{
>> +/* too early for the pinctrl driver, so configure the UART pins here */
>> +writel(BIT(30)|BIT(31), REG_GCB((0x68+8*4)));
>> +writel(~(BIT(30)|BIT(31)), REG_GCB((0x68+9*4)));
>
> Can this ad-hoc random address be replaced by a macro ?
Done!
Gregory
>
> [...]
>
> --
> Best regards,
> Marek Vasut
--
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Re: [U-Boot] [PATCH 3/6] MSCC: add board support for the VCoreIII based evaluation boards
Hi Daniel,
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> Adding the support for 3 boards sharing common code:
>> - PCB120 and PCB 123 for Ocelot chip
>> - PCB 91 for Luton chip
>>
[...]
>> diff --git a/board/mscc/ocelot/Kconfig b/board/mscc/ocelot/Kconfig
>> new file mode 100644
>> index 00..0804f5081d
>> --- /dev/null
>> +++ b/board/mscc/ocelot/Kconfig
>> @@ -0,0 +1,24 @@
>> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +config SYS_VENDOR
>> +default "mscc"
>> +
>> +if SOC_OCELOT
>> +
>> +config SYS_BOARD
>> +default "ocelot"
>> +
>> +config SYS_CONFIG_NAME
>> +default "ocelot"
>> +
>> +endif
>> +
>> +if SOC_LUTON
>> +
>> +config SYS_BOARD
>> +default "luton"
>> +
>> +config SYS_CONFIG_NAME
>> +default "luton"
>> +
>
> this is already defined in board/mscc/luton/Kconfig
I removed it
>
>> +endif
>> diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile
>> new file mode 100644
>> index 00..f6a665ca83
>> --- /dev/null
>> +++ b/board/mscc/ocelot/Makefile
>> @@ -0,0 +1,5 @@
>> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +obj-$(CONFIG_SOC_OCELOT):= ocelot.o
>> +obj-y += ../common/board.o
>> +
>> diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
>> new file mode 100644
>> index 00..971fa93d07
>> --- /dev/null
>> +++ b/board/mscc/ocelot/ocelot.c
>> @@ -0,0 +1,38 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2018 Microsemi Corporation
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +void external_cs_manage(struct udevice *dev, bool enable)
>> +{
>> +u32 cs = spi_chip_select(dev);
>> +/* IF_SI0_OWNER, select the owner of the SI interface
>> + * Encoding: 0: SI Slave
>> + * 1: SI Boot Master
>> + * 2: SI Master Controller
>> + */
>
> style issues like indentation and multi-line comments
I fixed it
Gregory
>
>> +if (!enable) {
>> +writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
>> + ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
>> + REG_CFG(ICPU_SW_MODE));
>> +writel((readl(REG_CFG(ICPU_GENERAL_CTRL))
>> +& ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M) |
>> + ICPU_GENERAL_CTRL_IF_SI_OWNER(2),
>> + REG_CFG(ICPU_GENERAL_CTRL));
>> +} else {
>> +writel(0, REG_CFG(ICPU_SW_MODE));
>> +writel((readl(REG_CFG(ICPU_GENERAL_CTRL)) &
>> +~ICPU_GENERAL_CTRL_IF_SI_OWNER_M) |
>> + ICPU_GENERAL_CTRL_IF_SI_OWNER(1),
>> + REG_CFG(ICPU_GENERAL_CTRL));
>> +}
>> +}
>>
>
> --
> - Daniel
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
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Re: [U-Boot] [PATCH 2/6] MSCC: add support for VCoreIII SoCs
Hi Daniel,
I am bout to send a new version of the series, but befor I am going to
answer to the pending point I didn't already address in my email 10 days
ago.
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> Hi Gregory,
>
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> These families of SoCs are found in the Microsemi Switches solution.
>>
>> Currently the support for two families support is added:
>> - Ocelot (VSC7513, VSC7514) already supported in Linux
>> - Luton (Luton10: VSC7423, VSC7424, VSC7428 and Luton26: VSC7425,
>>VSC7426, VSC7426, VSC7427, VSC7429)
[...]
>> machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))
>> libs-y += $(machdirs)
>> diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
>> new file mode 100644
>> index 00..20148bfe15
>> --- /dev/null
>> +++ b/arch/mips/mach-mscc/Kconfig
>> @@ -0,0 +1,101 @@
>> +# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +
>> +if ARCH_MSCC
>> +
>> +config SYS_DCACHE_SIZE
>> +default 32768
>> +
>> +config SYS_DCACHE_LINE_SIZE
>> +default 32
>> +
>> +config SYS_ICACHE_SIZE
>> +default 32768
>> +
>> +config SYS_ICACHE_LINE_SIZE
>> +default 32
>> +
>> +endif
>
> from the code below I assume you have a MIPS24k core? If so you should
> use the automatic cache size detection
Eventually I managed to use the automatic cache size detection.
>> +void vcoreiii_tlb_init(void)
>> +{
>> +register int tlbix = 0;
>> +
>> +init_tlb();
>> +
>> +/* 0x7000 size 32M (0x0200) */
>> +create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#ifdef CONFIG_SOC_LUTON
>> +create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#endif
>> +/* 0x4000 - 0x43ff - NON-CACHED! */
>> +/* Flash CS0-3, each 16M = 64M total (16 x 4 below ) */
>> +create_tlb(tlbix++, MSCC_FLASH_TO,SZ_16M, MMU_REGIO_RO,
>> MMU_REGIO_RO);
>> +create_tlb(tlbix++, MSCC_FLASH_TO+SZ_32M, SZ_16M, MMU_REGIO_RO,
>> MMU_REGIO_RO);
>> +
>> +/* 0x2000 - up */
>> +#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
>> +create_tlb(tlbix++, MSCC_DDR_TO,SZ_64M, MMU_REGIO_RW,
>> MMU_REGIO_INVAL);
>> +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
>> +create_tlb(tlbix++, MSCC_DDR_TO,SZ_64M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
>> +create_tlb(tlbix++, MSCC_DDR_TO, SZ_256M, MMU_REGIO_RW,
>> MMU_REGIO_INVAL);
>> +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
>> +create_tlb(tlbix++, MSCC_DDR_TO, SZ_256M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#else /* 1024M */
>> +create_tlb(tlbix++, MSCC_DDR_TO, SZ_512M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#endif
>
> can't you leave that to the kernel? U-Boot is only running in kernel
> mode and doesn't need MMU mappings.
Actually, U-Boot doesn't need MMU mappings, and without this chunk of
code U-Boot is running without any problem, but unlike most of the MIPS
based SoCs, the IO register address are not in KSEG0. The mainline linux
kernel built in legacy mode needs to access some of the registers very
early in the boot and make the assumption that the bootloader already
configured them, so we have to match this expectation.
So in code I only keep the tlb entry for MSCC_IO_ORIGIN1_OFFSET and
MSCC_IO_ORIGIN1_OFFSET (where the Io registers are) and I added a
comment to explain it.
>> +}
>> +
>> +int mach_cpu_init(void)
>> +{
>> +/* Speed up NOR flash access */
>> +#ifdef CONFIG_SOC_LUTON
>> +writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
>> +#else
>> +writel(
>> +#endif
>> + ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
>> + ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
>> +
>> +/* Disable all IRQs - map to destination map 0 */
>> +writel(0, REG_CFG(ICPU_INTR_ENA));
>> +#ifdef CONFIG_SOC_OCELOT
>> +writel(~0, REG_CFG(ICPU_DST_INTR_MAP(0)));
>> +writel(0, REG_CFG(ICPU_DST_INTR_MAP(1)));
>> +writel(0, REG_CFG(ICPU_DST_INTR_MAP(2)));
>> +writel(0, REG_CFG(ICPU_DST_INTR_MAP(3)));
>> +#else
>> +writel(ICPU_INTR_IRQ0_ENA_IRQ0_ENA, REG_CFG(ICPU_INTR_IRQ0_ENA));
>> +#endif
>
> do you really need to disable interrupts after a cold or warm boot?
It was a workaround for an issue in a legacy kernel that is now fixed so
indeed can remove it.
[...]
>> +
>> +static inline void init_tlb(void)
>> +{
>> +register int i, max;
>> +
>> +max = get_tlb_count();
>> +for(i = 0; i < max; i++)
>> +create_tlb(i, i * SZ_1M, SZ_4K, MMU_REGIO_INVAL, MMU_REGIO_INVAL);
>> +}
>
> again can't you leave the setup of MMU mappings to the kernel?
I removed this part
[...]
Gregory
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Re: [U-Boot] [PATCH 2/6] MSCC: add support for VCoreIII SoCs
Hi Daniel,
First thanks for you prompt review, it is much appreciate. :)
This week I am at kernel recipes conference, so I won't be able to fully
address your comments but I will do it next week.
However, here are some answers:
On mer., sept. 26 2018, Daniel Schwierzeck
wrote:
> Hi Gregory,
>
> On 25.09.2018 15:01, Gregory CLEMENT wrote:
>> These families of SoCs are found in the Microsemi Switches solution.
>>
>> Currently the support for two families support is added:
>> - Ocelot (VSC7513, VSC7514) already supported in Linux
>> - Luton (Luton10: VSC7423, VSC7424, VSC7428 and Luton26: VSC7425,
>>VSC7426, VSC7426, VSC7427, VSC7429)
>
> Is this some polished version of the original vendor U-Boot?
No the original vendor version was RedBoot
> Could you maybe add Ocelot and Luton in separate patches?
Yes sure the intent to have a uniq patch was to justify the common code
between both SoC.
>
>>
>> Signed-off-by: Gregory CLEMENT
>> ---
[..]
>> +endif
>
> from the code below I assume you have a MIPS24k core? If so you should
> use the automatic cache size detection
Yes it is a MIPS24k core. I will have a look on the automatic cache size
detection.
>
>> +
>> +menu "MSCC VCore-III platforms"
>> +depends on ARCH_MSCC
>> +
>> +config SOC_VCOREIII
>> +select SUPPORTS_LITTLE_ENDIAN
>> +select SUPPORTS_BIG_ENDIAN
>> +select SUPPORTS_CPU_MIPS32_R1
>> +select SUPPORTS_CPU_MIPS32_R2
>> +select ROM_EXCEPTION_VECTORS
>> +select MIPS_TUNE_24KC
>> +bool
>
> sort this alpahetically
OK
>
>> +
[...]
>> +void vcoreiii_tlb_init(void)
>> +{
>> +register int tlbix = 0;
>> +
>> +init_tlb();
>> +
>> +/* 0x7000 size 32M (0x0200) */
>> +create_tlb(tlbix++, MSCC_IO_ORIGIN1_OFFSET, SZ_16M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#ifdef CONFIG_SOC_LUTON
>> +create_tlb(tlbix++, MSCC_IO_ORIGIN2_OFFSET, SZ_16M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#endif
>> +/* 0x4000 - 0x43ff - NON-CACHED! */
>> +/* Flash CS0-3, each 16M = 64M total (16 x 4 below ) */
>> +create_tlb(tlbix++, MSCC_FLASH_TO,SZ_16M, MMU_REGIO_RO,
>> MMU_REGIO_RO);
>> +create_tlb(tlbix++, MSCC_FLASH_TO+SZ_32M, SZ_16M, MMU_REGIO_RO,
>> MMU_REGIO_RO);
>> +
>> +/* 0x2000 - up */
>> +#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M
>> +create_tlb(tlbix++, MSCC_DDR_TO,SZ_64M, MMU_REGIO_RW,
>> MMU_REGIO_INVAL);
>> +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M
>> +create_tlb(tlbix++, MSCC_DDR_TO,SZ_64M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M
>> +create_tlb(tlbix++, MSCC_DDR_TO, SZ_256M, MMU_REGIO_RW,
>> MMU_REGIO_INVAL);
>> +#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M
>> +create_tlb(tlbix++, MSCC_DDR_TO, SZ_256M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#else /* 1024M */
>> +create_tlb(tlbix++, MSCC_DDR_TO, SZ_512M, MMU_REGIO_RW,
>> MMU_REGIO_RW);
>> +#endif
>
> can't you leave that to the kernel? U-Boot is only running in kernel
> mode and doesn't need MMU mappings.
You should be right, I will check it.
>
>> +}
>> +
>> +int mach_cpu_init(void)
>> +{
>> +/* Speed up NOR flash access */
>> +#ifdef CONFIG_SOC_LUTON
>> +writel(ICPU_SPI_MST_CFG_FAST_READ_ENA +
>> +#else
>> +writel(
>> +#endif
>> + ICPU_SPI_MST_CFG_CS_DESELECT_TIME(0x19) +
>> + ICPU_SPI_MST_CFG_CLK_DIV(9), REG_CFG(ICPU_SPI_MST_CFG));
>> +
>> +/* Disable all IRQs - map to destination map 0 */
>> +writel(0, REG_CFG(ICPU_INTR_ENA));
>> +#ifdef CONFIG_SOC_OCELOT
>> +writel(~0, REG_CFG(ICPU_DST_INTR_MAP(0)));
>> +writel(0, REG_CFG(ICPU_DST_INTR_MAP(1)));
>> +writel(0, REG_CFG(ICPU_DST_INTR_MAP(2)));
>> +writel(0, REG_CFG(ICPU_DST_INTR_MAP(3)));
>> +#else
>> +writel(ICPU_INTR_IRQ0_ENA_IRQ0_ENA, REG_CFG(ICPU_INTR_IRQ0_ENA));
>> +#endif
>
> do you really need to disable interrupts after a cold or warm boot?
I think it is needed, but I will check.
>
>> +return 0;
>> +}
>> diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c
>> new file mode 100644
>> index 00..2db9001fe9
>> --- /dev/null
>> +++ b/arch/mips/mach-mscc/dram.c
>> @@ -0,0 +1,62 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> +
[U-Boot] [PATCH 2/6] MSCC: add support for VCoreIII SoCs
These families of SoCs are found in the Microsemi Switches solution. Currently the support for two families support is added: - Ocelot (VSC7513, VSC7514) already supported in Linux - Luton (Luton10: VSC7423, VSC7424, VSC7428 and Luton26: VSC7425, VSC7426, VSC7426, VSC7427, VSC7429) Signed-off-by: Gregory CLEMENT --- Hi, Actually this is the second version of this patch. Compared to the previous version which did not reach the mailing list, I remove a lot of unused defines in the header. They can be add later when needed. Sorry for the noise Gregory arch/mips/Kconfig | 6 + arch/mips/Makefile| 1 + arch/mips/mach-mscc/Kconfig | 101 +++ arch/mips/mach-mscc/Makefile | 6 + arch/mips/mach-mscc/cpu.c | 72 ++ arch/mips/mach-mscc/dram.c| 62 ++ arch/mips/mach-mscc/include/ioremap.h | 49 ++ arch/mips/mach-mscc/include/mach/cache.h | 36 + arch/mips/mach-mscc/include/mach/common.h | 31 + arch/mips/mach-mscc/include/mach/ddr.h| 753 ++ .../mips/mach-mscc/include/mach/luton/luton.h | 37 + .../include/mach/luton/luton_devcpu_gcb.h | 16 + .../include/mach/luton/luton_icpu_cfg.h | 247 ++ .../mach-mscc/include/mach/ocelot/ocelot.h| 35 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 49 ++ .../include/mach/ocelot/ocelot_icpu_cfg.h | 278 +++ arch/mips/mach-mscc/include/mach/tlb.h| 65 ++ arch/mips/mach-mscc/lowlevel_init.S | 29 + arch/mips/mach-mscc/lowlevel_init_luton.S | 63 ++ arch/mips/mach-mscc/reset.c | 37 + 20 files changed, 1973 insertions(+) create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/cache.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S create mode 100644 arch/mips/mach-mscc/reset.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6e5e0ffe65..c4fc3d077b 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -58,6 +58,11 @@ config ARCH_ATH79 select OF_CONTROL imply CMD_DM +config ARCH_MSCC + bool "Support MSCC VCore-III" + select OF_CONTROL + select DM + config ARCH_BMIPS bool "Support BMIPS SoCs" select CLK @@ -118,6 +123,7 @@ source "board/imgtec/xilfpga/Kconfig" source "board/micronas/vct/Kconfig" source "board/qemu-mips/Kconfig" source "arch/mips/mach-ath79/Kconfig" +source "arch/mips/mach-mscc/Kconfig" source "arch/mips/mach-bmips/Kconfig" source "arch/mips/mach-pic32/Kconfig" diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a36f5f1fb6..acb1340942 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -14,6 +14,7 @@ libs-y += arch/mips/lib/ machine-$(CONFIG_ARCH_ATH79) += ath79 machine-$(CONFIG_ARCH_BMIPS) += bmips machine-$(CONFIG_MACH_PIC32) += pic32 +machine-$(CONFIG_ARCH_MSCC) += mscc machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y)) libs-y += $(machdirs) diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig new file mode 100644 index 00..20148bfe15 --- /dev/null +++ b/arch/mips/mach-mscc/Kconfig @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +if ARCH_MSCC + +config SYS_DCACHE_SIZE + default 32768 + +config SYS_DCACHE_LINE_SIZE + default 32 + +config SYS_ICACHE_SIZE + default 32768 + +config SYS_ICACHE_LINE_SIZE + default 32 + +endif + +menu "MSCC VCore-III platforms" + depends on ARCH_MSCC + +config SOC_VCOREIII + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select ROM_EXCEPTION_VECTORS + select MIPS_TUNE_24KC + bool + +config SYS_SOC + default "mscc" + +config SOC_OCELOT + bool + select SOC_VCOREIII + help + This supports MSCC Ocelot family of SOCs
Re: [U-Boot] [PATCH 0/6] Add support for VCore III SoCs found in Microsemi switches
Hi, On mar., sept. 25 2018, Gregory CLEMENT wrote: > Hello, > > This series add the support of 2 SoCs: Ocelot and Luton from > Microsemi. Both of them belongs to the same family Vcore III. > > We found them on various advanced switches product. > > The support for Ocelot already have been submit to Linux, but not yet > the Luton support. > > Besides this series 3 others patches are needed but they are driver > related: > DW SPI: Allow to overload the management of the external CS > gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi > pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based) > > They will be submitted separately. > > Thanks, > > Gregory > > > Gregory CLEMENT (6): > MIPS: move create_tlb() in an proper header: mipsregs.h > MSCC: add support for VCoreIII SoCs This patch didn't reach the mailing because it was too large. Actually, many defined were not used, so I removed then, and I am going to send the missing patch now. Gregory > MSCC: add board support for the VCoreIII based evaluation boards > MSCC: add device tree for Ocelot and Luton (boards and SoCs) > MSCC: add configuration for Ocelot and Luton based boards > MIPS: bootm: Add support for Vcore III linux kernel > > arch/mips/Kconfig | 6 + > arch/mips/Makefile| 1 + > arch/mips/cpu/cpu.c | 10 - > arch/mips/dts/luton_pcb091.dts| 36 + > arch/mips/dts/mscc,luton.dtsi | 87 ++ > arch/mips/dts/mscc,ocelot.dtsi| 132 +++ > arch/mips/dts/mscc,ocelot_pcb.dtsi| 37 + > arch/mips/dts/ocelot_pcb120.dts | 12 + > arch/mips/dts/ocelot_pcb123.dts | 12 + > arch/mips/include/asm/mipsregs.h | 11 + > arch/mips/lib/bootm.c | 62 +- > arch/mips/mach-mscc/Kconfig | 101 ++ > arch/mips/mach-mscc/Makefile | 6 + > arch/mips/mach-mscc/cpu.c | 72 ++ > arch/mips/mach-mscc/dram.c| 62 ++ > arch/mips/mach-mscc/include/ioremap.h | 49 + > arch/mips/mach-mscc/include/mach/cache.h | 36 + > arch/mips/mach-mscc/include/mach/common.h | 31 + > arch/mips/mach-mscc/include/mach/ddr.h| 753 +++ > .../mips/mach-mscc/include/mach/luton/luton.h | 37 + > .../include/mach/luton/luton_devcpu_gcb.h | 16 + > .../include/mach/luton/luton_icpu_cfg-ref.h | 884 ++ > .../include/mach/luton/luton_icpu_cfg.h | 247 + > .../mach-mscc/include/mach/ocelot/ocelot.h| 35 + > .../include/mach/ocelot/ocelot_devcpu_gcb.h | 353 +++ > .../include/mach/ocelot/ocelot_icpu_cfg.h | 884 ++ > arch/mips/mach-mscc/include/mach/tlb.h| 65 ++ > arch/mips/mach-mscc/lowlevel_init.S | 29 + > arch/mips/mach-mscc/lowlevel_init_luton.S | 63 ++ > arch/mips/mach-mscc/reset.c | 37 + > board/mscc/common/board.c | 29 + > board/mscc/luton/Kconfig | 14 + > board/mscc/luton/Makefile | 4 + > board/mscc/luton/luton.c | 14 + > board/mscc/ocelot/Kconfig | 24 + > board/mscc/ocelot/Makefile| 5 + > board/mscc/ocelot/ocelot.c| 38 + > configs/mscc_luton_defconfig | 66 ++ > configs/mscc_ocelot_defconfig | 57 ++ > configs/mscc_ocelot_pcb120_defconfig | 56 ++ > include/configs/vcoreiii.h| 72 ++ > 41 files changed, 4515 insertions(+), 30 deletions(-) > create mode 100644 arch/mips/dts/luton_pcb091.dts > create mode 100644 arch/mips/dts/mscc,luton.dtsi > create mode 100644 arch/mips/dts/mscc,ocelot.dtsi > create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi > create mode 100644 arch/mips/dts/ocelot_pcb120.dts > create mode 100644 arch/mips/dts/ocelot_pcb123.dts > create mode 100644 arch/mips/mach-mscc/Kconfig > create mode 100644 arch/mips/mach-mscc/Makefile > create mode 100644 arch/mips/mach-mscc/cpu.c > create mode 100644 arch/mips/mach-mscc/dram.c > create mode 100644 arch/mips/mach-mscc/include/ioremap.h > create mode 100644 arch/mips/mach-mscc/include/mach/cache.h > create mode 100644 arch/mips/mach-mscc/include/mach/common.h > create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h > create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h > create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h > create mode 100644 > arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg-ref
[U-Boot] [PATCH] DW SPI: Allow to overload the management of the external CS
On some platforms, as the Ocelot ones, when wanting to control the CS
through software, it is not possible to do it through the GPIO
controller. Indeed, this signal is managed through a dedicated range of
registers inside the SoC..
By declaring the external_cs_manage function as weak, it is possible to
manage the CS at platform level and then using the appropriate registers.
Signed-off-by: Gregory CLEMENT
---
drivers/spi/designware_spi.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/designware_spi.c b/drivers/spi/designware_spi.c
index d8b73ea326..fe6e753bff 100644
--- a/drivers/spi/designware_spi.c
+++ b/drivers/spi/designware_spi.c
@@ -334,7 +334,13 @@ static int poll_transfer(struct dw_spi_priv *priv)
return 0;
}
-static void external_cs_manage(struct udevice *dev, bool on)
+/*
+ * We define external_cs_manage function as 'weak' as some targets
+ * (like OCELOT) don't control the external CS pin using a GPIO
+ * controller. These SoCs use specific registers to controll by
+ * software the SPI pins (and especially the CS).
+ */
+__weak void external_cs_manage(struct udevice *dev, bool on)
{
#if defined(CONFIG_DM_GPIO) && !defined(CONFIG_SPL_BUILD)
struct dw_spi_priv *priv = dev_get_priv(dev->parent);
--
2.19.0
___
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[U-Boot] [PATCH] gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi
The VCore III SoCs such as the Luton but also the Ocelot can remap an SPI
flash directly in memory. However, for writing in the flash the
communication has to be done by software.
Each of the signal used for the SPI are exposed in a single register. In
order to be able to use the soft-spi driver, the management of this pin
is done through this simple gpio driver.
Even if the main purpose of this driver is to be used by soft-spi, it can
still be used as a normal gpio driver but with limitation: for example
the first pin can't be used as output.
Signed-off-by: Gregory CLEMENT
---
drivers/gpio/Kconfig | 7 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/gpio-mscc-bitbang-spi.c | 126 +++
3 files changed, 134 insertions(+)
create mode 100644 drivers/gpio/gpio-mscc-bitbang-spi.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 5cd8b34400..947a59cce3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -99,6 +99,13 @@ config LPC32XX_GPIO
help
Support for the LPC32XX GPIO driver.
+config MSCC_BITBANG_SPI_GPIO
+ bool "Microsemi bitbang spi GPIO driver"
+ depends on DM_GPIO && SOC_VCOREIII
+ help
+ Support controlling the GPIO used for SPI bitbang by software. Can
+ be used by the VCoreIII SoCs, but it was mainly useful for Luton.
+
config MSM_GPIO
bool "Qualcomm GPIO driver"
depends on DM_GPIO
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index f186120684..2085dd3cba 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -58,3 +58,4 @@ obj-$(CONFIG_MVEBU_GPIO) += mvebu_gpio.o
obj-$(CONFIG_MSM_GPIO) += msm_gpio.o
obj-$(CONFIG_$(SPL_)PCF8575_GPIO) += pcf8575_gpio.o
obj-$(CONFIG_PM8916_GPIO) += pm8916_gpio.o
+obj-$(CONFIG_MSCC_BITBANG_SPI_GPIO)+= gpio-mscc-bitbang-spi.o
diff --git a/drivers/gpio/gpio-mscc-bitbang-spi.c
b/drivers/gpio/gpio-mscc-bitbang-spi.c
new file mode 100644
index 00..572107d010
--- /dev/null
+++ b/drivers/gpio/gpio-mscc-bitbang-spi.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author:
+ * License: Dual MIT/GPL
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+enum {
+ SDI,
+ CS0,
+ CS1,
+ CS2,
+ CS3,
+ SDO,
+ SCK
+};
+
+int pinmap[] = {0, 5, 6, 7, 8, 10, 12};
+
+#define SW_SPI_CSn_OE 0x1E /* bits 1 to 4 */
+#define SW_SPI_CS0_OE BIT(1)
+#define SW_SPI_SDO_OE BIT(9)
+#define SW_SPI_SCK_OE BIT(11)
+#define SW_PIN_CTRL_MODE BIT(13)
+
+struct mscc_bb_spi_gpio {
+ u32 *regs;
+ u32 cache_val;
+};
+
+static int mscc_bb_spi_gpio_set(struct udevice *dev, unsigned oft, int val)
+{
+ struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
+
+ if (val)
+ gpio->cache_val |= BIT(pinmap[oft]);
+ else
+ gpio->cache_val &= ~BIT(pinmap[oft]);
+
+ writel(gpio->cache_val, gpio->regs);
+
+ return 0;
+}
+
+static int mscc_bb_spi_gpio_direction_output(struct udevice *dev, unsigned oft,
+ int val)
+{
+ if (oft == 0) {
+ pr_err("SW_SPI_DSI can't be used as output\n");
+ return -ENOTSUPP;
+ }
+
+ mscc_bb_spi_gpio_set(dev, oft, val);
+
+ return 0;
+}
+
+static int mscc_bb_spi_gpio_direction_input(struct udevice *dev, unsigned oft)
+{
+ return 0;
+}
+
+static int mscc_bb_spi_gpio_get(struct udevice *dev, unsigned int oft)
+{
+ struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
+ u32 val = readl(gpio->regs);
+
+ return !!(val & BIT(pinmap[oft]));
+}
+
+static const struct dm_gpio_ops mscc_bb_spi_gpio_ops = {
+ .direction_output = mscc_bb_spi_gpio_direction_output,
+ .direction_input= mscc_bb_spi_gpio_direction_input,
+ .set_value = mscc_bb_spi_gpio_set,
+ .get_value = mscc_bb_spi_gpio_get,
+};
+
+static int mscc_bb_spi_gpio_probe(struct udevice *dev)
+{
+ struct mscc_bb_spi_gpio *gpio = dev_get_priv(dev);
+ struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
+ fdt_addr_t addr;
+ fdt_size_t size;
+
+ addr = devfdt_get_addr_size_index(dev, 0, );
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ gpio->regs = ioremap(addr, size);
+
+ uc_priv->bank_name = dev->name;
+ uc_priv->gpio_count = ARRAY_SIZE(pinmap);
+ /*
+* Enable software mode to control the SPI pin, enables the
+* output mode for most of the pin and initialize the cache
+* value in the same time
+*/
+
+ gpio->cache_val = SW_PIN_CTRL_MODE | SW_SPI_SCK_OE | SW_SPI_SDO_OE |
+ SW_SPI_CS0_OE;
+ writel(gpio->c
[U-Boot] [PATCH] pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based)
This driver supports the pin and gpio controller found in the Ocelot and
Luton SoCs.
The driver was inspired from the pinctrl driver in Linux, but was
simplified and was modified to allow supporting an other SoCs (Luton).
For Ocelot and Luton the controller is the same, only the pins to program
differ.
Signed-off-by: Gregory CLEMENT
---
drivers/pinctrl/Kconfig | 1 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/mscc/Kconfig | 22 +++
drivers/pinctrl/mscc/Makefile | 5 +
drivers/pinctrl/mscc/mscc-common.c| 258 ++
drivers/pinctrl/mscc/mscc-common.h| 51 +
drivers/pinctrl/mscc/pinctrl-luton.c | 176 ++
drivers/pinctrl/mscc/pinctrl-ocelot.c | 190 +++
8 files changed, 704 insertions(+)
create mode 100644 drivers/pinctrl/mscc/Kconfig
create mode 100644 drivers/pinctrl/mscc/Makefile
create mode 100644 drivers/pinctrl/mscc/mscc-common.c
create mode 100644 drivers/pinctrl/mscc/mscc-common.h
create mode 100644 drivers/pinctrl/mscc/pinctrl-luton.c
create mode 100644 drivers/pinctrl/mscc/pinctrl-ocelot.c
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index ad0b8daba6..cc82f91579 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -305,6 +305,7 @@ source "drivers/pinctrl/nxp/Kconfig"
source "drivers/pinctrl/renesas/Kconfig"
source "drivers/pinctrl/uniphier/Kconfig"
source "drivers/pinctrl/exynos/Kconfig"
+source "drivers/pinctrl/mscc/Kconfig"
source "drivers/pinctrl/mvebu/Kconfig"
source "drivers/pinctrl/broadcom/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index a3a6c6d163..2461dba293 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PINCTRL_UNIPHIER)+= uniphier/
obj-$(CONFIG_PINCTRL_PIC32)+= pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
+obj-y += mscc/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
obj-$(CONFIG_PINCTRL_STI) += pinctrl-sti.o
diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
new file mode 100644
index 00..cfc6c06076
--- /dev/null
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config PINCTRL_MSCC
+ bool
+
+config PINCTRL_MSCC_OCELOT
+ depends on SOC_OCELOT && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi ocelot family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi ocelot SoCs.
+
+config PINCTRL_MSCC_LUTON
+ depends on SOC_LUTON && PINCTRL_FULL && OF_CONTROL
+ select PINCTRL_MSCC
+ default y
+ bool "Microsemi luton family pin control driver"
+ help
+ Support pin multiplexing and pin configuration control on
+ Microsemi luton SoCs.
diff --git a/drivers/pinctrl/mscc/Makefile b/drivers/pinctrl/mscc/Makefile
new file mode 100644
index 00..941f418ff9
--- /dev/null
+++ b/drivers/pinctrl/mscc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_PINCTRL_MSCC) += mscc-common.o
+obj-$(CONFIG_PINCTRL_MSCC_OCELOT) += pinctrl-ocelot.o
+obj-$(CONFIG_PINCTRL_MSCC_LUTON) += pinctrl-luton.o
diff --git a/drivers/pinctrl/mscc/mscc-common.c
b/drivers/pinctrl/mscc/mscc-common.c
new file mode 100644
index 00..84b6844daa
--- /dev/null
+++ b/drivers/pinctrl/mscc/mscc-common.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Microsemi SoCs pinctrl driver
+ *
+ * Author:
+ * License: Dual MIT/GPL
+ * Copyright (c) 2017 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "mscc-common.h"
+
+#define clrbits(addr, clear) writel(readl(addr) & ~(clear), (addr))
+
+#define setbits(addr, set) writel(readl(addr) | (set), (addr))
+
+#define MSCC_GPIO_OUT_SET 0x0
+#define MSCC_GPIO_OUT_CLR 0x4
+#define MSCC_GPIO_OUT 0x8
+#define MSCC_GPIO_IN 0xc
+#define MSCC_GPIO_OE 0x10
+#define MSCC_GPIO_INTR 0x14
+#define MSCC_GPIO_INTR_ENA 0x18
+#define MSCC_GPIO_INTR_IDENT 0x1c
+#define MSCC_GPIO_ALT0 0x20
+#define MSCC_GPIO_ALT1 0x24
+
+static int mscc_get_functions_count(struct udevice *dev)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->num_func;
+}
+
+static const char *mscc_get_function_name(struct udevice *dev,
+ unsigned int function)
+{
+ struct mscc_pinctrl *info = dev_get_priv(dev);
+
+ return info->function_
[U-Boot] [PATCH 5/6] MSCC: add configuration for Ocelot and Luton based boards
Add common configuration header for the VCore III SoCs (currently Ocelot and Luton), but also the defconfig for the evaluation boards of these SoCs. Signed-off-by: Gregory CLEMENT --- configs/mscc_luton_defconfig | 66 + configs/mscc_ocelot_defconfig| 57 ++ configs/mscc_ocelot_pcb120_defconfig | 56 ++ include/configs/vcoreiii.h | 72 4 files changed, 251 insertions(+) create mode 100644 configs/mscc_luton_defconfig create mode 100644 configs/mscc_ocelot_defconfig create mode 100644 configs/mscc_ocelot_pcb120_defconfig create mode 100644 include/configs/vcoreiii.h diff --git a/configs/mscc_luton_defconfig b/configs/mscc_luton_defconfig new file mode 100644 index 00..47fe12b6ee --- /dev/null +++ b/configs/mscc_luton_defconfig @@ -0,0 +1,66 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x4000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0x7010 +CONFIG_DEBUG_UART_CLOCK=20833 +CONFIG_ARCH_MSCC=y +CONFIG_TARGET_LUTON_PCB091=y +CONFIG_DDRTYPE_MT47H128M8HQ=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="luton_pcb091" +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_LOGLEVEL=7 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_PROMPT="pcb091 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),6m@1m(linux)" +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_SOFT_SPI=y +CONFIG_LZMA=y +CONFIG_XZ=y diff --git a/configs/mscc_ocelot_defconfig b/configs/mscc_ocelot_defconfig new file mode 100644 index 00..eb0566189a --- /dev/null +++ b/configs/mscc_ocelot_defconfig @@ -0,0 +1,57 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x4000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_MSCC=y +CONFIG_TARGET_OCELOT_PCB123=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb123" +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_LOGLEVEL=7 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_PROMPT="pcb123 # " +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MD5SUM=y +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_DHCP=y +# CONFIG_NET_TFTP_VARS is not set +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_MTDPARTS=y +CONFIG_MTDIDS_DEFAULT="nor0=spi_flash" +CONFIG_MTDPARTS_DEFAULT="mtdparts=spi_flash:512k(UBoot),256k(Env),256k(conf),15m(linux),15m(linux.bk)" +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_EMBED=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_CLK=y +CONFIG_DM_GPIO=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCONF=y +CONFIG_DM_SERIAL=y +CONFIG_SYS_NS16550=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_LZMA=y diff --git a/configs/mscc_ocelot_pcb120_defconfig b/configs/mscc_ocelot_pcb120_defconfig new file mode 100644 index 00..40cdec45f1 --- /dev/null +++ b/configs/mscc_ocelot_pcb120_defconfig @@ -0,0 +1,56 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x4000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ARCH_MSCC=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_DEFAULT_DEVICE_TREE="ocelot_pcb120" +CONFIG_FIT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200" +CONFIG_LOGLEVEL=7 +CONFIG_DISPLAY_CPUINFO=y +CONFIG_SYS_PROMPT="
[U-Boot] [PATCH 6/6] MIPS: bootm: Add support for Vcore III linux kernel
The kernels built for the Vcore III linux kernel have different
expectation in the way the data were passed.
Unlike with yamon, the command line is expected to be a single string
passed in argv[1]. An other expectation is that the arguments are located
in the cached address space.
However, like yamon, they expect that rd_start and rd_size was passed by
the bootloader in the command line of the kernel, and besides that it
also wait for the root=/dev/ram0.
Signed-off-by: Gregory CLEMENT
---
arch/mips/lib/bootm.c | 62 +--
1 file changed, 42 insertions(+), 20 deletions(-)
diff --git a/arch/mips/lib/bootm.c b/arch/mips/lib/bootm.c
index deca5189e3..417f5ce452 100644
--- a/arch/mips/lib/bootm.c
+++ b/arch/mips/lib/bootm.c
@@ -44,22 +44,38 @@ void arch_lmb_reserve(struct lmb *lmb)
lmb_reserve(lmb, sp, gd->ram_top - sp);
}
-static void linux_cmdline_init(void)
+static void linux_cmdline_init(int vcoreiii)
{
+ if (!vcoreiii) {
+ linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ } else {
+ /*
+* Vcore III linux kernels expect arguments in the cached
+* address space. They also expect the command line being a
+* single string in the first argument
+*/
+ linux_argv = (char **)(gd->bd->bi_boot_params);
+ linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
+ linux_argv[1] = linux_argp;
+ }
linux_argc = 1;
- linux_argv = (char **)UNCACHED_SDRAM(gd->bd->bi_boot_params);
linux_argv[0] = 0;
- linux_argp = (char *)(linux_argv + LINUX_MAX_ARGS);
}
-static void linux_cmdline_set(const char *value, size_t len)
+static void linux_cmdline_set(const char *value, size_t len, int vcoreiii)
{
- linux_argv[linux_argc] = linux_argp;
memcpy(linux_argp, value, len);
- linux_argp[len] = 0;
-
+ if (!vcoreiii) {
+ linux_argv[linux_argc] = linux_argp;
+ linux_argp[len] = 0;
+ linux_argc++;
+ } else {
+ linux_argp[len] = ' ';
+ linux_argp[len + 1] = 0;
+ linux_argc = 2;
+ }
linux_argp += len + 1;
- linux_argc++;
}
static void linux_cmdline_dump(void)
@@ -73,12 +89,10 @@ static void linux_cmdline_dump(void)
debug(" arg %03d: %s\n", i, linux_argv[i]);
}
-static void linux_cmdline_legacy(bootm_headers_t *images)
+static void linux_cmdline_legacy(bootm_headers_t *images, int vcoreiii)
{
const char *bootargs, *next, *quote;
-
- linux_cmdline_init();
-
+ linux_cmdline_init(vcoreiii);
bootargs = env_get("bootargs");
if (!bootargs)
return;
@@ -104,7 +118,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
if (!next)
next = bootargs + strlen(bootargs);
- linux_cmdline_set(bootargs, next - bootargs);
+ linux_cmdline_set(bootargs, next - bootargs, vcoreiii);
if (*next)
next++;
@@ -113,7 +127,7 @@ static void linux_cmdline_legacy(bootm_headers_t *images)
}
}
-static void linux_cmdline_append(bootm_headers_t *images)
+static void linux_cmdline_append(bootm_headers_t *images, int vcoreiii)
{
char buf[24];
ulong mem, rd_start, rd_size;
@@ -121,7 +135,7 @@ static void linux_cmdline_append(bootm_headers_t *images)
/* append mem */
mem = gd->ram_size >> 20;
sprintf(buf, "mem=%luM", mem);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), vcoreiii);
/* append rd_start and rd_size */
rd_start = images->initrd_start;
@@ -129,9 +143,13 @@ static void linux_cmdline_append(bootm_headers_t *images)
if (rd_size) {
sprintf(buf, "rd_start=0x%08lX", rd_start);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), vcoreiii);
sprintf(buf, "rd_size=0x%lX", rd_size);
- linux_cmdline_set(buf, strlen(buf));
+ linux_cmdline_set(buf, strlen(buf), vcoreiii);
+ if (vcoreiii) {
+ sprintf(buf, "root=/dev/ram0");
+ linux_cmdline_set(buf, strlen(buf), vcoreiii);
+ }
}
}
@@ -276,11 +294,15 @@ static void boot_prep_linux(bootm_headers_t *images)
boot_reloc_fdt(images);
boot_setup_fdt(images);
} else {
- if (CONFIG_IS_ENABLED(MIPS_BOOT_CMDLINE_LEGACY)) {
- linux_cmdline_legacy(images);
+ if (CONFIG_IS_ENABLED(SOC_VCOREIII)) {
+
[U-Boot] [PATCH 4/6] MSCC: add device tree for Ocelot and Luton (boards and SoCs)
Adding device tree for Ocelot SoC (extract from Linux) and the 2
evaluation boards using this SoC: PCB120 and PCB132.
Adding device tree for Luton SoC (not yet in Linux) and the evaluation
boards using this SoC: PCB91.
Signed-off-by: Gregory CLEMENT
---
arch/mips/dts/luton_pcb091.dts | 36
arch/mips/dts/mscc,luton.dtsi | 87 +++
arch/mips/dts/mscc,ocelot.dtsi | 132 +
arch/mips/dts/mscc,ocelot_pcb.dtsi | 37
arch/mips/dts/ocelot_pcb120.dts| 12 +++
arch/mips/dts/ocelot_pcb123.dts| 12 +++
6 files changed, 316 insertions(+)
create mode 100644 arch/mips/dts/luton_pcb091.dts
create mode 100644 arch/mips/dts/mscc,luton.dtsi
create mode 100644 arch/mips/dts/mscc,ocelot.dtsi
create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi
create mode 100644 arch/mips/dts/ocelot_pcb120.dts
create mode 100644 arch/mips/dts/ocelot_pcb123.dts
diff --git a/arch/mips/dts/luton_pcb091.dts b/arch/mips/dts/luton_pcb091.dts
new file mode 100644
index 00..b5e0df8d04
--- /dev/null
+++ b/arch/mips/dts/luton_pcb091.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+/dts-v1/;
+#include "mscc,luton.dtsi"
+
+/ {
+ model = "Luton PCB091 Reference Board";
+ compatible = "mscc,luton-pcb091", "mscc,luton";
+
+ aliases {
+ serial0 =
+ spi0 =
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ spi-flash@0 {
+ compatible = "spi-flash";
+spi-max-frequency = <1800>; /* input clock */
+reg = <0>; /* CS0 */
+ };
+};
+
diff --git a/arch/mips/dts/mscc,luton.dtsi b/arch/mips/dts/mscc,luton.dtsi
new file mode 100644
index 00..6a4ad2a5be
--- /dev/null
+++ b/arch/mips/dts/mscc,luton.dtsi
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mscc,luton";
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "mips,mips24KEc";
+ device_type = "cpu";
+ reg = <0>;
+ };
+ };
+
+ aliases {
+ serial0 =
+ };
+
+ ahb_clk: ahb-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <20833>;
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x6000 0x1020>;
+
+ uart0: serial@1010 {
+ pinctrl-0 = <_pins>;
+ pinctrl-names = "default";
+
+ compatible = "ns16550a";
+ reg = <0x1010 0x20>;
+ clocks = <_clk>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+
+ status = "disabled";
+ };
+
+ gpio: pinctrl@70068 {
+ compatible = "mscc,luton-pinctrl";
+ reg = <0x70068 0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = < 0 0 32>;
+
+ uart_pins: uart-pins {
+ pins = "GPIO_30", "GPIO_31";
+ function = "uart";
+ };
+
+ };
+
+ gpio_spi_bitbang: gpio@1064 {
+ compatible = "mscc,spi-bitbang-gpio";
+ reg = <0x1064 0x4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ };
+
+ spi0: spi-bitbang {
+ compatible = "spi-gpio";
+ status = "okay";
+ gpio-sck = <_spi_bitbang 6 0>;
+ gpio-miso = <_spi_bitbang 0 0>;
+ gpio-mosi = <_spi_bitbang 5 0>;
+ cs-gpios = <_spi_bitbang 1 0>;
+ num-chipselects = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
[U-Boot] [PATCH 3/6] MSCC: add board support for the VCoreIII based evaluation boards
Adding the support for 3 boards sharing common code:
- PCB120 and PCB 123 for Ocelot chip
- PCB 91 for Luton chip
Signed-off-by: Gregory CLEMENT
---
board/mscc/common/board.c | 29 +
board/mscc/luton/Kconfig | 14 ++
board/mscc/luton/Makefile | 4
board/mscc/luton/luton.c | 14 ++
board/mscc/ocelot/Kconfig | 24
board/mscc/ocelot/Makefile | 5 +
board/mscc/ocelot/ocelot.c | 38 ++
7 files changed, 128 insertions(+)
create mode 100644 board/mscc/common/board.c
create mode 100644 board/mscc/luton/Kconfig
create mode 100644 board/mscc/luton/Makefile
create mode 100644 board/mscc/luton/luton.c
create mode 100644 board/mscc/ocelot/Kconfig
create mode 100644 board/mscc/ocelot/Makefile
create mode 100644 board/mscc/ocelot/ocelot.c
diff --git a/board/mscc/common/board.c b/board/mscc/common/board.c
new file mode 100644
index 00..86e7bf3353
--- /dev/null
+++ b/board/mscc/common/board.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_r(void)
+{
+ u32 ctrl;
+
+ /* Prepare SPI controller to be used in master mode */
+ writel(0, REG_CFG(ICPU_SW_MODE));
+ ctrl = readl(REG_CFG(ICPU_GENERAL_CTRL));
+
+ writel((ctrl & ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M) |
+ ICPU_GENERAL_CTRL_IF_SI_OWNER(2),
+ REG_CFG(ICPU_GENERAL_CTRL));
+
+ /* Address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE;
+ return 0;
+}
diff --git a/board/mscc/luton/Kconfig b/board/mscc/luton/Kconfig
new file mode 100644
index 00..e1199808d5
--- /dev/null
+++ b/board/mscc/luton/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+if SOC_LUTON
+
+config SYS_VENDOR
+ default "mscc"
+
+config SYS_BOARD
+ default "luton"
+
+config SYS_CONFIG_NAME
+ default "luton"
+
+endif
diff --git a/board/mscc/luton/Makefile b/board/mscc/luton/Makefile
new file mode 100644
index 00..98bc47ba82
--- /dev/null
+++ b/board/mscc/luton/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_LUTON):= luton.o
+obj-y += ../common/board.o
diff --git a/board/mscc/luton/luton.c b/board/mscc/luton/luton.c
new file mode 100644
index 00..8c31bbb12a
--- /dev/null
+++ b/board/mscc/luton/luton.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+
+void board_debug_uart_init(void)
+{
+ /* too early for the pinctrl driver, so configure the UART pins here */
+ writel(BIT(30)|BIT(31), REG_GCB((0x68+8*4)));
+ writel(~(BIT(30)|BIT(31)), REG_GCB((0x68+9*4)));
+}
diff --git a/board/mscc/ocelot/Kconfig b/board/mscc/ocelot/Kconfig
new file mode 100644
index 00..0804f5081d
--- /dev/null
+++ b/board/mscc/ocelot/Kconfig
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+config SYS_VENDOR
+ default "mscc"
+
+if SOC_OCELOT
+
+config SYS_BOARD
+ default "ocelot"
+
+config SYS_CONFIG_NAME
+ default "ocelot"
+
+endif
+
+if SOC_LUTON
+
+config SYS_BOARD
+ default "luton"
+
+config SYS_CONFIG_NAME
+ default "luton"
+
+endif
diff --git a/board/mscc/ocelot/Makefile b/board/mscc/ocelot/Makefile
new file mode 100644
index 00..f6a665ca83
--- /dev/null
+++ b/board/mscc/ocelot/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+obj-$(CONFIG_SOC_OCELOT) := ocelot.o
+obj-y += ../common/board.o
+
diff --git a/board/mscc/ocelot/ocelot.c b/board/mscc/ocelot/ocelot.c
new file mode 100644
index 00..971fa93d07
--- /dev/null
+++ b/board/mscc/ocelot/ocelot.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2018 Microsemi Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void external_cs_manage(struct udevice *dev, bool enable)
+{
+ u32 cs = spi_chip_select(dev);
+/* IF_SI0_OWNER, select the owner of the SI interface
+ * Encoding: 0: SI Slave
+ * 1: SI Boot Master
+ * 2: SI Master Controller
+ */
+if (!enable) {
+writel(ICPU_SW_MODE_SW_PIN_CTRL_MODE |
+ ICPU_SW_MODE_SW_SPI_CS(BIT(cs)),
+ REG_CFG(ICPU_SW_MODE));
+writel((readl(REG_CFG(ICPU_GENERAL_CTRL))
+ & ~ICPU_GENERAL_CTRL_IF_SI_OWNER_M) |
+ ICPU_GENERAL_CTRL_IF_SI_OWNER(2),
+ REG_CFG(ICPU_GENERAL_CTRL));
+} else {
+
[U-Boot] [PATCH 1/6] MIPS: move create_tlb() in an proper header: mipsregs.h
Export create_tlb() as an inline function in mipsregs.h. It allows to
remove the declaration of the function from the board files.
Then it will allow also to use this function very early in the boot when
the stack is not usable.
Signed-off-by: Gregory CLEMENT
---
arch/mips/cpu/cpu.c | 10 --
arch/mips/include/asm/mipsregs.h | 11 +++
2 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/mips/cpu/cpu.c b/arch/mips/cpu/cpu.c
index 5c56ab0289..a403ff729b 100644
--- a/arch/mips/cpu/cpu.c
+++ b/arch/mips/cpu/cpu.c
@@ -28,16 +28,6 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
}
#endif
-void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
-{
- write_c0_entrylo0(low0);
- write_c0_pagemask(pagemask);
- write_c0_entrylo1(low1);
- write_c0_entryhi(hi);
- write_c0_index(index);
- tlb_write_indexed();
-}
-
int arch_cpu_init(void)
{
mips_cache_probe();
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 48fa1f1f7f..930562ebb2 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -2005,6 +2005,17 @@ static inline unsigned int get_ebase_cpunum(void)
return read_c0_ebase() & 0x3ff;
}
+static inline void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0,
+u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
+
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_MIPSREGS_H */
--
2.19.0
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[U-Boot] [PATCH 0/6] Add support for VCore III SoCs found in Microsemi switches
Hello, This series add the support of 2 SoCs: Ocelot and Luton from Microsemi. Both of them belongs to the same family Vcore III. We found them on various advanced switches product. The support for Ocelot already have been submit to Linux, but not yet the Luton support. Besides this series 3 others patches are needed but they are driver related: DW SPI: Allow to overload the management of the external CS gpio: mscc-bitbang-spi: Add a simple gpio driver for bitbgang spi pinctrl: mscc: Add gpio and pinctrl driver for MSCC MIPS SoCs (VcoreIII based) They will be submitted separately. Thanks, Gregory Gregory CLEMENT (6): MIPS: move create_tlb() in an proper header: mipsregs.h MSCC: add support for VCoreIII SoCs MSCC: add board support for the VCoreIII based evaluation boards MSCC: add device tree for Ocelot and Luton (boards and SoCs) MSCC: add configuration for Ocelot and Luton based boards MIPS: bootm: Add support for Vcore III linux kernel arch/mips/Kconfig | 6 + arch/mips/Makefile| 1 + arch/mips/cpu/cpu.c | 10 - arch/mips/dts/luton_pcb091.dts| 36 + arch/mips/dts/mscc,luton.dtsi | 87 ++ arch/mips/dts/mscc,ocelot.dtsi| 132 +++ arch/mips/dts/mscc,ocelot_pcb.dtsi| 37 + arch/mips/dts/ocelot_pcb120.dts | 12 + arch/mips/dts/ocelot_pcb123.dts | 12 + arch/mips/include/asm/mipsregs.h | 11 + arch/mips/lib/bootm.c | 62 +- arch/mips/mach-mscc/Kconfig | 101 ++ arch/mips/mach-mscc/Makefile | 6 + arch/mips/mach-mscc/cpu.c | 72 ++ arch/mips/mach-mscc/dram.c| 62 ++ arch/mips/mach-mscc/include/ioremap.h | 49 + arch/mips/mach-mscc/include/mach/cache.h | 36 + arch/mips/mach-mscc/include/mach/common.h | 31 + arch/mips/mach-mscc/include/mach/ddr.h| 753 +++ .../mips/mach-mscc/include/mach/luton/luton.h | 37 + .../include/mach/luton/luton_devcpu_gcb.h | 16 + .../include/mach/luton/luton_icpu_cfg-ref.h | 884 ++ .../include/mach/luton/luton_icpu_cfg.h | 247 + .../mach-mscc/include/mach/ocelot/ocelot.h| 35 + .../include/mach/ocelot/ocelot_devcpu_gcb.h | 353 +++ .../include/mach/ocelot/ocelot_icpu_cfg.h | 884 ++ arch/mips/mach-mscc/include/mach/tlb.h| 65 ++ arch/mips/mach-mscc/lowlevel_init.S | 29 + arch/mips/mach-mscc/lowlevel_init_luton.S | 63 ++ arch/mips/mach-mscc/reset.c | 37 + board/mscc/common/board.c | 29 + board/mscc/luton/Kconfig | 14 + board/mscc/luton/Makefile | 4 + board/mscc/luton/luton.c | 14 + board/mscc/ocelot/Kconfig | 24 + board/mscc/ocelot/Makefile| 5 + board/mscc/ocelot/ocelot.c| 38 + configs/mscc_luton_defconfig | 66 ++ configs/mscc_ocelot_defconfig | 57 ++ configs/mscc_ocelot_pcb120_defconfig | 56 ++ include/configs/vcoreiii.h| 72 ++ 41 files changed, 4515 insertions(+), 30 deletions(-) create mode 100644 arch/mips/dts/luton_pcb091.dts create mode 100644 arch/mips/dts/mscc,luton.dtsi create mode 100644 arch/mips/dts/mscc,ocelot.dtsi create mode 100644 arch/mips/dts/mscc,ocelot_pcb.dtsi create mode 100644 arch/mips/dts/ocelot_pcb120.dts create mode 100644 arch/mips/dts/ocelot_pcb123.dts create mode 100644 arch/mips/mach-mscc/Kconfig create mode 100644 arch/mips/mach-mscc/Makefile create mode 100644 arch/mips/mach-mscc/cpu.c create mode 100644 arch/mips/mach-mscc/dram.c create mode 100644 arch/mips/mach-mscc/include/ioremap.h create mode 100644 arch/mips/mach-mscc/include/mach/cache.h create mode 100644 arch/mips/mach-mscc/include/mach/common.h create mode 100644 arch/mips/mach-mscc/include/mach/ddr.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg-ref.h create mode 100644 arch/mips/mach-mscc/include/mach/luton/luton_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_devcpu_gcb.h create mode 100644 arch/mips/mach-mscc/include/mach/ocelot/ocelot_icpu_cfg.h create mode 100644 arch/mips/mach-mscc/include/mach/tlb.h create mode 100644 arch/mips/mach-mscc/lowlevel_init.S create mode 100644 arch/mips/mach-mscc/lowlevel_init_luton.S create mode 100644 arch/mips/mach-mscc/reset.c create mode 100644 board/mscc/common/board.c create mode 100644 board/mscc/luton/Kconfig create mode 100644 board/mscc/luton/Makefile create
Re: [U-Boot] [PATCH] Convert CONFIG_USB_ETHER et al to Kconfig
Hi Adam, On mer., juil. 26 2017, Adam Ford <aford...@gmail.com> wrote: > This converts the following to Kconfig: >CONFIG_USB_ETHER >CONFIG_USB_ETHER_RNDIS > > Signed-off-by: Adam Ford <aford...@gmail.com> For the VInCo platform Acked-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> Thanks, Gregory > > diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig > index 09e028f..a25d24f 100644 > --- a/configs/am335x_baltos_defconfig > +++ b/configs/am335x_baltos_defconfig > @@ -57,6 +57,7 @@ CONFIG_USB_MUSB_HOST=y > CONFIG_USB_MUSB_GADGET=y > CONFIG_USB_STORAGE=y > CONFIG_USB_GADGET=y > +CONFIG_USB_ETHER=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_G_DNL_MANUFACTURER="Texas Instruments" > CONFIG_G_DNL_VENDOR_NUM=0x0403 > diff --git a/configs/am335x_boneblack_defconfig > b/configs/am335x_boneblack_defconfig > index 516ad70..1e360fd 100644 > --- a/configs/am335x_boneblack_defconfig > +++ b/configs/am335x_boneblack_defconfig > @@ -37,6 +37,7 @@ CONFIG_USB_MUSB_HOST=y > CONFIG_USB_MUSB_GADGET=y > CONFIG_USB_STORAGE=y > CONFIG_USB_GADGET=y > +CONFIG_USB_ETHER=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_G_DNL_MANUFACTURER="Texas Instruments" > CONFIG_G_DNL_VENDOR_NUM=0x0451 > diff --git a/configs/am335x_boneblack_vboot_defconfig > b/configs/am335x_boneblack_vboot_defconfig > index 33da1fa..3c53891 100644 > --- a/configs/am335x_boneblack_vboot_defconfig > +++ b/configs/am335x_boneblack_vboot_defconfig > @@ -46,6 +46,7 @@ CONFIG_USB_MUSB_HOST=y > CONFIG_USB_MUSB_GADGET=y > CONFIG_USB_STORAGE=y > CONFIG_USB_GADGET=y > +CONFIG_USB_ETHER=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_G_DNL_MANUFACTURER="Texas Instruments" > CONFIG_G_DNL_VENDOR_NUM=0x0451 > diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig > index 4ea5617..6e246a0 100644 > --- a/configs/am335x_evm_defconfig > +++ b/configs/am335x_evm_defconfig > @@ -47,6 +47,7 @@ CONFIG_USB_MUSB_GADGET=y > CONFIG_USB_MUSB_TI=y > CONFIG_USB_STORAGE=y > CONFIG_USB_GADGET=y > +CONFIG_USB_ETHER=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_G_DNL_MANUFACTURER="Texas Instruments" > CONFIG_G_DNL_VENDOR_NUM=0x0451 > diff --git a/configs/am335x_evm_nor_defconfig > b/configs/am335x_evm_nor_defconfig > index 49040a6..2220311 100644 > --- a/configs/am335x_evm_nor_defconfig > +++ b/configs/am335x_evm_nor_defconfig > @@ -46,6 +46,7 @@ CONFIG_USB_MUSB_HOST=y > CONFIG_USB_MUSB_GADGET=y > CONFIG_USB_STORAGE=y > CONFIG_USB_GADGET=y > +CONFIG_USB_ETHER=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_G_DNL_MANUFACTURER="Texas Instruments" > CONFIG_G_DNL_VENDOR_NUM=0x0451 > diff --git a/configs/am335x_evm_norboot_defconfig > b/configs/am335x_evm_norboot_defconfig > index f121e2f..2135d60 100644 > --- a/configs/am335x_evm_norboot_defconfig > +++ b/configs/am335x_evm_norboot_defconfig > @@ -30,6 +30,7 @@ CONFIG_USB_MUSB_HOST=y > CONFIG_USB_MUSB_GADGET=y > CONFIG_USB_STORAGE=y > CONFIG_USB_GADGET=y > +CONFIG_USB_ETHER=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_G_DNL_MANUFACTURER="Texas Instruments" > CONFIG_G_DNL_VENDOR_NUM=0x0451 > diff --git a/configs/am335x_evm_spiboot_defconfig > b/configs/am335x_evm_spiboot_defconfig > index 5cbfa8e..2f736d5 100644 > --- a/configs/am335x_evm_spiboot_defconfig > +++ b/configs/am335x_evm_spiboot_defconfig > @@ -35,6 +35,7 @@ CONFIG_USB_MUSB_HOST=y > CONFIG_USB_MUSB_GADGET=y > CONFIG_USB_STORAGE=y > CONFIG_USB_GADGET=y > +CONFIG_USB_ETHER=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_G_DNL_MANUFACTURER="Texas Instruments" > CONFIG_G_DNL_VENDOR_NUM=0x0451 > diff --git a/configs/am335x_evm_usbspl_defconfig > b/configs/am335x_evm_usbspl_defconfig > index 51d1042..cdf398a 100644 > --- a/configs/am335x_evm_usbspl_defconfig > +++ b/configs/am335x_evm_usbspl_defconfig > @@ -38,6 +38,7 @@ CONFIG_USB_MUSB_HOST=y > CONFIG_USB_MUSB_GADGET=y > CONFIG_USB_STORAGE=y > CONFIG_USB_GADGET=y > +CONFIG_USB_ETHER=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_G_DNL_MANUFACTURER="Texas Instruments" > CONFIG_G_DNL_VENDOR_NUM=0x0451 > diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig > index 2b1acb7..979af8b 100644 > --- a/configs/am335x_hs_evm_defconfig > +++ b/configs/am335x_hs_evm_defconfig > @@ -49,6 +49,7 @@ CONFIG_USB_MUSB_GADGET=y > CONFIG_USB_MUSB_TI=y > CONFIG_USB_STORAGE=y > CONFIG_USB_GADGET=y > +CONFIG_USB_ETHER=y > CONFIG_USB_GADGET_DOWNLOAD=y > CONFIG_G_DNL_MANUFACTURER="Texas Instruments" > CONFIG_G_DNL_VENDOR_NUM=0x0451 > diff --git a/configs/draco_defconfig b/configs/dra
Re: [U-Boot] [U-Boot,v3] ARM: Add Support for the VInCo platform
Hi Andreas, On jeu., févr. 18 2016, Andreas Bießmann <andreas.de...@googlemail.com> wrote: > Dear Gregory CLEMENT, > > Gregory CLEMENT <gregory.clem...@free-electrons.com> writes: >>The Versatile Industrial Communication platform is a community oriented >>board from Landis + Gyr. It comes with: >>- an RS-485 port >>- 2 Ethernet ports >>- a wireless M-BUS >>- a 4G modem >>- a 4MB SPI flash >>- a 4GB eMMC >> >>Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> >>Acked-by: Nicolas Ferre <nicolas.fe...@atmel.com> >>[rebase on current TOT] >>Signed-off-by: Andreas Bießmann <andreas.de...@googlemail.com> >>--- >> arch/arm/mach-at91/Kconfig | 6 ++ >> board/l+g/vinco/Kconfig| 12 +++ >> board/l+g/vinco/Makefile | 1 + >> board/l+g/vinco/vinco.c| 212 >> + >> configs/vinco_defconfig| 13 +++ >> include/configs/vinco.h| 168 +++ >> 6 files changed, 412 insertions(+) >> create mode 100644 board/l+g/vinco/Kconfig >> create mode 100644 board/l+g/vinco/Makefile >> create mode 100644 board/l+g/vinco/vinco.c >> create mode 100644 configs/vinco_defconfig >> create mode 100644 include/configs/vinco.h > > applied to u-boot-atmel/master, thanks! > > I had to rebase and remove an empty newline at EOF > in vinco.h. Thanks! Gregory > > Best regards, > Andreas Bießmann -- Gregory Clement, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3] ARM: Add Support for the VInCo platform
Hi Andreas, On jeu., janv. 21 2016, "Andreas Bießmann" <andreas.de...@googlemail.com> wrote: > Hi Gregory, > > On 21.01.2016 12:08, Gregory CLEMENT wrote: >> Hello all, >> >> On mer., déc. 16 2015, Gregory CLEMENT <gregory.clem...@free-electrons.com> >> wrote: >> >>> The Versatile Industrial Communication platform is a community oriented >>> board from Landis + Gyr. It comes with: >>> - an RS-485 port >>> - 2 Ethernet ports >>> - a wireless M-BUS >>> - a 4G modem >>> - a 4MB SPI flash >>> - a 4GB eMMC >>> >>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com> >>> Acked-by: Nicolas Ferre <nicolas.fe...@atmel.com> >> >> I sent this patch one month ago and it seems that it didn't get applied. > > I'm aware of it. Since it was way after merge window close for 2016.01 > it would not have been applied for this release. > >> What is the status of this patch? > > I'll review and eventually apply it until end of this Weekend. > >> Do you have any remark about it? > > Not yet ... > > Excuse me for the long waiting times for atmel patches. My list has some > unreplied patches back from end of November 2015. I'm looking forward to > improve this in future. No problem and thanks for the news :) Gregory > > Andreas > >> >> Thanks, >> >> Gregory >> >>> --- >>> Hi again, >>> >>> Some of my fixes were not commit in my previous version. >>> >>> This version should be the correct one, I also added the acked-by from >>> Nicolas. >>> >>> Sorry for not having seen it before. >>> >>> Thanks, >>> >>> Gregory >>> >>> >>> arch/arm/mach-at91/Kconfig | 6 ++ >>> board/l+g/vinco/Kconfig| 12 +++ >>> board/l+g/vinco/Makefile | 1 + >>> board/l+g/vinco/vinco.c| 212 >>> + >>> configs/vinco_defconfig| 13 +++ >>> include/configs/vinco.h| 169 >>> 6 files changed, 413 insertions(+) >>> create mode 100644 board/l+g/vinco/Kconfig >>> create mode 100644 board/l+g/vinco/Makefile >>> create mode 100644 board/l+g/vinco/vinco.c >>> create mode 100644 configs/vinco_defconfig >>> create mode 100644 include/configs/vinco.h >>> >>> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig >>> index c333647..3dfbb5f 100644 >>> --- a/arch/arm/mach-at91/Kconfig >>> +++ b/arch/arm/mach-at91/Kconfig >>> @@ -114,6 +114,11 @@ config TARGET_SMARTWEB >>> select CPU_ARM926EJS >>> select SUPPORT_SPL >>> >>> +config TARGET_VINCO >>> + bool "Support VINCO" >>> + select CPU_V7 >>> + select SUPPORT_SPL >>> + >>> endchoice >>> >>> config SYS_SOC >>> @@ -136,6 +141,7 @@ source "board/bluewater/snapper9260/Kconfig" >>> source "board/calao/usb_a9263/Kconfig" >>> source "board/egnite/ethernut5/Kconfig" >>> source "board/esd/meesc/Kconfig" >>> +source "board/l+g/vinco/Kconfig" >>> source "board/mini-box/picosam9g45/Kconfig" >>> source "board/ronetix/pm9261/Kconfig" >>> source "board/ronetix/pm9263/Kconfig" >>> diff --git a/board/l+g/vinco/Kconfig b/board/l+g/vinco/Kconfig >>> new file mode 100644 >>> index 000..229b5ea >>> --- /dev/null >>> +++ b/board/l+g/vinco/Kconfig >>> @@ -0,0 +1,12 @@ >>> +if TARGET_VINCO >>> + >>> +config SYS_BOARD >>> + default "vinco" >>> + >>> +config SYS_VENDOR >>> + default "l+g" >>> + >>> +config SYS_CONFIG_NAME >>> + default "vinco" >>> + >>> +endif >>> diff --git a/board/l+g/vinco/Makefile b/board/l+g/vinco/Makefile >>> new file mode 100644 >>> index 000..a2b8a2b >>> --- /dev/null >>> +++ b/board/l+g/vinco/Makefile >>> @@ -0,0 +1 @@ >>> +obj-y += vinco.o >>> diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c >>> new file mode 100644 >>> index 000..3d7af09 >>> --- /dev/null >>> +++ b/board/l+g/vinco/vinco.c >>> @@ -0,0 +1,212 @@ >>> +/* >>> + * Board file for
Re: [U-Boot] [PATCH v3] ARM: Add Support for the VInCo platform
Hello all,
On mer., déc. 16 2015, Gregory CLEMENT <gregory.clem...@free-electrons.com>
wrote:
> The Versatile Industrial Communication platform is a community oriented
> board from Landis + Gyr. It comes with:
> - an RS-485 port
> - 2 Ethernet ports
> - a wireless M-BUS
> - a 4G modem
> - a 4MB SPI flash
> - a 4GB eMMC
>
> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> Acked-by: Nicolas Ferre <nicolas.fe...@atmel.com>
I sent this patch one month ago and it seems that it didn't get applied.
What is the status of this patch?
Do you have any remark about it?
Thanks,
Gregory
> ---
> Hi again,
>
> Some of my fixes were not commit in my previous version.
>
> This version should be the correct one, I also added the acked-by from
> Nicolas.
>
> Sorry for not having seen it before.
>
> Thanks,
>
> Gregory
>
>
> arch/arm/mach-at91/Kconfig | 6 ++
> board/l+g/vinco/Kconfig| 12 +++
> board/l+g/vinco/Makefile | 1 +
> board/l+g/vinco/vinco.c| 212
> +
> configs/vinco_defconfig| 13 +++
> include/configs/vinco.h| 169
> 6 files changed, 413 insertions(+)
> create mode 100644 board/l+g/vinco/Kconfig
> create mode 100644 board/l+g/vinco/Makefile
> create mode 100644 board/l+g/vinco/vinco.c
> create mode 100644 configs/vinco_defconfig
> create mode 100644 include/configs/vinco.h
>
> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
> index c333647..3dfbb5f 100644
> --- a/arch/arm/mach-at91/Kconfig
> +++ b/arch/arm/mach-at91/Kconfig
> @@ -114,6 +114,11 @@ config TARGET_SMARTWEB
> select CPU_ARM926EJS
> select SUPPORT_SPL
>
> +config TARGET_VINCO
> + bool "Support VINCO"
> + select CPU_V7
> + select SUPPORT_SPL
> +
> endchoice
>
> config SYS_SOC
> @@ -136,6 +141,7 @@ source "board/bluewater/snapper9260/Kconfig"
> source "board/calao/usb_a9263/Kconfig"
> source "board/egnite/ethernut5/Kconfig"
> source "board/esd/meesc/Kconfig"
> +source "board/l+g/vinco/Kconfig"
> source "board/mini-box/picosam9g45/Kconfig"
> source "board/ronetix/pm9261/Kconfig"
> source "board/ronetix/pm9263/Kconfig"
> diff --git a/board/l+g/vinco/Kconfig b/board/l+g/vinco/Kconfig
> new file mode 100644
> index 000..229b5ea
> --- /dev/null
> +++ b/board/l+g/vinco/Kconfig
> @@ -0,0 +1,12 @@
> +if TARGET_VINCO
> +
> +config SYS_BOARD
> + default "vinco"
> +
> +config SYS_VENDOR
> + default "l+g"
> +
> +config SYS_CONFIG_NAME
> + default "vinco"
> +
> +endif
> diff --git a/board/l+g/vinco/Makefile b/board/l+g/vinco/Makefile
> new file mode 100644
> index 000..a2b8a2b
> --- /dev/null
> +++ b/board/l+g/vinco/Makefile
> @@ -0,0 +1 @@
> +obj-y += vinco.o
> diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
> new file mode 100644
> index 000..3d7af09
> --- /dev/null
> +++ b/board/l+g/vinco/vinco.c
> @@ -0,0 +1,212 @@
> +/*
> + * Board file for the VInCo platform
> + * Based on the the SAMA5-EK board file
> + * Configuration settings for the VInCo platform.
> + * Copyright (C) 2014 Atmel
> + * Bo Shen <voice.s...@atmel.com>
> + * Copyright (C) 2015 Free Electrons
> + * Gregory CLEMENT <gregory.clem...@free-electrons.com>
> + *
> + * SPDX-License-Identifier: GPL-2.0+
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +#ifdef CONFIG_ATMEL_SPI
> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
> +{
> + return bus == 0 && cs == 0;
> +}
> +
> +void spi_cs_activate(struct spi_slave *slave)
> +{
> + at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
> +}
> +
> +void spi_cs_deactivate(struct spi_slave *slave)
> +{
> + at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
> +}
> +
> +static void vinco_spi0_hw_init(void)
> +{
> + at91_set_a_periph(AT91_PIO_PORTC, 0, 0);/* SPI0_MISO */
> + at91_set_a_periph(AT91_PIO_PORTC, 1, 0);/* SPI0_MOSI */
> + at91_set_a_periph(AT91_PIO_PORTC, 2, 0);/* SPI0_SPCK */
> +
> + at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
> +
> + /* Enable clock */
Re: [U-Boot] [PATCH] ARM: Add Support for the VInCo platform
Hi Thomas,
On mer., déc. 16 2015, Thomas Petazzoni <thomas.petazz...@free-electrons.com>
wrote:
> Dear Gregory CLEMENT,
>
> On Wed, 16 Dec 2015 11:34:00 +0100, Gregory CLEMENT wrote:
>
>> diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
>> index c333647..d7e36cb 100644
>> --- a/arch/arm/mach-at91/Kconfig
>> +++ b/arch/arm/mach-at91/Kconfig
>> @@ -114,6 +114,12 @@ config TARGET_SMARTWEB
>> select CPU_ARM926EJS
>> select SUPPORT_SPL
>>
>> +config TARGET_VINCO
>> +bool "Support VINCO"
>> +select CPU_V7
>> +select SUPPORT_SPL
>> +
>> +
>
> One too many empty line.
>
>> endchoice
>>
>> config SYS_SOC
>> @@ -143,5 +149,6 @@ source "board/ronetix/pm9g45/Kconfig"
>> source "board/siemens/corvus/Kconfig"
>> source "board/siemens/taurus/Kconfig"
>> source "board/siemens/smartweb/Kconfig"
>> +source "board/l+g/vinco/Kconfig"
>
> Alphabetic ordering should be respected here.
>
>> diff --git a/board/l+g/vinco/Makefile b/board/l+g/vinco/Makefile
>> new file mode 100644
>> index 000..d68b3e4
>> --- /dev/null
>> +++ b/board/l+g/vinco/Makefile
>> @@ -0,0 +1,2 @@
>> +
>
> Useless newline.
>
>> +obj-y += vinco.o
>> diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
>> new file mode 100644
>> index 000..d9ba987
>> --- /dev/null
>> +++ b/board/l+g/vinco/vinco.c
>> @@ -0,0 +1,212 @@
>> +/*
>> + * Board file for the VinCo platform
>> + * Based on the the SAMA5-EK board file
>> + * Configuration settings for the VinCo platform.
>> + * Copyright (C) 2014 Atmel
>> + *Bo Shen <voice.s...@atmel.com>
>> + * Copyright (C) 2015 Free Electrons
>> + *Gregory CLEMENT gregory.clem...@free-electrons.com
>
> E-mail address should be enclosed in <...>.
>
>
>> +#ifdef CONFIG_ATMEL_SPI
>> +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
>> +{
>> +return bus == 0 && cs == 0;
>> +}
>> +
>> +void spi_cs_activate(struct spi_slave *slave)
>> +{
>> +at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
>> +}
>> +
>> +void spi_cs_deactivate(struct spi_slave *slave)
>> +{
>> +at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
>> +}
>> +
>> +static void sama5d4ek_spi0_hw_init(void)
>
> A function named sama5d4ek in the support for a board named L+G VInCo ?
>
>> +{
>> +at91_set_a_periph(AT91_PIO_PORTC, 0, 0);/* SPI0_MISO */
>> +at91_set_a_periph(AT91_PIO_PORTC, 1, 0);/* SPI0_MOSI */
>> +at91_set_a_periph(AT91_PIO_PORTC, 2, 0);/* SPI0_SPCK */
>> +
>> +at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
>> +
>> +/* Enable clock */
>> +at91_periph_clk_enable(ATMEL_ID_SPI0);
>> +}
>> +#endif /* CONFIG_ATMEL_SPI */
>> +
>> +
>> +#ifdef CONFIG_CMD_USB
>> +static void sama5d4ek_usb_hw_init(void)
>
> Ditto.
>
>> +{
>> +at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
>> +at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
>> +at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
>> +}
>> +#endif
>> +
>> +
>> +#ifdef CONFIG_GENERIC_ATMEL_MCI
>> +void sama5d4ek_mci0_hw_init(void)
>
> Ditto (and multiple times later).
>
>
>> diff --git a/include/configs/vinco.h b/include/configs/vinco.h
>> new file mode 100644
>> index 000..678b04b
>> --- /dev/null
>> +++ b/include/configs/vinco.h
>> @@ -0,0 +1,172 @@
>> +/*
>> + * Configuration settings for the VInCo platform.
>> + *
>> + * Based on the settings for the SAMA5-EK board
>> + * Copyright (C) 2014 Atmel
>> + *Bo Shen <voice.s...@atmel.com>
>> + * Copyright (C) 2015 Free Electrons
>> + *Gregory CLEMENT gregory.clem...@free-electrons.com
>
> <...> for e-mail address
>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0+
>> + */
>> +
>> +#ifndef __CONFIG_H
>> +#define __CONFIG_H
>> +
>> +/* No NOR flash, this definition should put before common header */
>
> "should put" ?
"should _be_ put" I guess, I dumbly copy and paste this one.
>
>> +#define CONFIG_SYS_NO_FLASH
>> +
>> +#ifdef CONFIG_SYS_TEXT_BASE
>> +#undef CONFIG_SYS_TEXT_BASE
>> +#endif
>
> Why here? Nothing has been included so far, I guess this is going to be
> defined by the next line, no?
>
>> +#include "at91-sama5_common.h"
>> +
>> +/* The value in the common file is too far away for the VinCo platform */
>> +#ifdef CONFIG_SYS_TEXT_BASE
>> +#undef CONFIG_SYS_TEXT_BASE
>> +#endif
>> +#define CONFIG_SYS_TEXT_BASE0x20f0
Thanks for your review, I agree with all your comment and will send a v2
soon.
Gregory
>
> Best regards,
>
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux, Kernel and Android engineering
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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[U-Boot] [PATCH v3] net: macb: Not all the GEM are gigabit capable
During the initialization of PHY the gigabit bit capable is set if the
controller is a GEM. However, for sama5d2 and sama5d4, the GEM is
configured to support only 10/100.
Improperly setting the GBE capability leads to an unresponsive MAC
controller. This patch fixes this behavior allowing using the gmac with
these SoCs.
Suggested-by: Nicolas Ferre <nicolas.fe...@atmel.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
Hi,
in this v3, I fixed the sama5d2 typo and the missing brace.
I also took care of the cpu_is_* symbols which may not be defined
depending of the choice of the SoC.
Gregory
drivers/net/macb.c | 21 +++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index a5c1880..e801313 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -109,6 +109,23 @@ static int macb_is_gem(struct macb_device *macb)
return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
}
+#ifndef cpu_is_sama5d2
+#define cpu_is_sama5d2() 0
+#endif
+
+#ifndef cpu_is_sama5d4
+#define cpu_is_sama5d4() 0
+#endif
+
+static int gem_is_gigabit_capable(struct macb_device *macb)
+{
+ /*
+* The GEM controllers embeded in SAMA5D2 and SAMA5D4 are
+* configured to support only 10/100.
+*/
+ return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d4();
+}
+
static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
{
unsigned long netctl;
@@ -480,8 +497,8 @@ static int macb_phy_init(struct macb_device *macb)
return 0;
}
- /* First check for GMAC */
- if (macb_is_gem(macb)) {
+ /* First check for GMAC and that it is GiB capable */
+ if (gem_is_gigabit_capable(macb)){
lpa = macb_mdio_read(macb, MII_STAT1000);
if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
--
2.5.0
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Re: [U-Boot] [PATCH v2] net: macb: Not all the GEM are gigabit capable
Hi Nicolas,
On mer., déc. 16 2015, Nicolas Ferre <nicolas.fe...@atmel.com> wrote:
> Le 16/12/2015 11:27, Gregory CLEMENT a écrit :
>> During the initialization of PHY the gigabit bit capable is set if the
>> controller is a GEM. However, for sama5d2 and sama5d4, the GEM is
>> configured to support only 10/100.
>>
>> Improperly setting the GBE capability leads to an unresponsive MAC
>> controller. This patch fix this behavior allowing to use the gmac with
>> these SoCs.
>>
>> Suggested-by: Nicolas Ferre <nicolas.fe...@atmel.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>>
>> fix gem
>> ---
>> drivers/net/macb.c | 13 +++--
>> 1 file changed, 11 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/net/macb.c b/drivers/net/macb.c
>> index a5c1880..ab38f48 100644
>> --- a/drivers/net/macb.c
>> +++ b/drivers/net/macb.c
>> @@ -109,6 +109,15 @@ static int macb_is_gem(struct macb_device *macb)
>> return MACB_BFEXT(IDNUM, macb_readl(macb, MID)) == 0x2;
>> }
>>
>> +static int gem_is_gigabit_capable(struct macb_device *macb)
>> +{
>> +/*
>> + * The GEM controllers embeded in SAMA5D2 and SAMA5D4 are
>> + * configured to support only 10/100.
>> + */
>> +return macb_is_gem(macb) && !cpu_is_sama5d2() && !cpu_is_sama5d2();
>
> Typo here: sama5d2 twice!
> ;-)
>
>
>> +}
>> +
>> static void macb_mdio_write(struct macb_device *macb, u8 reg, u16 value)
>> {
>> unsigned long netctl;
>> @@ -480,8 +489,8 @@ static int macb_phy_init(struct macb_device *macb)
>> return 0;
>> }
>>
>> -/* First check for GMAC */
>> -if (macb_is_gem(macb)) {
>> +/* First check for GMAC and that it is GiB capable */
>> +if (gem_is_gigabit_capable(macb))
And here a { was missing!
Sorry for the nois a v3 will come.
Gregory
>> lpa = macb_mdio_read(macb, MII_STAT1000);
>>
>> if (lpa & (LPA_1000FULL | LPA_1000HALF)) {
>>
>
>
> --
> Nicolas Ferre
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
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[U-Boot] [PATCH v2] ARM: Add Support for the VInCo platform
The Versatile Industrial Communication platform is a community oriented
board from Landis + Gyr. It comes with:
- an RS-485 port
- 2 Ethernet ports
- a wireless M-BUS
- a 4G modem
- a 4MB SPI flash
- a 4GB eMMC
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
arch/arm/mach-at91/Kconfig | 6 ++
board/l+g/vinco/Kconfig| 12 +++
board/l+g/vinco/Makefile | 1 +
board/l+g/vinco/vinco.c| 212 +
configs/vinco_defconfig| 13 +++
include/configs/vinco.h| 172
6 files changed, 416 insertions(+)
create mode 100644 board/l+g/vinco/Kconfig
create mode 100644 board/l+g/vinco/Makefile
create mode 100644 board/l+g/vinco/vinco.c
create mode 100644 configs/vinco_defconfig
create mode 100644 include/configs/vinco.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c333647..3dfbb5f 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -114,6 +114,11 @@ config TARGET_SMARTWEB
select CPU_ARM926EJS
select SUPPORT_SPL
+config TARGET_VINCO
+ bool "Support VINCO"
+ select CPU_V7
+ select SUPPORT_SPL
+
endchoice
config SYS_SOC
@@ -136,6 +141,7 @@ source "board/bluewater/snapper9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
+source "board/l+g/vinco/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
diff --git a/board/l+g/vinco/Kconfig b/board/l+g/vinco/Kconfig
new file mode 100644
index 000..229b5ea
--- /dev/null
+++ b/board/l+g/vinco/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VINCO
+
+config SYS_BOARD
+ default "vinco"
+
+config SYS_VENDOR
+ default "l+g"
+
+config SYS_CONFIG_NAME
+ default "vinco"
+
+endif
diff --git a/board/l+g/vinco/Makefile b/board/l+g/vinco/Makefile
new file mode 100644
index 000..a2b8a2b
--- /dev/null
+++ b/board/l+g/vinco/Makefile
@@ -0,0 +1 @@
+obj-y += vinco.o
diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
new file mode 100644
index 000..3d7af09
--- /dev/null
+++ b/board/l+g/vinco/vinco.c
@@ -0,0 +1,212 @@
+/*
+ * Board file for the VInCo platform
+ * Based on the the SAMA5-EK board file
+ * Configuration settings for the VInCo platform.
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.s...@atmel.com>
+ * Copyright (C) 2015 Free Electrons
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void vinco_spi0_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0);/* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0);/* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0);/* SPI0_SPCK */
+
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+
+#ifdef CONFIG_CMD_USB
+static void vinco_usb_hw_init(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
+ at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
+ at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
+}
+#endif
+
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void vinco_mci0_hw_init(void)
+{
+ at91_set_b_periph(AT91_PIO_PORTC, 5, 1);/* MCI0 CDA */
+ at91_set_b_periph(AT91_PIO_PORTC, 6, 1);/* MCI0 DA0 */
+ at91_set_b_periph(AT91_PIO_PORTC, 7, 1);/* MCI0 DA1 */
+ at91_set_b_periph(AT91_PIO_PORTC, 8, 1);/* MCI0 DA2 */
+ at91_set_b_periph(AT91_PIO_PORTC, 9, 1);/* MCI0 DA3 */
+ at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */
+ at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */
+ at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */
+ at91_set_b_periph(AT91_PIO_PORTC, 13, 1); /* MCI0 DA7 */
+ at91_set_b_periph(AT91_PIO_PORTC, 4, 0);/* MCI0 CLK */
+
+ /*
+* As the mci io internal pull down is too strong, so if the io needs
+* external pull up, the pull up
[U-Boot] [PATCH v3] ARM: Add Support for the VInCo platform
The Versatile Industrial Communication platform is a community oriented
board from Landis + Gyr. It comes with:
- an RS-485 port
- 2 Ethernet ports
- a wireless M-BUS
- a 4G modem
- a 4MB SPI flash
- a 4GB eMMC
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.fe...@atmel.com>
---
Hi again,
Some of my fixes were not commit in my previous version.
This version should be the correct one, I also added the acked-by from
Nicolas.
Sorry for not having seen it before.
Thanks,
Gregory
arch/arm/mach-at91/Kconfig | 6 ++
board/l+g/vinco/Kconfig| 12 +++
board/l+g/vinco/Makefile | 1 +
board/l+g/vinco/vinco.c| 212 +
configs/vinco_defconfig| 13 +++
include/configs/vinco.h| 169
6 files changed, 413 insertions(+)
create mode 100644 board/l+g/vinco/Kconfig
create mode 100644 board/l+g/vinco/Makefile
create mode 100644 board/l+g/vinco/vinco.c
create mode 100644 configs/vinco_defconfig
create mode 100644 include/configs/vinco.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index c333647..3dfbb5f 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -114,6 +114,11 @@ config TARGET_SMARTWEB
select CPU_ARM926EJS
select SUPPORT_SPL
+config TARGET_VINCO
+ bool "Support VINCO"
+ select CPU_V7
+ select SUPPORT_SPL
+
endchoice
config SYS_SOC
@@ -136,6 +141,7 @@ source "board/bluewater/snapper9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
+source "board/l+g/vinco/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
diff --git a/board/l+g/vinco/Kconfig b/board/l+g/vinco/Kconfig
new file mode 100644
index 000..229b5ea
--- /dev/null
+++ b/board/l+g/vinco/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_VINCO
+
+config SYS_BOARD
+ default "vinco"
+
+config SYS_VENDOR
+ default "l+g"
+
+config SYS_CONFIG_NAME
+ default "vinco"
+
+endif
diff --git a/board/l+g/vinco/Makefile b/board/l+g/vinco/Makefile
new file mode 100644
index 000..a2b8a2b
--- /dev/null
+++ b/board/l+g/vinco/Makefile
@@ -0,0 +1 @@
+obj-y += vinco.o
diff --git a/board/l+g/vinco/vinco.c b/board/l+g/vinco/vinco.c
new file mode 100644
index 000..3d7af09
--- /dev/null
+++ b/board/l+g/vinco/vinco.c
@@ -0,0 +1,212 @@
+/*
+ * Board file for the VInCo platform
+ * Based on the the SAMA5-EK board file
+ * Configuration settings for the VInCo platform.
+ * Copyright (C) 2014 Atmel
+ * Bo Shen <voice.s...@atmel.com>
+ * Copyright (C) 2015 Free Electrons
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_ATMEL_SPI
+int spi_cs_is_valid(unsigned int bus, unsigned int cs)
+{
+ return bus == 0 && cs == 0;
+}
+
+void spi_cs_activate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 0);
+}
+
+void spi_cs_deactivate(struct spi_slave *slave)
+{
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1);
+}
+
+static void vinco_spi0_hw_init(void)
+{
+ at91_set_a_periph(AT91_PIO_PORTC, 0, 0);/* SPI0_MISO */
+ at91_set_a_periph(AT91_PIO_PORTC, 1, 0);/* SPI0_MOSI */
+ at91_set_a_periph(AT91_PIO_PORTC, 2, 0);/* SPI0_SPCK */
+
+ at91_set_pio_output(AT91_PIO_PORTC, 3, 1); /* SPI0_CS0 */
+
+ /* Enable clock */
+ at91_periph_clk_enable(ATMEL_ID_SPI0);
+}
+#endif /* CONFIG_ATMEL_SPI */
+
+
+#ifdef CONFIG_CMD_USB
+static void vinco_usb_hw_init(void)
+{
+ at91_set_pio_output(AT91_PIO_PORTE, 11, 0);
+ at91_set_pio_output(AT91_PIO_PORTE, 12, 0);
+ at91_set_pio_output(AT91_PIO_PORTE, 10, 0);
+}
+#endif
+
+
+#ifdef CONFIG_GENERIC_ATMEL_MCI
+void vinco_mci0_hw_init(void)
+{
+ at91_set_b_periph(AT91_PIO_PORTC, 5, 1);/* MCI0 CDA */
+ at91_set_b_periph(AT91_PIO_PORTC, 6, 1);/* MCI0 DA0 */
+ at91_set_b_periph(AT91_PIO_PORTC, 7, 1);/* MCI0 DA1 */
+ at91_set_b_periph(AT91_PIO_PORTC, 8, 1);/* MCI0 DA2 */
+ at91_set_b_periph(AT91_PIO_PORTC, 9, 1);/* MCI0 DA3 */
+ at91_set_b_periph(AT91_PIO_PORTC, 10, 1); /* MCI0 DA4 */
+ at91_set_b_periph(AT91_PIO_PORTC, 11, 1); /* MCI0 DA5 */
+ at91_set_b_periph(AT91_PIO_PORTC, 12, 1); /* MCI0 DA6 */
+ at91_set_b_periph(AT91_PIO_PORTC,
