Re: [PATCH v2 0/4] riscv: Initial support for Lichee PI 4A board
For this series: Reviewed-by: Guo Ren On Sat, Jul 8, 2023 at 7:25 AM Yixun Lan wrote: > > Sipeed's Lichee PI 4A board is based on T-HEAD's TH1520 SoC which consists of > quad core XuanTie C910 CPU, plus one C906 CPU and one E902 CPU. > > In this series, we add a basic device tree, including UART CPU, PLIC, make it > capable of running into a serial console. > > Please note that, we rely on pre shipped vendor u-boot which run in M-Mode to > chain load this mainline u-boot either via eMMC storage or from tftp, thus the > pinctrl and clock setting are not implemented in this series, which certainly > can be improved later accordingly. > > Also the device tree is borrowed from kernel which is already accepted by > kernel > upstream [1]. > > [1] https://lore.kernel.org/all/20230617161529.2092-1-jszh...@kernel.org > > Changes since PATCH v1: > - sync device tree with mainline kernel's version > - update docs and also fix the build error > - fix missing header file > > PATCH v1: > https://lore.kernel.org/all/20230526124107.894-1-d...@gentoo.org > > Yixun Lan (4): > riscv: t-head: licheepi4a: initial support added > riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A > board > configs: th1520_lpi4a_defconfig: Add initial config > doc: t-head: lpi4a: document Lichee PI 4A board > > arch/riscv/Kconfig | 5 + > arch/riscv/dts/Makefile | 1 + > arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ > arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ > arch/riscv/dts/th1520.dtsi | 406 > board/thead/th1520_lpi4a/Kconfig| 42 ++ > board/thead/th1520_lpi4a/MAINTAINERS| 7 + > board/thead/th1520_lpi4a/Makefile | 5 + > board/thead/th1520_lpi4a/board.c| 15 + > configs/th1520_lpi4a_defconfig | 82 > doc/board/index.rst | 1 + > doc/board/thead/index.rst | 9 + > doc/board/thead/lpi4a.rst | 129 +++ > include/configs/th1520_lpi4a.h | 22 ++ > 14 files changed, 790 insertions(+) > create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi > create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts > create mode 100644 arch/riscv/dts/th1520.dtsi > create mode 100644 board/thead/th1520_lpi4a/Kconfig > create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS > create mode 100644 board/thead/th1520_lpi4a/Makefile > create mode 100644 board/thead/th1520_lpi4a/board.c > create mode 100644 configs/th1520_lpi4a_defconfig > create mode 100644 doc/board/thead/index.rst > create mode 100644 doc/board/thead/lpi4a.rst > create mode 100644 include/configs/th1520_lpi4a.h > > -- > 2.39.3 > -- Best Regards Guo Ren
Re: [RESEND PATCH v1 2/4] riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board
On Mon, May 29, 2023 at 3:54 PM Yixun Lan wrote: > > Hi Guo: > > On 14:50 Mon 29 May , Guo Ren wrote: > > On Mon, May 29, 2023 at 11:01 AM Yixun Lan wrote: > > > > > > Hi Guo: > > > > > > see my comment below. > > > > > > On 09:19 Mon 29 May , Guo Ren wrote: > > > > On Sat, May 27, 2023 at 5:17 PM Yixun Lan wrote: > > > > > > > > > > Hi Guo: > > > > > > > > > > On 09:43 Sat 27 May , Guo Ren wrote: > > > > > > Sorry, why we need dts here? If we put dts here, we could delete the > > > > > > one in Linux. > > > > > No, I think it's more than a historical reason for why we have two dts > > > > > both in u-boot and kernel. And this dts here is merely used by u-boot, > > > > > it could be a simplified version comparing to kernel's dts. > > > > > > > > > > > > > > > > > We shouldn't put it with two places, that would be bad for > > > > > > maintanice. > > > > > I can totally understand your concern, in fact, we are trying to keep > > > > > them sync, > > > > > so I will probably wait the dts of kernel settle down, before take > > > > > action here. > > > > > so, please conside this patch as RFC, and may change in next > > > > > revisions.. > > > > Thx for clarification. But I still concern the necessary of the patch, > > > > could you move this from this series first, because we've argument on > > > > it. Your other patches looks good, I'm looking forward your next v2. > > > > > > > > But for this one, let's talk it after kernel side merged. > > > I'd like to include dts in the first series, otherwise it won't be a > > > complete > > > working series, e.g. - not only it's unable to build, also can't do > > > run-time test > > I couldn't make sense how it block your build, The build operation is > > controlled by you Makefile modification. right? > > > you mostly right, but in patch "[ 3/4 ] configs: th1520_lpi4a_defconfig: Add > initial config", we will enable device tree, and require > CONFIG_DEFAULT_DEVICE_TREE="th1520-lichee-pi-4a.dtb" to be provided, > also since UART's base register is parsed from dts (run time), so I see no > reason > why the dts patch should be separated Oh, I see; u-boot needs a seperate dtb to boot indepedent. Maybe, we just keep a minimum dts here, then we needn't syncronize with the kernel side. > > > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile > > index 79a58694f5..72fd815a40 100644 > > --- a/arch/riscv/dts/Makefile > > +++ b/arch/riscv/dts/Makefile > > @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += > > hifive-unmatched-a00.dtb > > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += > > jh7110-starfive-visionfive-2-v1.3b.dtb > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += > > jh7110-starfive-visionfive-2-v1.2a.dtb > > +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb > > include $(srctree)/scripts/Makefile.dts > > > > > > > > I'm totally fine with kernel dts merged first, then submit this later, so > > > no push.. > > > > > > > > > > > > > > > > > > > > > > > > On Fri, May 26, 2023 at 8:41 PM Yixun Lan wrote: > > > > > > > > > > > > > > Only add basic support for CPU, PLIC UART and Timer. > > > > > > > > > > > > > > Reviewed-by: Wei Fu > > > > > > > Signed-off-by: Yixun Lan > > > > > > > --- > > > > > > > arch/riscv/dts/Makefile | 1 + > > > > > > > arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ > > > > > > > arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ > > > > > > > arch/riscv/dts/th1520.dtsi | 435 > > > > > > > > > > > > > > 4 files changed, 502 insertions(+) > > > > > > > create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi > > > > > > > create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts > > > > > > > create mode 100644 arch/riscv/dts/th1520.dtsi > > &
Re: [RESEND PATCH v1 2/4] riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board
On Mon, May 29, 2023 at 11:01 AM Yixun Lan wrote: > > Hi Guo: > > see my comment below. > > On 09:19 Mon 29 May , Guo Ren wrote: > > On Sat, May 27, 2023 at 5:17 PM Yixun Lan wrote: > > > > > > Hi Guo: > > > > > > On 09:43 Sat 27 May , Guo Ren wrote: > > > > Sorry, why we need dts here? If we put dts here, we could delete the > > > > one in Linux. > > > No, I think it's more than a historical reason for why we have two dts > > > both in u-boot and kernel. And this dts here is merely used by u-boot, > > > it could be a simplified version comparing to kernel's dts. > > > > > > > > > > > We shouldn't put it with two places, that would be bad for maintanice. > > > I can totally understand your concern, in fact, we are trying to keep > > > them sync, > > > so I will probably wait the dts of kernel settle down, before take action > > > here. > > > so, please conside this patch as RFC, and may change in next revisions.. > > Thx for clarification. But I still concern the necessary of the patch, > > could you move this from this series first, because we've argument on > > it. Your other patches looks good, I'm looking forward your next v2. > > > > But for this one, let's talk it after kernel side merged. > I'd like to include dts in the first series, otherwise it won't be a complete > working series, e.g. - not only it's unable to build, also can't do run-time > test I couldn't make sense how it block your build, The build operation is controlled by you Makefile modification. right? diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile index 79a58694f5..72fd815a40 100644 --- a/arch/riscv/dts/Makefile +++ b/arch/riscv/dts/Makefile @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.3b.dtb dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += jh7110-starfive-visionfive-2-v1.2a.dtb +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb include $(srctree)/scripts/Makefile.dts > > I'm totally fine with kernel dts merged first, then submit this later, so no > push.. > > > > > > > > > > > > > > On Fri, May 26, 2023 at 8:41 PM Yixun Lan wrote: > > > > > > > > > > Only add basic support for CPU, PLIC UART and Timer. > > > > > > > > > > Reviewed-by: Wei Fu > > > > > Signed-off-by: Yixun Lan > > > > > --- > > > > > arch/riscv/dts/Makefile | 1 + > > > > > arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++ > > > > > arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++ > > > > > arch/riscv/dts/th1520.dtsi | 435 > > > > > > > > > > 4 files changed, 502 insertions(+) > > > > > create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi > > > > > create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts > > > > > create mode 100644 arch/riscv/dts/th1520.dtsi > > > > > > > > > > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile > > > > > index 79a58694f5..72fd815a40 100644 > > > > > --- a/arch/riscv/dts/Makefile > > > > > +++ b/arch/riscv/dts/Makefile > > > > > @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += > > > > > hifive-unmatched-a00.dtb > > > > > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb > > > > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += > > > > > jh7110-starfive-visionfive-2-v1.3b.dtb > > > > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) += > > > > > jh7110-starfive-visionfive-2-v1.2a.dtb > > > > > +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb > > > > > include $(srctree)/scripts/Makefile.dts > > > > > > > > > > targets += $(dtb-y) > > > > > diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi > > > > > b/arch/riscv/dts/th1520-lichee-module-4a.dtsi > > > > > new file mode 100644 > > > > > index 00..dc00e3dfa0 > > > > > --- /dev/null > > > > > +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi > > > > > @@ -0,0 +1,34 @@ > > > > > +// SPDX-License-Identifier: GPL-2.0 > > > >
Re: [RESEND PATCH v1 2/4] riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board
On Sat, May 27, 2023 at 5:17 PM Yixun Lan wrote:
>
> Hi Guo:
>
> On 09:43 Sat 27 May , Guo Ren wrote:
> > Sorry, why we need dts here? If we put dts here, we could delete the
> > one in Linux.
> No, I think it's more than a historical reason for why we have two dts
> both in u-boot and kernel. And this dts here is merely used by u-boot,
> it could be a simplified version comparing to kernel's dts.
>
> >
> > We shouldn't put it with two places, that would be bad for maintanice.
> I can totally understand your concern, in fact, we are trying to keep them
> sync,
> so I will probably wait the dts of kernel settle down, before take action
> here.
> so, please conside this patch as RFC, and may change in next revisions..
Thx for clarification. But I still concern the necessary of the patch,
could you move this from this series first, because we've argument on
it. Your other patches looks good, I'm looking forward your next v2.
But for this one, let's talk it after kernel side merged.
>
> >
> > On Fri, May 26, 2023 at 8:41 PM Yixun Lan wrote:
> > >
> > > Only add basic support for CPU, PLIC UART and Timer.
> > >
> > > Reviewed-by: Wei Fu
> > > Signed-off-by: Yixun Lan
> > > ---
> > > arch/riscv/dts/Makefile | 1 +
> > > arch/riscv/dts/th1520-lichee-module-4a.dtsi | 34 ++
> > > arch/riscv/dts/th1520-lichee-pi-4a.dts | 32 ++
> > > arch/riscv/dts/th1520.dtsi | 435
> > > 4 files changed, 502 insertions(+)
> > > create mode 100644 arch/riscv/dts/th1520-lichee-module-4a.dtsi
> > > create mode 100644 arch/riscv/dts/th1520-lichee-pi-4a.dts
> > > create mode 100644 arch/riscv/dts/th1520.dtsi
> > >
> > > diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> > > index 79a58694f5..72fd815a40 100644
> > > --- a/arch/riscv/dts/Makefile
> > > +++ b/arch/riscv/dts/Makefile
> > > @@ -9,6 +9,7 @@ dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) +=
> > > hifive-unmatched-a00.dtb
> > > dtb-$(CONFIG_TARGET_SIPEED_MAIX) += k210-maix-bit.dtb
> > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
> > > jh7110-starfive-visionfive-2-v1.3b.dtb
> > > dtb-$(CONFIG_TARGET_STARFIVE_VISIONFIVE2) +=
> > > jh7110-starfive-visionfive-2-v1.2a.dtb
> > > +dtb-$(CONFIG_TARGET_TH1520_LPI4A) += th1520-lichee-pi-4a.dtb
> > > include $(srctree)/scripts/Makefile.dts
> > >
> > > targets += $(dtb-y)
> > > diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi
> > > b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
> > > new file mode 100644
> > > index 00..dc00e3dfa0
> > > --- /dev/null
> > > +++ b/arch/riscv/dts/th1520-lichee-module-4a.dtsi
> > > @@ -0,0 +1,34 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright (C) 2023 Jisheng Zhang
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include "th1520.dtsi"
> > > +
> > > +/ {
> > > + model = "Sipeed Lichee Module 4A";
> > > + compatible = "sipeed,lichee-module-4a", "thead,th1520";
> > > +
> > > + memory@0 {
> > > + device_type = "memory";
> > > + reg = <0x0 0x 0x2 0x>;
> > > + };
> > > +};
> > > +
> > > +&osc {
> > > + clock-frequency = <2400>;
> > > +};
> > > +
> > > +&osc_32k {
> > > + clock-frequency = <32768>;
> > > +};
> > > +
> > > +&apb_clk {
> > > + clock-frequency = <6250>;
> > > +};
> > > +
> > > +&uart_sclk {
> > > + clock-frequency = <1>;
> > > +};
> > > diff --git a/arch/riscv/dts/th1520-lichee-pi-4a.dts
> > > b/arch/riscv/dts/th1520-lichee-pi-4a.dts
> > > new file mode 100644
> > > index 00..a1248b2ee3
> > > --- /dev/null
> > > +++ b/arch/riscv/dts/th1520-lichee-pi-4a.dts
> > > @@ -0,0 +1,32 @@
> > > +// SPDX-License-Identifier: GPL-2.0
> > > +/*
> > > + * Copyright (C) 2023 Jisheng Zhang
> > > + */
> > > +
> > > +#include "th1520-lichee-module-4a.dtsi"
> > > +
> > > +/ {
> > > + model = "Sipeed Lichee Pi 4A";
> > > + compatible = "si
Re: [RESEND PATCH v1 1/4] riscv: t-head: licheepi4a: initial support added
On Fri, May 26, 2023 at 8:41 PM Yixun Lan wrote:
>
> Add support for Sipeed's Lichee Pi 4A board which based on
> T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled,
> so it's capable of chain booting from T-HEAD's vendor u-boot.
>
> Reviewed-by: Wei Fu
> Signed-off-by: Yixun Lan
> ---
> arch/riscv/Kconfig | 5
> board/thead/th1520_lpi4a/Kconfig | 42
> board/thead/th1520_lpi4a/MAINTAINERS | 7 +
> board/thead/th1520_lpi4a/Makefile| 5
> board/thead/th1520_lpi4a/board.c | 14 ++
> include/configs/th1520_lpi4a.h | 22 +++
> 6 files changed, 95 insertions(+)
> create mode 100644 board/thead/th1520_lpi4a/Kconfig
> create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS
> create mode 100644 board/thead/th1520_lpi4a/Makefile
> create mode 100644 board/thead/th1520_lpi4a/board.c
> create mode 100644 include/configs/th1520_lpi4a.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index f6ed05906a..419b6171a9 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED
> config TARGET_STARFIVE_VISIONFIVE2
> bool "Support StarFive VisionFive2 Board"
>
> +config TARGET_TH1520_LPI4A
> + bool "Support Sipeed's TH1520 Lichee PI 4A Board"
> + select SYS_CACHE_SHIFT_6
> +
> config TARGET_SIPEED_MAIX
> bool "Support Sipeed Maix Board"
> select SYS_CACHE_SHIFT_6
> @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig"
> source "board/microchip/mpfs_icicle/Kconfig"
> source "board/sifive/unleashed/Kconfig"
> source "board/sifive/unmatched/Kconfig"
> +source "board/thead/th1520_lpi4a/Kconfig"
> source "board/openpiton/riscv64/Kconfig"
> source "board/sipeed/maix/Kconfig"
> source "board/starfive/visionfive2/Kconfig"
> diff --git a/board/thead/th1520_lpi4a/Kconfig
> b/board/thead/th1520_lpi4a/Kconfig
> new file mode 100644
> index 00..622246127c
> --- /dev/null
> +++ b/board/thead/th1520_lpi4a/Kconfig
> @@ -0,0 +1,42 @@
> +if TARGET_TH1520_LPI4A
> +
> +config ARCH_THEAD
> + bool
> + default y
> +
> +config SYS_BOARD
> + default "th1520_lpi4a"
> +
> +config SYS_VENDOR
> + default "thread"
default "T-HEAD"
Thx
> +
> +config SYS_CPU
> + default "generic"
> +
> +config SYS_CONFIG_NAME
> + default "th1520_lpi4a"
> +
> +config TEXT_BASE
> + default 0x01b0 if SPL
> + default 0x01c0 if !RISCV_SMODE
> + default 0x01c0 if RISCV_SMODE
> +
> +config SPL_TEXT_BASE
> + default 0x0800
> +
> +config SPL_OPENSBI_LOAD_ADDR
> + default 0x8000
> +
> +config BOARD_SPECIFIC_OPTIONS
> + def_bool y
> + select ARCH_EARLY_INIT_R
> + imply CPU
> + imply CPU_RISCV
> + imply RISCV_TIMER if RISCV_SMODE
> + imply CMD_CPU
> + imply SMP
> + imply SUPPORT_OF_CONTROL
> + imply OF_CONTROL
> + imply OF_REAL
> +
> +endif
> diff --git a/board/thead/th1520_lpi4a/MAINTAINERS
> b/board/thead/th1520_lpi4a/MAINTAINERS
> new file mode 100644
> index 00..36c7ab7cc3
> --- /dev/null
> +++ b/board/thead/th1520_lpi4a/MAINTAINERS
> @@ -0,0 +1,7 @@
> +Lichee PI 4A
> +M: Wei Fu
> +M: Yixun Lan
> +S: Maintained
> +F: board/thead/th1520_lpi4a/
> +F: configs/th1520_lpi4a_defconfig
> +F: doc/board/thead/lpi4a.rst
> diff --git a/board/thead/th1520_lpi4a/Makefile
> b/board/thead/th1520_lpi4a/Makefile
> new file mode 100644
> index 00..9671b3bbb0
> --- /dev/null
> +++ b/board/thead/th1520_lpi4a/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (c) 2023, Yixun Lan
> +
> +obj-y += board.o
> diff --git a/board/thead/th1520_lpi4a/board.c
> b/board/thead/th1520_lpi4a/board.c
> new file mode 100644
> index 00..378bab098b
> --- /dev/null
> +++ b/board/thead/th1520_lpi4a/board.c
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2023, Yixun Lan
> + *
> + */
> +
> +#include
> +
> +int board_init(void)
> +{
> + enable_caches();
> +
> + return 0;
> +}
> diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h
> new file mode 100644
> index 00..87496a52c4
> --- /dev/null
> +++ b/include/configs/th1520_lpi4a.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2023 Yixun Lan
> + *
> + */
> +
> +#ifndef __TH1520_LPI4A_H
> +#define __TH1520_LPI4A_H
> +
> +#include
> +
> +#define CFG_SYS_SDRAM_BASE 0x
> +
> +#define UART_BASE 0xffe7014000
> +#define UART_REG_WIDTH 32
> +
> +/* Environment options */
> +
> +#define CFG_EXTRA_ENV_SETTINGS \
> + "PS1=[LPi4A]# \0"
> +
> +#endif /* __TH1520_LPI4A_H */
> --
> 2.40.0
>
--
Best Regards
Guo Ren
Re: [RESEND PATCH v1 1/4] riscv: t-head: licheepi4a: initial support added
On Fri, May 26, 2023 at 8:41 PM Yixun Lan wrote:
>
> Add support for Sipeed's Lichee Pi 4A board which based on
> T-HEAD's TH1520 SoC, only minimal device tree and serial onsole are enabled,
> so it's capable of chain booting from T-HEAD's vendor u-boot.
>
> Reviewed-by: Wei Fu
> Signed-off-by: Yixun Lan
> ---
> arch/riscv/Kconfig | 5
> board/thead/th1520_lpi4a/Kconfig | 42
> board/thead/th1520_lpi4a/MAINTAINERS | 7 +
> board/thead/th1520_lpi4a/Makefile| 5
> board/thead/th1520_lpi4a/board.c | 14 ++
> include/configs/th1520_lpi4a.h | 22 +++
> 6 files changed, 95 insertions(+)
> create mode 100644 board/thead/th1520_lpi4a/Kconfig
> create mode 100644 board/thead/th1520_lpi4a/MAINTAINERS
> create mode 100644 board/thead/th1520_lpi4a/Makefile
> create mode 100644 board/thead/th1520_lpi4a/board.c
> create mode 100644 include/configs/th1520_lpi4a.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index f6ed05906a..419b6171a9 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -27,6 +27,10 @@ config TARGET_SIFIVE_UNMATCHED
> config TARGET_STARFIVE_VISIONFIVE2
> bool "Support StarFive VisionFive2 Board"
>
> +config TARGET_TH1520_LPI4A
> + bool "Support Sipeed's TH1520 Lichee PI 4A Board"
> + select SYS_CACHE_SHIFT_6
> +
> config TARGET_SIPEED_MAIX
> bool "Support Sipeed Maix Board"
> select SYS_CACHE_SHIFT_6
> @@ -66,6 +70,7 @@ source "board/emulation/qemu-riscv/Kconfig"
> source "board/microchip/mpfs_icicle/Kconfig"
> source "board/sifive/unleashed/Kconfig"
> source "board/sifive/unmatched/Kconfig"
> +source "board/thead/th1520_lpi4a/Kconfig"
> source "board/openpiton/riscv64/Kconfig"
> source "board/sipeed/maix/Kconfig"
> source "board/starfive/visionfive2/Kconfig"
> diff --git a/board/thead/th1520_lpi4a/Kconfig
> b/board/thead/th1520_lpi4a/Kconfig
> new file mode 100644
> index 00..622246127c
> --- /dev/null
> +++ b/board/thead/th1520_lpi4a/Kconfig
> @@ -0,0 +1,42 @@
> +if TARGET_TH1520_LPI4A
> +
> +config ARCH_THEAD
> + bool
> + default y
> +
> +config SYS_BOARD
> + default "th1520_lpi4a"
> +
> +config SYS_VENDOR
> + default "thead"
> +
> +config SYS_CPU
> + default "generic"
> +
> +config SYS_CONFIG_NAME
> + default "th1520_lpi4a"
> +
> +config TEXT_BASE
> + default 0x01b0 if SPL
> + default 0x01c0 if !RISCV_SMODE
> + default 0x01c0 if RISCV_SMODE
> +
> +config SPL_TEXT_BASE
> + default 0x0800
> +
> +config SPL_OPENSBI_LOAD_ADDR
> + default 0x8000
> +
> +config BOARD_SPECIFIC_OPTIONS
> + def_bool y
> + select ARCH_EARLY_INIT_R
> + imply CPU
> + imply CPU_RISCV
> + imply RISCV_TIMER if RISCV_SMODE
> + imply CMD_CPU
> + imply SMP
> + imply SUPPORT_OF_CONTROL
> + imply OF_CONTROL
> + imply OF_REAL
> +
> +endif
> diff --git a/board/thead/th1520_lpi4a/MAINTAINERS
> b/board/thead/th1520_lpi4a/MAINTAINERS
> new file mode 100644
> index 00..36c7ab7cc3
> --- /dev/null
> +++ b/board/thead/th1520_lpi4a/MAINTAINERS
> @@ -0,0 +1,7 @@
> +Lichee PI 4A
> +M: Wei Fu
> +M: Yixun Lan
> +S: Maintained
> +F: board/thead/th1520_lpi4a/
> +F: configs/th1520_lpi4a_defconfig
> +F: doc/board/thead/lpi4a.rst
> diff --git a/board/thead/th1520_lpi4a/Makefile
> b/board/thead/th1520_lpi4a/Makefile
> new file mode 100644
> index 00..9671b3bbb0
> --- /dev/null
> +++ b/board/thead/th1520_lpi4a/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (c) 2023, Yixun Lan
> +
> +obj-y += board.o
> diff --git a/board/thead/th1520_lpi4a/board.c
> b/board/thead/th1520_lpi4a/board.c
> new file mode 100644
> index 00..378bab098b
> --- /dev/null
> +++ b/board/thead/th1520_lpi4a/board.c
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2023, Yixun Lan
> + *
> + */
> +
> +#include
> +
> +int board_init(void)
> +{
> + enable_caches();
> +
> + return 0;
> +}
> diff --git a/include/configs/th1520_lpi4a.h b/include/configs/th1520_lpi4a.h
> new file mode 100644
> index 00..87496a52c4
> --- /dev/null
> +++ b/include/configs/th1520_lpi4a.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2023 Yixun Lan
> + *
> + */
> +
> +#ifndef __TH1520_LPI4A_H
> +#define __TH1520_LPI4A_H
> +
> +#include
> +
> +#define CFG_SYS_SDRAM_BASE 0x
> +
> +#define UART_BASE 0xffe7014000
> +#define UART_REG_WIDTH 32
why couldn't we get it from dts? just like opensbi.
> +
> +/* Environment options */
> +
> +#define CFG_EXTRA_ENV_SETTINGS \
> + "PS1=[LPi4A]# \0"
> +
> +#endif /* __TH1520_LPI4A_H */
> --
> 2.40.0
>
--
Best Regards
Guo Ren
Re: [RESEND PATCH v1 2/4] riscv: dts: t-head: Add basic device tree for Sipeed Lichee PI 4A board
};
> +
> + timer1: timer@ffefc32014 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc32014 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer2: timer@ffefc32028 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc32028 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer3: timer@ffefc3203c {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xefc3203c 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + uart4: serial@fff7f08000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xf7f08000 0x0 0x4000>;
> + interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@fff7f0c000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0xff 0xf7f0c000 0x0 0x4000>;
> + interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_sclk>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + timer4: timer@c33000 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc33000 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer5: timer@c33014 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc33014 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <21 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer6: timer@c33028 {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc33028 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <22 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + timer7: timer@c3303c {
> + compatible = "snps,dw-apb-timer";
> + reg = <0xff 0xffc3303c 0x0 0x14>;
> + clocks = <&apb_clk>;
> + clock-names = "timer";
> + interrupts = <23 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + ao_gpio0: gpio@f41000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xfff41000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + porte: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <76 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> +
> + ao_gpio1: gpio@f52000 {
> + compatible = "snps,dw-apb-gpio";
> + reg = <0xff 0xfff52000 0x0 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + portf: gpio-controller@0 {
> + compatible = "snps,dw-apb-gpio-port";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <32>;
> + reg = <0>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + interrupts = <55 IRQ_TYPE_LEVEL_HIGH>;
> + };
> + };
> + };
> +};
> --
> 2.40.0
>
--
Best Regards
Guo Ren
