Re: [PATCH 1/1] pico-imx7d: add baseboard SD card boot detect
On Mon, 27 Nov 2023 23:26:08 + (GMT) Szőke Kálmán Benjamin wrote: > It was absolutely conform, i supressed the potentional warning. Once again i > say, i will not remove it, if you do not liket it you can remoce as a > maintainer. My patch is ready and final. Let's do something to improve i.MX > family as a maintainer. I am realy sad to see in last 2-3 years there was no > any significats new features for boards since their initial commits. > Eredeti levél Feladó: Fabio Estevam Dátum: 2023 > november 27 21:39:19Tárgy: Re: [PATCH 1/1] pico-imx7d: add baseboard SD card > boot detectCímzett: Szőke Kálmán Benjamin On Mon, Nov > 27, 2023 at 4:55 PM Szőke Kálmán Benjamin wrote: > > > Unused function parameters should be removed > https://rules.sonarsource.com/c/tag/based-on-misra/RSPEC-1172/ From this same URL: "Exceptions There are some cases when you want to have an unused parameter (usually because the function has to conform to a fixed prototype" which is the case here with your patch, where you need to conform to: int board_mmc_get_env_dev(int devno) Hi, please fix your mailer to wrap lines properly. Hugo Villeneuve.
[PATCH] boot: Fix syntax in fdt_overlay_apply_verbose() error message
From: Hugo Villeneuve
Remove superfluous "did".
Signed-off-by: Hugo Villeneuve
---
boot/fdt_support.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/boot/fdt_support.c b/boot/fdt_support.c
index 5e49078f8c3..b15d07765fe 100644
--- a/boot/fdt_support.c
+++ b/boot/fdt_support.c
@@ -2095,7 +2095,7 @@ int fdt_overlay_apply_verbose(void *fdt, void *fdto)
printf("failed on fdt_overlay_apply(): %s\n",
fdt_strerror(err));
if (!has_symbols) {
- printf("base fdt does did not have a /__symbols__
node\n");
+ printf("base fdt does not have a /__symbols__ node\n");
printf("make sure you've compiled with -@\n");
}
}
base-commit: fb428b61819444b9337075f49c72f326f5d12085
--
2.39.2
Re: [PATCH] MAINTAINERS: Remove non-working address from MAINTAINERS
On Thu, 26 Oct 2023 11:25:19 -0300 Fabio Estevam wrote: > On Mon, Oct 23, 2023 at 1:45 PM Hugo Villeneuve wrote: > > > > From: Hugo Villeneuve > > The Subject does indicate which board it refers to. > > It would be better to have it like: > > imx8mn_smm_s2: Remove non-working address from MAINTAINERS > > Reviewed-by: Fabio Estevam > Hi Fabio, since the change concerns two different boards, that is why I didn't indicate it. If required, I could send it as two separate patches. Hugo.
[PATCH] MAINTAINERS: Remove non-working address from MAINTAINERS
From: Hugo Villeneuve The address ariel.dalessan...@collabora.com is no longer working: A message that you sent could not be delivered to one or more of its recipients. This is a permanent error. The following address(es) failed: ariel.dalessan...@collabora.com host mx.collabora.co.uk [46.235.227.165] SMTP error from remote mail server after RCPT TO:: 550 5.1.1 : Recipient address rejected: undeliverable address: host mail.collabora.co.uk[46.235.227.172] said: 550 5.1.1 : Recipient address rejected: User unknown in local recipient table (in reply to RCPT TO command) Remove this address from MAINTAINERS. Signed-off-by: Hugo Villeneuve --- board/bsh/imx8mn_smm_s2/MAINTAINERS| 1 - board/variscite/imx8mn_var_som/MAINTAINERS | 1 - 2 files changed, 2 deletions(-) diff --git a/board/bsh/imx8mn_smm_s2/MAINTAINERS b/board/bsh/imx8mn_smm_s2/MAINTAINERS index 1de816ca871..c7898278359 100644 --- a/board/bsh/imx8mn_smm_s2/MAINTAINERS +++ b/board/bsh/imx8mn_smm_s2/MAINTAINERS @@ -1,5 +1,4 @@ ARM i.MX8MN BSH SMM S2 BOARDS -M: Ariel D'Alessandro M: Michael Trimarchi S: Maintained F: arch/arm/dts/imx8mn-bsh-smm-s2* diff --git a/board/variscite/imx8mn_var_som/MAINTAINERS b/board/variscite/imx8mn_var_som/MAINTAINERS index 367f72dfe4f..a0fb1546f2f 100644 --- a/board/variscite/imx8mn_var_som/MAINTAINERS +++ b/board/variscite/imx8mn_var_som/MAINTAINERS @@ -1,5 +1,4 @@ ARM i.MX8MN VARISCITE VAR-SOM-MX8MN MODULE -M: Ariel D'Alessandro M: Hugo Villeneuve S: Maintained F: arch/arm/dts/imx8mn-var-som* base-commit: 4655b75335384e040358a2e3e478cc42f32a96c9 prerequisite-patch-id: 046349f916b24300d12c076e4cc3f02d81599e5e -- 2.39.2
Re: [PATCH v3 2/2] imx8mp_evk: Remove unneeded header files
On Thu, 19 Oct 2023 18:51:13 -0300
Fabio Estevam wrote:
> From: Fabio Estevam
>
> Cleanup the file by removing unneeded header files.
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Hugo Villeneuve
> ---
> Changes since v2:
> - Also remove and DECLARE_GLOBAL_DATA_PTR. (Hugo)
>
> board/freescale/imx8mp_evk/imx8mp_evk.c | 13 -
> 1 file changed, 13 deletions(-)
>
> diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
> b/board/freescale/imx8mp_evk/imx8mp_evk.c
> index 42291c958e39..024b46ef8bc2 100644
> --- a/board/freescale/imx8mp_evk/imx8mp_evk.c
> +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
> @@ -3,20 +3,7 @@
> * Copyright 2019 NXP
> */
>
> -#include
> #include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -#include
> -
> -DECLARE_GLOBAL_DATA_PTR;
>
> int board_init(void)
> {
> --
> 2.34.1
>
>
Re: [PATCH v2 1/2] imx8mp_evk: Simplify Ethernet initialization
On Thu, 19 Oct 2023 16:21:54 -0300
Fabio Estevam wrote:
> From: Fabio Estevam
>
> With DM enabled, there is no need for board code to initialize
> the Ethernet interfaces.
>
> The RTL8211FDI Ethernet PHYs have 25MHz oscillator, so there is no
> need to enable the RGMII TX clk output.
>
> Also, there is no need for describing the deprecated phy-reset FEC
> properties, nor passing reset properties to the EQOS interface in
> u-boot.dtsi.
>
> Remove all these unneeded pieces.
>
> Tested both Ethernet interfaces after these changes.
>
> Signed-off-by: Fabio Estevam
Reviewed-by: Hugo Villeneuve
> ---
> Changes since v1:
> - Removed Ethernet related headers. (Hugo)
> - Also removed custom eqos reset properties from u-boot.dtsi.
>
> arch/arm/dts/imx8mp-evk-u-boot.dtsi | 14 -
> board/freescale/imx8mp_evk/imx8mp_evk.c | 28 +
> 2 files changed, 1 insertion(+), 41 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> index 0bf489b46248..51c84383673c 100644
> --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> @@ -137,17 +137,3 @@
> {
> bootph-pre-ram;
> };
> -
> - {
> - reset-gpios = < 22 GPIO_ACTIVE_LOW>;
> - reset-delay-us = <15000>;
> - reset-post-delay-us = <10>;
> -};
> -
> - {
> - phy-reset-gpios = < 2 GPIO_ACTIVE_LOW>;
> - phy-reset-duration = <15>;
> - phy-reset-post-delay = <100>;
> -};
> -
> -
> diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
> b/board/freescale/imx8mp_evk/imx8mp_evk.c
> index a24b8c1d8608..42291c958e39 100644
> --- a/board/freescale/imx8mp_evk/imx8mp_evk.c
> +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
> @@ -7,8 +7,6 @@
> #include
> #include
> #include
> -#include
> -#include
> #include
> #include
> #include
> @@ -20,33 +18,9 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -static void setup_fec(void)
> -{
> - struct iomuxc_gpr_base_regs *gpr =
> - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> -
> - /* Enable RGMII TX clk output */
> - setbits_le32(>gpr[1], BIT(22));
> -}
> -
> -#if CONFIG_IS_ENABLED(NET)
> -int board_phy_config(struct phy_device *phydev)
> -{
> - if (phydev->drv->config)
> - phydev->drv->config(phydev);
> - return 0;
> -}
> -#endif
> -
> int board_init(void)
> {
> - int ret = 0;
> -
> - if (IS_ENABLED(CONFIG_FEC_MXC)) {
> - setup_fec();
> - }
> -
> - return ret;
> + return 0;
> }
>
> int board_late_init(void)
> --
> 2.34.1
>
>
Re: [PATCH v2 2/2] mx8mp_evk: Remove unneeded header files
On Thu, 19 Oct 2023 16:21:55 -0300 Fabio Estevam wrote: > From: Fabio Estevam > > Cleanup the file by removing unneeded header files. > > Signed-off-by: Fabio Estevam > --- > Changes since v1: > - Newly introduced. (Hugo) > > board/freescale/imx8mp_evk/imx8mp_evk.c | 10 -- > 1 file changed, 10 deletions(-) > > diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c > b/board/freescale/imx8mp_evk/imx8mp_evk.c > index 42291c958e39..e62e27db48d9 100644 > --- a/board/freescale/imx8mp_evk/imx8mp_evk.c > +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c > @@ -3,18 +3,8 @@ > * Copyright 2019 NXP > */ > > -#include > #include > -#include > -#include > -#include > #include > -#include > -#include > -#include > -#include > -#include > -#include > > DECLARE_GLOBAL_DATA_PTR; Hi Fabio, after that, do you even need DECLARE_GLOBAL_DATA_PTR and its associated header file? Hugo.
[PATCH] imx8mn-var-som: Simplify FEC initialization
From: Hugo Villeneuve
With DM enabled, there is no need for board code to initialize
the FEC interface.
The ethernet PHYs on the symphony carrier board have a dedicated
crystal/oscillator. If the SOM has the EC configuration option
(onboard ethernet PHY), it also has a dedicated crystal/oscillator.
So in all cases, there is no need to enable the RGMII TX clk output.
This follows a similar change introduced by Fabio Estevam:
Link:
https://lore.kernel.org/u-boot/20231019170441.1610453-1-feste...@gmail.com/
Signed-off-by: Hugo Villeneuve
---
board/variscite/imx8mn_var_som/imx8mn_var_som.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index 61b9455a8f4..994fd4f7058 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -12,7 +12,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -46,20 +45,8 @@ struct var_imx8_eeprom_info {
u8 partnumber2[5];/* Part number 2 */
} __packed;
-static void setup_fec(void)
-{
- struct iomuxc_gpr_base_regs *gpr =
- (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
-
- /* Use 125M anatop REF_CLK1 for ENET1, not from external */
- clrsetbits_le32(>gpr[1], 0x2000, 0);
-}
-
int board_init(void)
{
- if (IS_ENABLED(CONFIG_FEC_MXC))
- setup_fec();
-
return 0;
}
base-commit: 4655b75335384e040358a2e3e478cc42f32a96c9
--
2.39.2
[PATCH] imx8mn_var_som: Add myself to MAINTAINERS
From: Hugo Villeneuve I would like to help maintaining the imx8mn_var_som symphony board. Add myself to MAINTAINERS. Signed-off-by: Hugo Villeneuve --- board/variscite/imx8mn_var_som/MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/board/variscite/imx8mn_var_som/MAINTAINERS b/board/variscite/imx8mn_var_som/MAINTAINERS index 068f807ae69..367f72dfe4f 100644 --- a/board/variscite/imx8mn_var_som/MAINTAINERS +++ b/board/variscite/imx8mn_var_som/MAINTAINERS @@ -1,5 +1,6 @@ ARM i.MX8MN VARISCITE VAR-SOM-MX8MN MODULE M: Ariel D'Alessandro +M: Hugo Villeneuve S: Maintained F: arch/arm/dts/imx8mn-var-som* F: board/variscite/imx8mn_var_som/ base-commit: 4655b75335384e040358a2e3e478cc42f32a96c9 -- 2.39.2
Re: [PATCH] imx8mp_evk: Simplify FEC initialization
On Thu, 19 Oct 2023 14:04:41 -0300
Fabio Estevam wrote:
> From: Fabio Estevam
>
> With DM enabled, there is no need for board code to initialize
> the FEC interface.
>
> The RTL8211FDI Ethernet PHYs have 25MHz oscillator, so there is no
> need to enable the RGMII TX clk output.
>
> Also, there is no need for describing the deprecated phy-reset properties
> in u-boot.dtsi.
>
> Remove all these uneeded pieces.
>
> Signed-off-by: Fabio Estevam
> ---
> arch/arm/dts/imx8mp-evk-u-boot.dtsi | 8
> board/freescale/imx8mp_evk/imx8mp_evk.c | 26 +
> 2 files changed, 1 insertion(+), 33 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> index 43f13a9c22f7..db6bc6a11883 100644
> --- a/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-evk-u-boot.dtsi
> @@ -150,11 +150,3 @@
> reset-delay-us = <15000>;
> reset-post-delay-us = <10>;
> };
> -
> - {
> - phy-reset-gpios = < 2 GPIO_ACTIVE_LOW>;
> - phy-reset-duration = <15>;
> - phy-reset-post-delay = <100>;
> -};
> -
> -
> diff --git a/board/freescale/imx8mp_evk/imx8mp_evk.c
> b/board/freescale/imx8mp_evk/imx8mp_evk.c
> index a24b8c1d8608..2c2b8383c8dc 100644
> --- a/board/freescale/imx8mp_evk/imx8mp_evk.c
> +++ b/board/freescale/imx8mp_evk/imx8mp_evk.c
> @@ -20,33 +20,9 @@
>
> DECLARE_GLOBAL_DATA_PTR;
Hi Fabio,
there is probably some #includes that are no longer necessary after
this change... maybe remove them as well, or in another cleanup patch?
Hugo.
> -static void setup_fec(void)
> -{
> - struct iomuxc_gpr_base_regs *gpr =
> - (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
> -
> - /* Enable RGMII TX clk output */
> - setbits_le32(>gpr[1], BIT(22));
> -}
> -
> -#if CONFIG_IS_ENABLED(NET)
> -int board_phy_config(struct phy_device *phydev)
> -{
> - if (phydev->drv->config)
> - phydev->drv->config(phydev);
> - return 0;
> -}
> -#endif
> -
> int board_init(void)
> {
> - int ret = 0;
> -
> - if (IS_ENABLED(CONFIG_FEC_MXC)) {
> - setup_fec();
> - }
> -
> - return ret;
> + return 0;
> }
>
> int board_late_init(void)
> --
> 2.34.1
>
[PATCH] arm: dts: imx8mn-var-som: Fix broken EEPROM read
From: Hugo Villeneuve
On branch WIP/17Oct2023, the EEPROM can no longer be read:
U-Boot 2023.10-latest (Oct 17 2023 - 15:53:43 -0400)
CPU: Freescale i.MX8MNano Quad rev1.0 at 1200 MHz
Reset cause: POR
Model: Variscite VAR-SOM-MX8MN Symphony evaluation board
var_read_som_eeprom: uclass_get_device_by_of_offset() failed: -19
initcall failed at call 4022207c (err=-19)
Convert EEPROM-related properties to bootph-all so that the EEPROM can
also be read outside of SPL.
Fixes: 9e644284ab81 ("dm: core: Report bootph-pre-ram/sram node as pre-reloc
after relocation")
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index e0caf3179ea..2bbc4a49418 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -39,11 +39,11 @@
};
{
- bootph-pre-ram;
+ bootph-all;
};
_i2c1 {
- bootph-pre-ram;
+ bootph-all;
};
_pmic {
@@ -83,5 +83,5 @@
};
_som {
- bootph-pre-ram;
+ bootph-all;
};
base-commit: e65b5d35c9116485366bb08138043d51220551da
--
2.39.2
[PATCH] imx8mn-var-som: add manufacturer to target description
From: Hugo Villeneuve Add Variscite manufacturer to the IMX8MN_VAR_SOM target menu label as the majority of targets include the manufacturer as part of their menu description/label and it helps when looking for a particular manufacturer/board. Signed-off-by: Hugo Villeneuve --- arch/arm/mach-imx/imx8m/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 3d62d7052e7..5cf862a8eb0 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -249,7 +249,7 @@ config TARGET_PICO_IMX8MQ select IMX8M_LPDDR4 config TARGET_IMX8MN_VAR_SOM - bool "imx8mn_var_som" + bool "Variscite imx8mn_var_som" select BINMAN select IMX8MN select SUPPORT_SPL base-commit: e65b5d35c9116485366bb08138043d51220551da -- 2.39.2
Re: [RESEND PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration
On Wed, 12 Jul 2023 12:42:26 +0200
Stefano Babic wrote:
> Hi Hugo,
>
> On 11.07.23 17:45, Hugo Villeneuve wrote:
> > From: Hugo Villeneuve
> >
> > For SOM with the EC configuration, the ethernet PHY is located on the
> > SOM itself, and connected to the CPU ethernet controller. It has a
> > reset line controlled via GPIO1_IO9. In this configuration, the PHY
> > located on the carrier board is not connected to anything and is
> > therefore not used.
> >
> > For SOM without EC configuration, the ethernet PHY on the carrier
> > board is connected to the CPU ethernet controller. It has a reset line
> > controlled via the GPIO expander PCA9534_IO5.
> >
> > The hardware configuration (EC) is determined at runtime by
> > reading from the SOM EEPROM.
> >
> > To support both hardware configurations (EC and non-EC), adjust/fix
> > the PHY reset gpios according to the hardware configuration
> > read at runtime from the SOM EEPROM. This adjustement is done in
> > U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.
> >
> > Signed-off-by: Hugo Villeneuve
>
> I rebased and applied yesterday
> https://patchwork.ozlabs.org/project/uboot/patch/20230525210228.4164480-6-h...@hugovil.com/,
>
> both are V2. What is supposed to do now ?
>
> Regards,
> Stefano
Hi Stefano,
thank you for that.
I resent V2 a few hours before you applied it since I didn't
receive any feedback up to this point, so you can now simply drop all
[RESEND PATCH v2] of this series.
Hugo.
> > ---
> > arch/arm/dts/imx8mn-var-som-symphony.dts | 4 -
> > .../variscite/imx8mn_var_som/imx8mn_var_som.c | 80 +++
> > configs/imx8mn_var_som_defconfig | 2 +
> > 3 files changed, 82 insertions(+), 4 deletions(-)
> >
> > diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts
> > b/arch/arm/dts/imx8mn-var-som-symphony.dts
> > index 3ed7021a487..5c8e4e81752 100644
> > --- a/arch/arm/dts/imx8mn-var-som-symphony.dts
> > +++ b/arch/arm/dts/imx8mn-var-som-symphony.dts
> > @@ -56,10 +56,6 @@
> > };
> > };
> >
> > - {
> > - reset-gpios = < 5 GPIO_ACTIVE_HIGH>;
> > -};
> > -
> >{
> > clock-frequency = <40>;
> > pinctrl-names = "default";
> > diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
> > b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
> > index a89457e8f57..61b9455a8f4 100644
> > --- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
> > +++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
> > @@ -14,6 +14,7 @@
> > #include
> > #include
> > #include
> > +#include
> > #include
> >
> > DECLARE_GLOBAL_DATA_PTR;
> > @@ -161,4 +162,83 @@ int checkboard(void)
> >
> > #endif /* CONFIG_DISPLAY_BOARDINFO */
> >
> > +static int insert_gpios_prop(void *blob, int node, const char *prop,
> > +unsigned int phandle, u32 gpio, u32 flags)
> > +{
> > + fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio),
> > + cpu_to_fdt32(flags) };
> > + return fdt_setprop(blob, node, prop, , sizeof(val));
> > +}
> > +
> > +static int configure_phy_reset_gpios(void *blob)
> > +{
> > + int node;
> > + int phynode;
> > + int ret;
> > + u32 handle;
> > + u32 gpio;
> > + u32 flags;
> > + char path[1024];
> > + const char *eth_alias = "ethernet0";
> > +
> > + snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4",
> > +fdt_get_alias(blob, eth_alias));
> > +
> > + phynode = fdt_path_offset(blob, path);
> > + if (phynode < 0) {
> > + pr_err("%s(): unable to locate PHY node: %s\n", __func__, path);
> > + return 0;
> > + }
> > +
> > + if (gd_board_type() & VAR_EEPROM_F_ETH) {
> > + snprintf(path, sizeof(path), "%s",
> > +fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */
> > + gpio = 9;
> > + flags = GPIO_ACTIVE_LOW;
> > + } else {
> > + snprintf(path, sizeof(path), "%s/gpio@20",
> > +fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */
> > + gpio = 5;
> > + flags = GPIO_ACTIVE_HIGH;
> > + }
> > +
> > + node = fdt_path_offset(blob, path);
> > + if (node < 0) {
> > + pr_err("%s(): unable to locate GP
[RESEND PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration
From: Hugo Villeneuve
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.
For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.
The hardware configuration (EC) is determined at runtime by
reading from the SOM EEPROM.
To support both hardware configurations (EC and non-EC), adjust/fix
the PHY reset gpios according to the hardware configuration
read at runtime from the SOM EEPROM. This adjustement is done in
U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som-symphony.dts | 4 -
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 80 +++
configs/imx8mn_var_som_defconfig | 2 +
3 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts
b/arch/arm/dts/imx8mn-var-som-symphony.dts
index 3ed7021a487..5c8e4e81752 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony.dts
+++ b/arch/arm/dts/imx8mn-var-som-symphony.dts
@@ -56,10 +56,6 @@
};
};
- {
- reset-gpios = < 5 GPIO_ACTIVE_HIGH>;
-};
-
{
clock-frequency = <40>;
pinctrl-names = "default";
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index a89457e8f57..61b9455a8f4 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -161,4 +162,83 @@ int checkboard(void)
#endif /* CONFIG_DISPLAY_BOARDINFO */
+static int insert_gpios_prop(void *blob, int node, const char *prop,
+unsigned int phandle, u32 gpio, u32 flags)
+{
+ fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio),
+ cpu_to_fdt32(flags) };
+ return fdt_setprop(blob, node, prop, , sizeof(val));
+}
+
+static int configure_phy_reset_gpios(void *blob)
+{
+ int node;
+ int phynode;
+ int ret;
+ u32 handle;
+ u32 gpio;
+ u32 flags;
+ char path[1024];
+ const char *eth_alias = "ethernet0";
+
+ snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4",
+fdt_get_alias(blob, eth_alias));
+
+ phynode = fdt_path_offset(blob, path);
+ if (phynode < 0) {
+ pr_err("%s(): unable to locate PHY node: %s\n", __func__, path);
+ return 0;
+ }
+
+ if (gd_board_type() & VAR_EEPROM_F_ETH) {
+ snprintf(path, sizeof(path), "%s",
+fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */
+ gpio = 9;
+ flags = GPIO_ACTIVE_LOW;
+ } else {
+ snprintf(path, sizeof(path), "%s/gpio@20",
+fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */
+ gpio = 5;
+ flags = GPIO_ACTIVE_HIGH;
+ }
+
+ node = fdt_path_offset(blob, path);
+ if (node < 0) {
+ pr_err("%s(): unable to locate GPIO node: %s\n", __func__,
+ path);
+ return 0;
+ }
+
+ handle = fdt_get_phandle(blob, node);
+ if (handle < 0) {
+ pr_err("%s(): unable to locate GPIO controller handle: %s\n",
+ __func__, path);
+ }
+
+ ret = insert_gpios_prop(blob, phynode, "reset-gpios",
+ handle, gpio, flags);
+ if (ret < 0) {
+ pr_err("%s(): failed to set reset-gpios property\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+ /* Fix U-Boot device tree: */
+ return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_FIXUP */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Fix kernel device tree: */
+ return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
#endif /* CONFIG_SPL_BUILD */
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index e54c20e1531..b346b14ebdd 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -23,9 +23,11 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
CONFIG_SYS_LOAD_ADDR=0x4048
+CONFIG_OF_BOARD_FIXUP=y
CONFIG_FIT=y
CONFIG_FIT
[RESEND PATCH v2 4/5] imx8mn-var-som: read eth MAC address from EEPROM
From: Hugo Villeneuve
Read ethernet MAC address from EEPROM located on the SOM.
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 13 +
arch/arm/mach-imx/imx8m/Kconfig | 1 +
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index 7272fc2b4ca..e0caf3179ea 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -13,6 +13,19 @@
bootph-pre-ram;
};
+_som {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ eth_mac_address: eth-mac-address@19 {
+ reg = <0x19 0x06>;
+ };
+};
+
+ {
+ nvmem-cells = <_mac_address>;
+ nvmem-cell-names = "mac-address";
+};
+
{
bootph-pre-ram;
};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index a940d8a9509..67db3e46ecd 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -248,6 +248,7 @@ config TARGET_IMX8MN_VAR_SOM
select MISC
select I2C_EEPROM
select DM_ETH_PHY
+ select NVMEM
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
--
2.30.2
[RESEND PATCH v2 0/5] imx8mn-var-som: fix ethernet for Variscite symphony board and imx8m nano SOM
From: Hugo Villeneuve Hello, This patch series fixes bugs and add missing features related to the ethernet PHY on Variscite symphony carrier board with an imx8m nano SOM (P/N VAR-SOM-MX8M-NANO). Ethernet functionality is currently broken for the VAR-SOM-MX8M-NANO. Variscite imx8m nano SOM comes in multiple hardware configuration options. One of this hardware configuration option is called EC: EC: Ethernet Controller PHY assembled on SOM For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is therefore not used. For SOM without EC configuration, the ethernet PHY on the carrier board is connected to the CPU ethernet controller. It has a reset line controlled via the GPIO expander PCA9534_IO5. Patch 1 add code to read and display the SOM configuration stored in the SOM EEPROM. Part of this patch was submitted and accepted to the Linux kernel (section that adds the EEPROM to the device tree), so that it will be easier to sync the DT between kernel and U-Boot. Patch 2 fixes bugs with the PHY reset properties. Patch 3 fixes a bug with a missing PHY reset deassert delay (also submitted and accepted to kernel). Patch 4 enables automatic read of PHY MAC address from the SOM EEPROM. Patch 5 is used for auto-detecting at runtime the SOM hardware configuration option related to the PHY (EC), and dynamically adjust the device tree to support both SOM PHY options. I have succesfully tested the changes on a Variscite symphony carrier board with a VAR-SOM-MX8M-NANO having the EC configuration option. Unfortunately, I do not have a VAR-SOM-MX8M-NANO with a non-EC configuration option so I couldn't test it on real hardware, altough I simulated it and confirmed that the device tree fixing seems to be correct by using debug/print statements. Thank you. Link: [v1] https://lore.kernel.org/u-boot/20230501200121.3137519-1-h...@hugovil.com/ Changes for V2: - Resend since I received 0 answers/comments after almost 4 weeks and I have a few minor updates to add: - Update defconfig using savedefconfig - Remove requirement about required patch (now in master) - Update status of patches also sent to the Linux kernel Hugo Villeneuve (5): imx8mn-var-som: read and print SoM infos from eeprom on startup imx8mn-var-som: fix non-applied PHY reset-gpios properties arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay imx8mn-var-som: read eth MAC address from EEPROM imx8mn-var-som: adjust PHY reset gpios according to hardware configuration .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 17 ++ arch/arm/dts/imx8mn-var-som-symphony.dts | 4 - arch/arm/dts/imx8mn-var-som.dtsi | 18 +- arch/arm/mach-imx/imx8m/Kconfig | 4 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 214 ++ configs/imx8mn_var_som_defconfig | 4 + 6 files changed, 256 insertions(+), 5 deletions(-) base-commit: 7876a695468c9bc17a6dc02054da101450468a40 -- 2.30.2
[RESEND PATCH v2 3/5] arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay
From: Hugo Villeneuve
While testing the ethernet interface on a Variscite symphony carrier
board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware
configuration), the ethernet PHY is not detected.
The ADIN1300 datasheet indicate that the "Management interface
active (t4)" state is reached at most 5ms after the reset signal is
deasserted.
The device tree in Variscite custom git repository uses the following
property:
phy-reset-post-delay = <20>;
Add a new MDIO property 'reset-deassert-us' of 20ms to have the same
delay inside the ethphy node. Adding this property fixes the problem
with the PHY detection.
Note that this SOM can also have an Atheros AR8033 PHY. In this case,
a 1ms deassert delay is sufficient. Add a comment to that effect.
Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite
VAR-SOM-MX8M-NANO board")
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som.dtsi | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index dea9eff3f00..4eb578a03fc 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -102,11 +102,17 @@
#address-cells = <1>;
#size-cells = <0>;
- ethphy: ethernet-phy@4 {
+ ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = < 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <1>;
+ /*
+* Deassert delay:
+* ADIN1300 requires 5ms.
+* AR8033 requires 1ms.
+*/
+ reset-deassert-us = <2>;
};
};
};
--
2.30.2
[RESEND PATCH v2 2/5] imx8mn-var-som: fix non-applied PHY reset-gpios properties
From: Hugo Villeneuve
Select DM_ETH_PHY so that the reset-gpios property of the ethphy node
can be used.
Also select DM_PCA953X, which is needed for resetting the
ethernet PHY on the carrier board via the PCA9534 I/O expander.
Commit 4e5114daf9eb ("imx8mn: synchronise device tree with linux") did
synchronise device tree with linux, which in effect removed obsolete
PHY reset properties and replaced them with new mdio DM
properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X.
Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux")
Signed-off-by: Hugo Villeneuve
---
arch/arm/mach-imx/imx8m/Kconfig | 1 +
configs/imx8mn_var_som_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 3450399d6fe..a940d8a9509 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -247,6 +247,7 @@ config TARGET_IMX8MN_VAR_SOM
select IMX8M_DDR4
select MISC
select I2C_EEPROM
+ select DM_ETH_PHY
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index 9de7c91f1da..e54c20e1531 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -77,6 +77,7 @@ CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
--
2.30.2
[RESEND PATCH v2 1/5] imx8mn-var-som: read and print SoM infos from eeprom on startup
From: Hugo Villeneuve
Enable support to read and display configuration/manufacturing infos
from 4Kbit EEPROM located on SOM board.
Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch.
Signed-off-by: Hugo Villeneuve
---
.../dts/imx8mn-var-som-symphony-u-boot.dtsi | 4 +
arch/arm/dts/imx8mn-var-som.dtsi | 10 ++
arch/arm/mach-imx/imx8m/Kconfig | 2 +
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 134 ++
configs/imx8mn_var_som_defconfig | 1 +
5 files changed, 151 insertions(+)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index af80aaea0b8..7272fc2b4ca 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -68,3 +68,7 @@
{
bootph-pre-ram;
};
+
+_som {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index 87b5e23c766..dea9eff3f00 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -11,6 +11,10 @@
model = "Variscite VAR-SOM-MX8MN module";
compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
+ aliases {
+ eeprom-som = _som;
+ };
+
chosen {
stdout-path =
};
@@ -222,6 +226,12 @@
};
};
};
+
+ eeprom_som: eeprom@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
};
{
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 7639439bdc9..3450399d6fe 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -245,6 +245,8 @@ config TARGET_IMX8MN_VAR_SOM
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
+ select MISC
+ select I2C_EEPROM
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index d40f4d01761..a89457e8f57 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -1,11 +1,49 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
+ * Copyright 2018-2020 Variscite Ltd.
+ * Copyright 2023 DimOnOff Inc.
*/
#include
+#include
#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Optional SOM features flags. */
+#define VAR_EEPROM_F_WIFI BIT(0)
+#define VAR_EEPROM_F_ETH BIT(1) /* Ethernet PHY on SOM. */
+#define VAR_EEPROM_F_AUDIO BIT(2)
+#define VAR_EEPROM_F_MX8M_LVDS BIT(3) /* i.MX8MM, i.MX8MN, i.MX8MQ
only */
+#define VAR_EEPROM_F_MX8Q_SOC_ID BIT(3) /* 0 = i.MX8QM, 1 = i.MX8QP */
+#define VAR_EEPROM_F_NAND BIT(4)
+
+#define VAR_IMX8_EEPROM_MAGIC 0x384D /* "8M" */
+
+/* Number of DRAM adjustment tables. */
+#define DRAM_TABLES_NUM 7
+
+struct var_imx8_eeprom_info {
+ u16 magic;
+ u8 partnumber[3]; /* Part number */
+ u8 assembly[10]; /* Assembly number */
+ u8 date[9]; /* Build date */
+ u8 mac[6];/* MAC address */
+ u8 somrev;
+ u8 eeprom_version;
+ u8 features; /* SOM features */
+ u8 dramsize; /* DRAM size */
+ u8 off[DRAM_TABLES_NUM + 1]; /* DRAM table offsets */
+ u8 partnumber2[5];/* Part number 2 */
+} __packed;
static void setup_fec(void)
{
@@ -28,3 +66,99 @@ int board_mmc_get_env_dev(int devno)
{
return devno;
}
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+
+static void display_som_infos(struct var_imx8_eeprom_info *info)
+{
+ char partnumber[sizeof(info->partnumber) +
+ sizeof(info->partnumber2) + 1];
+ char assembly[sizeof(info->assembly) + 1];
+ char date[sizeof(info->date) + 1];
+
+ /* Read first part of P/N. */
+ memcpy(partnumber, info->partnumber, sizeof(info->partnumber));
+
+ /* Read second part of P/N. */
+ if (info->eeprom_version >= 3)
+ memcpy(partnumber + sizeof(info->partnumber), info->partnumber2,
+ sizeof(info->partnumber2));
+
+ memcpy(assembly, info->assembly, sizeof(info->assembly));
+ memcpy(date, info->date, sizeof(info->date));
+
+ /* Make sure strings are null terminated. */
+ partnumber[sizeof(partnumber) - 1] = '\0';
+ assembly[sizeof(assembly) - 1] = '\0';
+ date[sizeof(date) - 1] = '\0';
+
+ printf("SOM board: P/N: %s, Assy: %s, Date: %s\n&qu
[PATCH v2 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration
From: Hugo Villeneuve
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.
For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.
The hardware configuration (EC) is determined at runtime by
reading from the SOM EEPROM.
To support both hardware configurations (EC and non-EC), adjust/fix
the PHY reset gpios according to the hardware configuration
read at runtime from the SOM EEPROM. This adjustement is done in
U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som-symphony.dts | 4 -
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 80 +++
configs/imx8mn_var_som_defconfig | 2 +
3 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts
b/arch/arm/dts/imx8mn-var-som-symphony.dts
index 3ed7021a48..5c8e4e8175 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony.dts
+++ b/arch/arm/dts/imx8mn-var-som-symphony.dts
@@ -56,10 +56,6 @@
};
};
- {
- reset-gpios = < 5 GPIO_ACTIVE_HIGH>;
-};
-
{
clock-frequency = <40>;
pinctrl-names = "default";
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index a89457e8f5..61b9455a8f 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -161,4 +162,83 @@ int checkboard(void)
#endif /* CONFIG_DISPLAY_BOARDINFO */
+static int insert_gpios_prop(void *blob, int node, const char *prop,
+unsigned int phandle, u32 gpio, u32 flags)
+{
+ fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio),
+ cpu_to_fdt32(flags) };
+ return fdt_setprop(blob, node, prop, , sizeof(val));
+}
+
+static int configure_phy_reset_gpios(void *blob)
+{
+ int node;
+ int phynode;
+ int ret;
+ u32 handle;
+ u32 gpio;
+ u32 flags;
+ char path[1024];
+ const char *eth_alias = "ethernet0";
+
+ snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4",
+fdt_get_alias(blob, eth_alias));
+
+ phynode = fdt_path_offset(blob, path);
+ if (phynode < 0) {
+ pr_err("%s(): unable to locate PHY node: %s\n", __func__, path);
+ return 0;
+ }
+
+ if (gd_board_type() & VAR_EEPROM_F_ETH) {
+ snprintf(path, sizeof(path), "%s",
+fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */
+ gpio = 9;
+ flags = GPIO_ACTIVE_LOW;
+ } else {
+ snprintf(path, sizeof(path), "%s/gpio@20",
+fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */
+ gpio = 5;
+ flags = GPIO_ACTIVE_HIGH;
+ }
+
+ node = fdt_path_offset(blob, path);
+ if (node < 0) {
+ pr_err("%s(): unable to locate GPIO node: %s\n", __func__,
+ path);
+ return 0;
+ }
+
+ handle = fdt_get_phandle(blob, node);
+ if (handle < 0) {
+ pr_err("%s(): unable to locate GPIO controller handle: %s\n",
+ __func__, path);
+ }
+
+ ret = insert_gpios_prop(blob, phynode, "reset-gpios",
+ handle, gpio, flags);
+ if (ret < 0) {
+ pr_err("%s(): failed to set reset-gpios property\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+ /* Fix U-Boot device tree: */
+ return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_FIXUP */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Fix kernel device tree: */
+ return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
#endif /* CONFIG_SPL_BUILD */
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index f0e232081f..d8a442d623 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -22,10 +22,12 @@ CONFIG_SPL_SYS_MALLOC_F_LEN=0x2000
CONFIG_SPL=y
CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x4800
CONFIG_SYS_LOAD_ADDR=0x4048
+CONFIG_OF_BOARD_FIXUP=y
CONFIG_SYS_MONITOR_LEN=524288
[PATCH v2 3/5] arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay
From: Hugo Villeneuve
While testing the ethernet interface on a Variscite symphony carrier
board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware
configuration), the ethernet PHY is not detected.
The ADIN1300 datasheet indicate that the "Management interface
active (t4)" state is reached at most 5ms after the reset signal is
deasserted.
The device tree in Variscite custom git repository uses the following
property:
phy-reset-post-delay = <20>;
Add a new MDIO property 'reset-deassert-us' of 20ms to have the same
delay inside the ethphy node. Adding this property fixes the problem
with the PHY detection.
Note that this SOM can also have an Atheros AR8033 PHY. In this case,
a 1ms deassert delay is sufficient. Add a comment to that effect.
Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite
VAR-SOM-MX8M-NANO board")
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som.dtsi | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index dea9eff3f0..4eb578a03f 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -102,11 +102,17 @@
#address-cells = <1>;
#size-cells = <0>;
- ethphy: ethernet-phy@4 {
+ ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = < 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <1>;
+ /*
+* Deassert delay:
+* ADIN1300 requires 5ms.
+* AR8033 requires 1ms.
+*/
+ reset-deassert-us = <2>;
};
};
};
--
2.30.2
[PATCH v2 4/5] imx8mn-var-som: read eth MAC address from EEPROM
From: Hugo Villeneuve
Read ethernet MAC address from EEPROM located on the SOM.
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 13 +
arch/arm/mach-imx/imx8m/Kconfig | 1 +
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index 7272fc2b4c..e0caf3179e 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -13,6 +13,19 @@
bootph-pre-ram;
};
+_som {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ eth_mac_address: eth-mac-address@19 {
+ reg = <0x19 0x06>;
+ };
+};
+
+ {
+ nvmem-cells = <_mac_address>;
+ nvmem-cell-names = "mac-address";
+};
+
{
bootph-pre-ram;
};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index a940d8a950..67db3e46ec 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -248,6 +248,7 @@ config TARGET_IMX8MN_VAR_SOM
select MISC
select I2C_EEPROM
select DM_ETH_PHY
+ select NVMEM
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
--
2.30.2
[PATCH v2 1/5] imx8mn-var-som: read and print SoM infos from eeprom on startup
From: Hugo Villeneuve
Enable support to read and display configuration/manufacturing infos
from 4Kbit EEPROM located on SOM board.
Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch.
Signed-off-by: Hugo Villeneuve
---
.../dts/imx8mn-var-som-symphony-u-boot.dtsi | 4 +
arch/arm/dts/imx8mn-var-som.dtsi | 10 ++
arch/arm/mach-imx/imx8m/Kconfig | 2 +
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 134 ++
configs/imx8mn_var_som_defconfig | 1 +
5 files changed, 151 insertions(+)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index af80aaea0b..7272fc2b4c 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -68,3 +68,7 @@
{
bootph-pre-ram;
};
+
+_som {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index 87b5e23c76..dea9eff3f0 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -11,6 +11,10 @@
model = "Variscite VAR-SOM-MX8MN module";
compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
+ aliases {
+ eeprom-som = _som;
+ };
+
chosen {
stdout-path =
};
@@ -222,6 +226,12 @@
};
};
};
+
+ eeprom_som: eeprom@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
};
{
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 7639439bdc..3450399d6f 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -245,6 +245,8 @@ config TARGET_IMX8MN_VAR_SOM
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
+ select MISC
+ select I2C_EEPROM
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index d40f4d0176..a89457e8f5 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -1,11 +1,49 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
+ * Copyright 2018-2020 Variscite Ltd.
+ * Copyright 2023 DimOnOff Inc.
*/
#include
+#include
#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Optional SOM features flags. */
+#define VAR_EEPROM_F_WIFI BIT(0)
+#define VAR_EEPROM_F_ETH BIT(1) /* Ethernet PHY on SOM. */
+#define VAR_EEPROM_F_AUDIO BIT(2)
+#define VAR_EEPROM_F_MX8M_LVDS BIT(3) /* i.MX8MM, i.MX8MN, i.MX8MQ
only */
+#define VAR_EEPROM_F_MX8Q_SOC_ID BIT(3) /* 0 = i.MX8QM, 1 = i.MX8QP */
+#define VAR_EEPROM_F_NAND BIT(4)
+
+#define VAR_IMX8_EEPROM_MAGIC 0x384D /* "8M" */
+
+/* Number of DRAM adjustment tables. */
+#define DRAM_TABLES_NUM 7
+
+struct var_imx8_eeprom_info {
+ u16 magic;
+ u8 partnumber[3]; /* Part number */
+ u8 assembly[10]; /* Assembly number */
+ u8 date[9]; /* Build date */
+ u8 mac[6];/* MAC address */
+ u8 somrev;
+ u8 eeprom_version;
+ u8 features; /* SOM features */
+ u8 dramsize; /* DRAM size */
+ u8 off[DRAM_TABLES_NUM + 1]; /* DRAM table offsets */
+ u8 partnumber2[5];/* Part number 2 */
+} __packed;
static void setup_fec(void)
{
@@ -28,3 +66,99 @@ int board_mmc_get_env_dev(int devno)
{
return devno;
}
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+
+static void display_som_infos(struct var_imx8_eeprom_info *info)
+{
+ char partnumber[sizeof(info->partnumber) +
+ sizeof(info->partnumber2) + 1];
+ char assembly[sizeof(info->assembly) + 1];
+ char date[sizeof(info->date) + 1];
+
+ /* Read first part of P/N. */
+ memcpy(partnumber, info->partnumber, sizeof(info->partnumber));
+
+ /* Read second part of P/N. */
+ if (info->eeprom_version >= 3)
+ memcpy(partnumber + sizeof(info->partnumber), info->partnumber2,
+ sizeof(info->partnumber2));
+
+ memcpy(assembly, info->assembly, sizeof(info->assembly));
+ memcpy(date, info->date, sizeof(info->date));
+
+ /* Make sure strings are null terminated. */
+ partnumber[sizeof(partnumber) - 1] = '\0';
+ assembly[sizeof(assembly) - 1] = '\0';
+ date[sizeof(date) - 1] = '\0';
+
+ printf("SOM board: P/N: %s, Assy: %s, Date: %s\n"
+
[PATCH v2 2/5] imx8mn-var-som: fix non-applied PHY reset-gpios properties
From: Hugo Villeneuve
Select DM_ETH_PHY so that the reset-gpios property of the ethphy node
can be used.
Also select DM_PCA953X, which is needed for resetting the
ethernet PHY on the carrier board via the PCA9534 I/O expander.
Commit 4e5114daf9eb ("imx8mn: synchronise device tree with linux") did
synchronise device tree with linux, which in effect removed obsolete
PHY reset properties and replaced them with new mdio DM
properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X.
Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux")
Signed-off-by: Hugo Villeneuve
---
arch/arm/mach-imx/imx8m/Kconfig | 1 +
configs/imx8mn_var_som_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 3450399d6f..a940d8a950 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -247,6 +247,7 @@ config TARGET_IMX8MN_VAR_SOM
select IMX8M_DDR4
select MISC
select I2C_EEPROM
+ select DM_ETH_PHY
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index f8bbdb6935..f0e232081f 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -77,6 +77,7 @@ CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_UUU_SUPPORT=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=2
CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
--
2.30.2
[PATCH v2 0/5] imx8mn-var-som: fix ethernet for Variscite symphony board and imx8m nano SOM
From: Hugo Villeneuve Hello, This patch series fixes bugs and add missing features related to the ethernet PHY on Variscite symphony carrier board with an imx8m nano SOM (P/N VAR-SOM-MX8M-NANO). Ethernet functionality is currently broken for the VAR-SOM-MX8M-NANO. Variscite imx8m nano SOM comes in multiple hardware configuration options. One of this hardware configuration option is called EC: EC: Ethernet Controller PHY assembled on SOM For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is therefore not used. For SOM without EC configuration, the ethernet PHY on the carrier board is connected to the CPU ethernet controller. It has a reset line controlled via the GPIO expander PCA9534_IO5. Patch 1 add code to read and display the SOM configuration stored in the SOM EEPROM. Part of this patch was submitted and accepted to the Linux kernel (section that adds the EEPROM to the device tree), so that it will be easier to sync the DT between kernel and U-Boot. Patch 2 fixes bugs with the PHY reset properties. Patch 3 fixes a bug with a missing PHY reset deassert delay (also submitted and accepted to kernel). Patch 4 enables automatic read of PHY MAC address from the SOM EEPROM. Patch 5 is used for auto-detecting at runtime the SOM hardware configuration option related to the PHY (EC), and dynamically adjust the device tree to support both SOM PHY options. I have succesfully tested the changes on a Variscite symphony carrier board with a VAR-SOM-MX8M-NANO having the EC configuration option. Unfortunately, I do not have a VAR-SOM-MX8M-NANO with a non-EC configuration option so I couldn't test it on real hardware, altough I simulated it and confirmed that the device tree fixing seems to be correct by using debug/print statements. Thank you. Link: [v1] https://lore.kernel.org/u-boot/20230501200121.3137519-1-h...@hugovil.com/ Changes for V2: - Resend since I received 0 answers/comments after almost 4 weeks and I have a few minor updates to add: - Update defconfig using savedefconfig - Remove requirement about required patch (now in master) - Update status of patches also sent to the Linux kernel Hugo Villeneuve (5): imx8mn-var-som: read and print SoM infos from eeprom on startup imx8mn-var-som: fix non-applied PHY reset-gpios properties arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay imx8mn-var-som: read eth MAC address from EEPROM imx8mn-var-som: adjust PHY reset gpios according to hardware configuration .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 17 ++ arch/arm/dts/imx8mn-var-som-symphony.dts | 4 - arch/arm/dts/imx8mn-var-som.dtsi | 18 +- arch/arm/mach-imx/imx8m/Kconfig | 4 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 214 ++ configs/imx8mn_var_som_defconfig | 4 + 6 files changed, 256 insertions(+), 5 deletions(-) base-commit: 62df7a39442902a71259568c13a4d496d5a514f4 -- 2.30.2
[PATCH 5/5] imx8mn-var-som: adjust PHY reset gpios according to hardware configuration
From: Hugo Villeneuve
For SOM with the EC configuration, the ethernet PHY is located on the
SOM itself, and connected to the CPU ethernet controller. It has a
reset line controlled via GPIO1_IO9. In this configuration, the PHY
located on the carrier board is not connected to anything and is
therefore not used.
For SOM without EC configuration, the ethernet PHY on the carrier
board is connected to the CPU ethernet controller. It has a reset line
controlled via the GPIO expander PCA9534_IO5.
The hardware configuration (EC) is determined at runtime by
reading from the SOM EEPROM.
To support both hardware configurations (EC and non-EC), adjust/fix
the PHY reset gpios according to the hardware configuration
read at runtime from the SOM EEPROM. This adjustement is done in
U-Boot (OF_BOARD_FIXUP) and kernel (OF_BOARD_SETUP) device trees.
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som-symphony.dts | 4 -
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 80 +++
configs/imx8mn_var_som_defconfig | 2 +
3 files changed, 82 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts
b/arch/arm/dts/imx8mn-var-som-symphony.dts
index 3ed7021a48..5c8e4e8175 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony.dts
+++ b/arch/arm/dts/imx8mn-var-som-symphony.dts
@@ -56,10 +56,6 @@
};
};
- {
- reset-gpios = < 5 GPIO_ACTIVE_HIGH>;
-};
-
{
clock-frequency = <40>;
pinctrl-names = "default";
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index a89457e8f5..61b9455a8f 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -161,4 +162,83 @@ int checkboard(void)
#endif /* CONFIG_DISPLAY_BOARDINFO */
+static int insert_gpios_prop(void *blob, int node, const char *prop,
+unsigned int phandle, u32 gpio, u32 flags)
+{
+ fdt32_t val[3] = { cpu_to_fdt32(phandle), cpu_to_fdt32(gpio),
+ cpu_to_fdt32(flags) };
+ return fdt_setprop(blob, node, prop, , sizeof(val));
+}
+
+static int configure_phy_reset_gpios(void *blob)
+{
+ int node;
+ int phynode;
+ int ret;
+ u32 handle;
+ u32 gpio;
+ u32 flags;
+ char path[1024];
+ const char *eth_alias = "ethernet0";
+
+ snprintf(path, sizeof(path), "%s/mdio/ethernet-phy@4",
+fdt_get_alias(blob, eth_alias));
+
+ phynode = fdt_path_offset(blob, path);
+ if (phynode < 0) {
+ pr_err("%s(): unable to locate PHY node: %s\n", __func__, path);
+ return 0;
+ }
+
+ if (gd_board_type() & VAR_EEPROM_F_ETH) {
+ snprintf(path, sizeof(path), "%s",
+fdt_get_alias(blob, "gpio0")); /* Alias to gpio1 */
+ gpio = 9;
+ flags = GPIO_ACTIVE_LOW;
+ } else {
+ snprintf(path, sizeof(path), "%s/gpio@20",
+fdt_get_alias(blob, "i2c1")); /* Alias to i2c2 */
+ gpio = 5;
+ flags = GPIO_ACTIVE_HIGH;
+ }
+
+ node = fdt_path_offset(blob, path);
+ if (node < 0) {
+ pr_err("%s(): unable to locate GPIO node: %s\n", __func__,
+ path);
+ return 0;
+ }
+
+ handle = fdt_get_phandle(blob, node);
+ if (handle < 0) {
+ pr_err("%s(): unable to locate GPIO controller handle: %s\n",
+ __func__, path);
+ }
+
+ ret = insert_gpios_prop(blob, phynode, "reset-gpios",
+ handle, gpio, flags);
+ if (ret < 0) {
+ pr_err("%s(): failed to set reset-gpios property\n", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_BOARD_FIXUP)
+int board_fix_fdt(void *blob)
+{
+ /* Fix U-Boot device tree: */
+ return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_FIXUP */
+
+#if defined(CONFIG_OF_BOARD_SETUP)
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ /* Fix kernel device tree: */
+ return configure_phy_reset_gpios(blob);
+}
+#endif /* CONFIG_OF_BOARD_SETUP */
+
#endif /* CONFIG_SPL_BUILD */
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index da48ec0a21..0f3d2a0288 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -112,3 +112,5 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
CONFIG_CI_UDC=y
CONFIG_IMX_WATCHDOG=y
CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_OF_BOARD_FIXUP=y
+CONFIG_OF_BOARD_SETUP=y
--
2.30.2
[PATCH 4/5] imx8mn-var-som: read eth MAC address from EEPROM
From: Hugo Villeneuve
Read ethernet MAC address from EEPROM located on the SOM.
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi | 13 +
arch/arm/mach-imx/imx8m/Kconfig | 1 +
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index 7272fc2b4c..e0caf3179e 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -13,6 +13,19 @@
bootph-pre-ram;
};
+_som {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ eth_mac_address: eth-mac-address@19 {
+ reg = <0x19 0x06>;
+ };
+};
+
+ {
+ nvmem-cells = <_mac_address>;
+ nvmem-cell-names = "mac-address";
+};
+
{
bootph-pre-ram;
};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 94f4d584f1..7e5a3e31dd 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -242,6 +242,7 @@ config TARGET_IMX8MN_VAR_SOM
select MISC
select I2C_EEPROM
select DM_ETH_PHY
+ select NVMEM
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
--
2.30.2
[PATCH 3/5] arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay
From: Hugo Villeneuve
While testing the ethernet interface on a Variscite symphony carrier
board using an imx8mn SOM with an onboard ADIN1300 PHY (EC hardware
configuration), the ethernet PHY is not detected.
The ADIN1300 datasheet indicate that the "Management interface
active (t4)" state is reached at most 5ms after the reset signal is
deasserted.
The device tree in Variscite custom git repository uses the following
property:
phy-reset-post-delay = <20>;
Add a new MDIO property 'reset-deassert-us' of 20ms to have the same
delay inside the ethphy node. Adding this property fixes the problem
with the PHY detection.
Note that this SOM can also have an Atheros AR8033 PHY. In this case,
a 1ms deassert delay is sufficient. Add a comment to that effect.
Fixes: c4c1ed68c1e8 ("imx8mn_var_som: Add support for Variscite
VAR-SOM-MX8M-NANO board")
Signed-off-by: Hugo Villeneuve
---
arch/arm/dts/imx8mn-var-som.dtsi | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index dea9eff3f0..4eb578a03f 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -102,11 +102,17 @@
#address-cells = <1>;
#size-cells = <0>;
- ethphy: ethernet-phy@4 {
+ ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
compatible = "ethernet-phy-ieee802.3-c22";
reg = <4>;
reset-gpios = < 9 GPIO_ACTIVE_LOW>;
reset-assert-us = <1>;
+ /*
+* Deassert delay:
+* ADIN1300 requires 5ms.
+* AR8033 requires 1ms.
+*/
+ reset-deassert-us = <2>;
};
};
};
--
2.30.2
[PATCH 2/5] imx8mn-var-som: fix non-applied PHY reset-gpios properties
From: Hugo Villeneuve
Select DM_ETH_PHY so that the reset-gpios property of the ethphy node
can be used.
Also select DM_PCA953X, which is needed for resetting the
ethernet PHY on the carrier board via the PCA9534 I/O expander.
Commit 4e5114daf9eb ("imx8mn: synchronise device tree with linux") did
synchronise device tree with linux, which in effect removed obsolete
PHY reset properties and replaced them with new mdio DM
properties. But the commit didn't activate DM_ETH_PHY or DM_PCA953X.
Fixes: 4e5114daf9eb ("imx8mn: synchronise device tree with linux")
Signed-off-by: Hugo Villeneuve
---
arch/arm/mach-imx/imx8m/Kconfig | 1 +
configs/imx8mn_var_som_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index ec0abb92b8..94f4d584f1 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -241,6 +241,7 @@ config TARGET_IMX8MN_VAR_SOM
select IMX8M_DDR4
select MISC
select I2C_EEPROM
+ select DM_ETH_PHY
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index bb1245bd35..da48ec0a21 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -9,6 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xDE00
CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
CONFIG_DEFAULT_DEVICE_TREE="imx8mn-var-som-symphony"
CONFIG_SPL_TEXT_BASE=0x912000
CONFIG_TARGET_IMX8MN_VAR_SOM=y
--
2.30.2
[PATCH 0/5] imx8mn-var-som: fix ethernet for Variscite symphony board and imx8m nano SOM
From: Hugo Villeneuve Hello, This patch series fixes bugs and add missing features related to the ethernet PHY on Variscite symphony carrier board with an imx8m nano SOM (P/N VAR-SOM-MX8M-NANO). Ethernet functionality is currently broken for the VAR-SOM-MX8M-NANO. Variscite imx8m nano SOM comes in multiple hardware configuration options. One of this hardware configuration option is called EC: EC: Ethernet Controller PHY assembled on SOM For SOM with the EC configuration, the ethernet PHY is located on the SOM itself, and connected to the CPU ethernet controller. It has a reset line controlled via GPIO1_IO9. In this configuration, the PHY located on the carrier board is not connected to anything and is therefore not used. For SOM without EC configuration, the ethernet PHY on the carrier board is connected to the CPU ethernet controller. It has a reset line controlled via the GPIO expander PCA9534_IO5. Patch 1 add code to read and display the SOM configuration stored in the SOM EEPROM. This patch is also submitted to the Linux kernel (section that adds the EEPROM to the device tree), so that it will be easier to sync the DT between kernel and U-Boot. Patch 2 fixes bugs with the PHY reset properties. Patch 3 fixes a bug with a missing PHY reset deassert delay (also submitted to kernel). Patch 4 enables automatic read of PHY MAC address from the SOM EEPROM. Patch 5 is used for auto-detecting at runtime the SOM hardware configuration option related to the PHY (EC), and dynamically adjust the device tree to support both SOM PHY options. This series need the following patch to be applied first: https://lore.kernel.org/u-boot/20230425141935.2324406-1-h...@hugovil.com/ I have succesfully tested the changes on a Variscite symphony carrier board with a VAR-SOM-MX8M-NANO having the EC configuration option. Unfortunately, I do not have a VAR-SOM-MX8M-NANO with a non-EC configuration option so I couldn't test it on real hardware, altough I simulated it and confirmed that the device tree fixing seems to be correct by using debug/print statements. Thank you. Hugo Villeneuve (5): imx8mn-var-som: read and print SoM infos from eeprom on startup imx8mn-var-som: fix non-applied PHY reset-gpios properties arm: dts: imx8mn-var-som: fix PHY detection bug by adding deassert delay imx8mn-var-som: read eth MAC address from EEPROM imx8mn-var-som: adjust PHY reset gpios according to hardware configuration .../dts/imx8mn-var-som-symphony-u-boot.dtsi | 17 ++ arch/arm/dts/imx8mn-var-som-symphony.dts | 4 - arch/arm/dts/imx8mn-var-som.dtsi | 18 +- arch/arm/mach-imx/imx8m/Kconfig | 4 + .../variscite/imx8mn_var_som/imx8mn_var_som.c | 214 ++ configs/imx8mn_var_som_defconfig | 4 + 6 files changed, 256 insertions(+), 5 deletions(-) base-commit: 2e83d560c115d6a6616edc8054fe6be9803f9577 -- 2.30.2
[PATCH 1/5] imx8mn-var-som: read and print SoM infos from eeprom on startup
From: Hugo Villeneuve
Enable support to read and display configuration/manufacturing infos
from 4Kbit EEPROM located on SOM board.
Note: CONFIG_DISPLAY_BOARDINFO is automatically selected for ARM arch.
Signed-off-by: Hugo Villeneuve
---
.../dts/imx8mn-var-som-symphony-u-boot.dtsi | 4 +
arch/arm/dts/imx8mn-var-som.dtsi | 10 ++
arch/arm/mach-imx/imx8m/Kconfig | 2 +
.../variscite/imx8mn_var_som/imx8mn_var_som.c | 134 ++
configs/imx8mn_var_som_defconfig | 1 +
5 files changed, 151 insertions(+)
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index af80aaea0b..7272fc2b4c 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -68,3 +68,7 @@
{
bootph-pre-ram;
};
+
+_som {
+ bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
index 87b5e23c76..dea9eff3f0 100644
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ b/arch/arm/dts/imx8mn-var-som.dtsi
@@ -11,6 +11,10 @@
model = "Variscite VAR-SOM-MX8MN module";
compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
+ aliases {
+ eeprom-som = _som;
+ };
+
chosen {
stdout-path =
};
@@ -222,6 +226,12 @@
};
};
};
+
+ eeprom_som: eeprom@52 {
+ compatible = "atmel,24c04";
+ reg = <0x52>;
+ pagesize = <16>;
+ };
};
{
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index dc51f971d4..ec0abb92b8 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -239,6 +239,8 @@ config TARGET_IMX8MN_VAR_SOM
select IMX8MN
select SUPPORT_SPL
select IMX8M_DDR4
+ select MISC
+ select I2C_EEPROM
config TARGET_KONTRON_PITX_IMX8M
bool "Support Kontron pITX-imx8m"
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index d40f4d0176..a89457e8f5 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -1,11 +1,49 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Collabora Ltd.
+ * Copyright 2018-2020 Variscite Ltd.
+ * Copyright 2023 DimOnOff Inc.
*/
#include
+#include
#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/* Optional SOM features flags. */
+#define VAR_EEPROM_F_WIFI BIT(0)
+#define VAR_EEPROM_F_ETH BIT(1) /* Ethernet PHY on SOM. */
+#define VAR_EEPROM_F_AUDIO BIT(2)
+#define VAR_EEPROM_F_MX8M_LVDS BIT(3) /* i.MX8MM, i.MX8MN, i.MX8MQ
only */
+#define VAR_EEPROM_F_MX8Q_SOC_ID BIT(3) /* 0 = i.MX8QM, 1 = i.MX8QP */
+#define VAR_EEPROM_F_NAND BIT(4)
+
+#define VAR_IMX8_EEPROM_MAGIC 0x384D /* "8M" */
+
+/* Number of DRAM adjustment tables. */
+#define DRAM_TABLES_NUM 7
+
+struct var_imx8_eeprom_info {
+ u16 magic;
+ u8 partnumber[3]; /* Part number */
+ u8 assembly[10]; /* Assembly number */
+ u8 date[9]; /* Build date */
+ u8 mac[6];/* MAC address */
+ u8 somrev;
+ u8 eeprom_version;
+ u8 features; /* SOM features */
+ u8 dramsize; /* DRAM size */
+ u8 off[DRAM_TABLES_NUM + 1]; /* DRAM table offsets */
+ u8 partnumber2[5];/* Part number 2 */
+} __packed;
static void setup_fec(void)
{
@@ -28,3 +66,99 @@ int board_mmc_get_env_dev(int devno)
{
return devno;
}
+
+#if !defined(CONFIG_SPL_BUILD)
+
+#if defined(CONFIG_DISPLAY_BOARDINFO)
+
+static void display_som_infos(struct var_imx8_eeprom_info *info)
+{
+ char partnumber[sizeof(info->partnumber) +
+ sizeof(info->partnumber2) + 1];
+ char assembly[sizeof(info->assembly) + 1];
+ char date[sizeof(info->date) + 1];
+
+ /* Read first part of P/N. */
+ memcpy(partnumber, info->partnumber, sizeof(info->partnumber));
+
+ /* Read second part of P/N. */
+ if (info->eeprom_version >= 3)
+ memcpy(partnumber + sizeof(info->partnumber), info->partnumber2,
+ sizeof(info->partnumber2));
+
+ memcpy(assembly, info->assembly, sizeof(info->assembly));
+ memcpy(date, info->date, sizeof(info->date));
+
+ /* Make sure strings are null terminated. */
+ partnumber[sizeof(partnumber) - 1] = '\0';
+ assembly[sizeof(assembly) - 1] = '\0';
+ date[sizeof(date) - 1] = '\0';
+
+ printf("SOM board: P/N: %s, Assy: %s, Date: %s\n"
+
[PATCH v2] common/Kconfig: fix comments syntax error
From: Hugo Villeneuve Fix comments error in EVENT_DEBUG description: this get usefui -> this to get useful Signed-off-by: Hugo Villeneuve --- common/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/Kconfig b/common/Kconfig index f2783ee65d..0d69e83a33 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -626,7 +626,7 @@ config EVENT_DEBUG bool "Enable event debugging assistance" default y if SANDBOX help - Enable this get usefui features for seeing what is happening with + Enable this to get useful features for seeing what is happening with events, such as event-type names. This adds to the code size of U-Boot so can be turned off for production builds. -- 2.30.2
Re: [PATCH] common/Kconfig: fix comments syntax error
On Tue, 25 Apr 2023 12:00:58 -0600 Simon Glass wrote: > Hi Hugo, > > On Tue, 25 Apr 2023 at 07:46, Hugo Villeneuve wrote: > > > > From: Hugo Villeneuve > > > > Fix comments error in EVENT_DEBUG description: > > usefui -> useful > > > > Signed-off-by: Hugo Villeneuve > > --- > > common/Kconfig | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/common/Kconfig b/common/Kconfig > > index f2783ee65d..8c5b672cdf 100644 > > --- a/common/Kconfig > > +++ b/common/Kconfig > > @@ -626,7 +626,7 @@ config EVENT_DEBUG > > bool "Enable event debugging assistance" > > default y if SANDBOX > > help > > - Enable this get usefui features for seeing what is happening with > > + Enable this get useful features for seeing what is happening with > > I think 'Enable this to get useful' would be better Yes agreed, will resubmit. Thank you. Hugo. > > > events, such as event-type names. This adds to the code size of > > U-Boot so can be turned off for production builds. > > > > -- > > 2.30.2 > > > > Reviewed-by: Simon Glass > > Regards, > Simon
[PATCH] arm: imx8m: remove unused and obsolete board_fix_fdt() in SOC context
From: Hugo Villeneuve
It doesn't seem appropriate for arch/SOC to use a board-level
functionality (CONFIG_OF_BOARD_FIXUP), because this prevents boards
that need to do FDT fixup from using that feature.
Also, this code is completely dead and useless (from comments by
Rasmus Villemoes on the mailing list):
- No in-tree imx8m-based board seems to set CONFIG_OF_BOARD_FIXUP
- The nodes which that function wants to disable don't even exist in
the U-Boot copy of imx8mp.dtsi.
This code was introduced in commit 35bb60787b88. It seems to be some
random import of code from downstream NXP U-Boot, with a commit
message that makes no sense in upstream context.
Signed-off-by: Hugo Villeneuve
---
arch/arm/mach-imx/imx8m/soc.c | 34 --
1 file changed, 34 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index df865e997d..2ec5c3dc43 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -1395,40 +1395,6 @@ usb_modify_speed:
}
#endif
-#ifdef CONFIG_OF_BOARD_FIXUP
-#ifndef CONFIG_SPL_BUILD
-int board_fix_fdt(void *fdt)
-{
- if (is_imx8mpul()) {
- int i = 0;
- int nodeoff, ret;
- const char *status = "disabled";
- static const char * const dsi_nodes[] = {
- "/soc@0/bus@32c0/mipi_dsi@32e6",
- "/soc@0/bus@32c0/lcd-controller@32e8",
- "/dsi-host"
- };
-
- for (i = 0; i < ARRAY_SIZE(dsi_nodes); i++) {
- nodeoff = fdt_path_offset(fdt, dsi_nodes[i]);
- if (nodeoff > 0) {
-set_status:
- ret = fdt_setprop(fdt, nodeoff, "status",
status,
- strlen(status) + 1);
- if (ret == -FDT_ERR_NOSPACE) {
- ret = fdt_increase_size(fdt, 512);
- if (!ret)
- goto set_status;
- }
- }
- }
- }
-
- return 0;
-}
-#endif
-#endif
-
#if !CONFIG_IS_ENABLED(SYSRESET)
void reset_cpu(void)
{
--
2.30.2
Re: Unable to implement board fdt-fixup for imx8m CPU
On Tue, 25 Apr 2023 14:19:14 +0200 Rasmus Villemoes wrote: > On 25/04/2023 04.17, Hugo Villeneuve wrote: > > > I need to detect at runtime the SOM configuration from an EEPROM, and based > > on that information adjust the ethernet PHY property inside the device tree. > > > > I have already done that with success, it works great and as a temporary > > workaround I simply call my own function imx8m_board_fix_fdt() at the end > > of the function board_fix_fdt() of arch/arm/mach-imx/imx8m/soc.c. > > > > But I don't think that a "board" level function should have been put in a > > SOC/arch source file in arch/arm/mach-imx/imx8m/soc.c in the first place. > > If it were not for that, there wouldn't be any need to define something new > > (event or other). > > > > Maybe we should try to remove that board level function from > > arch/arm/mach-imx/imx8m/soc.c and use some other already existing mechanism > > for SOC-level device tree fixups? > > AFAICT, you/we can just nuke that function completely. > > (1) As you say, it's not appropriate for arch/SOC to provide that in the > first place. > (2) It's completely dead and useless code: > (2a) No in-tree imx8m-based board seems to set CONFIG_OF_BOARD_FIXUP > (2b) The nodes which that function wants to disable don't even exist in > the U-Boot copy of imx8mp.dtsi. > > Commit 35bb60787b88 should never have been applied in mainline U-Boot, > it's some random import of code from downstream NXP U-Boot, with a > commit message that makes no sense in upstream context. > > Rasmus Hi Rasmus, I agree with your analysis, and I will submit a patch to remove that code. Thank you. -- Hugo Villeneuve
[PATCH] event: fix comments syntax error
From: Hugo Villeneuve Fix comments syntax error in event description: creasted -> created Signed-off-by: Hugo Villeneuve --- doc/develop/event.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/doc/develop/event.rst b/doc/develop/event.rst index 4ff5934837..e60cbf6569 100644 --- a/doc/develop/event.rst +++ b/doc/develop/event.rst @@ -12,7 +12,7 @@ Rather than using weak functions and direct calls across subsystemss, it is often easier to use an event. An event consists of a type (e.g. EVT_DM_POST_INIT) and some optional data, -in `union event_data`. An event spy can be creasted to watch for events of a +in `union event_data`. An event spy can be created to watch for events of a particular type. When the event is created, it is sent to each spy in turn. -- 2.30.2
[PATCH] common/Kconfig: fix comments syntax error
From: Hugo Villeneuve Fix comments error in EVENT_DEBUG description: usefui -> useful Signed-off-by: Hugo Villeneuve --- common/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/common/Kconfig b/common/Kconfig index f2783ee65d..8c5b672cdf 100644 --- a/common/Kconfig +++ b/common/Kconfig @@ -626,7 +626,7 @@ config EVENT_DEBUG bool "Enable event debugging assistance" default y if SANDBOX help - Enable this get usefui features for seeing what is happening with + Enable this get useful features for seeing what is happening with events, such as event-type names. This adds to the code size of U-Boot so can be turned off for production builds. -- 2.30.2
Re: Unable to implement board fdt-fixup for imx8m CPU
On Mon, 24 Apr 2023 20:09:53 -0500 Adam Ford wrote: > On Mon, Apr 24, 2023 at 4:57 PM Hugo Villeneuve wrote: > > > > On Mon, 24 Apr 2023 15:01:35 -0600 > > Simon Glass wrote: > > > > > Hi Hugo, > > > > > > On Mon, 24 Apr 2023 at 14:53, Hugo Villeneuve wrote: > > > > > > > > Hi, > > > > according to this document: > > > > > > > > doc/develop/driver-model/fdt-fixup.rst > > > > > > > > it is suggested that boards implement the board_fix_fdt() function to > > > > tweak the device tree. I am trying to do just that, but unfortunately I > > > > cannot because the following source file already has an implementation > > > > of board_fix_fdt(): > > > > > > > > arch/arm/mach-imx/imx8m/soc.c > > > > > > > > For all boards using a imx8m CPU, how can we implement board_fix_fdt()? > > > > > > If you enable CONFIG_EVENT you can use EVT_FT_FIXUP to add as many > > > fixup functions as you need. > > > > > > Migration to use that mechanism everywhere hasn't really started, but > > > I think it would be useful. > > > > Hi Simon, > > to be more precise, I need to modify the FDT used by U-Boot to tweak some > > ethernet PHY properties before initializing the ethernet controller. I do > > _not_ need to fix the FDT before booting in the OS. > > Can you modify the -u-boot.dtsi file? You can add additional device > tree stuff to that. I think a few boards do this already specifically > for the Ethernet stuff. > > adam Hi Adam, I need to detect at runtime the SOM configuration from an EEPROM, and based on that information adjust the ethernet PHY property inside the device tree. I have already done that with success, it works great and as a temporary workaround I simply call my own function imx8m_board_fix_fdt() at the end of the function board_fix_fdt() of arch/arm/mach-imx/imx8m/soc.c. But I don't think that a "board" level function should have been put in a SOC/arch source file in arch/arm/mach-imx/imx8m/soc.c in the first place. If it were not for that, there wouldn't be any need to define something new (event or other). Maybe we should try to remove that board level function from arch/arm/mach-imx/imx8m/soc.c and use some other already existing mechanism for SOC-level device tree fixups? Hugo. > > > > With that in mind, do you still think using CONFIG_EVENT is the way to go? > > I am not sure from my reading of the source code because it seems that > > fixup events are called just before booting into the OS. > > > > Thank you, > > Hugo.
Re: Unable to implement board fdt-fixup for imx8m CPU
On Mon, 24 Apr 2023 15:01:35 -0600 Simon Glass wrote: > Hi Hugo, > > On Mon, 24 Apr 2023 at 14:53, Hugo Villeneuve wrote: > > > > Hi, > > according to this document: > > > > doc/develop/driver-model/fdt-fixup.rst > > > > it is suggested that boards implement the board_fix_fdt() function to tweak > > the device tree. I am trying to do just that, but unfortunately I cannot > > because the following source file already has an implementation of > > board_fix_fdt(): > > > > arch/arm/mach-imx/imx8m/soc.c > > > > For all boards using a imx8m CPU, how can we implement board_fix_fdt()? > > If you enable CONFIG_EVENT you can use EVT_FT_FIXUP to add as many > fixup functions as you need. > > Migration to use that mechanism everywhere hasn't really started, but > I think it would be useful. Hi Simon, to be more precise, I need to modify the FDT used by U-Boot to tweak some ethernet PHY properties before initializing the ethernet controller. I do _not_ need to fix the FDT before booting in the OS. With that in mind, do you still think using CONFIG_EVENT is the way to go? I am not sure from my reading of the source code because it seems that fixup events are called just before booting into the OS. Thank you, Hugo.
[PATCH] fdt_support: fix comments syntax error
From: Hugo Villeneuve Fix comments syntax error in fdt_node_offset_by_compat_reg() description: compatiable -> compatible Signed-off-by: Hugo Villeneuve --- common/fdt_support.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index dbceec6f2d..2053fe3bad 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -1486,11 +1486,11 @@ out: } /** - * fdt_node_offset_by_compat_reg: Find a node that matches compatiable and + * fdt_node_offset_by_compat_reg: Find a node that matches compatible and * who's reg property matches a physical cpu address * * @blob: ptr to device tree - * @compat: compatiable string to match + * @compat: compatible string to match * @compat_off: property name * */ -- 2.30.2
[PATCH] boot/Kconfig: fix comments syntax error
From: Hugo Villeneuve Fix comments syntax error in SPL_LOAD_FIT_APPLY_OVERLAY description. Signed-off-by: Hugo Villeneuve --- boot/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/boot/Kconfig b/boot/Kconfig index ad035695a4..9cb7a14628 100644 --- a/boot/Kconfig +++ b/boot/Kconfig @@ -231,7 +231,7 @@ config SPL_LOAD_FIT_APPLY_OVERLAY depends on SPL_LOAD_FIT select OF_LIBFDT_OVERLAY help - The device tree is loaded from the FIT image. Allow the SPL is to + The device tree is loaded from the FIT image. Allow the SPL to also load device-tree overlays from the FIT image an apply them over the device tree. -- 2.30.2
Unable to implement board fdt-fixup for imx8m CPU
Hi, according to this document: doc/develop/driver-model/fdt-fixup.rst it is suggested that boards implement the board_fix_fdt() function to tweak the device tree. I am trying to do just that, but unfortunately I cannot because the following source file already has an implementation of board_fix_fdt(): arch/arm/mach-imx/imx8m/soc.c For all boards using a imx8m CPU, how can we implement board_fix_fdt()? Thank you. -- Hugo Villeneuve
Re: Reading GPIOs with DM_GPIO before device tree is loaded
On Wed, 20 Jul 2022 09:01:01 -0600
Simon Glass wrote:
> Hi Hugo,
>
> On Wed, 20 Jul 2022 at 04:54, Hugo Villeneuve wrote:
> >
> > Hi,
> > in board_early_init_f(), i call a custom function get_som_revision() to
> > read some GPIOs that are used to determine the SOM revision. This function
> > basically sets the iomux, and then uses
> > gpio_request/gpio_direction_input/gpio_get_value functions to read the
> > GPIOs. Then, this SOM revision information is used in
> > board_fit_config_name_match() to decide which device tree to load.
> >
> > This works perfectly fine without CONFIG_DM_GPIO. However, if I enable
> > CONFIG_DM_GPIO, it doesn't work anymore. There is an error when calling
> > gpio_request().
> >
> > What is the correct way to read GPIOs BEFORE any device tree is loaded?
> >
> > My board uses an MX6Q SOM.
> >
> > Here is part of the code I am using:
> >
> >
> > static iomux_v3_cfg_t const boardcfg_pads[] = {
> > MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
> > MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
> > MX6_PAD_DISP0_DAT0__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
> > MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
> > MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
> > };
> >
> > static int som_revision = -1;
> >
> > static const int boardcfg_gpio[] = {
> > IMX_GPIO_NR(5, 9),
> > IMX_GPIO_NR(4, 29),
> > IMX_GPIO_NR(4, 21),
> > IMX_GPIO_NR(1, 27),
> > IMX_GPIO_NR(1, 26),
> > };
> >
> > static void get_som_revision(void)
> > {
> > int i;
> > int rc;
> >
> > som_revision = 0;
> >
> > SETUP_IOMUX_PADS(boardcfg_pads);
> >
> > for (i = 0; i < ARRAY_SIZE(boardcfg_gpio); ++i) {
> > int v;
> >
> > rc = gpio_request(boardcfg_gpio[i], "som-revision-gpio");
> > if (rc) {
> > printf("%s(): gpio request %d failed\n", __func__,
> > i);
> > som_revision = -1;
> > return;
> > }
> >
> > gpio_direction_input(boardcfg_gpio[i]);
> > v = gpio_get_value(boardcfg_gpio[i]);
> >
> > if ((v == 0) || (v == 1))
> > som_revision |= v << i;
> > else {
> > som_revision = -1;
> > return;
> > }
> > }
> > }
> >
> > int board_early_init_f(void)
> > {
> > setup_iomux_uart();
> > get_som_revision();
> >
> > return 0;
> > }
> >
> >
>
> Well driver model needs the device tree to init, for example DM_GPIO
> cannot operate without one unless you are hacking around with
> platdata, which is a bit of a pain.
>
> One option you might have is to use a general DT before relocation,
> then figure out which one you really want to use and select that for
> post relocation. That works better with driver model.
>
> Regards,
> Simon
Hi Simon,
I finally fixed the problem by hacking the mxc_gpio driver and simply enabling
the DM_FLAG_PRE_RELOC flag with this simple patch:
diff --git a/drivers/gpio/mxc_gpio.c b/drivers/gpio/mxc_gpio.c
index 3cc0e7f353..be2bc6d655 100644
--- a/drivers/gpio/mxc_gpio.c
+++ b/drivers/gpio/mxc_gpio.c
@@ -396,6 +396,7 @@ U_BOOT_DRIVER(gpio_mxc) = {
.priv_auto = sizeof(struct mxc_bank_info),
.of_match = mxc_gpio_ids,
.bind = mxc_gpio_bind,
+ .flags = DM_FLAG_PRE_RELOC,
};
DM_DRIVER_ALIAS(gpio_mxc, fsl_imx6q_gpio)
No other changes were required.
However, this is probably not a solution that would get accepted into mainline
U-Boot, or not?
--
Hugo Villeneuve
Reading GPIOs with DM_GPIO before device tree is loaded
Hi,
in board_early_init_f(), i call a custom function get_som_revision() to read
some GPIOs that are used to determine the SOM revision. This function basically
sets the iomux, and then uses gpio_request/gpio_direction_input/gpio_get_value
functions to read the GPIOs. Then, this SOM revision information is used in
board_fit_config_name_match() to decide which device tree to load.
This works perfectly fine without CONFIG_DM_GPIO. However, if I enable
CONFIG_DM_GPIO, it doesn't work anymore. There is an error when calling
gpio_request().
What is the correct way to read GPIOs BEFORE any device tree is loaded?
My board uses an MX6Q SOM.
Here is part of the code I am using:
static iomux_v3_cfg_t const boardcfg_pads[] = {
MX6_PAD_DISP0_DAT15__GPIO5_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT8__GPIO4_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_DISP0_DAT0__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL),
MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
};
static int som_revision = -1;
static const int boardcfg_gpio[] = {
IMX_GPIO_NR(5, 9),
IMX_GPIO_NR(4, 29),
IMX_GPIO_NR(4, 21),
IMX_GPIO_NR(1, 27),
IMX_GPIO_NR(1, 26),
};
static void get_som_revision(void)
{
int i;
int rc;
som_revision = 0;
SETUP_IOMUX_PADS(boardcfg_pads);
for (i = 0; i < ARRAY_SIZE(boardcfg_gpio); ++i) {
int v;
rc = gpio_request(boardcfg_gpio[i], "som-revision-gpio");
if (rc) {
printf("%s(): gpio request %d failed\n", __func__, i);
som_revision = -1;
return;
}
gpio_direction_input(boardcfg_gpio[i]);
v = gpio_get_value(boardcfg_gpio[i]);
if ((v == 0) || (v == 1))
som_revision |= v << i;
else {
som_revision = -1;
return;
}
}
}
int board_early_init_f(void)
{
setup_iomux_uart();
get_som_revision();
return 0;
}
====
Thank you,
Hugo Villeneuve.
Re: [U-Boot] U-Boot and CONFIG_SYS_DAVINCI_BROKEN_ECC
On Sun, 26 Apr 2009 16:56:40 -0700 David Brownell davi...@pacbell.net wrote: On Sunday 26 April 2009, Jean-Christophe PLAGNIOL-VILLARD wrote: Before I submit a patch to remove it from U-Boot GIT (nothing there enables it, and it will nastify 4-bit support), I thought I'd see if anyone knows exactly what software it was trying to emulate. ... maybe add it in the feature-removal-schedule.txt will let people time to explain why they need it Hm... I don't think this is needed. Since there are no users of this code in U-Boot, we can as well remove it without warning. That was my thought. If it were important enough to keep in *this* source base, someone would have submitted some board that uses it. It's badly enough broken that I don't know who would bother using it, though; anyone trying to use it has some kind of (non-Linux?) support nightmare already. no necessarelly the boards Maintainer choose to use the other ECC but part of the U-Boot user may need it. So add it in the removal schedule make sense. We can evenif plan it for the next Release. I wouldn't mind doing that. After my only request will be to use the same ECC as the mainline kernel or if someone explain why he need it add on other ECC algo Right, mainline does not use that broken ECC. I can't figure out who *does* use it, either... We certainly don't use it for the SFFSDR board. Hugo V. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot git] there are non-DM6446 DaVinci chips
On Thu, 16 Apr 2009 23:31:12 -0700 David Brownell davi...@pacbell.net wrote: On Thursday 16 April 2009, Jean-Christophe PLAGNIOL-VILLARD wrote: On 15:44 Sun 12 Apr , David Brownell wrote: could you split it in more logical change please I'll fragment it a bit more, ok. later. @@ -129,10 +122,12 @@ void davinci_enable_uart0(void) lpsc_on(DAVINCI_LPSC_UART0); /* Bringup UART0 out of reset */ - REG(UART0_PWREMU_MGMT) = 0xe003; + REG(UART0_PWREMU_MGMT) = 0x6001; +#ifdef CONFIG_SOC_DM6446 /* Enable UART0 MUX lines */ - REG(PINMUX1) |= PINMUX1_UART0; + REG(PINMUX1) |= DM644X_PINMUX1_UART0; is this the same for all DM6446? and the same question for the I2C and EMAC Yes, that's why I did it that way. PINMUX1 is part of the DM6446 SoC itself, not an FPGA or CPLD, and on other SoCs the bits in that register have different meanings assigned. UART0 might be in PINMUX4, etc. (Or, if by this you meant the PWREMU_MGMT register, that's also a yes ... plus, I looked at docs for other DaVinci chips, and they all have the same definition for that register.) Hi David, I would suggest renaming (or adding) CONFIG_SOC_DM6446 to CONFIG_SOC_DM644x and also introducing CONFIG_SOC_DM35x, so that we don't have to add a switch statement with all the variants inside one family. Hugo V. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/1] ARM DaVinci: Add common peripherals andmodules enable functions.
On Sat, 24 Jan 2009 17:16:58 +0100
Jean-Christophe PLAGNIOL-VILLARD plagn...@jcrosoft.com wrote:
On 09:56 Mon 19 Jan , Hugo Villeneuve wrote:
From: u-boot-boun...@lists.denx.de on behalf of Hugo Villeneuve
Sent: Fri 11/21/2008 2:35 PM
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/1] ARM DaVinci: Add common peripherals
andmodules enable functions.
Taken all the duplicated code for enabling common modules and
apply software workarounds from the board specific code into
common functions. Also added comments explaining the workarounds
(from TI errata documents) and replaced some numerical bit numbers
with more meaningful defines.
Signed-off-by: Hugo Villeneuve hugo.villene...@lyrtech.com
---
board/davinci/common/psc.c | 65 ++
+ board/davinci/common/psc.h |3 ++
board/davinci/dvevm/dvevm.c | 35 +--
board/davinci/schmoogie/schmoogie.c | 37 +--
board/davinci/sffsdr/sffsdr.c | 31 +++--
board/davinci/sonata/sonata.c | 35 +--
6 files changed, 101 insertions(+), 105 deletions(-)
I sent this patch two months ago but I didn´t receive feedback...
Ack
they will be present in the next merge
Best Regards,
J.
Hi Jean-Christophe,
Still no sign of it in the arm tree.
Hugo V.
---
Hugo Villeneuve
www.hugovil.com
---
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Re: [U-Boot] [PATCH 1/1] ARM DaVinci: Add common peripherals andmodules enable functions.
From: u-boot-boun...@lists.denx.de on behalf of Hugo Villeneuve
Sent: Fri 11/21/2008 2:35 PM
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 1/1] ARM DaVinci: Add common peripherals
andmodules enable functions.
Taken all the duplicated code for enabling common modules and apply
software workarounds from the board specific code into common
functions. Also added comments explaining the workarounds
(from TI errata documents) and replaced some numerical bit numbers
with more meaningful defines.
Signed-off-by: Hugo Villeneuve hugo.villene...@lyrtech.com
---
board/davinci/common/psc.c | 65 ++
+ board/davinci/common/psc.h |3 ++
board/davinci/dvevm/dvevm.c | 35 +--
board/davinci/schmoogie/schmoogie.c | 37 +--
board/davinci/sffsdr/sffsdr.c | 31 +++--
board/davinci/sonata/sonata.c | 35 +--
6 files changed, 101 insertions(+), 105 deletions(-)
I sent this patch two months ago but I didn´t receive feedback...
Hugo V.
diff --git a/board/davinci/common/psc.c b/board/davinci/common/psc.c
index d538d51..28e2a4b 100644
--- a/board/davinci/common/psc.c
+++ b/board/davinci/common/psc.c
@@ -26,6 +26,14 @@
#include common.h
#include asm/arch/hardware.h
+#define PINMUX0_EMACEN (1 31)
+#define PINMUX0_AECS5 (1 11)
+#define PINMUX0_AECS4 (1 10)
+
+#define PINMUX1_I2C(1 7)
+#define PINMUX1_UART1 (1 1)
+#define PINMUX1_UART0 (1 0)
+
/*
* The DM6446 includes two separate power domains: Always On and
DSP. The
* Always On power domain is always on when the chip is on. The
Always On @@ -115,3 +123,60 @@ void dsp_on(void)
REG(PSC_GBLCTL) = ~0x1f;
}
#endif /* CONFIG_SYS_USE_DSPLINK */
+
+void davinci_enable_uart0(void)
+{
+ lpsc_on(DAVINCI_LPSC_UART0);
+
+ /* Bringup UART0 out of reset */
+ REG(UART0_PWREMU_MGMT) = 0xe003;
+
+ /* Enable UART0 MUX lines */
+ REG(PINMUX1) |= PINMUX1_UART0;
+}
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+void davinci_enable_emac(void)
+{
+ lpsc_on(DAVINCI_LPSC_EMAC);
+ lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
+ lpsc_on(DAVINCI_LPSC_MDIO);
+
+ /* Enable GIO3.3V cells used for EMAC */
+ REG(VDD3P3V_PWDN) = 0;
+
+ /* Enable EMAC. */
+ REG(PINMUX0) |= PINMUX0_EMACEN;
+}
+#endif
+
+void davinci_enable_i2c(void)
+{
+ lpsc_on(DAVINCI_LPSC_I2C);
+
+ /* Enable I2C pin Mux */
+ REG(PINMUX1) |= PINMUX1_I2C;
+}
+
+void davinci_errata_workarounds(void)
+{
+ /*
+ * Workaround for TMS320DM6446 errata 1.3.22:
+ * PSC: PTSTAT Register Does Not Clear After Warm/Maximum
Reset
+ * Revision(s) Affected: 1.3 and earlier
+ */
+ REG(PSC_SILVER_BULLET) = 0;
+
+ /*
+ * Set the PR_OLD_COUNT bits in the Bus Burst Priority
Register (PBBPR)
+ * as suggested in TMS320DM6446 errata 2.1.2:
+ *
+ * On DM6446 Silicon Revision 2.1 and earlier, under certain
conditions
+ * low priority modules can occupy the bus and prevent high
priority
+ * modules like the VPSS from getting the required DDR2
throughput.
+ * A hex value of 0x20 should provide a good ARM (cache
enabled)
+ * performance and still allow good utilization by the VPSS
or other
+ * modules.
+ */
+ REG(VBPR) = 0x20;
+}
diff --git a/board/davinci/common/psc.h b/board/davinci/common/psc.h
index 6ab2575..b18a185 100644
--- a/board/davinci/common/psc.h
+++ b/board/davinci/common/psc.h
@@ -24,5 +24,8 @@
void lpsc_on(unsigned int id);
void dsp_on(void);
+void davinci_enable_uart0(void);
+void davinci_enable_emac(void);
+void davinci_enable_i2c(void);
#endif /* __PSC_H */
diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c
index abf60b3..f740124 100644
--- a/board/davinci/dvevm/dvevm.c
+++ b/board/davinci/dvevm/dvevm.c
@@ -27,7 +27,6 @@
#include common.h
#include i2c.h
#include asm/arch/hardware.h
-#include asm/arch/emac_defs.h
#include ../common/psc.h
#include ../common/misc.h
@@ -41,16 +40,13 @@ int board_init(void)
/* address of boot parameters */
gd-bd-bi_boot_params = LINUX_BOOT_PARAM_ADDR;
- /* Workaround for TMS320DM6446 errata 1.3.22 */
- REG(PSC_SILVER_BULLET) = 0;
+ /* Configure AEMIF pins (although this should be configured
at boot time
+ * with pull-up/pull-down resistors) */
+ REG(PINMUX0) = 0x0c1f;
+
+ davinci_errata_workarounds();
/* Power on required peripherals */
- lpsc_on(DAVINCI_LPSC_EMAC);
- lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER);
- lpsc_on(DAVINCI_LPSC_MDIO);
- lpsc_on(DAVINCI_LPSC_I2C);
- lpsc_on(DAVINCI_LPSC_UART0);
- lpsc_on(DAVINCI_LPSC_TIMER1);
lpsc_on(DAVINCI_LPSC_GPIO);
#if !defined(CONFIG_SYS_USE_DSPLINK)
@@ -58,24 +54,11 @@ int board_init(void)
dsp_on();
#endif
Re: [U-Boot] FPGA programming driver architecture
On Fri, 12 Dec 2008 15:00:47 -0500 Hugo Villeneuve h...@hugovil.com wrote: Hi, I have written some code to program a FPGA in Linux... Sorry, wrong mailing list :) Hugo V. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] FPGA programming driver architecture
On Sat, 13 Dec 2008 00:10:26 +0100 Wolfgang Denk w...@denx.de wrote: Dear Hugo Villeneuve, In message 20081212150047.e3dbbbef.h...@hugovil.com you wrote: I have written some code to program a FPGA in Linux, for two different types of boards: one uses a serial interface (SPI) and the second a parallel interface. I have been able to sucessfully program both boards. I'm now trying to clean my code and make it more generic, as well as better in line with the Linux driver model. I would also like to include it in the mainline kernel if there is interest. Your lines are way too long, and discussing Linux kernel code is off topic here. You probably have missed the email I sent 30 seconds after having sent the first one stating it was the wrong list. Please read your emails carefully next time. Hugo V. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM DaVinci: Add maintainer informations for SFFSDR board.
ARM DaVinci: Add maintainer informations for SFFSDR board. Signed-off-by: Hugo Villeneuve [EMAIL PROTECTED] --- MAINTAINERS |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 750e374..9c0d6bf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -594,6 +594,10 @@ Greg Ungerer [EMAIL PROTECTED] cm4116 ks8695p cm4148 ks8695p +Hugo Villeneuve [EMAIL PROTECTED] + + SFFSDR ARM926EJS + Richard Woodruff [EMAIL PROTECTED] omap2420h4 ARM1136EJS ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ARM DaVinci: Remove redundant setting of GD_FLG_RELOC for sffsdr board.
ARM DaVinci: Remove redundant setting of GD_FLG_RELOC for sffsdr board. This is no longer necessary now that the GD_FLG_RELOC flag is set for all ARM boards. Signed-off-by: Hugo Villeneuve [EMAIL PROTECTED] --- This is a cleanup following Jean-Christophe Plagniol-Villard patch. board/davinci/sffsdr/sffsdr.c |4 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c index f47ba0f..6e878eb 100644 --- a/board/davinci/sffsdr/sffsdr.c +++ b/board/davinci/sffsdr/sffsdr.c @@ -170,9 +170,5 @@ int misc_init_r(void) if (!eth_hw_init()) printf(Ethernet init failed\n); - /* On this platform, U-Boot is copied in RAM by the UBL, -* so we are always in the relocated state. */ - gd-flags |= GD_FLG_RELOC; - return(0); } ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] fix checkpatch errors
git diff ${GITDIFF_OPTS} ${commit} [EMAIL PROTECTED] wrote:
Dear Georg Schardt,
In message [EMAIL PROTECTED] you wrote:
- create my own testing branch: git branch testing
- switch to this branch: git checkout testing
- copy/modify files
- add the new files with git add board/xilinx/fx12mm/
- commit the changes with git commit -a
- create a patch with git format-patch origin
- check this patch with checkpatch.pl
- fix the errors, commit again, create patch again get 2 patchfiles
I´m not an expert with GIT, but I would suggest the following change to avoid
unnecessary commits:
1. Create my own testing branch: git branch testing
2. Switch to this branch: git checkout testing
3.Copy/modify files
4.Create temporary patch from local changes: git diff temporary.patch
5.Check this patch with checkpatch.pl
6. If errors found: go back to step 3, else go to step 7
7. Add the new/modified files with git add board/xilinx/fx12mm/
8. Commit the changes with git commit -a
9. Create a patch with git format-patch origin
10. Check this patch with checkpatch.pl
Hugo V.
Hugo Villeneuve
Hardware developer | Concepteur matériel
Lyrtech
Phone/Tél. : (1) (418) 877-4644 #2395
Toll-free/Sans frais - Canada USA : (1) (888) 922-4644 #2395
Fax/Téléc. : (1) (418) 877-7710
www.lyrtech.com
Infinite possibilities...TM
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[U-Boot] [PATCH V2] ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c
ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c
Signed-off-by: Hugo Villeneuve [EMAIL PROTECTED]
---
Remove duplicate code in a if/else block in
cpu/arm926ejs/davinci/dp83848.c.
cpu/arm926ejs/davinci/dp83848.c | 27 +++
1 files changed, 7 insertions(+), 20 deletions(-)
diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c
index 59f039b..c71c685 100644
--- a/cpu/arm926ejs/davinci/dp83848.c
+++ b/cpu/arm926ejs/davinci/dp83848.c
@@ -64,29 +64,16 @@ int dp83848_get_link_speed(int phy_addr)
return(0);
/* Speed doesn't matter, there is no setting for it in EMAC... */
- if (tmp DP83848_SPEED) {
- if (tmp DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
+ if (tmp DP83848_DUPLEX) {
+ /* set DM644x EMAC for Full Duplex */
+ emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+ EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
} else {
- if (tmp DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
+ /*set DM644x EMAC for Half Duplex */
+ emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
}
- return(0);
+ return(1);
}
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[U-Boot] [PATCH] ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c
ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c
Signed-off-by: Hugo Villeneuve [EMAIL PROTECTED]
---
Remove duplicate code in a if/else block in
cpu/arm926ejs/davinci/dp83848.c.
cpu/arm926ejs/config.mk |2 +-
cpu/arm926ejs/davinci/dp83848.c | 32 +---
2 files changed, 10 insertions(+), 24 deletions(-)
diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk
index 8db4adb..fc54845 100644
--- a/cpu/arm926ejs/config.mk
+++ b/cpu/arm926ejs/config.mk
@@ -30,5 +30,5 @@ PLATFORM_CPPFLAGS += -march=armv4
# Supply options according to compiler version
#
# =
-PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu)
+PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32)
PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,$(call
cc-option,-malignment-traps,))
diff --git a/cpu/arm926ejs/davinci/dp83848.c b/cpu/arm926ejs/davinci/dp83848.c
index 2aa9ef1..ef77ecb 100644
--- a/cpu/arm926ejs/davinci/dp83848.c
+++ b/cpu/arm926ejs/davinci/dp83848.c
@@ -64,29 +64,15 @@ int dp83848_get_link_speed(int phy_addr)
return(0);
/* Speed doesn't matter, there is no setting for it in EMAC... */
- if (tmp DP83848_SPEED) {
- if (tmp DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
- } else {
- if (tmp DP83848_DUPLEX) {
- /* set DM644x EMAC for Full Duplex */
- emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
- } else {
- /*set DM644x EMAC for Half Duplex */
- emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
- }
-
- return(1);
- }
-
- return(0);
+ if (tmp DP83848_DUPLEX)
+ /* Set DM644x EMAC for Full Duplex */
+ emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE |
+ EMAC_MACCONTROL_FULLDUPLEX_ENABLE;
+ else
+ /* Set DM644x EMAC for Half Duplex */
+ emac-MACCONTROL = EMAC_MACCONTROL_MIIEN_ENABLE;
+
+ return(1);
}
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Re: [U-Boot] [PATCH] ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c
On Mon, 2008-09-01 at 19:16 +0200, Jean-Christophe PLAGNIOL-VILLARD wrote: On 12:00 Mon 01 Sep , Hugo Villeneuve wrote: ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c Signed-off-by: Hugo Villeneuve [EMAIL PROTECTED] --- Remove duplicate code in a if/else block in cpu/arm926ejs/davinci/dp83848.c. cpu/arm926ejs/config.mk |2 +- cpu/arm926ejs/davinci/dp83848.c | 32 +--- 2 files changed, 10 insertions(+), 24 deletions(-) diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk index 8db4adb..fc54845 100644 --- a/cpu/arm926ejs/config.mk +++ b/cpu/arm926ejs/config.mk @@ -30,5 +30,5 @@ PLATFORM_CPPFLAGS += -march=armv4 # Supply options according to compiler version # # = -PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32,-mabi=apcs-gnu) +PLATFORM_CPPFLAGS +=$(call cc-option,-mapcs-32) why do you remove -mabi=apcs-gnu which is unrelated to the commit comment Sorry about that, you can forget it, it was some temporary workaround for an old toolchain :) Hugo V. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [U-Boot-Users] [PATCH 4/4] ARM DaVinci: Standardize names ofdirectories/files
Jean-Christophe PLAGNIOL-VILLARD wrote:
On 15:10 Fri 11 Jul , Hugo Villeneuve wrote:
ARM DaVinci: Standardize names of directories/files.
Signed-off-by: Hugo Villeneuve [EMAIL PROTECTED]
---
Makefile |2 +-
board/davinci/{dv-evm = dvevm}/Makefile |2 +-
board/davinci/{dv-evm = dvevm}/board_init.S |0
board/davinci/{dv-evm = dvevm}/config.mk |0
board/davinci/{dv-evm/dv_board.c = dvevm/dvevm.c} |0
board/davinci/{dv-evm = dvevm}/u-boot.lds |0
board/davinci/schmoogie/Makefile |2 +-
.../davinci/schmoogie/{dv_board.c = schmoogie.c} |0
board/davinci/sonata/Makefile |2 +-
board/davinci/sonata/{dv_board.c = sonata.c} |0
10 files changed, 4 insertions(+), 4 deletions(-)
Applied to u-boot-arm with merge
please check
Everything seems OK.
Hugo V.
Hugo Villeneuve
Hardware developer | Concepteur matériel
Lyrtech
Phone/Tél. : (1) (418) 877-4644 #2395
Toll-free/Sans frais - Canada USA : (1) (888) 922-4644 #2395
Fax/Téléc. : (1) (418) 877-7710
www.lyrtech.com
Infinite possibilities...TM
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