Re: [RFT PATCH 2/2] mmc: meson-gx: set 270 core phase during the identification
On Thu 09 Nov 2023 at 16:49, Viacheslav wrote:
> After running some tests, I've noticed inconsistent behavior with the eMMC:
> On a cold boot (following a shutdown), the eMMC operates as expected within
> U-Boot.
> On a hot reboot (via the kernel's reboot command), the eMMC sometimes (not
> always, but if
> fit in error, next need to do poweroff) does not work:
No sure I understand.
MMC appears to work (passes the ID phases - which was the problem
before) but fitImage (or dtb) you get is not correct out of eMMC read,
is not correct ?
Have you checked the content ? some checksum maybe ?
What does 'mmc info' reports on boot and reboot (when it fails or not) ?
> U-Boot is able to read the dtb file but won't boot kernel completely, or
> U-Boot might fail to read from the eMMC altogether.
>
> This behavior had not occurred before (when the phase was set to 270 on axg).
>
> On Fri, 2023-09-15 at 18:01 +0200, Jerome Brunet wrote:
>> It has been reported that some devices have problems with a 180 degree
>> core phase. Setting 270 helped some of these devices. Other continue to
>> struggle (while it works fine with 180 in Linux ... :sigh:)
>>
>> Poking around the HW, it seems that setting a 270 core phase during the
>> identification, then using 180 for the rest of the operations, helps the
>> device operate correctly.
>>
>> Signed-off-by: Jerome Brunet
>> ---
>> drivers/mmc/meson_gx_mmc.c | 7 ++-
>> 1 file changed, 6 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>> index c6168792cbae..284be2b9dca4 100644
>> --- a/drivers/mmc/meson_gx_mmc.c
>> +++ b/drivers/mmc/meson_gx_mmc.c
>> @@ -54,9 +54,14 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>>
>> /* Clk always on */
>> meson_mmc_clk |= pdata->version->clk_always_on;
>> -meson_mmc_clk |= CLK_CO_PHASE_180;
>> meson_mmc_clk |= CLK_TX_PHASE_000;
>>
>> +/* Core phase according to mode */
>> +if (mmc->selected_mode == MMC_LEGACY)
>> +meson_mmc_clk |= CLK_CO_PHASE_270;
>> +else
>> +meson_mmc_clk |= CLK_CO_PHASE_180;
>> +
>> /* 1GHz / CLK_MAX_DIV = 15,9 MHz */
>> if (mmc->clock > 1600) {
>> clk = SD_EMMC_CLKSRC_DIV2;
[RFT PATCH 2/2] mmc: meson-gx: set 270 core phase during the identification
It has been reported that some devices have problems with a 180 degree
core phase. Setting 270 helped some of these devices. Other continue to
struggle (while it works fine with 180 in Linux ... :sigh:)
Poking around the HW, it seems that setting a 270 core phase during the
identification, then using 180 for the rest of the operations, helps the
device operate correctly.
Signed-off-by: Jerome Brunet
---
drivers/mmc/meson_gx_mmc.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index c6168792cbae..284be2b9dca4 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -54,9 +54,14 @@ static void meson_mmc_config_clock(struct mmc *mmc)
/* Clk always on */
meson_mmc_clk |= pdata->version->clk_always_on;
- meson_mmc_clk |= CLK_CO_PHASE_180;
meson_mmc_clk |= CLK_TX_PHASE_000;
+ /* Core phase according to mode */
+ if (mmc->selected_mode == MMC_LEGACY)
+ meson_mmc_clk |= CLK_CO_PHASE_270;
+ else
+ meson_mmc_clk |= CLK_CO_PHASE_180;
+
/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
if (mmc->clock > 1600) {
clk = SD_EMMC_CLKSRC_DIV2;
--
2.40.1
[RFT PATCH 1/2] mmc: meson-gx: clean up and align on Linux settings
* Remove obsolete comments
* Set core phase to 180 regardless of the SoC like Linux
* Enable always-on clock
AML mmc driver has been working okay(ish) for a few years
The purpose of this patch is to bring u-boot closer to what
Linux is doing
Signed-off-by: Jerome Brunet
---
drivers/mmc/meson_gx_mmc.c | 45 --
drivers/mmc/meson_gx_mmc.h | 9 ++--
2 files changed, 26 insertions(+), 28 deletions(-)
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index fcf4f03d1e24..c6168792cbae 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -17,13 +17,14 @@
#include
#include "meson_gx_mmc.h"
-bool meson_gx_mmc_is_compatible(struct udevice *dev,
- enum meson_gx_mmc_compatible family)
-{
- enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
-
- return compat == family;
-}
+struct meson_gx_mmc_version_data meson_gx_mmc_version[] = {
+ [MMC_COMPATIBLE_V2] = {
+ .clk_always_on = BIT(24),
+ },
+ [MMC_COMPATIBLE_V3] = {
+ .clk_always_on = BIT(28),
+ },
+};
static inline void *get_regbase(const struct mmc *mmc)
{
@@ -44,13 +45,17 @@ static inline void meson_write(struct mmc *mmc, uint32_t
val, int offset)
static void meson_mmc_config_clock(struct mmc *mmc)
{
+ struct meson_mmc_plat *pdata = mmc->priv;
uint32_t meson_mmc_clk = 0;
unsigned int clk, clk_src, clk_div;
if (!mmc->clock)
return;
- /* TOFIX This should use the proper clock taken from DT */
+ /* Clk always on */
+ meson_mmc_clk |= pdata->version->clk_always_on;
+ meson_mmc_clk |= CLK_CO_PHASE_180;
+ meson_mmc_clk |= CLK_TX_PHASE_000;
/* 1GHz / CLK_MAX_DIV = 15,9 MHz */
if (mmc->clock > 1600) {
@@ -62,20 +67,6 @@ static void meson_mmc_config_clock(struct mmc *mmc)
}
clk_div = DIV_ROUND_UP(clk, mmc->clock);
- /*
-* SM1 SoCs doesn't work fine over 50MHz with CLK_CO_PHASE_180
-* If CLK_CO_PHASE_270 is used, it's more stable than other.
-* Other SoCs use CLK_CO_PHASE_180 by default.
-* It needs to find what is a proper value about each SoCs.
-*/
- if (meson_gx_mmc_is_compatible(mmc->dev, MMC_COMPATIBLE_SM1))
- meson_mmc_clk |= CLK_CO_PHASE_270;
- else
- meson_mmc_clk |= CLK_CO_PHASE_180;
-
- /* 180 phase tx clock */
- meson_mmc_clk |= CLK_TX_PHASE_000;
-
/* clock settings */
meson_mmc_clk |= clk_src;
meson_mmc_clk |= clk_div;
@@ -243,6 +234,7 @@ static const struct dm_mmc_ops meson_dm_mmc_ops = {
static int meson_mmc_of_to_plat(struct udevice *dev)
{
+ enum meson_gx_mmc_compatible compat = dev_get_driver_data(dev);
struct meson_mmc_plat *pdata = dev_get_plat(dev);
fdt_addr_t addr;
@@ -251,6 +243,7 @@ static int meson_mmc_of_to_plat(struct udevice *dev)
return -EINVAL;
pdata->regbase = (void *)addr;
+ pdata->version = &meson_gx_mmc_version[compat];
return 0;
}
@@ -277,7 +270,7 @@ static int meson_mmc_probe(struct udevice *dev)
cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 |
MMC_VDD_31_32 | MMC_VDD_165_195;
cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT |
- MMC_MODE_HS_52MHz | MMC_MODE_HS;
+SD_HS | MMC_MODE_HS_52MHz | MMC_MODE_HS;
cfg->f_min = DIV_ROUND_UP(SD_EMMC_CLKSRC_24M, CLK_MAX_DIV);
cfg->f_max = 1; /* 100 MHz */
cfg->b_max = 511; /* max 512 - 1 blocks */
@@ -321,9 +314,9 @@ int meson_mmc_bind(struct udevice *dev)
}
static const struct udevice_id meson_mmc_match[] = {
- { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_GX },
- { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_GX },
- { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_SM1 },
+ { .compatible = "amlogic,meson-gx-mmc", .data = MMC_COMPATIBLE_V2 },
+ { .compatible = "amlogic,meson-axg-mmc", .data = MMC_COMPATIBLE_V3 },
+ { .compatible = "amlogic,meson-sm1-mmc", .data = MMC_COMPATIBLE_V3 },
{ /* sentinel */ }
};
diff --git a/drivers/mmc/meson_gx_mmc.h b/drivers/mmc/meson_gx_mmc.h
index 8974b78f559d..3ec913d1b5ef 100644
--- a/drivers/mmc/meson_gx_mmc.h
+++ b/drivers/mmc/meson_gx_mmc.h
@@ -10,8 +10,8 @@
#include
enum meson_gx_mmc_compatible {
- MMC_COMPATIBLE_GX,
- MMC_COMPATIBLE_SM1,
+ MMC_COMPATIBLE_V2,
+ MMC_COMPATIBLE_V3,
};
#define SDIO_PORT_A0
@@ -84,7 +84,12 @@ enum meson_gx_mmc_compatible {
#define MESON_SD_EMMC_CMD_RSP2 0x64
#define MESON_SD_EMMC_CMD_RSP3 0x68
+struct meson_gx_mm
[RFT PATCH 0/2] mmc: meson-gx: improve MMC reliabilty
Amlogic MMC on the GX (and later) SoCs has been problematic for years, especially with u-boot. Linux has been fairly stable for a few years. It is using a fixed phase setting with Core = 180, Tx = 0 and Rx = 0 (the latter cannot be set starting from the v3 MMC IPs) Still the results were not good with those settings with u-boot, on some sm1 based platforms. U-boot then started using a 270 core phase for sm1 only. This worked for most sm1 platforms but problems persist on others. The proposal with this patchset is to use 270 for the ID phase, 180 otherwise. This works well on the platforms I have tested (Libretech's boards and VIM3L) It would be great if others could test this and report whether this work for them or not. If the results are good, this might be ported to Linux as well (... but the situation is less critical there) Jerome Brunet (2): mmc: meson-gx: clean up and align on Linux settings mmc: meson-gx: set 270 core phase during the identification drivers/mmc/meson_gx_mmc.c | 50 ++ drivers/mmc/meson_gx_mmc.h | 9 +-- 2 files changed, 31 insertions(+), 28 deletions(-) -- 2.40.1
[PATCH] ARM: meson: fixup error on efuse commands return
All `sm efuseread/efusewrite` commands exit with an error, even if the fuse
have actually been dealt with correctly.
This is because the smc call return the size it actually processed but this
result is checked against 0.
Return failure in do_efuse_read/write if the return value of
meson_sm_read/write_efuse() is not the requested size.
Fixes: 52195ba5f579 ("ARM: amlogic: add sm efuse write support and cmd for
read/write efuse")
Signed-off-by: Jerome Brunet
---
arch/arm/mach-meson/sm.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-meson/sm.c b/arch/arm/mach-meson/sm.c
index 6c28c0f5e445..d6eb910689f4 100644
--- a/arch/arm/mach-meson/sm.c
+++ b/arch/arm/mach-meson/sm.c
@@ -82,10 +82,7 @@ ssize_t meson_sm_write_efuse(uintptr_t offset, void *buffer,
size_t size)
smc_call(®s);
- if (regs.regs[0] == 0)
- return -1;
-
- return 0;
+ return regs.regs[0];
}
#define SM_CHIP_ID_LENGTH 119
@@ -222,7 +219,7 @@ static int do_efuse_read(struct cmd_tbl *cmdtp, int flag,
int argc,
address = simple_strtoul(argv[3], NULL, 0);
ret = meson_sm_read_efuse(offset, (void *)address, size);
- if (ret)
+ if (ret != size)
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
@@ -243,7 +240,7 @@ static int do_efuse_write(struct cmd_tbl *cmdtp, int flag,
int argc,
address = simple_strtoul(argv[3], NULL, 0);
ret = meson_sm_write_efuse(offset, (void *)address, size);
- if (ret)
+ if (ret != size)
return CMD_RET_FAILURE;
return CMD_RET_SUCCESS;
--
2.36.1
[PATCH RESEND v2 1/2] arm64: dts: import libretech-cc-v2 from linux v5.10-rc1
Sync the libretech cc v2 device tree from Linux v5.10-rc1
commit 3650b228f83a ("Linux 5.10-rc1")
Signed-off-by: Jerome Brunet
---
arch/arm/dts/Makefile | 1 +
.../dts/meson-gxl-s905x-libretech-cc-v2.dts | 318 ++
2 files changed, 319 insertions(+)
create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b195723f1645..e957820e8e62 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-gxl-s905x-p212.dtb \
meson-gxl-s805x-libretech-ac.dtb \
meson-gxl-s905x-libretech-cc.dtb \
+ meson-gxl-s905x-libretech-cc-v2.dtb \
meson-gxl-s905x-khadas-vim.dtb \
meson-gxl-s905d-libretech-pc.dtb \
meson-gxm-khadas-vim2.dtb \
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
new file mode 100644
index ..675eaa87963e
--- /dev/null
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS.
+ * Author: Jerome Brunet
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include
+
+#include "meson-gxl-s905x.dtsi"
+
+/ {
+ compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x",
+"amlogic,meson-gxl";
+ model = "Libre Computer AML-S905X-CC V2";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = ;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+
+ led-green {
+ color = ;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+
+ vcck: regulator-vcck {
+ compatible = "regulator-fixed";
+ regulator-name = "VCCK";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vcc_card: regulator-vcc_card {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_CARD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vddio_ao3v3>;
+
+ gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc5v: regulator-vcc5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&ao_5v>;
+
+ gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>;
+
[PATCH RESEND v2 2/2] arm64: meson: add support for libretech-cc v2
Add support for the Amlogic based libretech cc version 2. As version 1, it is based on the s905x SoC. Signed-off-by: Jerome Brunet --- ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 ++ board/amlogic/p212/MAINTAINERS| 1 + configs/libretech-cc_v2_defconfig | 82 doc/board/amlogic/index.rst | 117 +- doc/board/amlogic/libretech-cc.rst| 15 ++- 5 files changed, 161 insertions(+), 61 deletions(-) create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi create mode 100644 configs/libretech-cc_v2_defconfig diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi new file mode 100644 index ..8ff5a0ef2ba5 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 BayLibre, SAS. + * Author: Jerome Brunet + */ + +#include "meson-gxl-u-boot.dtsi" diff --git a/board/amlogic/p212/MAINTAINERS b/board/amlogic/p212/MAINTAINERS index cae6994393d7..3d622af29ba9 100644 --- a/board/amlogic/p212/MAINTAINERS +++ b/board/amlogic/p212/MAINTAINERS @@ -7,6 +7,7 @@ F: include/configs/p212.h F: configs/khadas-vim_defconfig F: configs/libretech-ac_defconfig F: configs/libretech-cc_defconfig +F: configs/libretech-cc_v2_defconfig F: configs/p212_defconfig F: doc/board/amlogic/p212.rst F: doc/board/amlogic/libretech-ac.rst diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig new file mode 100644 index ..e71f88edaec6 --- /dev/null +++ b/configs/libretech-cc_v2_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x0100 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x +CONFIG_ENV_SECT_SIZE=0x1 +CONFIG_DM_GPIO=y +CONFIG_MESON_GXL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_IDENT_STRING=" libretech-cc-v2" +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc-v2" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SARADC_MESON=y +CONFIG_DM_KEYBOARD=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=8 +CONFIG_PHY_MESON_GXL=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY=y +CONFIG_MESON_GXL_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_GX_VPU_POWER_DOMAIN=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/doc/board/amlogic/index.rst b/doc/board/amlogic/index.rst index 0e2f8c9aadde..37451028288a 100644 --- a/doc/board/amlogic/index.rst +++ b/doc/board/amlogic/index.rst @@ -10,64 +10,65 @@ An up-do-date matrix is also available on: http://linux-meson.com This matrix concerns the actual source code version. -+---+---+--+--+++-+--+ -| | S905 | S905X| S912 | A113X | S905X2 | S922X | S905X3 | -| | | S805X| S905D| | S905D2 | A311D | S905D3 | -| | | | | | S905Y2 | | | -+===+===+==+==+++=+==+ -| Boards | Odroid-C2 | P212 | Khadas VIM
[PATCH RESEND v2 0/2] arm64: meson: add libretech cc v2 support
This patchset adds support for the Amlogic based libretech cc v2. Like the v1, this revised platform used the s905x SoC. Changes since v1: - Move Makefile change to patch #1 - Amend documentation for libretech cc v2 Jerome Brunet (2): arm64: dts: import libretech-cc-v2 from linux v5.10-rc1 arm64: meson: add support for libretech-cc v2 arch/arm/dts/Makefile | 1 + ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 + .../dts/meson-gxl-s905x-libretech-cc-v2.dts | 318 ++ board/amlogic/p212/MAINTAINERS| 1 + configs/libretech-cc_v2_defconfig | 82 + doc/board/amlogic/index.rst | 117 +++ doc/board/amlogic/libretech-cc.rst| 15 +- 7 files changed, 480 insertions(+), 61 deletions(-) create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts create mode 100644 configs/libretech-cc_v2_defconfig -- 2.28.0
Re: [PATCH v2 0/2] arm64: meson: add libretech cc v2 support
On Fri 06 Nov 2020 at 10:29, Neil Armstrong wrote: > Hi, > > On 06/11/2020 10:07, Jerome Brunet wrote: >> This patchset adds support for the Amlogic based libretech cc v2. >> Like the v1, this revised platform used the s905x SoC. >> >> Changes since v1: >> - Move Makefile change to patch #1 >> - Amend documentation for libretech cc v2 > > Seems you had a patch issue, the following patches are the same as v1 Ugh indeed, sorry about that > > Neil > >> >> Jerome Brunet (2): >> arm64: dts: import libretech-cc-v2 from linux v5.10-rc1 >> arm64: meson: add support for libretech-cc v2 >> >> arch/arm/dts/Makefile | 1 + >> ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 + >> .../dts/meson-gxl-s905x-libretech-cc-v2.dts | 318 ++ >> configs/libretech-cc_v2_defconfig | 82 + >> 4 files changed, 408 insertions(+) >> create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi >> create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts >> create mode 100644 configs/libretech-cc_v2_defconfig >>
[PATCH v2 1/2] arm64: dts: import libretech-cc-v2 from linux v5.10-rc1
Sync the libretech cc v2 device tree from Linux v5.10-rc1
commit 3650b228f83a ("Linux 5.10-rc1")
Signed-off-by: Jerome Brunet
---
.../dts/meson-gxl-s905x-libretech-cc-v2.dts | 318 ++
1 file changed, 318 insertions(+)
create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
new file mode 100644
index ..675eaa87963e
--- /dev/null
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS.
+ * Author: Jerome Brunet
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include
+
+#include "meson-gxl-s905x.dtsi"
+
+/ {
+ compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x",
+"amlogic,meson-gxl";
+ model = "Libre Computer AML-S905X-CC V2";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = ;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+
+ led-green {
+ color = ;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+
+ vcck: regulator-vcck {
+ compatible = "regulator-fixed";
+ regulator-name = "VCCK";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vcc_card: regulator-vcc_card {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_CARD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vddio_ao3v3>;
+
+ gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc5v: regulator-vcc5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&ao_5v>;
+
+ gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>;
+ };
+
+ vddio_ao3v3: regulator-vddio_ao3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+
+ vddio_card: regulator-vddio-card {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_CARD";
+
[PATCH v2 2/2] arm64: meson: add support for libretech-cc v2
Add support for the Amlogic based libretech cc version 2. As version 1, it is based on the s905x SoC. Signed-off-by: Jerome Brunet --- arch/arm/dts/Makefile | 1 + ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 ++ configs/libretech-cc_v2_defconfig | 82 +++ 3 files changed, 90 insertions(+) create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi create mode 100644 configs/libretech-cc_v2_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b195723f1645..e957820e8e62 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s905x-p212.dtb \ meson-gxl-s805x-libretech-ac.dtb \ meson-gxl-s905x-libretech-cc.dtb \ + meson-gxl-s905x-libretech-cc-v2.dtb \ meson-gxl-s905x-khadas-vim.dtb \ meson-gxl-s905d-libretech-pc.dtb \ meson-gxm-khadas-vim2.dtb \ diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi new file mode 100644 index ..8ff5a0ef2ba5 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 BayLibre, SAS. + * Author: Jerome Brunet + */ + +#include "meson-gxl-u-boot.dtsi" diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig new file mode 100644 index ..e71f88edaec6 --- /dev/null +++ b/configs/libretech-cc_v2_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x0100 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x +CONFIG_ENV_SECT_SIZE=0x1 +CONFIG_DM_GPIO=y +CONFIG_MESON_GXL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_IDENT_STRING=" libretech-cc-v2" +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc-v2" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SARADC_MESON=y +CONFIG_DM_KEYBOARD=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=8 +CONFIG_PHY_MESON_GXL=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY=y +CONFIG_MESON_GXL_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_GX_VPU_POWER_DOMAIN=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.28.0
[PATCH v2 0/2] arm64: meson: add libretech cc v2 support
This patchset adds support for the Amlogic based libretech cc v2. Like the v1, this revised platform used the s905x SoC. Changes since v1: - Move Makefile change to patch #1 - Amend documentation for libretech cc v2 Jerome Brunet (2): arm64: dts: import libretech-cc-v2 from linux v5.10-rc1 arm64: meson: add support for libretech-cc v2 arch/arm/dts/Makefile | 1 + ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 + .../dts/meson-gxl-s905x-libretech-cc-v2.dts | 318 ++ configs/libretech-cc_v2_defconfig | 82 + 4 files changed, 408 insertions(+) create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts create mode 100644 configs/libretech-cc_v2_defconfig -- 2.28.0
Re: [PATCH 2/2] arm64: meson: add support for libretech-cc v2
On Thu 05 Nov 2020 at 15:22, Neil Armstrong wrote: > Hi, > > On 05/11/2020 15:15, Jerome Brunet wrote: >> Add support for the Amlogic based libretech cc version 2. >> As version 1, it is based on the s905x SoC. >> >> Signed-off-by: Jerome Brunet >> --- >> arch/arm/dts/Makefile | 1 + >> ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 ++ >> configs/libretech-cc_v2_defconfig | 82 +++ >> 3 files changed, 90 insertions(+) >> create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi >> create mode 100644 configs/libretech-cc_v2_defconfig >> >> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile >> index b195723f1645..e957820e8e62 100644 >> --- a/arch/arm/dts/Makefile >> +++ b/arch/arm/dts/Makefile >> @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_MESON) += \ >> meson-gxl-s905x-p212.dtb \ >> meson-gxl-s805x-libretech-ac.dtb \ >> meson-gxl-s905x-libretech-cc.dtb \ >> +meson-gxl-s905x-libretech-cc-v2.dtb \ >> meson-gxl-s905x-khadas-vim.dtb \ >> meson-gxl-s905d-libretech-pc.dtb \ >> meson-gxm-khadas-vim2.dtb \ > > This should be part of the previous patch > I'm happy to do it but the previous patch is supposed to just be copy of the linux file, isn't it ? If it is not the case, can we just fold the whole thing in a single patch ? >> diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi >> b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi >> new file mode 100644 >> index ..8ff5a0ef2ba5 >> --- /dev/null >> +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi >> @@ -0,0 +1,7 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Copyright (c) 2020 BayLibre, SAS. >> + * Author: Jerome Brunet >> + */ >> + >> +#include "meson-gxl-u-boot.dtsi" >> diff --git a/configs/libretech-cc_v2_defconfig >> b/configs/libretech-cc_v2_defconfig >> new file mode 100644 >> index ..e71f88edaec6 >> --- /dev/null >> +++ b/configs/libretech-cc_v2_defconfig >> @@ -0,0 +1,82 @@ >> +CONFIG_ARM=y >> +CONFIG_ARCH_MESON=y >> +CONFIG_SYS_TEXT_BASE=0x0100 >> +CONFIG_ENV_SIZE=0x2000 >> +CONFIG_ENV_OFFSET=0x >> +CONFIG_ENV_SECT_SIZE=0x1 >> +CONFIG_DM_GPIO=y >> +CONFIG_MESON_GXL=y >> +CONFIG_NR_DRAM_BANKS=1 >> +CONFIG_DEBUG_UART_BASE=0xc81004c0 >> +CONFIG_DEBUG_UART_CLOCK=2400 >> +CONFIG_IDENT_STRING=" libretech-cc-v2" >> +CONFIG_DEBUG_UART=y >> +CONFIG_OF_BOARD_SETUP=y >> +CONFIG_USE_PREBOOT=y >> +CONFIG_PREBOOT="usb start" >> +CONFIG_MISC_INIT_R=y >> +# CONFIG_DISPLAY_CPUINFO is not set >> +# CONFIG_DISPLAY_BOARDINFO is not set >> +# CONFIG_CMD_BDI is not set >> +# CONFIG_CMD_IMI is not set >> +CONFIG_CMD_ADC=y >> +CONFIG_CMD_GPIO=y >> +# CONFIG_CMD_LOADS is not set >> +CONFIG_CMD_MMC=y >> +CONFIG_CMD_SPI=y >> +CONFIG_CMD_USB=y >> +CONFIG_CMD_USB_MASS_STORAGE=y >> +# CONFIG_CMD_SETEXPR is not set >> +CONFIG_CMD_REGULATOR=y >> +CONFIG_OF_CONTROL=y >> +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc-v2" >> +CONFIG_ENV_IS_IN_SPI_FLASH=y >> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y >> +CONFIG_NET_RANDOM_ETHADDR=y >> +CONFIG_SARADC_MESON=y >> +CONFIG_DM_KEYBOARD=y >> +CONFIG_DM_MMC=y >> +CONFIG_MMC_MESON_GX=y >> +CONFIG_MTD=y >> +CONFIG_DM_MTD=y >> +CONFIG_DM_SPI_FLASH=y >> +CONFIG_SPI_FLASH_GIGADEVICE=y >> +CONFIG_PHY_ADDR_ENABLE=y >> +CONFIG_PHY_ADDR=8 >> +CONFIG_PHY_MESON_GXL=y >> +CONFIG_DM_ETH=y >> +CONFIG_ETH_DESIGNWARE=y >> +CONFIG_PHY=y >> +CONFIG_MESON_GXL_USB_PHY=y >> +CONFIG_PINCTRL=y >> +CONFIG_PINCTRL_MESON_GXL=y >> +CONFIG_POWER_DOMAIN=y >> +CONFIG_MESON_GX_VPU_POWER_DOMAIN=y >> +CONFIG_DM_REGULATOR_FIXED=y >> +CONFIG_DM_RESET=y >> +CONFIG_DEBUG_UART_ANNOUNCE=y >> +CONFIG_DEBUG_UART_SKIP_INIT=y >> +CONFIG_MESON_SERIAL=y >> +CONFIG_SPI=y >> +CONFIG_DM_SPI=y >> +CONFIG_MESON_SPIFC=y >> +CONFIG_USB=y >> +CONFIG_DM_USB=y >> +CONFIG_USB_XHCI_HCD=y >> +CONFIG_USB_XHCI_DWC3=y >> +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y >> +CONFIG_USB_DWC3=y >> +# CONFIG_USB_DWC3_GADGET is not set >> +CONFIG_USB_KEYBOARD=y >> +CONFIG_USB_GADGET=y >> +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e >> +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada >> +CONFIG_USB_GADGET_DWC2_OTG=y >> +CONFIG_USB_GADGET_DOWNLOAD=y >> +CONFIG_DM_VIDEO=y >> +# CONFIG_VIDEO_BPP8 is not set >> +# CONFIG_VIDEO_BPP16 is not set >> +CONFIG_SYS_WHITE_ON_BLACK=y >> +CONFIG_VIDEO_MESON=y >> +CONFIG_VIDEO_DT_SIMPLEFB=y >> +CONFIG_OF_LIBFDT_OVERLAY=y >> > > And can you also update : > doc/board/amlogic/libretech-cc.rst > doc/board/amlogic/index.rst > and > board/amlogic/p212/MAINTAINERS > > Thanks, > Neil
[PATCH 2/2] arm64: meson: add support for libretech-cc v2
Add support for the Amlogic based libretech cc version 2. As version 1, it is based on the s905x SoC. Signed-off-by: Jerome Brunet --- arch/arm/dts/Makefile | 1 + ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 ++ configs/libretech-cc_v2_defconfig | 82 +++ 3 files changed, 90 insertions(+) create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi create mode 100644 configs/libretech-cc_v2_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b195723f1645..e957820e8e62 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -159,6 +159,7 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s905x-p212.dtb \ meson-gxl-s805x-libretech-ac.dtb \ meson-gxl-s905x-libretech-cc.dtb \ + meson-gxl-s905x-libretech-cc-v2.dtb \ meson-gxl-s905x-khadas-vim.dtb \ meson-gxl-s905d-libretech-pc.dtb \ meson-gxm-khadas-vim2.dtb \ diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi new file mode 100644 index ..8ff5a0ef2ba5 --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 BayLibre, SAS. + * Author: Jerome Brunet + */ + +#include "meson-gxl-u-boot.dtsi" diff --git a/configs/libretech-cc_v2_defconfig b/configs/libretech-cc_v2_defconfig new file mode 100644 index ..e71f88edaec6 --- /dev/null +++ b/configs/libretech-cc_v2_defconfig @@ -0,0 +1,82 @@ +CONFIG_ARM=y +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x0100 +CONFIG_ENV_SIZE=0x2000 +CONFIG_ENV_OFFSET=0x +CONFIG_ENV_SECT_SIZE=0x1 +CONFIG_DM_GPIO=y +CONFIG_MESON_GXL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_IDENT_STRING=" libretech-cc-v2" +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905x-libretech-cc-v2" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SARADC_MESON=y +CONFIG_DM_KEYBOARD=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_ADDR_ENABLE=y +CONFIG_PHY_ADDR=8 +CONFIG_PHY_MESON_GXL=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY=y +CONFIG_MESON_GXL_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_GX_VPU_POWER_DOMAIN=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3=y +# CONFIG_USB_DWC3_GADGET is not set +CONFIG_USB_KEYBOARD=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e +CONFIG_USB_GADGET_PRODUCT_NUM=0xfada +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USB_GADGET_DOWNLOAD=y +CONFIG_DM_VIDEO=y +# CONFIG_VIDEO_BPP8 is not set +# CONFIG_VIDEO_BPP16 is not set +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.28.0
[PATCH 1/2] arm64: dts: import libretech-cc-v2 from linux v5.10-rc1
Sync the libretech cc v2 device tree from Linux v5.10-rc1
commit 3650b228f83a ("Linux 5.10-rc1")
Signed-off-by: Jerome Brunet
---
.../dts/meson-gxl-s905x-libretech-cc-v2.dts | 318 ++
1 file changed, 318 insertions(+)
create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
diff --git a/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
new file mode 100644
index ..675eaa87963e
--- /dev/null
+++ b/arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 BayLibre, SAS.
+ * Author: Jerome Brunet
+ */
+
+/dts-v1/;
+
+#include
+#include
+#include
+
+#include "meson-gxl-s905x.dtsi"
+
+/ {
+ compatible = "libretech,aml-s905x-cc-v2", "amlogic,s905x",
+"amlogic,meson-gxl";
+ model = "Libre Computer AML-S905X-CC V2";
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-blue {
+ color = ;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIODV_24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+
+ led-green {
+ color = ;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+
+ vcck: regulator-vcck {
+ compatible = "regulator-fixed";
+ regulator-name = "VCCK";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+ vcc_card: regulator-vcc_card {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_CARD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vddio_ao3v3>;
+
+ gpio = <&gpio GPIOCLK_1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc5v: regulator-vcc5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&ao_5v>;
+
+ gpio = <&gpio GPIOH_3 GPIO_OPEN_DRAIN>;
+ };
+
+ vddio_ao3v3: regulator-vddio_ao3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&ao_5v>;
+ regulator-always-on;
+ };
+
+
+ vddio_card: regulator-vddio-card {
+ compatible = "regulator-gpio";
+ regulator-name = "VDDIO_CARD";
+
[PATCH 0/2] arm64: meson: add libretech cc v2 support
This patchset adds support for the Amlogic based libretech cc v2. Like the v1, this revised platform used the s905x SoC. Jerome Brunet (2): arm64: dts: import libretech-cc-v2 from linux v5.10-rc1 arm64: meson: add support for libretech-cc v2 arch/arm/dts/Makefile | 1 + ...eson-gxl-s905x-libretech-cc-v2-u-boot.dtsi | 7 + .../dts/meson-gxl-s905x-libretech-cc-v2.dts | 318 ++ configs/libretech-cc_v2_defconfig | 82 + 4 files changed, 408 insertions(+) create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905x-libretech-cc-v2.dts create mode 100644 configs/libretech-cc_v2_defconfig -- 2.28.0
[PATCH] edid: investigate dtd from cea861 extension if necessary
If no valid detailed timing can be found in the edid base block, check the
detailed timing provided in the cea861 extension block, if any.
Reported-by: Da Xue
Tested-by: Da Xue
Signed-off-by: Jerome Brunet
---
common/edid.c | 72 +++
1 file changed, 49 insertions(+), 23 deletions(-)
diff --git a/common/edid.c b/common/edid.c
index 553ab8fd01a1..7dd0c924c24a 100644
--- a/common/edid.c
+++ b/common/edid.c
@@ -169,6 +169,33 @@ static bool cea_is_hdmi_vsdb_present(struct
edid_cea861_info *info)
return false;
}
+bool edid_get_dtd_timing_validate(struct edid_monitor_descriptor *desc,
+ unsigned int dtd_count,
+ struct display_timing *timing,
+ bool (*mode_valid)(void *priv,
+const struct
display_timing *timing),
+ void *mode_valid_priv)
+{
+ bool timing_done = false;
+ int i;
+
+ for (i = 0; i < dtd_count; i++, desc++) {
+ if (desc->zero_flag_1 != 0) {
+ decode_timing((u8 *)desc, timing);
+ if (mode_valid)
+ timing_done = mode_valid(mode_valid_priv,
+timing);
+ else
+ timing_done = true;
+
+ if (timing_done)
+ break;
+ }
+ }
+
+ return timing_done;
+}
+
int edid_get_timing_validate(u8 *buf, int buf_size,
struct display_timing *timing,
int *panel_bits_per_colourp,
@@ -177,8 +204,9 @@ int edid_get_timing_validate(u8 *buf, int buf_size,
void *mode_valid_priv)
{
struct edid1_info *edid = (struct edid1_info *)buf;
+ struct edid_cea861_info *info = NULL;
+ struct edid_monitor_descriptor *desc;
bool timing_done;
- int i;
if (buf_size < sizeof(*edid) || edid_check_info(edid)) {
debug("%s: Invalid buffer\n", __func__);
@@ -190,24 +218,27 @@ int edid_get_timing_validate(u8 *buf, int buf_size,
return -ENOENT;
}
- /* Look for detailed timing */
- timing_done = false;
- for (i = 0; i < 4; i++) {
- struct edid_monitor_descriptor *desc;
+ desc = edid->monitor_details.descriptor;
+ timing_done = edid_get_dtd_timing_validate(desc, 4, timing,
+ mode_valid, mode_valid_priv);
- desc = &edid->monitor_details.descriptor[i];
- if (desc->zero_flag_1 != 0) {
- decode_timing((u8 *)desc, timing);
- if (mode_valid)
- timing_done = mode_valid(mode_valid_priv,
-timing);
- else
- timing_done = true;
+ if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) {
+ info = (struct edid_cea861_info *)(buf + sizeof(*edid));
- if (timing_done)
- break;
- }
+ if (info->extension_tag != EDID_CEA861_EXTENSION_TAG)
+ info = NULL;
+ }
+
+ /* Check CEA861 info block for timing if don't have one yet */
+ if (info && !timing_done && info->dtd_offset) {
+ unsigned int dtd_count = EDID_CEA861_DTD_COUNT(*info);
+
+ desc = (struct edid_monitor_descriptor *)((u8 *)info +
+ info->dtd_offset);
+ timing_done = edid_get_dtd_timing_validate(desc, dtd_count,
timing,
+ mode_valid,
mode_valid_priv);
}
+
if (!timing_done)
return -EINVAL;
@@ -225,13 +256,8 @@ int edid_get_timing_validate(u8 *buf, int buf_size,
}
timing->hdmi_monitor = false;
- if (edid->extension_flag && (buf_size >= EDID_EXT_SIZE)) {
- struct edid_cea861_info *info =
- (struct edid_cea861_info *)(buf + sizeof(*edid));
-
- if (info->extension_tag == EDID_CEA861_EXTENSION_TAG)
- timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info);
- }
+ if (info)
+ timing->hdmi_monitor = cea_is_hdmi_vsdb_present(info);
return 0;
}
--
2.28.0
Re: [PATCH] ARM: dts: add missing meson-gxl-s805x-libretech-ac-u-boot.dtsi file
On Wed 15 Apr 2020 at 17:58, Neil Armstrong wrote:
> The libretech-ac u-boot.dtsi file is missing to enabled DT nodes changes
> to enable Video output on U-Boot.
>
> Fixes: 671b1db8f8 ("arm64: dts: meson-gx: vpu should be probed before
> relocation")
> Reported-by: Jerome Brunet
> Signed-off-by: Neil Armstrong
Thanks
Tested-by: Jerome Brunet
> ---
> arch/arm/dts/meson-gxl-s805x-libretech-ac-u-boot.dtsi | 7 +++
> 1 file changed, 7 insertions(+)
> create mode 100644 arch/arm/dts/meson-gxl-s805x-libretech-ac-u-boot.dtsi
>
> diff --git a/arch/arm/dts/meson-gxl-s805x-libretech-ac-u-boot.dtsi
> b/arch/arm/dts/meson-gxl-s805x-libretech-ac-u-boot.dtsi
> new file mode 100644
> index 00..c35158d7e9
> --- /dev/null
> +++ b/arch/arm/dts/meson-gxl-s805x-libretech-ac-u-boot.dtsi
> @@ -0,0 +1,7 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2019 BayLibre, SAS.
> + * Author: Neil Armstrong
> + */
> +
> +#include "meson-gx-u-boot.dtsi"
[PATCH v3 4/6] arm64: dts: meson: sync dt and bindings from v5.6-rc2
Sync the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2")
The only exception to this is the mmc pinctrl pin bias of gxl SoC family.
This is a fix which found its way to u-boot but not Linux yet.
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
arch/arm/dts/meson-axg-s400.dts | 70 ++-
arch/arm/dts/meson-axg.dtsi | 273 --
arch/arm/dts/meson-g12-common.dtsi| 478 ++
arch/arm/dts/meson-g12.dtsi | 398 +++
arch/arm/dts/meson-g12a-sei510.dts| 64 +++
arch/arm/dts/meson-g12a-u200.dts | 54 ++
arch/arm/dts/meson-g12a.dtsi | 33 +-
arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 25 +
arch/arm/dts/meson-g12b-odroid-n2.dts | 2 +-
arch/arm/dts/meson-g12b.dtsi | 26 +-
arch/arm/dts/meson-gx.dtsi| 87 +++-
arch/arm/dts/meson-gxbb-nanopi-k2.dts | 26 +-
arch/arm/dts/meson-gxbb-odroidc2.dts | 100 +++-
arch/arm/dts/meson-gxbb-p200.dts | 9 +-
arch/arm/dts/meson-gxbb-p201.dts | 2 +-
arch/arm/dts/meson-gxbb-p20x.dtsi | 9 +-
arch/arm/dts/meson-gxbb.dtsi | 118 -
arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 2 +-
arch/arm/dts/meson-gxl-s905x-khadas-vim.dts | 20 +-
arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 26 +-
arch/arm/dts/meson-gxl-s905x-p212.dtsi| 10 +-
arch/arm/dts/meson-gxl.dtsi | 76 ++-
arch/arm/dts/meson-gxm-khadas-vim2.dts| 71 +--
arch/arm/dts/meson-gxm.dtsi | 39 +-
arch/arm/dts/meson-khadas-vim3.dtsi | 7 +
arch/arm/dts/meson-sm1-sei610.dts | 236 -
arch/arm/dts/meson-sm1.dtsi | 356 +
include/dt-bindings/clock/axg-audio-clkc.h| 10 +
include/dt-bindings/clock/gxbb-aoclkc.h | 7 +
include/dt-bindings/clock/gxbb-clkc.h | 21 +
include/dt-bindings/gpio/meson-gxbb-gpio.h| 8 +-
include/dt-bindings/gpio/meson-gxl-gpio.h | 8 +-
.../reset/amlogic,meson-axg-audio-arb.h | 2 +
.../reset/amlogic,meson-axg-reset.h | 3 +-
.../reset/amlogic,meson-g12a-audio-reset.h| 15 +
.../reset/amlogic,meson-gxbb-reset.h | 51 +-
36 files changed, 2119 insertions(+), 623 deletions(-)
create mode 100644 arch/arm/dts/meson-g12.dtsi
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
index 18778ada7bd3..4cd2d5951822 100644
--- a/arch/arm/dts/meson-axg-s400.dts
+++ b/arch/arm/dts/meson-axg-s400.dts
@@ -60,7 +60,7 @@
serial1 = &uart_A;
};
- linein: audio-codec@0 {
+ linein: audio-codec-0 {
#sound-dai-cells = <0>;
compatible = "everest,es7241";
VDDA-supply = <&vcc_3v3>;
@@ -70,7 +70,7 @@
sound-name-prefix = "Linein";
};
- lineout: audio-codec@1 {
+ lineout: audio-codec-1 {
#sound-dai-cells = <0>;
compatible = "everest,es7154";
VDD-supply = <&vcc_3v3>;
@@ -79,14 +79,14 @@
sound-name-prefix = "Lineout";
};
- spdif_dit: audio-codec@2 {
+ spdif_dit: audio-codec-2 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
status = "okay";
sound-name-prefix = "DIT";
};
- dmics: audio-codec@3 {
+ dmics: audio-codec-3 {
#sound-dai-cells = <0>;
compatible = "dmic-codec";
num-channels = <7>;
@@ -95,6 +95,13 @@
sound-name-prefix = "MIC";
};
+ spdif_dir: audio-codec-4 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dir";
+ status = "okay";
+ sound-name-prefix = "DIR";
+ };
+
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
@@ -249,6 +256,9 @@
"TODDR_A IN 2", "TDMIN_C OUT",
"TODDR_B IN 2", "TDMIN_C OUT",
"TODDR_C IN 2", "TDMIN_C OUT",
+ "TODDR_A IN 3", "SPDIFIN Capture",
+ "TODDR_B IN 3", "SPDIFIN Capture",
+ "TODDR_C IN 3", "SPDIFIN Capture",
"TODDR_A IN 4", "PDM Capture",
"
[PATCH v3 5/6] arm64: dts: meson: import libretech-pc from linux v5.6-rc2
Sync the libretech-pc device tree from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2")
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
arch/arm/dts/meson-gx-libretech-pc.dtsi | 375 ++
arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 16 +
arch/arm/dts/meson-gxl-s905d.dtsi | 12 +
arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 +++
4 files changed, 465 insertions(+)
create mode 100644 arch/arm/dts/meson-gx-libretech-pc.dtsi
create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc.dts
create mode 100644 arch/arm/dts/meson-gxl-s905d.dtsi
create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc.dts
diff --git a/arch/arm/dts/meson-gx-libretech-pc.dtsi
b/arch/arm/dts/meson-gx-libretech-pc.dtsi
new file mode 100644
index ..248b018c83d5
--- /dev/null
+++ b/arch/arm/dts/meson-gx-libretech-pc.dtsi
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 BayLibre SAS.
+ * Author: Jerome Brunet
+ */
+
+/* Libretech Amlogic GX PC form factor - AKA: Tartiflette */
+
+#include
+#include
+
+/ {
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+
+ update-button {
+ label = "update";
+ linux,code = ;
+ press-threshold-microvolt = <130>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+ status = "disabled";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ power-button {
+ label = "power";
+ linux,code = ;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green {
+ color = ;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
+
+ blue {
+ color = ;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+ };
+
+ vcc_card: regulator-vcc_card {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_CARD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vddio_ao3v3>;
+
+ gpio = <&gpio GPIODV_4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
[PATCH v3 2/6] mmc: meson-gx: enable input clocks
Until now, the mmc clock was left in a good enough state by the ROM code to be used by the controller. However on some SoC, if the ROM code finds a bootloader on USB or SPI, it might leave the MMC clock in state the controller cannot work with. Enable the input clocks provided to the mmc controller. While the u-boot mmc controller driver is not doing fancy settings like the Linux, it at least needs to make these clocks are running. Reviewed-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/mmc/meson_gx_mmc.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index b5f5122b1b7b..86c1a7164a93 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -241,12 +242,23 @@ static int meson_mmc_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct mmc *mmc = &pdata->mmc; struct mmc_config *cfg = &pdata->cfg; + struct clk_bulk clocks; uint32_t val; + int ret; + #ifdef CONFIG_PWRSEQ struct udevice *pwr_dev; - int ret; #endif + /* Enable the clocks feeding the MMC controller */ + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 | MMC_VDD_31_32 | MMC_VDD_165_195; cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | -- 2.24.1
[PATCH v3 6/6] arm64: dts: meson: add libretech-pc support
Add support for the Amlogic based libretech-pc platform. This platform comes with 2 variant, based on the s905d or s912 SoC. Acked-by: Neil Armstrong Signed-off-by: Jerome Brunet --- arch/arm/dts/Makefile | 2 + .../meson-gxl-s905d-libretech-pc-u-boot.dtsi | 7 ++ .../meson-gxm-s912-libretech-pc-u-boot.dtsi | 7 ++ configs/libretech-s905d-pc_defconfig | 73 +++ configs/libretech-s912-pc_defconfig | 73 +++ 5 files changed, 162 insertions(+) create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi create mode 100644 configs/libretech-s905d-pc_defconfig create mode 100644 configs/libretech-s912-pc_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 9c593b2c986a..cfe1b7849f46 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -147,7 +147,9 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s805x-libretech-ac.dtb \ meson-gxl-s905x-libretech-cc.dtb \ meson-gxl-s905x-khadas-vim.dtb \ + meson-gxl-s905d-libretech-pc.dtb \ meson-gxm-khadas-vim2.dtb \ + meson-gxm-s912-libretech-pc.dtb \ meson-axg-s400.dtb \ meson-g12a-u200.dtb \ meson-g12a-sei510.dtb \ diff --git a/arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi b/arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi new file mode 100644 index ..c35158d7e9ee --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong + */ + +#include "meson-gx-u-boot.dtsi" diff --git a/arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi b/arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi new file mode 100644 index ..c35158d7e9ee --- /dev/null +++ b/arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong + */ + +#include "meson-gx-u-boot.dtsi" diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig new file mode 100644 index ..7e0c95872a62 --- /dev/null +++ b/configs/libretech-s905d-pc_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="q200" +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x0100 +CONFIG_MESON_GXL=y +CONFIG_ENV_SIZE=0x1 +CONFIG_ENV_OFFSET=0x +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_ENV_SECT_SIZE=0x1 +CONFIG_IDENT_STRING=" libretech-s905d-pc" +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905d-libretech-pc" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SARADC_MESON=y +CONFIG_DM_GPIO=y +CONFIG_DM_KEYBOARD=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY=y +CONFIG_MESON_GXL_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_GX_VPU_POWER_DOMAIN=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3=y +CONFIG_USB_KEYBOARD=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig new file mode 100644 index ..5f4ee329e276 --- /dev/null +++ b/configs/libretech-s912-pc_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_SYS_BOARD="q200" +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x0100 +CONFIG_MESON_GXM=y +CONFIG_ENV_SIZE=0x1 +CONFIG_ENV_OFFSET=0x +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_ENV_SECT_SIZE=0x1 +CONFIG_IDENT_STRING=" libretech-s912-pc" +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +# C
[PATCH v3 3/6] clk: meson: reset mmc clock on probe
On some SoCs, depending on the boot device, the MMC clock block may be
left in a weird state by the ROM code, in which no decent clock may be
provided. Reset the related register to make sure a sane MMC clock is
ready for the controller.
Reviewed-by: Neil Armstrong
Tested-by: Anand Moon
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 7 +++
drivers/clk/meson/g12a.c | 7 +++
drivers/clk/meson/gxbb.c | 7 +++
3 files changed, 21 insertions(+)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 7035b59a1379..4b0028d04bf6 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -291,6 +291,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+* Depending on the boot src, the state of the MMC clock might
+* be different. Reset it to make sure we won't get stuck
+*/
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk-axg: probed\n");
return 0;
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 686d94ebfe85..9e6beca94ac3 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -977,6 +977,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+* Depending on the boot src, the state of the MMC clock might
+* be different. Reset it to make sure we won't get stuck
+*/
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk-g12a: probed\n");
return 0;
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index e781e08d9d5d..5ef4dd794d52 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -887,6 +887,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+* Depending on the boot src, the state of the MMC clock might
+* be different. Reset it to make sure we won't get stuck
+*/
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk: probed\n");
return 0;
--
2.24.1
[PATCH v3 1/6] dt-bindings: leds: import common led bindings from linux v5.5
Import the common leds bindings definition from linux
d5226fa6dbae ("Linux 5.5")
Reviewed-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
include/dt-bindings/leds/common.h | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 include/dt-bindings/leds/common.h
diff --git a/include/dt-bindings/leds/common.h
b/include/dt-bindings/leds/common.h
new file mode 100644
index ..9e1256a7c1bf
--- /dev/null
+++ b/include/dt-bindings/leds/common.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides macros for the common LEDs device tree bindings.
+ *
+ * Copyright (C) 2015, Samsung Electronics Co., Ltd.
+ * Author: Jacek Anaszewski
+ *
+ * Copyright (C) 2019 Jacek Anaszewski
+ */
+
+#ifndef __DT_BINDINGS_LEDS_H
+#define __DT_BINDINGS_LEDS_H
+
+/* External trigger type */
+#define LEDS_TRIG_TYPE_EDGE0
+#define LEDS_TRIG_TYPE_LEVEL 1
+
+/* Boost modes */
+#define LEDS_BOOST_OFF 0
+#define LEDS_BOOST_ADAPTIVE1
+#define LEDS_BOOST_FIXED 2
+
+/* Standard LED colors */
+#define LED_COLOR_ID_WHITE 0
+#define LED_COLOR_ID_RED 1
+#define LED_COLOR_ID_GREEN 2
+#define LED_COLOR_ID_BLUE 3
+#define LED_COLOR_ID_AMBER 4
+#define LED_COLOR_ID_VIOLET5
+#define LED_COLOR_ID_YELLOW6
+#define LED_COLOR_ID_IR7
+#define LED_COLOR_ID_MAX 8
+
+/* Standard LED functions */
+#define LED_FUNCTION_ACTIVITY "activity"
+#define LED_FUNCTION_ALARM "alarm"
+#define LED_FUNCTION_BACKLIGHT "backlight"
+#define LED_FUNCTION_BLUETOOTH "bluetooth"
+#define LED_FUNCTION_BOOT "boot"
+#define LED_FUNCTION_CPU "cpu"
+#define LED_FUNCTION_CAPSLOCK "capslock"
+#define LED_FUNCTION_CHARGING "charging"
+#define LED_FUNCTION_DEBUG "debug"
+#define LED_FUNCTION_DISK "disk"
+#define LED_FUNCTION_DISK_ACTIVITY "disk-activity"
+#define LED_FUNCTION_DISK_ERR "disk-err"
+#define LED_FUNCTION_DISK_READ "disk-read"
+#define LED_FUNCTION_DISK_WRITE "disk-write"
+#define LED_FUNCTION_FAULT "fault"
+#define LED_FUNCTION_FLASH "flash"
+#define LED_FUNCTION_HEARTBEAT "heartbeat"
+#define LED_FUNCTION_INDICATOR "indicator"
+#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight"
+#define LED_FUNCTION_LAN "lan"
+#define LED_FUNCTION_MAIL "mail"
+#define LED_FUNCTION_MTD "mtd"
+#define LED_FUNCTION_MICMUTE "micmute"
+#define LED_FUNCTION_MUTE "mute"
+#define LED_FUNCTION_NUMLOCK "numlock"
+#define LED_FUNCTION_PANIC "panic"
+#define LED_FUNCTION_PROGRAMMING "programming"
+#define LED_FUNCTION_POWER "power"
+#define LED_FUNCTION_RX "rx"
+#define LED_FUNCTION_SD "sd"
+#define LED_FUNCTION_SCROLLLOCK "scrolllock"
+#define LED_FUNCTION_STANDBY "standby"
+#define LED_FUNCTION_STATUS "status"
+#define LED_FUNCTION_TORCH "torch"
+#define LED_FUNCTION_TX "tx"
+#define LED_FUNCTION_USB "usb"
+#define LED_FUNCTION_WAN "wan"
+#define LED_FUNCTION_WLAN "wlan"
+#define LED_FUNCTION_WPS "wps"
+
+#endif /* __DT_BINDINGS_LEDS_H */
--
2.24.1
[PATCH v3 0/6] arm64: meson: add libretech-pc support
Add libretech PC platform support. This platform comes in 2 variants, one with the s905d and the other s912. While working on these boards, I've found a problem related the mmc clock. In some cases, the ROM code will leave the mmc clocks in such a weird state that any access to the mmc controller would lock the device. Making sure the MMC clocks are properly reset and enabled is enough to solve the problem. I have also synced all amlogic supported dts. Since I had to update the gx dsti files, it made sense to update the dts as well. This is done to keep things coherent even if it is not the original purpose of this series. Changes since v2: - actually rebase on master Changes since v1: - Split dt sync, libretech-pc import and config addition. - Rebase on master (... not really) Jerome Brunet (6): dt-bindings: leds: import common led bindings from linux v5.5 mmc: meson-gx: enable input clocks clk: meson: reset mmc clock on probe arm64: dts: meson: sync dt and bindings from v5.6-rc2 arm64: dts: meson: import libretech-pc from linux v5.6-rc2 arm64: dts: meson: add libretech-pc support arch/arm/dts/Makefile | 2 + arch/arm/dts/meson-axg-s400.dts | 70 ++- arch/arm/dts/meson-axg.dtsi | 273 -- arch/arm/dts/meson-g12-common.dtsi| 478 ++ arch/arm/dts/meson-g12.dtsi | 398 +++ arch/arm/dts/meson-g12a-sei510.dts| 64 +++ arch/arm/dts/meson-g12a-u200.dts | 54 ++ arch/arm/dts/meson-g12a.dtsi | 33 +- arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 25 + arch/arm/dts/meson-g12b-odroid-n2.dts | 2 +- arch/arm/dts/meson-g12b.dtsi | 26 +- arch/arm/dts/meson-gx-libretech-pc.dtsi | 375 ++ arch/arm/dts/meson-gx.dtsi| 87 +++- arch/arm/dts/meson-gxbb-nanopi-k2.dts | 26 +- arch/arm/dts/meson-gxbb-odroidc2.dts | 100 +++- arch/arm/dts/meson-gxbb-p200.dts | 9 +- arch/arm/dts/meson-gxbb-p201.dts | 2 +- arch/arm/dts/meson-gxbb-p20x.dtsi | 9 +- arch/arm/dts/meson-gxbb.dtsi | 118 - arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 2 +- .../meson-gxl-s905d-libretech-pc-u-boot.dtsi | 7 + arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 16 + arch/arm/dts/meson-gxl-s905d.dtsi | 12 + arch/arm/dts/meson-gxl-s905x-khadas-vim.dts | 20 +- arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 26 +- arch/arm/dts/meson-gxl-s905x-p212.dtsi| 10 +- arch/arm/dts/meson-gxl.dtsi | 76 ++- arch/arm/dts/meson-gxm-khadas-vim2.dts| 71 +-- .../meson-gxm-s912-libretech-pc-u-boot.dtsi | 7 + arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 +++ arch/arm/dts/meson-gxm.dtsi | 39 +- arch/arm/dts/meson-khadas-vim3.dtsi | 7 + arch/arm/dts/meson-sm1-sei610.dts | 236 - arch/arm/dts/meson-sm1.dtsi | 356 + configs/libretech-s905d-pc_defconfig | 73 +++ configs/libretech-s912-pc_defconfig | 73 +++ drivers/clk/meson/axg.c | 7 + drivers/clk/meson/g12a.c | 7 + drivers/clk/meson/gxbb.c | 7 + drivers/mmc/meson_gx_mmc.c| 14 +- include/dt-bindings/clock/axg-audio-clkc.h| 10 + include/dt-bindings/clock/gxbb-aoclkc.h | 7 + include/dt-bindings/clock/gxbb-clkc.h | 21 + include/dt-bindings/gpio/meson-gxbb-gpio.h| 8 +- include/dt-bindings/gpio/meson-gxl-gpio.h | 8 +- include/dt-bindings/leds/common.h | 75 +++ .../reset/amlogic,meson-axg-audio-arb.h | 2 + .../reset/amlogic,meson-axg-reset.h | 3 +- .../reset/amlogic,meson-g12a-audio-reset.h| 15 + .../reset/amlogic,meson-gxbb-reset.h | 51 +- 50 files changed, 2855 insertions(+), 624 deletions(-) create mode 100644 arch/arm/dts/meson-g12.dtsi create mode 100644 arch/arm/dts/meson-gx-libretech-pc.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc.dts create mode 100644 arch/arm/dts/meson-gxl-s905d.dtsi create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc.dts create mode 100644 configs/libretech-s905d-pc_defconfig create mode 100644 configs/libretech-s912-pc_defconfig create mode 100644 include/dt-bindings/leds/common.h -- 2.24.1
Re: [PATCH v2 6/6] arm64: dts: meson: add libretech-pc support
On Mon 02 Mar 2020 at 10:52, Neil Armstrong wrote: > On 02/03/2020 10:34, Neil Armstrong wrote: >> On 27/02/2020 12:27, Jerome Brunet wrote: > > The defconfig fails with : > scripts/kconfig/conf --syncconfig Kconfig > .config:164:warning: symbol value '' invalid for ENV_SECT_SIZE > .config:165:warning: symbol value '' invalid for ENV_OFFSET > > for both configs on master. That's quite a few comment about master which propably means I messed up while rebasing on it (or trying to). I can fix this up a resubmit the whole thing if you want. > > Neil
[PATCH v2 4/6] arm64: dts: meson: sync dt and bindings from v5.6-rc2
Sync the device tree and dt-bindings from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2")
The only exception to this is the mmc pinctrl pin bias of gxl SoC family.
This is a fix which found its way to u-boot but not Linux yet.
Signed-off-by: Jerome Brunet
---
arch/arm/dts/meson-axg-s400.dts | 70 ++-
arch/arm/dts/meson-axg.dtsi | 273 --
arch/arm/dts/meson-g12-common.dtsi| 478 ++
arch/arm/dts/meson-g12.dtsi | 398 +++
arch/arm/dts/meson-g12a-sei510.dts| 64 +++
arch/arm/dts/meson-g12a-u200.dts | 54 ++
arch/arm/dts/meson-g12a.dtsi | 33 +-
arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 25 +
arch/arm/dts/meson-g12b-odroid-n2.dts | 2 +-
arch/arm/dts/meson-g12b.dtsi | 26 +-
arch/arm/dts/meson-gx.dtsi| 87 +++-
arch/arm/dts/meson-gxbb-nanopi-k2.dts | 26 +-
arch/arm/dts/meson-gxbb-odroidc2.dts | 100 +++-
arch/arm/dts/meson-gxbb-p200.dts | 9 +-
arch/arm/dts/meson-gxbb-p201.dts | 2 +-
arch/arm/dts/meson-gxbb-p20x.dtsi | 9 +-
arch/arm/dts/meson-gxbb.dtsi | 118 -
arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 2 +-
arch/arm/dts/meson-gxl-s905x-khadas-vim.dts | 20 +-
arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 26 +-
arch/arm/dts/meson-gxl-s905x-p212.dtsi| 10 +-
arch/arm/dts/meson-gxl.dtsi | 76 ++-
arch/arm/dts/meson-gxm-khadas-vim2.dts| 71 +--
arch/arm/dts/meson-gxm.dtsi | 39 +-
arch/arm/dts/meson-khadas-vim3.dtsi | 7 +
arch/arm/dts/meson-sm1-khadas-vim3l.dts | 95
arch/arm/dts/meson-sm1-sei610.dts | 236 -
arch/arm/dts/meson-sm1.dtsi | 356 +
include/dt-bindings/clock/axg-audio-clkc.h| 10 +
include/dt-bindings/clock/gxbb-aoclkc.h | 7 +
include/dt-bindings/clock/gxbb-clkc.h | 21 +
include/dt-bindings/gpio/meson-gxbb-gpio.h| 8 +-
include/dt-bindings/gpio/meson-gxl-gpio.h | 8 +-
.../reset/amlogic,meson-axg-audio-arb.h | 2 +
.../reset/amlogic,meson-axg-reset.h | 3 +-
.../reset/amlogic,meson-g12a-audio-reset.h| 15 +
.../reset/amlogic,meson-gxbb-reset.h | 51 +-
37 files changed, 2214 insertions(+), 623 deletions(-)
create mode 100644 arch/arm/dts/meson-g12.dtsi
create mode 100644 arch/arm/dts/meson-sm1-khadas-vim3l.dts
diff --git a/arch/arm/dts/meson-axg-s400.dts b/arch/arm/dts/meson-axg-s400.dts
index 18778ada7bd3..4cd2d5951822 100644
--- a/arch/arm/dts/meson-axg-s400.dts
+++ b/arch/arm/dts/meson-axg-s400.dts
@@ -60,7 +60,7 @@
serial1 = &uart_A;
};
- linein: audio-codec@0 {
+ linein: audio-codec-0 {
#sound-dai-cells = <0>;
compatible = "everest,es7241";
VDDA-supply = <&vcc_3v3>;
@@ -70,7 +70,7 @@
sound-name-prefix = "Linein";
};
- lineout: audio-codec@1 {
+ lineout: audio-codec-1 {
#sound-dai-cells = <0>;
compatible = "everest,es7154";
VDD-supply = <&vcc_3v3>;
@@ -79,14 +79,14 @@
sound-name-prefix = "Lineout";
};
- spdif_dit: audio-codec@2 {
+ spdif_dit: audio-codec-2 {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
status = "okay";
sound-name-prefix = "DIT";
};
- dmics: audio-codec@3 {
+ dmics: audio-codec-3 {
#sound-dai-cells = <0>;
compatible = "dmic-codec";
num-channels = <7>;
@@ -95,6 +95,13 @@
sound-name-prefix = "MIC";
};
+ spdif_dir: audio-codec-4 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dir";
+ status = "okay";
+ sound-name-prefix = "DIR";
+ };
+
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
@@ -249,6 +256,9 @@
"TODDR_A IN 2", "TDMIN_C OUT",
"TODDR_B IN 2", "TDMIN_C OUT",
"TODDR_C IN 2", "TDMIN_C OUT",
+ "TODDR_A IN 3", "SPDIFIN Capture",
+ "TODDR_B IN 3", "SPDIFIN Capture",
+ "TODDR_C IN 3", "SPDIFIN Capture",
[PATCH v2 3/6] clk: meson: reset mmc clock on probe
On some SoCs, depending on the boot device, the MMC clock block may be
left in a weird state by the ROM code, in which no decent clock may be
provided. Reset the related register to make sure a sane MMC clock is
ready for the controller.
Reviewed-by: Neil Armstrong
Tested-by: Anand Moon
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 7 +++
drivers/clk/meson/g12a.c | 7 +++
drivers/clk/meson/gxbb.c | 7 +++
3 files changed, 21 insertions(+)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 32cbf752aed8..0ba6c303e122 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -290,6 +290,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+* Depending on the boot src, the state of the MMC clock might
+* be different. Reset it to make sure we won't get stuck
+*/
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk-axg: probed\n");
return 0;
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 1b2523bbf1fe..03d885d986b8 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -976,6 +976,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+* Depending on the boot src, the state of the MMC clock might
+* be different. Reset it to make sure we won't get stuck
+*/
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk-g12a: probed\n");
return 0;
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index abb5337e7829..aedba991603f 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -886,6 +886,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+* Depending on the boot src, the state of the MMC clock might
+* be different. Reset it to make sure we won't get stuck
+*/
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk: probed\n");
return 0;
--
2.24.1
[PATCH v2 6/6] arm64: dts: meson: add libretech-pc support
Add support for the Amlogic based libretech-pc platform. This platform comes with 2 variant, based on the s905d or s912 SoC. Signed-off-by: Jerome Brunet --- arch/arm/dts/Makefile | 2 + .../meson-gxl-s905d-libretech-pc-u-boot.dtsi | 7 ++ .../meson-gxm-s912-libretech-pc-u-boot.dtsi | 7 ++ configs/libretech-s905d-pc_defconfig | 71 +++ configs/libretech-s912-pc_defconfig | 71 +++ include/configs/libretech-pc.h| 17 + 6 files changed, 175 insertions(+) create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi create mode 100644 configs/libretech-s905d-pc_defconfig create mode 100644 configs/libretech-s912-pc_defconfig create mode 100644 include/configs/libretech-pc.h diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 3b8dc2f56fd2..45120d8f20ce 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -137,7 +137,9 @@ dtb-$(CONFIG_ARCH_MESON) += \ meson-gxl-s805x-libretech-ac.dtb \ meson-gxl-s905x-libretech-cc.dtb \ meson-gxl-s905x-khadas-vim.dtb \ + meson-gxl-s905d-libretech-pc.dtb \ meson-gxm-khadas-vim2.dtb \ + meson-gxm-s912-libretech-pc.dtb \ meson-axg-s400.dtb \ meson-g12a-u200.dtb \ meson-g12a-sei510.dtb \ diff --git a/arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi b/arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi new file mode 100644 index ..c35158d7e9ee --- /dev/null +++ b/arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong + */ + +#include "meson-gx-u-boot.dtsi" diff --git a/arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi b/arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi new file mode 100644 index ..c35158d7e9ee --- /dev/null +++ b/arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi @@ -0,0 +1,7 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 BayLibre, SAS. + * Author: Neil Armstrong + */ + +#include "meson-gx-u-boot.dtsi" diff --git a/configs/libretech-s905d-pc_defconfig b/configs/libretech-s905d-pc_defconfig new file mode 100644 index ..0dbacf60046a --- /dev/null +++ b/configs/libretech-s905d-pc_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="libretech-pc" +CONFIG_SYS_BOARD="q200" +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x0100 +CONFIG_MESON_GXL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_IDENT_STRING=" libretech-s905d-pc" +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_CMD_BDI is not set +# CONFIG_CMD_IMI is not set +CONFIG_CMD_ADC=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_SF_TEST=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_REGULATOR=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="meson-gxl-s905d-libretech-pc" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SARADC_MESON=y +CONFIG_DM_GPIO=y +CONFIG_DM_KEYBOARD=y +CONFIG_DM_MMC=y +CONFIG_MMC_MESON_GX=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_PHY_REALTEK=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY=y +CONFIG_MESON_GXL_USB_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MESON_GXL=y +CONFIG_POWER_DOMAIN=y +CONFIG_MESON_GX_VPU_POWER_DOMAIN=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_RESET=y +CONFIG_DEBUG_UART_MESON=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_DEBUG_UART_SKIP_INIT=y +CONFIG_MESON_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MESON_SPIFC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_XHCI_DWC3_OF_SIMPLE=y +CONFIG_USB_DWC3=y +CONFIG_USB_KEYBOARD=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_VIDEO_MESON=y +CONFIG_VIDEO_DT_SIMPLEFB=y +CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/configs/libretech-s912-pc_defconfig b/configs/libretech-s912-pc_defconfig new file mode 100644 index ..63b44b389be6 --- /dev/null +++ b/configs/libretech-s912-pc_defconfig @@ -0,0 +1,71 @@ +CONFIG_ARM=y +CONFIG_SYS_CONFIG_NAME="libretech-pc" +CONFIG_SYS_BOARD="q200" +CONFIG_ARCH_MESON=y +CONFIG_SYS_TEXT_BASE=0x0100 +CONFIG_MESON_GXM=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_DEBUG_UART_BASE=0xc81004c0 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_IDENT_STRING=" libretech-s912-pc" +CONFIG_DEBUG_UART=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_USE_PREBOOT=y +CONFIG_PREBOOT="usb start" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_CPU
[PATCH v2 5/6] arm64: dts: meson: import libretech-pc from linux v5.6-rc2
Sync the libretech-pc device tree from Linux v5.6-rc2
11a48a5a18c6 ("Linux 5.6-rc2")
Signed-off-by: Jerome Brunet
---
arch/arm/dts/meson-gx-libretech-pc.dtsi | 375 ++
arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 16 +
arch/arm/dts/meson-gxl-s905d.dtsi | 12 +
arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 +++
4 files changed, 465 insertions(+)
create mode 100644 arch/arm/dts/meson-gx-libretech-pc.dtsi
create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc.dts
create mode 100644 arch/arm/dts/meson-gxl-s905d.dtsi
create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc.dts
diff --git a/arch/arm/dts/meson-gx-libretech-pc.dtsi
b/arch/arm/dts/meson-gx-libretech-pc.dtsi
new file mode 100644
index ..248b018c83d5
--- /dev/null
+++ b/arch/arm/dts/meson-gx-libretech-pc.dtsi
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 BayLibre SAS.
+ * Author: Jerome Brunet
+ */
+
+/* Libretech Amlogic GX PC form factor - AKA: Tartiflette */
+
+#include
+#include
+
+/ {
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+
+ update-button {
+ label = "update";
+ linux,code = ;
+ press-threshold-microvolt = <130>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+ status = "disabled";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ power-button {
+ label = "power";
+ linux,code = ;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regulator-always-on;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ green {
+ color = ;
+ function = LED_FUNCTION_DISK_ACTIVITY;
+ gpios = <&gpio_ao GPIOAO_9 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "disk-activity";
+ };
+
+ blue {
+ color = ;
+ function = LED_FUNCTION_STATUS;
+ gpios = <&gpio GPIODV_28 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ panic-indicator;
+ };
+ };
+
+ vcc_card: regulator-vcc_card {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_CARD";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&vddio_ao3v3>;
+
+ gpio = <&gpio GPIODV_4 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ vcc5v: regul
[PATCH v2 1/6] dt-bindings: leds: import common led bindings from linux v5.5
Import the common leds bindings definition from linux
d5226fa6dbae ("Linux 5.5")
Reviewed-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
include/dt-bindings/leds/common.h | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 include/dt-bindings/leds/common.h
diff --git a/include/dt-bindings/leds/common.h
b/include/dt-bindings/leds/common.h
new file mode 100644
index ..9e1256a7c1bf
--- /dev/null
+++ b/include/dt-bindings/leds/common.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides macros for the common LEDs device tree bindings.
+ *
+ * Copyright (C) 2015, Samsung Electronics Co., Ltd.
+ * Author: Jacek Anaszewski
+ *
+ * Copyright (C) 2019 Jacek Anaszewski
+ */
+
+#ifndef __DT_BINDINGS_LEDS_H
+#define __DT_BINDINGS_LEDS_H
+
+/* External trigger type */
+#define LEDS_TRIG_TYPE_EDGE0
+#define LEDS_TRIG_TYPE_LEVEL 1
+
+/* Boost modes */
+#define LEDS_BOOST_OFF 0
+#define LEDS_BOOST_ADAPTIVE1
+#define LEDS_BOOST_FIXED 2
+
+/* Standard LED colors */
+#define LED_COLOR_ID_WHITE 0
+#define LED_COLOR_ID_RED 1
+#define LED_COLOR_ID_GREEN 2
+#define LED_COLOR_ID_BLUE 3
+#define LED_COLOR_ID_AMBER 4
+#define LED_COLOR_ID_VIOLET5
+#define LED_COLOR_ID_YELLOW6
+#define LED_COLOR_ID_IR7
+#define LED_COLOR_ID_MAX 8
+
+/* Standard LED functions */
+#define LED_FUNCTION_ACTIVITY "activity"
+#define LED_FUNCTION_ALARM "alarm"
+#define LED_FUNCTION_BACKLIGHT "backlight"
+#define LED_FUNCTION_BLUETOOTH "bluetooth"
+#define LED_FUNCTION_BOOT "boot"
+#define LED_FUNCTION_CPU "cpu"
+#define LED_FUNCTION_CAPSLOCK "capslock"
+#define LED_FUNCTION_CHARGING "charging"
+#define LED_FUNCTION_DEBUG "debug"
+#define LED_FUNCTION_DISK "disk"
+#define LED_FUNCTION_DISK_ACTIVITY "disk-activity"
+#define LED_FUNCTION_DISK_ERR "disk-err"
+#define LED_FUNCTION_DISK_READ "disk-read"
+#define LED_FUNCTION_DISK_WRITE "disk-write"
+#define LED_FUNCTION_FAULT "fault"
+#define LED_FUNCTION_FLASH "flash"
+#define LED_FUNCTION_HEARTBEAT "heartbeat"
+#define LED_FUNCTION_INDICATOR "indicator"
+#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight"
+#define LED_FUNCTION_LAN "lan"
+#define LED_FUNCTION_MAIL "mail"
+#define LED_FUNCTION_MTD "mtd"
+#define LED_FUNCTION_MICMUTE "micmute"
+#define LED_FUNCTION_MUTE "mute"
+#define LED_FUNCTION_NUMLOCK "numlock"
+#define LED_FUNCTION_PANIC "panic"
+#define LED_FUNCTION_PROGRAMMING "programming"
+#define LED_FUNCTION_POWER "power"
+#define LED_FUNCTION_RX "rx"
+#define LED_FUNCTION_SD "sd"
+#define LED_FUNCTION_SCROLLLOCK "scrolllock"
+#define LED_FUNCTION_STANDBY "standby"
+#define LED_FUNCTION_STATUS "status"
+#define LED_FUNCTION_TORCH "torch"
+#define LED_FUNCTION_TX "tx"
+#define LED_FUNCTION_USB "usb"
+#define LED_FUNCTION_WAN "wan"
+#define LED_FUNCTION_WLAN "wlan"
+#define LED_FUNCTION_WPS "wps"
+
+#endif /* __DT_BINDINGS_LEDS_H */
--
2.24.1
[PATCH v2 2/6] mmc: meson-gx: enable input clocks
Until now, the mmc clock was left in a good enough state by the ROM code to be used by the controller. However on some SoC, if the ROM code finds a bootloader on USB or SPI, it might leave the MMC clock in state the controller cannot work with. Enable the input clocks provided to the mmc controller. While the u-boot mmc controller driver is not doing fancy settings like the Linux, it at least needs to make these clocks are running. Reviewed-by: Neil Armstrong Signed-off-by: Jerome Brunet --- drivers/mmc/meson_gx_mmc.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index 031cc79ccb1f..7060f15787f6 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -240,12 +241,23 @@ static int meson_mmc_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct mmc *mmc = &pdata->mmc; struct mmc_config *cfg = &pdata->cfg; + struct clk_bulk clocks; uint32_t val; + int ret; + #ifdef CONFIG_PWRSEQ struct udevice *pwr_dev; - int ret; #endif + /* Enable the clocks feeding the MMC controller */ + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 | MMC_VDD_31_32 | MMC_VDD_165_195; cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | -- 2.24.1
[PATCH v2 0/6] arm64: meson: add libretech-pc support
Add libretech PC platform support. This platform comes in 2 variants, one with the s905d and the other s912. While working on these boards, I've found a problem related the mmc clock. In some cases, the ROM code will leave the mmc clocks in such a weird state that any access to the mmc controller would lock the device. Making sure the MMC clocks are properly reset and enabled is enough to solve the problem. I have also synced all amlogic supported dts. Since I had to update the gx dsti files, it made sense to update the dts as well. This is done to keep things coherent even if it is not the original purpose of this series. Changes since v1: - Split dt sync, libretech-pc import and config addition. - Rebase on master Jerome Brunet (6): dt-bindings: leds: import common led bindings from linux v5.5 mmc: meson-gx: enable input clocks clk: meson: reset mmc clock on probe arm64: dts: meson: sync dt and bindings from v5.6-rc2 arm64: dts: meson: import libretech-pc from linux v5.6-rc2 arm64: dts: meson: add libretech-pc support arch/arm/dts/Makefile | 2 + arch/arm/dts/meson-axg-s400.dts | 70 ++- arch/arm/dts/meson-axg.dtsi | 273 -- arch/arm/dts/meson-g12-common.dtsi| 478 ++ arch/arm/dts/meson-g12.dtsi | 398 +++ arch/arm/dts/meson-g12a-sei510.dts| 64 +++ arch/arm/dts/meson-g12a-u200.dts | 54 ++ arch/arm/dts/meson-g12a.dtsi | 33 +- arch/arm/dts/meson-g12b-a311d-khadas-vim3.dts | 25 + arch/arm/dts/meson-g12b-odroid-n2.dts | 2 +- arch/arm/dts/meson-g12b.dtsi | 26 +- arch/arm/dts/meson-gx-libretech-pc.dtsi | 375 ++ arch/arm/dts/meson-gx.dtsi| 87 +++- arch/arm/dts/meson-gxbb-nanopi-k2.dts | 26 +- arch/arm/dts/meson-gxbb-odroidc2.dts | 100 +++- arch/arm/dts/meson-gxbb-p200.dts | 9 +- arch/arm/dts/meson-gxbb-p201.dts | 2 +- arch/arm/dts/meson-gxbb-p20x.dtsi | 9 +- arch/arm/dts/meson-gxbb.dtsi | 118 - arch/arm/dts/meson-gxl-s805x-libretech-ac.dts | 2 +- .../meson-gxl-s905d-libretech-pc-u-boot.dtsi | 7 + arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 16 + arch/arm/dts/meson-gxl-s905d.dtsi | 12 + arch/arm/dts/meson-gxl-s905x-khadas-vim.dts | 20 +- arch/arm/dts/meson-gxl-s905x-libretech-cc.dts | 26 +- arch/arm/dts/meson-gxl-s905x-p212.dtsi| 10 +- arch/arm/dts/meson-gxl.dtsi | 76 ++- arch/arm/dts/meson-gxm-khadas-vim2.dts| 71 +-- .../meson-gxm-s912-libretech-pc-u-boot.dtsi | 7 + arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 +++ arch/arm/dts/meson-gxm.dtsi | 39 +- arch/arm/dts/meson-khadas-vim3.dtsi | 7 + arch/arm/dts/meson-sm1-khadas-vim3l.dts | 95 arch/arm/dts/meson-sm1-sei610.dts | 236 - arch/arm/dts/meson-sm1.dtsi | 356 + configs/libretech-s905d-pc_defconfig | 71 +++ configs/libretech-s912-pc_defconfig | 71 +++ drivers/clk/meson/axg.c | 7 + drivers/clk/meson/g12a.c | 7 + drivers/clk/meson/gxbb.c | 7 + drivers/mmc/meson_gx_mmc.c| 14 +- include/configs/libretech-pc.h| 17 + include/dt-bindings/clock/axg-audio-clkc.h| 10 + include/dt-bindings/clock/gxbb-aoclkc.h | 7 + include/dt-bindings/clock/gxbb-clkc.h | 21 + include/dt-bindings/gpio/meson-gxbb-gpio.h| 8 +- include/dt-bindings/gpio/meson-gxl-gpio.h | 8 +- include/dt-bindings/leds/common.h | 75 +++ .../reset/amlogic,meson-axg-audio-arb.h | 2 + .../reset/amlogic,meson-axg-reset.h | 3 +- .../reset/amlogic,meson-g12a-audio-reset.h| 15 + .../reset/amlogic,meson-gxbb-reset.h | 51 +- 52 files changed, 2963 insertions(+), 624 deletions(-) create mode 100644 arch/arm/dts/meson-g12.dtsi create mode 100644 arch/arm/dts/meson-gx-libretech-pc.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc.dts create mode 100644 arch/arm/dts/meson-gxl-s905d.dtsi create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc.dts create mode 100644 arch/arm/dts/meson-sm1-khadas-vim3l.dts create mode 100644 configs/libretech-s905d-pc_defconfig create mode 100644 configs/libretech-s912-pc_defconfig create mode 100644 include/configs/libretech-pc.h create mode 100644 include/dt-bindings/leds/common.h -- 2.24.1
Re: [PATCHv6 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
On Sun 09 Feb 2020 at 18:22, Anand Moon wrote:
> Hi Neil,
>
> Thanks for you review comments.
>
> On Sun, 9 Feb 2020 at 18:38, Neil Armstrong wrote:
>>
>> Hi,
>>
>> Le 09/02/2020 à 12:05, Anand Moon a écrit :
>> > As per mainline line kernel fix the clk tuning phase for mmc,
>> > set Core=180, Tx=0, Rx=0 clk phase for mmc initialization.
>> > As per S905, S905X, AGX and S922X datasheet set the default
>> > values for clk tuning.
>> >
>> > Signed-off-by: Anand Moon
>> > ---
>> > Changes from previous
>> > v5 Fix the commit message, configure as per mainline kernel.
>> > drop the RX_DELAY_MASK and TX_DELAY_MASK as they are not used.
>> >
>> > v4 Fix the update mask value using FIELD_PREP macro.
>> >
>> > v3 Fix the initialization of core clk tunning phase as per datasheet.
>> > Fix the commit message.
>> >
>> > v2: Fix the clk phase macro to support PHASE_180
>> > drop the wrong CLK_CORE_PHASE_MASK macro.
>> >
>> > v1: use the mainline kernel tuning for clk tuning.
>> >
>> > Fixed the commmit messages.
>> > Patch v1:
>> > https://patchwork.ozlabs.org/patch/1201208/
>> >
>> > Before these changes.
>> > clock is enabled (380953Hz)
>> > clock is enabled (2500Hz)
>> > After these changes
>> > clock is enabled (380953Hz)
>> > clock is enabled (2500Hz)
>> > clock is enabled (5200Hz)
>> > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards
>> > ---
>> > arch/arm/include/asm/arch-meson/sd_emmc.h | 24 +++
>> > drivers/mmc/meson_gx_mmc.c| 28 +++
>> > 2 files changed, 38 insertions(+), 14 deletions(-)
>> >
>> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > index e3a72c8b66..f4299485dc 100644
>> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > @@ -7,6 +7,7 @@
>> > #define __SD_EMMC_H__
>> >
>> > #include
>> > +#include
>> >
>> > #define SDIO_PORT_A 0
>> > #define SDIO_PORT_B 1
>> > @@ -19,15 +20,20 @@
>> > #define CLK_MAX_DIV63
>> > #define CLK_SRC_24M(0 << 6)
>> > #define CLK_SRC_DIV2 (1 << 6)
>> > -#define CLK_CO_PHASE_000 (0 << 8)
>> > -#define CLK_CO_PHASE_090 (1 << 8)
>> > -#define CLK_CO_PHASE_180 (2 << 8)
>> > -#define CLK_CO_PHASE_270 (3 << 8)
>> > -#define CLK_TX_PHASE_000 (0 << 10)
>> > -#define CLK_TX_PHASE_090 (1 << 10)
>> > -#define CLK_TX_PHASE_180 (2 << 10)
>> > -#define CLK_TX_PHASE_270 (3 << 10)
>> > -#define CLK_ALWAYS_ON BIT(24)
>> > +
>> > +#define CRYSTAL_24MHZ 0
>> > +#define CLK_PHASE_00
>> > +#define CLK_PHASE_180 2
>> > +
>> > +#define CLK_DIV_MASK GENMASK(5, 0)
>> > +#define CLK_SRC_MASK GENMASK(7, 6)
>> > +#define CLK_CORE_PHASE_MASKGENMASK(9, 8)
>> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
>> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
>> > +
>> > +#define CLK_V2_ALWAYS_ON BIT(24)
>> > +
>> > +#define CLK_V3_ALWAYS_ON BIT(28)
>> >
>> > #define MESON_SD_EMMC_CFG0x44
>> > #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
>> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>> > index 86c1a7164a..b013c7c5fb 100644
>> > --- a/drivers/mmc/meson_gx_mmc.c
>> > +++ b/drivers/mmc/meson_gx_mmc.c
>> > @@ -16,6 +16,10 @@
>> > #include
>> > #include
>> >
>> > +#include
>> > +#include
>> > +#include
>> > +
>> > static inline void *get_regbase(const struct mmc *mmc)
>> > {
>> > struct meson_mmc_platdata *pdata = mmc->priv;
>> > @@ -51,11 +55,25 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>> > }
>> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
>> >
>> > - /* 180 phase core clock */
>> > - meson_mmc_clk |= CLK_CO_PHASE_180;
>> > -
>> > - /* 180 phase tx clock */
>> > - meson_mmc_clk |= CLK_TX_PHASE_000;
>> > + /* Clock divider */
>> > + meson_mmc_clk |= CLK_DIV_MASK;
>>
>> This will set the max divider, whatever the value of clk_div, so the
>> following statement:
>> meson_mmc_clk |= clk_div;
>> will have no effect.
>
> As per the datasheet S905 and S922X max divider is 63.
> CLK_DIV_MASK[0-5] Cfg_div: Clock divider
> Frequency = clock source/cfg_div
> Clock off: cfg_div==0, the
> clock is disabled
> Divider bypass: cfg_div==1,
> clock source is used as core clock without divider
> Maximum divider 63
>
> So here is the log of clk_div and clk_freq at my end.
>
> MMC Device 0 not found
> no mmc device a
Re: [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
On Mon 03 Feb 2020 at 17:38, Anand Moon wrote:
> Hi Jerome,
>
> Thanks for your review,
>
> On Mon, 3 Feb 2020 at 21:11, Jerome Brunet wrote:
>>
>>
>> On Mon 03 Feb 2020 at 16:13, Anand Moon wrote:
>>
>> > As per mainline line kernel fix the clk tuning phase for mmc,
>> > set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
Which version ?
I don't recall any version of mainline linux kernel which has used these
default settings.
>> > As per S905, S905X, AGX and S922X datasheet set the default
>> > values for clk tuning.
>> >
>> > Signed-off-by: Anand Moon
>> > ---
>> > arch/arm/include/asm/arch-meson/sd_emmc.h | 28 --
>> > drivers/mmc/meson_gx_mmc.c| 36 +++
>> > 2 files changed, 50 insertions(+), 14 deletions(-)
>> >
>> > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > index e3a72c8b66..b7a99947b3 100644
>> > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
>> > @@ -7,6 +7,7 @@
>> > #define __SD_EMMC_H__
>> >
>> > #include
>> > +#include
>> >
>> > #define SDIO_PORT_A 0
>> > #define SDIO_PORT_B 1
>> > @@ -19,15 +20,24 @@
>> > #define CLK_MAX_DIV63
>> > #define CLK_SRC_24M(0 << 6)
>> > #define CLK_SRC_DIV2 (1 << 6)
>> > -#define CLK_CO_PHASE_000 (0 << 8)
>> > -#define CLK_CO_PHASE_090 (1 << 8)
>> > -#define CLK_CO_PHASE_180 (2 << 8)
>> > -#define CLK_CO_PHASE_270 (3 << 8)
>> > -#define CLK_TX_PHASE_000 (0 << 10)
>> > -#define CLK_TX_PHASE_090 (1 << 10)
>> > -#define CLK_TX_PHASE_180 (2 << 10)
>> > -#define CLK_TX_PHASE_270 (3 << 10)
>> > -#define CLK_ALWAYS_ON BIT(24)
>> > +
>> > +#define CRYSTAL_24MHZ 0
>> > +#define CLK_PHASE_00
>> > +#define CLK_PHASE_180 2
>> > +
>> > +#define CLK_DIV_MASK GENMASK(5, 0)
>> > +#define CLK_SRC_MASK GENMASK(7, 6)
>> > +#define CLK_CORE_PHASE_MASKGENMASK(9, 8)
>> > +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
>> > +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
>> > +
>> > +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
>> > +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
>> > +#define CLK_V2_ALWAYS_ON BIT(24)
>> > +
>> > +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
>> > +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
>> > +#define CLK_V3_ALWAYS_ON BIT(28)
>> >
>> > #define MESON_SD_EMMC_CFG0x44
>> > #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
>> > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
>> > index 86c1a7164a..03fb70e717 100644
>> > --- a/drivers/mmc/meson_gx_mmc.c
>> > +++ b/drivers/mmc/meson_gx_mmc.c
>> > @@ -16,6 +16,10 @@
>> > #include
>> > #include
>> >
>> > +#include
>> > +#include
>> > +#include
>> > +
>> > static inline void *get_regbase(const struct mmc *mmc)
>> > {
>> > struct meson_mmc_platdata *pdata = mmc->priv;
>> > @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
>> > }
>> > clk_div = DIV_ROUND_UP(clk, mmc->clock);
>> >
>> > - /* 180 phase core clock */
>> > - meson_mmc_clk |= CLK_CO_PHASE_180;
>> > -
>> > - /* 180 phase tx clock */
>> > - meson_mmc_clk |= CLK_TX_PHASE_000;
>> > + /* Clock divider */
>> > + meson_mmc_clk |= CLK_DIV_MASK;
>> > + /* Clock source : Crystal 24MHz */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
>> > + /* Core clock phase 2:180 */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
>> > + /* TX clock phase 2:180 */
>> > + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
>>
&
Re: [PATCHv5 1/5] mmc: meson-gx: Fix clk phase tuning for MMC
On Mon 03 Feb 2020 at 16:13, Anand Moon wrote:
> As per mainline line kernel fix the clk tuning phase for mmc,
> set Core=180, Tx=180, Rx=0 clk phase for mmc initialization.
> As per S905, S905X, AGX and S922X datasheet set the default
> values for clk tuning.
>
> Signed-off-by: Anand Moon
> ---
> arch/arm/include/asm/arch-meson/sd_emmc.h | 28 --
> drivers/mmc/meson_gx_mmc.c| 36 +++
> 2 files changed, 50 insertions(+), 14 deletions(-)
>
> diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h
> b/arch/arm/include/asm/arch-meson/sd_emmc.h
> index e3a72c8b66..b7a99947b3 100644
> --- a/arch/arm/include/asm/arch-meson/sd_emmc.h
> +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h
> @@ -7,6 +7,7 @@
> #define __SD_EMMC_H__
>
> #include
> +#include
>
> #define SDIO_PORT_A 0
> #define SDIO_PORT_B 1
> @@ -19,15 +20,24 @@
> #define CLK_MAX_DIV63
> #define CLK_SRC_24M(0 << 6)
> #define CLK_SRC_DIV2 (1 << 6)
> -#define CLK_CO_PHASE_000 (0 << 8)
> -#define CLK_CO_PHASE_090 (1 << 8)
> -#define CLK_CO_PHASE_180 (2 << 8)
> -#define CLK_CO_PHASE_270 (3 << 8)
> -#define CLK_TX_PHASE_000 (0 << 10)
> -#define CLK_TX_PHASE_090 (1 << 10)
> -#define CLK_TX_PHASE_180 (2 << 10)
> -#define CLK_TX_PHASE_270 (3 << 10)
> -#define CLK_ALWAYS_ON BIT(24)
> +
> +#define CRYSTAL_24MHZ 0
> +#define CLK_PHASE_00
> +#define CLK_PHASE_180 2
> +
> +#define CLK_DIV_MASK GENMASK(5, 0)
> +#define CLK_SRC_MASK GENMASK(7, 6)
> +#define CLK_CORE_PHASE_MASKGENMASK(9, 8)
> +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> +
> +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
> +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
> +#define CLK_V2_ALWAYS_ON BIT(24)
> +
> +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
> +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
> +#define CLK_V3_ALWAYS_ON BIT(28)
>
> #define MESON_SD_EMMC_CFG0x44
> #define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
> diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
> index 86c1a7164a..03fb70e717 100644
> --- a/drivers/mmc/meson_gx_mmc.c
> +++ b/drivers/mmc/meson_gx_mmc.c
> @@ -16,6 +16,10 @@
> #include
> #include
>
> +#include
> +#include
> +#include
> +
> static inline void *get_regbase(const struct mmc *mmc)
> {
> struct meson_mmc_platdata *pdata = mmc->priv;
> @@ -51,11 +55,33 @@ static void meson_mmc_config_clock(struct mmc *mmc)
> }
> clk_div = DIV_ROUND_UP(clk, mmc->clock);
>
> - /* 180 phase core clock */
> - meson_mmc_clk |= CLK_CO_PHASE_180;
> -
> - /* 180 phase tx clock */
> - meson_mmc_clk |= CLK_TX_PHASE_000;
> + /* Clock divider */
> + meson_mmc_clk |= CLK_DIV_MASK;
> + /* Clock source : Crystal 24MHz */
> + meson_mmc_clk |= FIELD_PREP(CLK_SRC_MASK, CRYSTAL_24MHZ);
> + /* Core clock phase 2:180 */
> + meson_mmc_clk |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
> + /* TX clock phase 2:180 */
> + meson_mmc_clk |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_180);
I think I mentionned already but this is not aligned with the setting
used by the linux driver. If you have problems with these, please report
it to the linux mailing list
> + /* RX clock phase 0:180 */
> + meson_mmc_clk |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
> +
> +#ifdef CONFIG_MESON_GX
> + /* TX clock delay line */
> + meson_mmc_clk |= CLK_V2_TX_DELAY_MASK;
> + /* RX clock delay line */
> + meson_mmc_clk |= CLK_V2_RX_DELAY_MASK;
Why do you need to this ?
> + /* clk always on */
> + meson_mmc_clk |= CLK_V2_ALWAYS_ON;
> +#endif
> +#if (defined(CONFIG_MESON_AXG) || defined(CONFIG_MESON_G12A))
> + /* TX clock delay line */
> + meson_mmc_clk |= CLK_V3_TX_DELAY_MASK;
> + /* RX clock delay line */
> + meson_mmc_clk |= CLK_V3_RX_DELAY_MASK;
> + /* clk always on */
> + meson_mmc_clk |= CLK_V3_ALWAYS_ON;
> +#endif
>
> /* clock settings */
> meson_mmc_clk |= clk_src;
Re: [PATCHv3 1/3] mmc: meson-gx: Fix clk phase tuning for MMC
On Thu 26 Dec 2019 at 12:33, Anand Moon wrote: > As per mainline line kernel fix the clk tunnig phase for > mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization. > > Signed-off-by: Anand Moon > --- > Changes from previous > v2: Fix the clk phase macro to support PHASE_180 > drop the wrong CLK_CORE_PHASE_MASK macro. > > v1: use the mainline kernel tuning for clk tuning. > Fixed the commmit messages. > Patch v1: > https://patchwork.ozlabs.org/patch/1201208/ > > Before these changes. > clock is enabled (380953Hz) > clock is enabled (2500Hz) > After these changes > clock is enabled (380953Hz) > clock is enabled (2500Hz) > clock is enabled (5200Hz) > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards > --- > arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++ > drivers/mmc/meson_gx_mmc.c| 9 + > 2 files changed, 11 insertions(+), 12 deletions(-) > > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h > b/arch/arm/include/asm/arch-meson/sd_emmc.h > index e3a72c8b66..ee20c009e2 100644 > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h > @@ -7,6 +7,7 @@ > #define __SD_EMMC_H__ > > #include > +#include > > #define SDIO_PORT_A 0 > #define SDIO_PORT_B 1 > @@ -19,14 +20,11 @@ > #define CLK_MAX_DIV63 > #define CLK_SRC_24M(0 << 6) > #define CLK_SRC_DIV2 (1 << 6) > -#define CLK_CO_PHASE_000 (0 << 8) > -#define CLK_CO_PHASE_090 (1 << 8) > -#define CLK_CO_PHASE_180 (2 << 8) > -#define CLK_CO_PHASE_270 (3 << 8) > -#define CLK_TX_PHASE_000 (0 << 10) > -#define CLK_TX_PHASE_090 (1 << 10) > -#define CLK_TX_PHASE_180 (2 << 10) > -#define CLK_TX_PHASE_270 (3 << 10) > + > +#define CLK_PHASE_180 2 > +#define CLK_TX_PHASE_MASK GENMASK(11, 10) > +#define CLK_RX_PHASE_MASK GENMASK(13, 12) > + > #define CLK_ALWAYS_ON BIT(24) > > #define MESON_SD_EMMC_CFG0x44 > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c > index 86c1a7164a..ad697d3a5e 100644 > --- a/drivers/mmc/meson_gx_mmc.c > +++ b/drivers/mmc/meson_gx_mmc.c > @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc) > clk_div = DIV_ROUND_UP(clk, mmc->clock); > > /* 180 phase core clock */ > - meson_mmc_clk |= CLK_CO_PHASE_180; > - > - /* 180 phase tx clock */ > - meson_mmc_clk |= CLK_TX_PHASE_000; > + meson_mmc_clk |= CLK_PHASE_180; > + /* 000 phase rx clock */ > + meson_mmc_clk |= CLK_RX_PHASE_MASK; > + /* 000 phase tx clock */ > + meson_mmc_clk |= CLK_TX_PHASE_MASK; The comment on your previous version seemed correct but I think what you have implemented here is still not doing what you expect. > > /* clock settings */ > meson_mmc_clk |= clk_src;
Re: [U-Boot] [PATCHv2 1/3] mmc: meson-gx: Fix clk phase tuning for MMC
On Tue 24 Dec 2019 at 14:25, Anand Moon wrote: > As per mainline line kernel fix the clk tunnig phase for > mmc, set Core=180, Tx=0, Rx=0 clk phase for mmc initialization. > > Signed-off-by: Anand Moon > --- > Changes from previous > use the mainline kernel tuning for clk tuning. > Fixed the commmit messages. > Patch v1: > https://patchwork.ozlabs.org/patch/1201208/ > > Before these changes. > clock is enabled (380953Hz) > clock is enabled (2500Hz) > After these changes > clock is enabled (380953Hz) > clock is enabled (2500Hz) > clock is enabled (5200Hz) > Test on Odroid N2 and Odroid C2 with eMMC and microSD cards > --- > arch/arm/include/asm/arch-meson/sd_emmc.h | 14 ++ > drivers/mmc/meson_gx_mmc.c| 9 + > 2 files changed, 11 insertions(+), 12 deletions(-) > > diff --git a/arch/arm/include/asm/arch-meson/sd_emmc.h > b/arch/arm/include/asm/arch-meson/sd_emmc.h > index e3a72c8b66..d70fe4f03e 100644 > --- a/arch/arm/include/asm/arch-meson/sd_emmc.h > +++ b/arch/arm/include/asm/arch-meson/sd_emmc.h > @@ -7,6 +7,7 @@ > #define __SD_EMMC_H__ > > #include > +#include > > #define SDIO_PORT_A 0 > #define SDIO_PORT_B 1 > @@ -19,14 +20,11 @@ > #define CLK_MAX_DIV63 > #define CLK_SRC_24M(0 << 6) > #define CLK_SRC_DIV2 (1 << 6) > -#define CLK_CO_PHASE_000 (0 << 8) > -#define CLK_CO_PHASE_090 (1 << 8) > -#define CLK_CO_PHASE_180 (2 << 8) > -#define CLK_CO_PHASE_270 (3 << 8) > -#define CLK_TX_PHASE_000 (0 << 10) > -#define CLK_TX_PHASE_090 (1 << 10) > -#define CLK_TX_PHASE_180 (2 << 10) > -#define CLK_TX_PHASE_270 (3 << 10) > + > +#define CLK_CORE_PHASE_MASKGENMASK(9, 8) > +#define CLK_TX_PHASE_MASK GENMASK(11, 10) > +#define CLK_RX_PHASE_MASK GENMASK(13, 12) > + > #define CLK_ALWAYS_ON BIT(24) > > #define MESON_SD_EMMC_CFG0x44 > diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c > index 86c1a7164a..402981c3bb 100644 > --- a/drivers/mmc/meson_gx_mmc.c > +++ b/drivers/mmc/meson_gx_mmc.c > @@ -52,10 +52,11 @@ static void meson_mmc_config_clock(struct mmc *mmc) > clk_div = DIV_ROUND_UP(clk, mmc->clock); > > /* 180 phase core clock */ > - meson_mmc_clk |= CLK_CO_PHASE_180; > - > - /* 180 phase tx clock */ > - meson_mmc_clk |= CLK_TX_PHASE_000; > + meson_mmc_clk |= CLK_CORE_PHASE_MASK; > + /* 000 phase rx clock */ > + meson_mmc_clk |= CLK_RX_PHASE_MASK; > + /* 000 phase tx clock */ > + meson_mmc_clk |= CLK_TX_PHASE_MASK; > I'm not sure how this acheive what is descibed in the commit description. It looks more that it would set a 270 degree phase on all clocks, which is not desirable. > /* clock settings */ > meson_mmc_clk |= clk_src;
Re: [U-Boot] [PATCH 1/4] mmc: meson-gx: Fix tx phase in the tuning process
On Fri 20 Dec 2019 at 19:47, Anand Moon wrote: > Hi Neil, + Jerome, > > On Sat, 21 Dec 2019 at 00:28, Anand Moon wrote: >> >> Hi Neil, >> >> > Could you try the following patches instead of this one ? >> > >> > https://patchwork.ozlabs.org/patch/1213648/ >> > https://patchwork.ozlabs.org/patch/1213650/ >> > >> >> Yes I have tried this series it worked for me. It's much better fix >> than my approach. >> > > Looks like I did some wrong testing, with microSD card connected, I missed > that. > For me at this point this issue persist. Here is the logs below. > > emmc switch 1 ok > > emmc switch 2 ok > fastboot data verify > verify result: 255 > Cfg max: 1, cur: 1. Board id: 255. Force loop cfg > DDR4 probe > ddr clk to 1320MHz > Load ddrfw from eMMC, src: 0x00014200, des: 0xfffd, size: > 0xc000, part: 0 > > emmc switch 0 ok > Check phy result > INFO : End of initialization > INFO : End of read enable training > INFO : End of fine write leveling > INFO : End of read dq deskew training > INFO : End of MPR read delay center optimization > INFO : End of Write leveling coarse delay > INFO : End of write delay center optimization > INFO : End of read delay center optimization > INFO : End of max read latency training > INFO : Training has run successfully! > 1D training succeed > Load ddrfw from eMMC, src: 0x00020200, des: 0xfffd, size: > 0xc000, part: 0 > Check phy result > INFO : End of initialization > INFO : End of 2D read delay Voltage center optimization > INFO : End of 2D write delay Voltage center optimization > INFO : Training has run successfully! > > R0_RxClkDly_Margin==82 ps 7 > R0_TxDqDly_Margi==106 ps 9 > > > R1_RxClkDly_Margin==0 ps 0 > R1_TxDqDly_Margi==0 ps 0 > > dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0):0001 > 2D training succeed > auto size-- 65535DDR cs0 size: 2048MB > DDR cs1 size: 2048MB > DMC_DDR_CTRL: 00600024DDR size: 3928MB > cs0 DataBus test pass > cs1 DataBus test pass > cs0 AddrBus test pass > cs1 AddrBus test pass > pre test bdlr_100_average==435 bdlr_100_min==435 bdlr_100_max==435 > bdlr_100_cur==435 > aft test bdlr_100_average==435 bdlr_100_min==435 bdlr_100_max==435 > bdlr_100_cur==435 > non-sec scramble use zero key > ddr scramble enabled > > 100bdlr_step_size ps== 435 > result report > boot times 2Enable ddr reg access > > emmc switch 3 ok > Authentication key not yet programmed > get rpmb counter error 0x0007 > > emmc switch 0 ok > Load FIP HDR from eMMC, src: 0x00010200, des: 0x0170, size: > 0x4000, part: 0 > Load BL3X from eMMC, src: 0x0006c200, des: 0x0175c000, size: 0x00088200, > part: 0 > 0.0;M3 CHK:0;cm4_sp_mode 0 > E30HDR > MVN_1=0x > MVN_2=0x > [Image: g12b_v1.1.3375-8f9c8a7 2019-01-24 10:44:46 guotai.shen@droid11-sz] > OPS=0x40 > ring efuse init > chipver efuse init > 29 0a 40 00 01 20 10 00 00 15 30 32 54 52 4d 50 > [3.472682 Inits done] > secure task start! > high task start! > low task start! > run into bl31 > NOTICE: BL31: v1.3(release):ab8811b > NOTICE: BL31: Built : 15:03:31, Feb 12 2019 > NOTICE: BL31: G12A normal boot! > NOTICE: BL31: BL33 decompress pass > ERROR: Error initializing runtime service opteed_fast > > > U-Boot 2020.01-rc5-9-g269c6e8c39 (Dec 20 2019 - 15:38:58 +0530) odroid-n2 > > Model: Hardkernel ODROID-N2 > SoC: Amlogic Meson G12B (S922X) Revision 29:a (40:2) > DRAM: 3.8 GiB > MMC: sd@ffe05000: 0, mmc@ffe07000: 1 > In:serial@3000 > Out: serial@3000 > Err: serial@3000 > Net: > Warning: ethernet@ff3f (eth0) using random MAC address - 4a:ab:15:ba:29:62 > eth0: ethernet@ff3f > Hit any key to stop autoboot: 0 > Card did not respond to voltage select! > unable to select a mode > switch to partitions #0, OK > mmc1(part 0) is current device > ** No partition table - mmc 1 ** > MMC Device 2 not found > no mmc device at slot 2 > starting USB... > Bus usb@ff50: Register 3000140 NbrPorts 3 > Starting the controller > USB XHCI 1.10 > scanning bus usb@ff50 for devices... 1 USB Device(s) found >scanning usb for storage devices... 0 Storage Device(s) found > > complete logs in below linked. > [0] http://pastebin.com/UsVMYAvW > > -Anand I'm not quite sure I get what I should understand from this log. I can comment on the original patch though. I think you should keep the phase settings aligned with Linux. A) Among the exchange I had with amlogic, I got that there should always be a phase shift of 180 degree between the core and Tx phase. B) So far, Core=180, Tx=0, Rx=0 has proven to be quite stable for all the devices. I spent significant amount of time testing that. If that's not the case for the N2 under linux, please report it to the related ML. If these settings works under Linux, then it is not the problem and I don't think you should change them in u-boot.
[PATCH 5/5] arm64: dts: meson: add libretech-pc support
Add support for the Amlogic based libretech-pc platform.
This platform comes with 2 variant, based on the s905d or s912 SoC.
Signed-off-by: Jerome Brunet
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/meson-gx-libretech-pc.dtsi | 376 ++
.../meson-gxl-s905d-libretech-pc-u-boot.dtsi | 7 +
arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 17 +
arch/arm/dts/meson-gxl-s905d.dtsi | 12 +
arch/arm/dts/meson-gxl.dtsi | 35 +-
.../meson-gxm-s912-libretech-pc-u-boot.dtsi | 7 +
arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 +++
configs/libretech-s905d-pc_defconfig | 73
configs/libretech-s912-pc_defconfig | 73
10 files changed, 654 insertions(+), 10 deletions(-)
create mode 100644 arch/arm/dts/meson-gx-libretech-pc.dtsi
create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi
create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc.dts
create mode 100644 arch/arm/dts/meson-gxl-s905d.dtsi
create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi
create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc.dts
create mode 100644 configs/libretech-s905d-pc_defconfig
create mode 100644 configs/libretech-s912-pc_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3dc9c4d41c8d..fca0834aa7c6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -146,7 +146,9 @@ dtb-$(CONFIG_ARCH_MESON) += \
meson-gxl-s805x-libretech-ac.dtb \
meson-gxl-s905x-libretech-cc.dtb \
meson-gxl-s905x-khadas-vim.dtb \
+ meson-gxl-s905d-libretech-pc.dtb \
meson-gxm-khadas-vim2.dtb \
+ meson-gxm-s912-libretech-pc.dtb \
meson-axg-s400.dtb \
meson-g12a-u200.dtb \
meson-g12a-sei510.dtb \
diff --git a/arch/arm/dts/meson-gx-libretech-pc.dtsi
b/arch/arm/dts/meson-gx-libretech-pc.dtsi
new file mode 100644
index ..2857c3b6b006
--- /dev/null
+++ b/arch/arm/dts/meson-gx-libretech-pc.dtsi
@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 BayLibre SAS.
+ * Author: Jerome Brunet
+ */
+
+/* Libretech Amlogic GX PC form factor - AKA: Tartiflette */
+
+#include
+#include
+
+/ {
+ adc-keys {
+ compatible = "adc-keys";
+ io-channels = <&saradc 0>;
+ io-channel-names = "buttons";
+ keyup-threshold-microvolt = <180>;
+
+ update-button {
+ label = "update";
+ linux,code = ;
+ press-threshold-microvolt = <130>;
+ };
+ };
+
+ aliases {
+ serial0 = &uart_AO;
+ ethernet0 = ðmac;
+ spi0 = &spifc;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cvbs-connector {
+ compatible = "composite-video-connector";
+ status = "disabled";
+
+ port {
+ cvbs_connector_in: endpoint {
+ remote-endpoint = <&cvbs_vdac_out>;
+ };
+ };
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
+ hdmi-connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&hdmi_tx_tmds_out>;
+ };
+ };
+ };
+
+ gpio-keys-polled {
+ compatible = "gpio-keys-polled";
+ poll-interval = <100>;
+
+ power-button {
+ label = "power";
+ linux,code = ;
+ gpios = <&gpio_ao GPIOAO_2 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x8000>;
+ };
+
+ ao_5v: regulator-ao_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "AO_5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&dc_in>;
+ regulator-always-on;
+ };
+
+ dc_in: regulator-dc_in {
+ compatible = "regulator-fixed";
+ regulator-name = "DC_IN";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ regul
[PATCH 3/5] clk: meson: reset mmc clock on probe
On some SoCs, depending on the boot device, the MMC clock block may be
left in a weird state by the ROM code, in which no decent clock may be
provided. Reset the related register to make sure a sane MMC clock is
ready for the controller.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 7 +++
drivers/clk/meson/g12a.c | 7 +++
drivers/clk/meson/gxbb.c | 7 +++
3 files changed, 21 insertions(+)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 32cbf752aed8..0ba6c303e122 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -290,6 +290,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+* Depending on the boot src, the state of the MMC clock might
+* be different. Reset it to make sure we won't get stuck
+*/
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk-axg: probed\n");
return 0;
diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 1b2523bbf1fe..03d885d986b8 100644
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -976,6 +976,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+* Depending on the boot src, the state of the MMC clock might
+* be different. Reset it to make sure we won't get stuck
+*/
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk-g12a: probed\n");
return 0;
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index abb5337e7829..aedba991603f 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -886,6 +886,13 @@ static int meson_clk_probe(struct udevice *dev)
if (IS_ERR(priv->map))
return PTR_ERR(priv->map);
+ /*
+* Depending on the boot src, the state of the MMC clock might
+* be different. Reset it to make sure we won't get stuck
+*/
+ regmap_write(priv->map, HHI_NAND_CLK_CNTL, 0);
+ regmap_write(priv->map, HHI_SD_EMMC_CLK_CNTL, 0);
+
debug("meson-clk: probed\n");
return 0;
--
2.23.0
[PATCH 4/5] arm64: dts: meson: gxl: add i2c C pins
Add dv18 i2c C pins on the gxl SoC
Signed-off-by: Jerome Brunet
---
arch/arm/dts/meson-gxl.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/dts/meson-gxl.dtsi b/arch/arm/dts/meson-gxl.dtsi
index d5c3d78aafeb..4ef11e5381d8 100644
--- a/arch/arm/dts/meson-gxl.dtsi
+++ b/arch/arm/dts/meson-gxl.dtsi
@@ -511,6 +511,15 @@
};
};
+ i2c_c_dv18_pins: i2c_c_dv18 {
+ mux {
+ groups = "i2c_sck_c_dv19",
+ "i2c_sda_c_dv18";
+ function = "i2c_c";
+ bias-disable;
+ };
+ };
+
eth_pins: eth_c {
mux {
groups = "eth_mdio",
--
2.23.0
[PATCH 0/5] arm64: meson: add libretech-pc support
Add libretech PC platform support. This platform comes in 2 variants, one with the s905d and the other s912. The corresponding DT have been applied and should be merged during the next merge window [0] While working on these boards, I've found a problem related the mmc clock. In some cases, the ROM code will leave the mmc clocks in such a weird state that any access to the mmc controller would lock the device. Making sure the MMC clocks are properly reset and enabled is enough to solve the problem. [0]: https://lkml.kernel.org/r/7h5zig82ha@baylibre.com Jerome Brunet (5): dt-bindings: leds: import common led bindings from linux v5.4 mmc: meson-gx: enable input clocks clk: meson: reset mmc clock on probe arm64: dts: meson: gxl: add i2c C pins arm64: dts: meson: add libretech-pc support arch/arm/dts/Makefile | 2 + arch/arm/dts/meson-gx-libretech-pc.dtsi | 376 ++ .../meson-gxl-s905d-libretech-pc-u-boot.dtsi | 7 + arch/arm/dts/meson-gxl-s905d-libretech-pc.dts | 17 + arch/arm/dts/meson-gxl-s905d.dtsi | 12 + arch/arm/dts/meson-gxl.dtsi | 44 +- .../meson-gxm-s912-libretech-pc-u-boot.dtsi | 7 + arch/arm/dts/meson-gxm-s912-libretech-pc.dts | 62 +++ configs/libretech-s905d-pc_defconfig | 73 configs/libretech-s912-pc_defconfig | 73 drivers/clk/meson/axg.c | 7 + drivers/clk/meson/g12a.c | 7 + drivers/clk/meson/gxbb.c | 7 + drivers/mmc/meson_gx_mmc.c| 14 +- include/dt-bindings/leds/common.h | 75 15 files changed, 772 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/meson-gx-libretech-pc.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxl-s905d-libretech-pc.dts create mode 100644 arch/arm/dts/meson-gxl-s905d.dtsi create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc-u-boot.dtsi create mode 100644 arch/arm/dts/meson-gxm-s912-libretech-pc.dts create mode 100644 configs/libretech-s905d-pc_defconfig create mode 100644 configs/libretech-s912-pc_defconfig create mode 100644 include/dt-bindings/leds/common.h -- 2.23.0
[PATCH 1/5] dt-bindings: leds: import common led bindings from linux v5.4
Import the common leds bindings definition from linux v5.4 Signed-off-by: Jerome Brunet --- include/dt-bindings/leds/common.h | 75 +++ 1 file changed, 75 insertions(+) create mode 100644 include/dt-bindings/leds/common.h diff --git a/include/dt-bindings/leds/common.h b/include/dt-bindings/leds/common.h new file mode 100644 index ..9e1256a7c1bf --- /dev/null +++ b/include/dt-bindings/leds/common.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides macros for the common LEDs device tree bindings. + * + * Copyright (C) 2015, Samsung Electronics Co., Ltd. + * Author: Jacek Anaszewski + * + * Copyright (C) 2019 Jacek Anaszewski + */ + +#ifndef __DT_BINDINGS_LEDS_H +#define __DT_BINDINGS_LEDS_H + +/* External trigger type */ +#define LEDS_TRIG_TYPE_EDGE0 +#define LEDS_TRIG_TYPE_LEVEL 1 + +/* Boost modes */ +#define LEDS_BOOST_OFF 0 +#define LEDS_BOOST_ADAPTIVE1 +#define LEDS_BOOST_FIXED 2 + +/* Standard LED colors */ +#define LED_COLOR_ID_WHITE 0 +#define LED_COLOR_ID_RED 1 +#define LED_COLOR_ID_GREEN 2 +#define LED_COLOR_ID_BLUE 3 +#define LED_COLOR_ID_AMBER 4 +#define LED_COLOR_ID_VIOLET5 +#define LED_COLOR_ID_YELLOW6 +#define LED_COLOR_ID_IR7 +#define LED_COLOR_ID_MAX 8 + +/* Standard LED functions */ +#define LED_FUNCTION_ACTIVITY "activity" +#define LED_FUNCTION_ALARM "alarm" +#define LED_FUNCTION_BACKLIGHT "backlight" +#define LED_FUNCTION_BLUETOOTH "bluetooth" +#define LED_FUNCTION_BOOT "boot" +#define LED_FUNCTION_CPU "cpu" +#define LED_FUNCTION_CAPSLOCK "capslock" +#define LED_FUNCTION_CHARGING "charging" +#define LED_FUNCTION_DEBUG "debug" +#define LED_FUNCTION_DISK "disk" +#define LED_FUNCTION_DISK_ACTIVITY "disk-activity" +#define LED_FUNCTION_DISK_ERR "disk-err" +#define LED_FUNCTION_DISK_READ "disk-read" +#define LED_FUNCTION_DISK_WRITE "disk-write" +#define LED_FUNCTION_FAULT "fault" +#define LED_FUNCTION_FLASH "flash" +#define LED_FUNCTION_HEARTBEAT "heartbeat" +#define LED_FUNCTION_INDICATOR "indicator" +#define LED_FUNCTION_KBD_BACKLIGHT "kbd_backlight" +#define LED_FUNCTION_LAN "lan" +#define LED_FUNCTION_MAIL "mail" +#define LED_FUNCTION_MTD "mtd" +#define LED_FUNCTION_MICMUTE "micmute" +#define LED_FUNCTION_MUTE "mute" +#define LED_FUNCTION_NUMLOCK "numlock" +#define LED_FUNCTION_PANIC "panic" +#define LED_FUNCTION_PROGRAMMING "programming" +#define LED_FUNCTION_POWER "power" +#define LED_FUNCTION_RX "rx" +#define LED_FUNCTION_SD "sd" +#define LED_FUNCTION_SCROLLLOCK "scrolllock" +#define LED_FUNCTION_STANDBY "standby" +#define LED_FUNCTION_STATUS "status" +#define LED_FUNCTION_TORCH "torch" +#define LED_FUNCTION_TX "tx" +#define LED_FUNCTION_USB "usb" +#define LED_FUNCTION_WAN "wan" +#define LED_FUNCTION_WLAN "wlan" +#define LED_FUNCTION_WPS "wps" + +#endif /* __DT_BINDINGS_LEDS_H */ -- 2.23.0
[PATCH 2/5] mmc: meson-gx: enable input clocks
Until now, the mmc clock was left in a good enough state by the ROM code to be used by the controller. However on some SoC, if the ROM code finds a bootloader on USB or SPI, it might leave the MMC clock in state the controller cannot work with. Enable the input clocks provided to the mmc controller. While the u-boot mmc controller driver is not doing fancy settings like the Linux, it at least needs to make these clocks are running. Signed-off-by: Jerome Brunet --- drivers/mmc/meson_gx_mmc.c | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c index b5f5122b1b7b..86c1a7164a93 100644 --- a/drivers/mmc/meson_gx_mmc.c +++ b/drivers/mmc/meson_gx_mmc.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -241,12 +242,23 @@ static int meson_mmc_probe(struct udevice *dev) struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct mmc *mmc = &pdata->mmc; struct mmc_config *cfg = &pdata->cfg; + struct clk_bulk clocks; uint32_t val; + int ret; + #ifdef CONFIG_PWRSEQ struct udevice *pwr_dev; - int ret; #endif + /* Enable the clocks feeding the MMC controller */ + ret = clk_get_bulk(dev, &clocks); + if (ret) + return ret; + + ret = clk_enable_bulk(&clocks); + if (ret) + return ret; + cfg->voltages = MMC_VDD_33_34 | MMC_VDD_32_33 | MMC_VDD_31_32 | MMC_VDD_165_195; cfg->host_caps = MMC_MODE_8BIT | MMC_MODE_4BIT | -- 2.23.0
[U-Boot] [PATCH u-boot] pinctrl: meson: add pinconf support
Adding pinconf support is necessary to enable boot from SPI
without breaking the eMMC. When booting from SPI, the ROM code
leave pull downs on the eMMC pad.
We need to set pinconf provided in DT to solve this
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/Kconfig | 1 +
drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 10 ++
drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c | 10 ++
drivers/pinctrl/meson/pinctrl-meson.c | 101 --
drivers/pinctrl/meson/pinctrl-meson.h | 8 ++
5 files changed, 123 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index ee820a57a0e0..162642d7289b 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -2,6 +2,7 @@ if ARCH_MESON
config PINCTRL_MESON
select PINCTRL_GENERIC
+ select PINCONF
bool
config PINCTRL_MESON_GX_PMX
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
index c82413d08f34..f9065723eea9 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
@@ -93,6 +93,12 @@ static int meson_axg_pinmux_group_set(struct udevice *dev,
return 0;
}
+const struct pinconf_param meson_axg_pinconf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+};
+
const struct pinctrl_ops meson_axg_pinctrl_ops = {
.get_groups_count = meson_pinctrl_get_groups_count,
.get_group_name = meson_pinctrl_get_group_name,
@@ -100,6 +106,10 @@ const struct pinctrl_ops meson_axg_pinctrl_ops = {
.get_function_name = meson_pinmux_get_function_name,
.pinmux_group_set = meson_axg_pinmux_group_set,
.set_state = pinctrl_generic_set_state,
+ .pinconf_params = meson_axg_pinconf_params
+ .pinconf_num_params = ARRAY_SIZE(meson_axg_pinconf_params),
+ .pinconf_set = meson_pinconf_set,
+ .pinconf_group_set = meson_pinconf_group_set,
};
static int meson_axg_gpio_request(struct udevice *dev,
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
index fc1538ea719e..cf72576b6ce2 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gx-pmx.c
@@ -72,6 +72,12 @@ static int meson_gx_pinmux_group_set(struct udevice *dev,
return 0;
}
+const struct pinconf_param meson_gx_pinconf_params[] = {
+ { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
+ { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
+ { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
+};
+
const struct pinctrl_ops meson_gx_pinctrl_ops = {
.get_groups_count = meson_pinctrl_get_groups_count,
.get_group_name = meson_pinctrl_get_group_name,
@@ -79,6 +85,10 @@ const struct pinctrl_ops meson_gx_pinctrl_ops = {
.get_function_name = meson_pinmux_get_function_name,
.pinmux_group_set = meson_gx_pinmux_group_set,
.set_state = pinctrl_generic_set_state,
+ .pinconf_params = meson_gx_pinconf_params,
+ .pinconf_num_params = ARRAY_SIZE(meson_gx_pinconf_params),
+ .pinconf_set = meson_pinconf_set,
+ .pinconf_group_set = meson_pinconf_group_set,
};
static const struct dm_gpio_ops meson_gx_gpio_ops = {
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c
b/drivers/pinctrl/meson/pinctrl-meson.c
index b539749752c8..fa3d78858a9e 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -57,7 +57,7 @@ static int meson_gpio_calc_reg_and_bit(struct udevice *dev,
unsigned int offset,
enum meson_reg_type reg_type,
unsigned int *reg, unsigned int *bit)
{
- struct meson_pinctrl *priv = dev_get_priv(dev->parent);
+ struct meson_pinctrl *priv = dev_get_priv(dev);
struct meson_bank *bank = NULL;
struct meson_reg_desc *desc;
unsigned int pin;
@@ -89,7 +89,8 @@ int meson_gpio_get(struct udevice *dev, unsigned int offset)
unsigned int reg, bit;
int ret;
- ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_IN, ®, &bit);
+ ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_IN, ®,
+ &bit);
if (ret)
return ret;
@@ -102,7 +103,8 @@ int meson_gpio_set(struct udevice *dev, unsigned int
offset, int value)
unsigned int reg, bit;
int ret;
- ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit);
+ ret = meson_gpio_calc_reg_and_bit(dev->parent, offset, REG_OUT, ®,
+ &bit);
if (ret)
return ret;
Re: [U-Boot] [PATCH u-boot] arm: dts: s400: Fix status for eMMC and SDIO ports
On Mon, 2018-12-17 at 10:26 +0100, Neil Armstrong wrote:
> Under U-boot, the WiFi SDIO Module should be disabled and the
> eMMC modules should be enabled, so this patch adds an s400-u-boot.dtsi
> include file specific for U-Boot that will be included by the build system.
>
> Signed-off-by: Neil Armstrong
Tested-by: Jerome Brunet
> ---
> arch/arm/dts/meson-axg-s400-u-boot.dtsi | 14 ++
> 1 file changed, 14 insertions(+)
> create mode 100644 arch/arm/dts/meson-axg-s400-u-boot.dtsi
>
> diff --git a/arch/arm/dts/meson-axg-s400-u-boot.dtsi b/arch/arm/dts/meson-
> axg-s400-u-boot.dtsi
> new file mode 100644
> index 00..c46eb3f38d
> --- /dev/null
> +++ b/arch/arm/dts/meson-axg-s400-u-boot.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
> + */
> +
> +/* wifi module */
> +&sd_emmc_b {
> + status = "disabled";
> +};
> +
> +/* emmc storage */
> +&sd_emmc_c {
> + status = "okay";
> +};
___
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U-Boot@lists.denx.de
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Re: [U-Boot] [PATCH] pinctrl: meson: Fix GPIO direction registers access
On Mon, 2018-12-03 at 18:00 +, Carlo Caione wrote: > The macros used to set the direction of the GPIO pins are misused, > resulting in a wrong behavior when trying to read the GPIO input level > from U-Boot. > > A better macro is also used when setting the output direction. > > Signed-off-by: Carlo Caione > --- > drivers/pinctrl/meson/pinctrl-meson.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pinctrl/meson/pinctrl-meson.c > b/drivers/pinctrl/meson/pinctrl-meson.c > index 0bd6152803..b539749752 100644 > --- a/drivers/pinctrl/meson/pinctrl-meson.c > +++ b/drivers/pinctrl/meson/pinctrl-meson.c > @@ -136,7 +136,7 @@ int meson_gpio_direction_input(struct udevice *dev, > unsigned int offset) > if (ret) > return ret; > > - clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 1); > + setbits_le32(priv->reg_gpio + reg, BIT(bit)); > > return 0; > } > @@ -152,7 +152,7 @@ int meson_gpio_direction_output(struct udevice *dev, > if (ret) > return ret; > > - clrsetbits_le32(priv->reg_gpio + reg, BIT(bit), 0); > + clrbits_le32(priv->reg_gpio + reg, BIT(bit)); > > ret = meson_gpio_calc_reg_and_bit(dev, offset, REG_OUT, ®, &bit); > if (ret) Reviewed-by: Jerome Brunet ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH u-boot v3 0/3] Add Amlogic Meson SPI Flash Controller driver
On Wed, 2018-11-14 at 11:25 +0100, Neil Armstrong wrote: > The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC. > > This patchset add the driver ported from linux, but also import the regmap > regmap_read_poll_timeout() to implify the register polling in the driver. > > Neil Armstrong (3): > regmap: add regmap_read_poll_timeout() helper > test: regmap: add regmap_read_poll_timeout test > spi: Add Amlogic Meson SPI Flash Controller driver > > drivers/spi/Kconfig | 8 + > drivers/spi/Makefile | 1 + > drivers/spi/meson_spifc.c | 330 ++ > include/regmap.h | 38 + > test/dm/regmap.c | 26 +++ > 5 files changed, 403 insertions(+) > create mode 100644 drivers/spi/meson_spifc.c > Tested-by: Jerome Brunet ... on the libretech aml-s805x-ac which should be submitted soon. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 0/3] GPIO support for Meson GXBB and Odroid-C2
On Sun, 2017-06-25 at 17:55 +0200, Beniamino Galvani wrote: > Hi, > > this series adds a GPIO driver for Meson GXBB and enables it on > Odroid-C2. > > Beniamino Galvani (3): > arm: dts: meson: import dts files from Linux 4.12-rc6 > pinctrl: meson: add GPIO support > odroid-c2: enable GPIO > > arch/arm/dts/meson-gx.dtsi | 97 +-- > arch/arm/dts/meson-gxbb-odroidc2.dts | 82 - > arch/arm/dts/meson-gxbb.dtsi | 187 -- > --- > configs/odroid-c2_defconfig| 2 + > drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 21 > drivers/pinctrl/meson/pinctrl-meson.c | 167 +- > drivers/pinctrl/meson/pinctrl-meson.h | 63 ++ > include/dt-bindings/clock/gxbb-clkc.h | 14 ++- > 8 files changed, 586 insertions(+), 47 deletions(-) > From the recipient list, I'm guessing this patch is addressed to the u-boot community, right ? Would you mind stating it a bit more clearly next time ? especially if you include linux-amlogic list. Thx Jerome ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
