[PATCH v1 5/5] board: rockchip: Add rk3568 evb support
Add support for rk3568 evaluation board. Signed-off-by: Joseph Chen --- arch/arm/mach-rockchip/Kconfig | 1 + board/rockchip/evb_rk3568/Kconfig | 15 +++ board/rockchip/evb_rk3568/MAINTAINERS | 6 + board/rockchip/evb_rk3568/Makefile | 7 ++ board/rockchip/evb_rk3568/evb_rk3568.c | 4 +++ configs/evb-rk3568_defconfig | 35 ++ include/configs/evb_rk3568.h | 17 + 7 files changed, 85 insertions(+) create mode 100644 board/rockchip/evb_rk3568/Kconfig create mode 100644 board/rockchip/evb_rk3568/MAINTAINERS create mode 100644 board/rockchip/evb_rk3568/Makefile create mode 100644 board/rockchip/evb_rk3568/evb_rk3568.c create mode 100644 configs/evb-rk3568_defconfig create mode 100644 include/configs/evb_rk3568.h diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index 4a2d35aee2..35bdef29fe 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -403,5 +403,6 @@ source "arch/arm/mach-rockchip/rk3308/Kconfig" source "arch/arm/mach-rockchip/rk3328/Kconfig" source "arch/arm/mach-rockchip/rk3368/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" +source "arch/arm/mach-rockchip/rk3568/Kconfig" source "arch/arm/mach-rockchip/rv1108/Kconfig" endif diff --git a/board/rockchip/evb_rk3568/Kconfig b/board/rockchip/evb_rk3568/Kconfig new file mode 100644 index 00..f3d3a7e111 --- /dev/null +++ b/board/rockchip/evb_rk3568/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EVB_RK3568 + +config SYS_BOARD + default "evb_rk3568" + +config SYS_VENDOR + default "rockchip" + +config SYS_CONFIG_NAME + default "evb_rk3568" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/board/rockchip/evb_rk3568/MAINTAINERS b/board/rockchip/evb_rk3568/MAINTAINERS new file mode 100644 index 00..b6ea498d2b --- /dev/null +++ b/board/rockchip/evb_rk3568/MAINTAINERS @@ -0,0 +1,6 @@ +EVB-RK3568 +M: Joseph Chen +S: Maintained +F: board/rockchip/evb_rk3568 +F: include/configs/evb_rk3568.h +F: configs/evb-rk3568_defconfig diff --git a/board/rockchip/evb_rk3568/Makefile b/board/rockchip/evb_rk3568/Makefile new file mode 100644 index 00..cbda95fe94 --- /dev/null +++ b/board/rockchip/evb_rk3568/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2021 Rockchip Electronics Co., Ltd +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += evb_rk3568.o diff --git a/board/rockchip/evb_rk3568/evb_rk3568.c b/board/rockchip/evb_rk3568/evb_rk3568.c new file mode 100644 index 00..c2fdf95d9a --- /dev/null +++ b/board/rockchip/evb_rk3568/evb_rk3568.c @@ -0,0 +1,4 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ diff --git a/configs/evb-rk3568_defconfig b/configs/evb-rk3568_defconfig new file mode 100644 index 00..03511d790e --- /dev/null +++ b/configs/evb-rk3568_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SYS_TEXT_BASE=0x00a0 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ROCKCHIP_RK3568=y +CONFIG_TARGET_EVB_RK3568=y +CONFIG_DEBUG_UART_BASE=0xFE66 +CONFIG_DEBUG_UART_CLOCK=2400 +CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb" +CONFIG_DEBUG_UART=y +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MISC=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_SDMA=y +CONFIG_MMC_SDHCI_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_REGULATOR_PWM=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=150 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_ERRNO_STR=y diff --git a/include/configs/evb_rk3568.h b/include/configs/evb_rk3568.h new file mode 100644 index 00..2b255a11da --- /dev/null +++ b/include/configs/evb_rk3568.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2021 Rockchip Electronics Co., Ltd + */ + +#ifndef __EVB_RK3568_H +#define __EVB_RK3568_H + +#include + +#define CONFIG_SUPPORT_EMMC_RPMB + +#define ROCKCHIP_DEVICE_SETTINGS \ + "stdout=serial,vidconsole\0" \ + "stderr=serial,vidconsole\0" + +#endif -- 2.17.1
[PATCH v1 4/5] rockchip: Add rk3568 architecture core
RK3568 is a high-performance and low power quad-core application
processor designed for personal mobile internet device and AIoT
equipments.
Signed-off-by: Joseph Chen
---
arch/arm/include/asm/arch-rk3568/boot0.h | 11 +
arch/arm/include/asm/arch-rk3568/gpio.h | 11 +
.../include/asm/arch-rockchip/grf_rk3568.h| 369 ++
arch/arm/mach-rockchip/Kconfig| 17 +
arch/arm/mach-rockchip/Makefile | 1 +
arch/arm/mach-rockchip/rk3568/Kconfig | 20 +
arch/arm/mach-rockchip/rk3568/Makefile| 9 +
arch/arm/mach-rockchip/rk3568/clk_rk3568.c| 53 +++
arch/arm/mach-rockchip/rk3568/rk3568.c| 85
arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 24 ++
include/configs/rk3568_common.h | 43 ++
11 files changed, 643 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rk3568/boot0.h
create mode 100644 arch/arm/include/asm/arch-rk3568/gpio.h
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3568.h
create mode 100644 arch/arm/mach-rockchip/rk3568/Kconfig
create mode 100644 arch/arm/mach-rockchip/rk3568/Makefile
create mode 100644 arch/arm/mach-rockchip/rk3568/clk_rk3568.c
create mode 100644 arch/arm/mach-rockchip/rk3568/rk3568.c
create mode 100644 arch/arm/mach-rockchip/rk3568/syscon_rk3568.c
create mode 100644 include/configs/rk3568_common.h
diff --git a/arch/arm/include/asm/arch-rk3568/boot0.h
b/arch/arm/include/asm/arch-rk3568/boot0.h
new file mode 100644
index 00..dea2b20252
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3568/boot0.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include
+
+#endif
diff --git a/arch/arm/include/asm/arch-rk3568/gpio.h
b/arch/arm/include/asm/arch-rk3568/gpio.h
new file mode 100644
index 00..b48c0a5cf8
--- /dev/null
+++ b/arch/arm/include/asm/arch-rk3568/gpio.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include
+
+#endif
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3568.h
b/arch/arm/include/asm/arch-rockchip/grf_rk3568.h
new file mode 100644
index 00..d4e9b56292
--- /dev/null
+++ b/arch/arm/include/asm/arch-rockchip/grf_rk3568.h
@@ -0,0 +1,369 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __SOC_ROCKCHIP_RK3568_GRF_H__
+#define __SOC_ROCKCHIP_RK3568_GRF_H__
+
+struct rk3568_grf {
+ unsigned int gpio1a_iomux_l;
+ unsigned int gpio1a_iomux_h;
+ unsigned int gpio1b_iomux_l;
+ unsigned int gpio1b_iomux_h;
+ unsigned int gpio1c_iomux_l;
+ unsigned int gpio1c_iomux_h;
+ unsigned int gpio1d_iomux_l;
+ unsigned int gpio1d_iomux_h;
+ unsigned int gpio2a_iomux_l;
+ unsigned int gpio2a_iomux_h;
+ unsigned int gpio2b_iomux_l;
+ unsigned int gpio2b_iomux_h;
+ unsigned int gpio2c_iomux_l;
+ unsigned int gpio2c_iomux_h;
+ unsigned int gpio2d_iomux_l;
+ unsigned int gpio2d_iomux_h;
+ unsigned int gpio3a_iomux_l;
+ unsigned int gpio3a_iomux_h;
+ unsigned int gpio3b_iomux_l;
+ unsigned int gpio3b_iomux_h;
+ unsigned int gpio3c_iomux_l;
+ unsigned int gpio3c_iomux_h;
+ unsigned int gpio3d_iomux_l;
+ unsigned int gpio3d_iomux_h;
+ unsigned int gpio4a_iomux_l;
+ unsigned int gpio4a_iomux_h;
+ unsigned int gpio4b_iomux_l;
+ unsigned int gpio4b_iomux_h;
+ unsigned int gpio4c_iomux_l;
+ unsigned int gpio4c_iomux_h;
+ unsigned int gpio4d_iomux_l;
+ unsigned int reserved0[(0x0080 - 0x0078) / 4 - 1];
+ unsigned int gpio1a_p;
+ unsigned int gpio1b_p;
+ unsigned int gpio1c_p;
+ unsigned int gpio1d_p;
+ unsigned int gpio2a_p;
+ unsigned int gpio2b_p;
+ unsigned int gpio2c_p;
+ unsigned int gpio2d_p;
+ unsigned int gpio3a_p;
+ unsigned int gpio3b_p;
+ unsigned int gpio3c_p;
+ unsigned int gpio3d_p;
+ unsigned int gpio4a_p;
+ unsigned int gpio4b_p;
+ unsigned int gpio4c_p;
+ unsigned int gpio4d_p;
+ unsigned int gpio1a_ie;
+ unsigned int gpio1b_ie;
+ unsigned int gpio1c_ie;
+ unsigned int gpio1d_ie;
+ unsigned int gpio2a_ie;
+ unsigned int gpio2b_ie;
+ unsigned int gpio2c_ie;
+ unsigned int gpio2d_ie;
+ unsigned int gpio3a_ie;
+ unsigned int gpio3b_ie;
+ unsigned int gpio3c_ie;
+ unsigned int gpio3d_ie;
+ unsigned int gpio4a_ie;
+ unsigned int gpio4b_ie;
+ unsigned int gpio4c_ie;
+ unsigned int gpio4d_ie;
+ unsigned int gpio1a_opd;
+ unsigned int gpio1b_opd;
+ unsigned int gpio1c_opd;
+ unsigned int
[PATCH v1 3/5] rockchip: rk3568: Add sdram driver
Add the driver for rk3568 u-boot to get sdram capacity.
Signed-off-by: Joseph Chen
---
drivers/ram/rockchip/Makefile | 1 +
drivers/ram/rockchip/sdram_rk3568.c | 56 +
2 files changed, 57 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram_rk3568.c
diff --git a/drivers/ram/rockchip/Makefile b/drivers/ram/rockchip/Makefile
index c3ec89ada4..ca1c289b88 100644
--- a/drivers/ram/rockchip/Makefile
+++ b/drivers/ram/rockchip/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_ROCKCHIP_RK3288) = sdram_rk3288.o
obj-$(CONFIG_ROCKCHIP_RK3308) = sdram_rk3308.o
obj-$(CONFIG_ROCKCHIP_RK3328) = sdram_rk3328.o sdram_pctl_px30.o
sdram_phy_px30.o
obj-$(CONFIG_ROCKCHIP_RK3399) += sdram_rk3399.o
+obj-$(CONFIG_ROCKCHIP_RK3568) += sdram_rk3568.o
obj-$(CONFIG_ROCKCHIP_SDRAM_COMMON) += sdram_common.o
diff --git a/drivers/ram/rockchip/sdram_rk3568.c
b/drivers/ram/rockchip/sdram_rk3568.c
new file mode 100644
index 00..0ac4b54eef
--- /dev/null
+++ b/drivers/ram/rockchip/sdram_rk3568.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct dram_info {
+ struct ram_info info;
+ struct rk3568_pmugrf *pmugrf;
+};
+
+static int rk3568_dmc_probe(struct udevice *dev)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
+ priv->info.base = CONFIG_SYS_SDRAM_BASE;
+ priv->info.size =
+ rockchip_sdram_size((phys_addr_t)&priv->pmugrf->pmu_os_reg2);
+
+ return 0;
+}
+
+static int rk3568_dmc_get_info(struct udevice *dev, struct ram_info *info)
+{
+ struct dram_info *priv = dev_get_priv(dev);
+
+ *info = priv->info;
+
+ return 0;
+}
+
+static struct ram_ops rk3568_dmc_ops = {
+ .get_info = rk3568_dmc_get_info,
+};
+
+static const struct udevice_id rk3568_dmc_ids[] = {
+ { .compatible = "rockchip,rk3568-dmc" },
+ { }
+};
+
+U_BOOT_DRIVER(dmc_rk3568) = {
+ .name = "rockchip_rk3568_dmc",
+ .id = UCLASS_RAM,
+ .of_match = rk3568_dmc_ids,
+ .ops = &rk3568_dmc_ops,
+ .probe = rk3568_dmc_probe,
+ .priv_auto = sizeof(struct dram_info),
+};
--
2.17.1
[PATCH v1 2/5] arm: dts: rockchip: Add dts for rk3568 evb
Add dts for rk3568 evb, sync from the linux kernel
upstream list [0].
[0] https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969
Signed-off-by: Joseph Chen
---
arch/arm/dts/Makefile |3 +
arch/arm/dts/rk3568-evb-u-boot.dtsi | 23 +
arch/arm/dts/rk3568-evb.dts | 79 +
arch/arm/dts/rk3568-pinctrl.dtsi| 3111 +++
arch/arm/dts/rk3568-u-boot.dtsi | 37 +
arch/arm/dts/rk3568.dtsi| 779 +++
6 files changed, 4032 insertions(+)
create mode 100644 arch/arm/dts/rk3568-evb-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568-evb.dts
create mode 100644 arch/arm/dts/rk3568-pinctrl.dtsi
create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi
create mode 100644 arch/arm/dts/rk3568.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 096068261d..9918e46633 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -146,6 +146,9 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
rk3399-rockpro64.dtb \
rk3399pro-rock-pi-n10.dtb
+dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+ rk3568-evb.dtb
+
dtb-$(CONFIG_ROCKCHIP_RV1108) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb
diff --git a/arch/arm/dts/rk3568-evb-u-boot.dtsi
b/arch/arm/dts/rk3568-evb-u-boot.dtsi
new file mode 100644
index 00..b03cbeaedf
--- /dev/null
+++ b/arch/arm/dts/rk3568-evb-u-boot.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+ chosen {
+ stdout-path = &uart2;
+ u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+ };
+};
+
+&sdmmc0 {
+ status = "okay";
+};
+
+&uart2 {
+ clock-frequency = <2400>;
+ u-boot,dm-spl;
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-evb.dts b/arch/arm/dts/rk3568-evb.dts
new file mode 100644
index 00..6978655709
--- /dev/null
+++ b/arch/arm/dts/rk3568-evb.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ *
+ */
+
+/dts-v1/;
+#include
+#include
+#include "rk3568.dtsi"
+
+/ {
+ model = "Rockchip RK3568 EVB1 DDR4 V10 Board";
+ compatible = "rockchip,rk3568-evb1-v10", "rockchip,rk3568";
+
+ chosen: chosen {
+ stdout-path = "serial2:150n8";
+ };
+
+ dc_12v: dc-12v {
+ compatible = "regulator-fixed";
+ regulator-name = "dc_12v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1200>;
+ regulator-max-microvolt = <1200>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&dc_12v>;
+ };
+
+ vcc3v3_lcd0_n: vcc3v3-lcd0-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd0_n";
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_lcd1_n: vcc3v3-lcd1-n {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_lcd1_n";
+ regulator-boot-on;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+};
+
+&sdhci {
+ bus-width = <8>;
+ max-frequency = <2>;
+ non-removable;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/rk3568-pinctrl.dtsi b/arch/arm/dts/rk3568-pinctrl.dtsi
new file mode 100644
index 00..a588ca95ac
--- /dev/null
+++ b/arch/arm/dts/rk3568-pinctrl.dtsi
@@ -0,0 +1,3111 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+#include
+#include "rockchip-pinconf.dtsi"
+
+/*
+ * This file is auto generated by pin2dts tool, please
[PATCH v1 1/5] arm: dts: Sync rockchip-pinconf.dtsi from kernel
Sync from linux kernel:
https://patchwork.kernel.org/project/linux-rockchip/list/?series=474969
Signed-off-by: Joseph Chen
---
arch/arm/dts/rockchip-pinconf.dtsi | 344 +
1 file changed, 344 insertions(+)
create mode 100644 arch/arm/dts/rockchip-pinconf.dtsi
diff --git a/arch/arm/dts/rockchip-pinconf.dtsi
b/arch/arm/dts/rockchip-pinconf.dtsi
new file mode 100644
index 00..5c645437b5
--- /dev/null
+++ b/arch/arm/dts/rockchip-pinconf.dtsi
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+ */
+
+&pinctrl {
+ /omit-if-no-ref/
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_0: pcfg-pull-none-drv-level-0 {
+ bias-disable;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_1: pcfg-pull-none-drv-level-1 {
+ bias-disable;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_2: pcfg-pull-none-drv-level-2 {
+ bias-disable;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_3: pcfg-pull-none-drv-level-3 {
+ bias-disable;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_4: pcfg-pull-none-drv-level-4 {
+ bias-disable;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_5: pcfg-pull-none-drv-level-5 {
+ bias-disable;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_6: pcfg-pull-none-drv-level-6 {
+ bias-disable;
+ drive-strength = <6>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_7: pcfg-pull-none-drv-level-7 {
+ bias-disable;
+ drive-strength = <7>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_8: pcfg-pull-none-drv-level-8 {
+ bias-disable;
+ drive-strength = <8>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_9: pcfg-pull-none-drv-level-9 {
+ bias-disable;
+ drive-strength = <9>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_10: pcfg-pull-none-drv-level-10 {
+ bias-disable;
+ drive-strength = <10>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_11: pcfg-pull-none-drv-level-11 {
+ bias-disable;
+ drive-strength = <11>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_12: pcfg-pull-none-drv-level-12 {
+ bias-disable;
+ drive-strength = <12>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_13: pcfg-pull-none-drv-level-13 {
+ bias-disable;
+ drive-strength = <13>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_14: pcfg-pull-none-drv-level-14 {
+ bias-disable;
+ drive-strength = <14>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_none_drv_level_15: pcfg-pull-none-drv-level-15 {
+ bias-disable;
+ drive-strength = <15>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_0: pcfg-pull-up-drv-level-0 {
+ bias-pull-up;
+ drive-strength = <0>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_1: pcfg-pull-up-drv-level-1 {
+ bias-pull-up;
+ drive-strength = <1>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_2: pcfg-pull-up-drv-level-2 {
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_3: pcfg-pull-up-drv-level-3 {
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_4: pcfg-pull-up-drv-level-4 {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_5: pcfg-pull-up-drv-level-5 {
+ bias-pull-up;
+ drive-strength = <5>;
+ };
+
+ /omit-if-no-ref/
+ pcfg_pull_up_drv_level_6: pcfg-pull-up-drv-level-6 {
+ bias-pull-up;
+ drive-strengt
[PATCH v1 0/5] Add RK3568 SoC support
This series adds support for the rk3588 soc and its evaluation board. SPL will be supported after this series of patches. Joseph Chen (5): arm: dts: Sync rockchip-pinconf.dtsi from kernel arm: dts: rockchip: Add dts for rk3568 evb rockchip: rk3568: Add sdram driver rockchip: Add rk3568 architecture core board: rockchip: Add rk3568 evb support arch/arm/dts/Makefile |3 + arch/arm/dts/rk3568-evb-u-boot.dtsi | 23 + arch/arm/dts/rk3568-evb.dts | 79 + arch/arm/dts/rk3568-pinctrl.dtsi | 3111 + arch/arm/dts/rk3568-u-boot.dtsi | 37 + arch/arm/dts/rk3568.dtsi | 779 + arch/arm/dts/rockchip-pinconf.dtsi| 344 ++ arch/arm/include/asm/arch-rk3568/boot0.h | 11 + arch/arm/include/asm/arch-rk3568/gpio.h | 11 + .../include/asm/arch-rockchip/grf_rk3568.h| 369 ++ arch/arm/mach-rockchip/Kconfig| 18 + arch/arm/mach-rockchip/Makefile |1 + arch/arm/mach-rockchip/rk3568/Kconfig | 20 + arch/arm/mach-rockchip/rk3568/Makefile|9 + arch/arm/mach-rockchip/rk3568/clk_rk3568.c| 53 + arch/arm/mach-rockchip/rk3568/rk3568.c| 85 + arch/arm/mach-rockchip/rk3568/syscon_rk3568.c | 24 + board/rockchip/evb_rk3568/Kconfig | 15 + board/rockchip/evb_rk3568/MAINTAINERS |6 + board/rockchip/evb_rk3568/Makefile|7 + board/rockchip/evb_rk3568/evb_rk3568.c|4 + configs/evb-rk3568_defconfig | 35 + drivers/ram/rockchip/Makefile |1 + drivers/ram/rockchip/sdram_rk3568.c | 56 + include/configs/evb_rk3568.h | 17 + include/configs/rk3568_common.h | 43 + 26 files changed, 5161 insertions(+) create mode 100644 arch/arm/dts/rk3568-evb-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568-evb.dts create mode 100644 arch/arm/dts/rk3568-pinctrl.dtsi create mode 100644 arch/arm/dts/rk3568-u-boot.dtsi create mode 100644 arch/arm/dts/rk3568.dtsi create mode 100644 arch/arm/dts/rockchip-pinconf.dtsi create mode 100644 arch/arm/include/asm/arch-rk3568/boot0.h create mode 100644 arch/arm/include/asm/arch-rk3568/gpio.h create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rk3568.h create mode 100644 arch/arm/mach-rockchip/rk3568/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3568/Makefile create mode 100644 arch/arm/mach-rockchip/rk3568/clk_rk3568.c create mode 100644 arch/arm/mach-rockchip/rk3568/rk3568.c create mode 100644 arch/arm/mach-rockchip/rk3568/syscon_rk3568.c create mode 100644 board/rockchip/evb_rk3568/Kconfig create mode 100644 board/rockchip/evb_rk3568/MAINTAINERS create mode 100644 board/rockchip/evb_rk3568/Makefile create mode 100644 board/rockchip/evb_rk3568/evb_rk3568.c create mode 100644 configs/evb-rk3568_defconfig create mode 100644 drivers/ram/rockchip/sdram_rk3568.c create mode 100644 include/configs/evb_rk3568.h create mode 100644 include/configs/rk3568_common.h -- 2.17.1
Re: [U-Boot] [PATCH 00/10] rockchip: add tpl and OPTEE support for rk3229
in the SPL/TPL ? maybe it helps. -- Best Regards -------- 陈健洪 (Joseph Chen) E-mail：che...@rock-chips.com 福州瑞芯微电子股份有限公司 Fuzhou Rockchip Electronics Co.Ltd 福建省福州市铜盘路软件大道89号软件园A区21号楼 (350003) No. 21 Building, A District, No.89,software Boulevard Fuzhou,Fujian,PRC TEL：0591-83991906/07-8573 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
