Re: [U-Boot] [PATCH v3 2/3] Tegra114: fdt: Update DT files with I2C info for T114/Dalmore
On Friday 08 February 2013 11:34 PM, Stephen Warren wrote:
On 02/08/2013 10:25 AM, Tom Warren wrote:
T114, like T30, does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics). PWR_I2C is set to 400KHz.
diff --git a/board/nvidia/dts/tegra114-dalmore.dts
b/board/nvidia/dts/tegra114-dalmore.dts
+ aliases {
+ };
+
There's no point adding an empty aliases node here. Feel free to fix
that up when you apply it rather than reposting if you want.
I'd like too see Laxman sign-off on the *2 question he had earlier
before actually checking this in.
We do not require *2 as the i2c clock divider is DIVU16 type. There was
bug in early code on kernel also which we fixed in dowstream long back.
Possibly uboot have not fixed this yet.
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Re: [U-Boot] [PATCH v2 1/3] Tegra: I2C: Add T114 clock support to tegra_i2c driver
On Thursday 07 February 2013 04:56 AM, Tom Warren wrote: T114 has a slightly different I2C clock, with a new divisor for standard/fast mode and HS mode. Tested on my Dalmore, and the I2C clock is 100KHz +/- 3% on my Saleae Logic analyzer. Signed-off-by: Tom Warren twar...@nvidia.com --- v2: new */ clock_start_periph_pll(i2c_bus-periph_id, CLOCK_ID_PERIPH, - i2c_bus-speed * 2 * 8); + i2c_bus-speed * 2 * 8); I think you do not need to multipled by 2 again here. *2 can be remove. I2C clock divder is U16 type. + + clock_start_periph_pll(i2c_bus-periph_id, CLOCK_ID_PERIPH, + CLK_MULT_STD_FAST_MODE * (clk_div_std_fast_mode+1) * + i2c_bus-speed * 2); Same as above, *2 is not required. --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 1/3] Tegra: I2C: Add T114 clock support to tegra_i2c driver
On Thursday 07 February 2013 04:56 AM, Tom Warren wrote: T114 has a slightly different I2C clock, with a new divisor for standard/fast mode and HS mode. Tested on my Dalmore, and the I2C clock is 100KHz +/- 3% on my Saleae Logic analyzer. Signed-off-by: Tom Warren twar...@nvidia.com --- Changes looks good. Acked-by: Laxman Dewanganldewan...@nvidia.com --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/3] Tegra114: fdt: Update DT files with I2C info for T114/Dalmore
On Thursday 07 February 2013 04:56 AM, Tom Warren wrote:
Note that T114 does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics).
Signed-off-by: Tom Warren twar...@nvidia.com
---
diff --git a/board/nvidia/dts/tegra114-dalmore.dts
b/board/nvidia/dts/tegra114-dalmore.dts
index 7315577..13b07f3 100644
--- a/board/nvidia/dts/tegra114-dalmore.dts
+++ b/board/nvidia/dts/tegra114-dalmore.dts
@@ -6,8 +6,41 @@
model =NVIDIA Dalmore;
compatible =nvidia,dalmore, nvidia,tegra114;
+ aliases {
+ i2c0 =/i2c@7000d000;
+ i2c1 =/i2c@7000c000;
+ i2c2 =/i2c@7000c400;
+ i2c3 =/i2c@7000c500;
+ i2c4 =/i2c@7000c700;
+ };
Can we move this to tegar114.dtsi file.
otherwise it looks good.
Acked-by: Laxman Dewangan ldewan...@nvidia.com
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Re: [U-Boot] [PATCH v2 3/3] Tegra114: I2C: Enable I2C driver on Dalmore E1611 eval board
On Thursday 07 February 2013 04:56 AM, Tom Warren wrote: Tested all 5 'buses', i2c probe enumerates device addresses on bus 1 and 2. Signed-off-by: Tom Warren twar...@nvidia.com --- v2: No change Looks good. Acked-by: Laxman Dewanganldewan...@nvidia.com --- This email message is for the sole use of the intended recipient(s) and may contain confidential information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. --- ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] Tegra114: fdt: Update DT files with I2C info for T114/Dalmore
On Wednesday 30 January 2013 03:43 AM, Stephen Warren wrote:
On 01/29/2013 02:57 PM, Tom Warren wrote:
Stephen,
On Tue, Jan 29, 2013 at 2:08 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 01/29/2013 01:40 PM, Tom Warren wrote:
Stephen,
On Tue, Jan 29, 2013 at 1:09 PM, Stephen Warren swar...@wwwdotorg.org wrote:
On 01/29/2013 12:19 PM, Tom Warren wrote:
Note that T114 does not have a separate/different DVC (power I2C)
controller like T20 - all 5 I2C controllers are identical, but
I2C5 is used to designate the controller intended for power
control (PWR_I2C in the schematics).
If you do keep this node, it needs the clocks property filled in.
+ i2c@7000c000 {
+ compatible = nvidia,tegra114-i2c, nvidia,tegra20-i2c;
The I2C nodes also aren't backwards-compatible.
They were on T30 (same compatible string there, except of course
s/114/30/). And the tegra20-i2c is needed for fdtdec.c to find it
(compat_names table).
Yes, I believe the HW changes between Tegra20 and Tegra30 were such that
the Tegra20 driver would run unmodified on Tegra30 without issue. I
don't believe that's the case for Tegra114 though. The solution would be
to add the Tegra114 compatible value to the I2C driver so that it can
search for both.
Looking at the TRMs for both T30 and T114, I2C looks nearly identical,
except for some additional registers tacked onto the end for bus clear
support. 99% of the bits appear exactly the same, too (with the
addition of a bus clear int bit on T114 in an used bit position). I
know next to nothing about I2C, but it appears to me that the current
tegra_I2C.c driver should work fine on T114 (and does, since I can
probe addresses with it). I don't see a need for a different driver
or compat value here.
I Cc'd in Laxman here, since he wrote the Tegra114 I2C support for the
kernel. He made the decision that Tegra114 I2C wasn't compatible with
Tegra20/30 I2C, and can explain that. Certainly looking at the kernel
patch I pointed at, it seems some of the clock divisors must be
programmed differently, which certainly seems enough to declare the HW
blocks incompatible, even if everything else is identical.
Tegra30 i2c driver will not work as straight. There is los of change
which need to be taken care.
I posted the change for kernel driver.
Changes are:
- Enable/disable control for per packet transfer complete interrupt.
Earlier SoCs could not disable this.
- Single clock source for standard/fast and HS mode clock speed.
The clock divisor for fast/standard mode is added into the i2c
controller to meet the HS and standard/fast mode of clock speed
from single source.
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