Re: [U-Boot] [u-boot-release] [PATCH 3/3] board/c29xpcie: Add support of 8K page size NAND flash
> -Original Message- > From: u-boot-release-boun...@linux.freescale.net [mailto:u-boot-release- > boun...@linux.freescale.net] On Behalf Of Kushwaha Prabhakar-B32579 > Sent: Tuesday, September 24, 2013 4:17 PM > To: u-boot@lists.denx.de > Cc: Wood Scott-B07421; Kushwaha Prabhakar-B32579 > Subject: [u-boot-release] [PATCH 3/3] board/c29xpcie: Add support of 8K page > size NAND flash > > Defines constants required to support 8K page size NAND flash. > > Signed-off-by: Prabhakar Kushwaha > --- > Based upon git://git.denx.de/u-boot.git branch master > > include/configs/C29XPCIE.h | 10 ++ > 1 file changed, 6 insertions(+), 4 deletions(-) > > diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index > 83779ef..6a1e145 100644 > --- a/include/configs/C29XPCIE.h > +++ b/include/configs/C29XPCIE.h > @@ -189,13 +189,14 @@ > | CSPR_MSEL_NAND \ > | CSPR_V) > #define CONFIG_SYS_NAND_AMASKIFC_AMASK(64*1024) > +#define CONFIG_SYS_NAND_OOBSIZE 0x0280 /* 640b */ > #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ > | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ > | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ > - | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ > - | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ > - | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ > - | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ > + | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \ > + | CSOR_NAND_PGS_8K /* Page Size = 8K */ \ > + | CSOR_NAND_SPRZ_CSOR_EXT /*oob in csor_ext*/\ > + | CSOR_NAND_PB(128))/*128 Pages Per Block*/ > #define CONFIG_SYS_NAND_FTIM0(FTIM0_NAND_TCCST(0x01) | \ > FTIM0_NAND_TWP(0x0c) | \ > FTIM0_NAND_TWCHT(0x08) | \ Is it possible to do it with ONFI detection automatically instead of defining manually for different devices? such as what Linux driver does. -Shengzhou ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROM
> -Original Message- > From: sun york-R58495 > Sent: Friday, September 13, 2013 11:13 PM > To: Liu Shengzhou-B36685 > Cc: u-boot@lists.denx.de > Subject: Re: [PATCH 2/4] powerpc/eeprom: update MAX_NUM_PORTS to adapt > non-256- > bytes EEPROM > > I would appreciate it if you update the version number and put a change log > under the --- line, even there is no change. With a clear version number and > change log, reviewers will be able to identify this is a resend and not > spending > much time on it. > > You are also encouraged to mark previous patch as "superseded". > > York > Sorry for missing the updated version number, will keep it later. Previous patch has been marked as "superseded". Thanks, Shengzhou ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to adapt non-256-bytes EEPROM
> -Original Message- > From: sun york-R58495 > Sent: Wednesday, September 04, 2013 1:29 AM > To: Timur Tabi > Cc: Liu Shengzhou-B36685; U-Boot Mailing List > Subject: Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to adapt > non- > 256-bytes EEPROM > > On 08/30/2013 06:56 AM, Timur Tabi wrote: > > On Fri, Aug 30, 2013 at 5:07 AM, Shengzhou Liu > > wrote: > > > >> #ifdef CONFIG_SYS_I2C_EEPROM_NXID > >> +/* some boards with non-256-bytes EEPROM have special define */ > >> +/* for MAX_NUM_PORTS in board-specific file */ #ifndef MAX_NUM_PORTS > >> #define MAX_NUM_PORTS 23 > >> +#endif > >> #define NXID_VERSION 1 > >> #endif > > > > I'll have to think about this. On one hand, this works. As long as > > the board-specific value of MAX_NUM_PORTS is valid, then it will work. > > > > On the other hand, it's fragile and violates the specification. An > > NXID v1 EEPROM has the CRC at offset 0xFC. I'm just not sure it > > really matters. > > We need to verify the CRC is still valid. It had been verified on P1010RDB-PB with 128 Bytes, The CRC is still at the end of EEPROM and is still valid. -Shengzhou > > > > York, I'm okay with this patch if you are. You're the one maintaining > > this code now. Is there anyone left at Freescale who cares about the > > integrity of the EEPROM specification? > > Some many boards pop up from different design groups. Unfortunately not all > came > to us to review. It is often too late when we find the design is different. > > York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to fix program failure
> -Original Message- > From: Timur Tabi [mailto:ti...@tabi.org] > Sent: Thursday, August 29, 2013 11:09 PM > To: Liu Shengzhou-B36685 > Cc: U-Boot Mailing List; sun york-R58495 > Subject: Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to fix > program failure > > Actually, the 23 should be changed to 31. York, this patch needs to be > applied: http://patchwork.ozlabs.org/patch/170753/ According to AN3638, it should be 30 rather than 31 for 256-bytes EEPROM. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to fix program failure
> -Original Message- > From: Timur Tabi [mailto:ti...@tabi.org] > Sent: Monday, August 12, 2013 7:51 AM > To: Liu Shengzhou-B36685 > Cc: U-Boot Mailing List; sun york-R58495 > Subject: Re: [U-Boot] [PATCH] powerpc/eeprom: update MAX_NUM_PORTS to fix > program failure > > On Thu, Aug 8, 2013 at 5:14 AM, Shengzhou Liu > wrote: > > On some boards, the size of EEPROM is 128 Bytes instead of 256. > > so we set default MAX_NUM_PORTS to 9 rather than previous 23 to avoid > > the programming failure, we can define MAX_NUM_PORTS in board-specific > > header file to overwrite the default value. > > NACK. > > If the EEPROM is 128 bytes, then you have a non-conformant EEPROM. What is a conformant EEPROM? The size of struct of EEPROM_NXID should be able to conform to real size of EEPROM, regardless it's 128 or 256 EEPROM. It's not reasonable to limit MAX_NUM_PORTS to 23, generally we don't need 23 MAC addresses to store in EEPROM. 23 is just suitable to 256 bytes EEPROM. > And using the #ifdef to determine this is definitely the wrong way. Why? What's your way? ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/p1010rdb: remove CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
It seems there is no CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK in the latest master. I intended to do that for P1010RDB rather than BSC9132, so just drop the patch. Thanks. > -Original Message- > From: sun york-R58495 > Sent: Tuesday, August 20, 2013 7:38 AM > To: Liu Shengzhou-B36685 > Cc: u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH] powerpc/p1010rdb: remove > CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK > > Shengzhou, > > Please check your patch and rebase to latest master if necessary. I cannot > find > CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK for P1010RDB. It does show up for > BSC9132 but I doubt that is what you are trying to remove. > > York ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU hang when missing USB PHY clock
> -Original Message-
> From: Andy Fleming [mailto:aflem...@gmail.com]
> Sent: Saturday, October 20, 2012 5:22 AM
> To: Marek Vasut
> Cc: Liu Shengzhou-B36685; u-boot@lists.denx.de; Stefan Roese
> Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU hang when
> missing USB PHY clock
>
> On Thu, Oct 18, 2012 at 4:04 AM, Marek Vasut wrote:
> > Dear Liu Shengzhou-B36685,
>
> >> > > >
> >> > > > > +/* Check USB PHY clock valid */ static int
> >> > > > > +usb_phy_clk_valid(struct usb_ehci *ehci) {
> >> > > > > + if ((!(in_be32(&ehci->control) & PHY_CLK_VALID)) &&
> >> > > > > + (!in_be32(&ehci->prictrl))) {
> >> > > >
> >> > > > (!A && !B) condition can certainly be done without the double
> >> > > > negation ;-)
> >> > >
> >> > > [Shengzhou] Yes, using !(A||B) is also okay:)
> >> >
> >> > Good, you did your logic homework well. Now go one step further:
> >> >
> >> > if (a || b)
> >> >
> >> > return 1;
> >>
> >> [Shengzhou] No, this doesn't work, b is 0 at initial time, but b is 1
> >> at the second time, a is depend on the register PHY_CLK_VALID bit, We
> >> just want to check it at the first time and then think it is always
> >> valid after that, it's using a trick:)
> >
> > Good point, I was just testing you of course ;-)
>
>
> I may just be dim. Why is this a good point? If
> in_be32(&ehci->prictrl) is non-zero, then this function will return '1'.
> If (in_be32(&ehci->control) & PHY_CLK_VALID) is non-zero, this function
> will return 1.
>
> What am I missing?
>
> Andy
[Shengzhou] Because the indication of PHY_CLK_VALID is time-sensitive, we just
think the value read at the first time is reliable, then PHY_CLK_VALID will be
zero after that though actually PHY clock is still valid.
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Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU hang when missing USB PHY clock
> -Original Message- > From: Anatolij Gustschin [mailto:ag...@denx.de] > Sent: Saturday, October 20, 2012 4:14 AM > To: Liu Shengzhou-B36685 > Cc: Marek Vasut; u-boot@lists.denx.de; Stefan Roese > Subject: Re: [PATCH] powerpc/usb: fix bug of CPU hang when missing USB > PHY clock > > you moved the USB interface enabling before the PHY CLK check but the > commit description doesn't mention why it is needed. It would be good to > mention the reason in the commit log. > > Thanks, > Anatolij [Shengzhou] Ok, will add it in the commit log, thanks. ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU hang when missing USB PHY clock
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Thursday, October 18, 2012 3:16 PM
> To: Liu Shengzhou-B36685
> Cc: u-boot@lists.denx.de; Stefan Roese; ag...@denx.de
> Subject: Re: [PATCH] powerpc/usb: fix bug of CPU hang when missing USB
> PHY clock
>
> Dear Liu Shengzhou-B36685,
>
> > > -Original Message-
> > >
> > > > +/* Check USB PHY clock valid */
> > > > +static int usb_phy_clk_valid(struct usb_ehci *ehci) {
> > > > + if ((!(in_be32(&ehci->control) & PHY_CLK_VALID)) &&
> > > > + (!in_be32(&ehci->prictrl))) {
> > >
> > > (!A && !B) condition can certainly be done without the double negation ;-)
> >
> > [Shengzhou] Yes, using !(A||B) is also okay:)
>
> Good, you did your logic homework well. Now go one step further:
>
> if (a || b)
> return 1;
>
[Shengzhou] No, this doesn't work, b is 0 at initial time, but b is 1 at the
second time, a is depend on the register PHY_CLK_VALID bit,
We just want to check it at the first time and then think it is always valid
after that, it's using a trick:)
> printf()
> return 0;
>
> How will that work?
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Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU hang when missing USB PHY clock
> -Original Message-
> >
> > +/* Check USB PHY clock valid */
> > +static int usb_phy_clk_valid(struct usb_ehci *ehci) {
> > + if ((!(in_be32(&ehci->control) & PHY_CLK_VALID)) &&
> > + (!in_be32(&ehci->prictrl))) {
>
> (!A && !B) condition can certainly be done without the double negation ;-)
[Shengzhou] Yes, using !(A||B) is also okay:)
>
> > + printf("USB PHY clock invalid!\n");
>
> debug() ?
>
[Shengzhou] No, it's not for debug purpose, it should be printf() as a
necessary info.
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Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when missing USB PHY clock
> -Original Message- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: Tuesday, October 16, 2012 2:23 PM > To: Liu Shengzhou-B36685 > Cc: Andy Fleming; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when > missing USB PHY clock > > Dear Liu Shengzhou-B36685, > > > Hello guys, > > > > I didn't get an explicit list from silicon team to point out which > > platforms contain this PHY_CLK_VALID bit or not, Someone said all > > platforms have this bit, it's not true, at least we found P4080 and > > P1022 no this bit. I'll trace it later. > > > > This patch is not necessary for boards with USB PHY clock valid, just > > for those case of USB PHY clock invalid. > > > > Thanks, > > Shengzhou > [...] > > So did anything new happen here or shall I just discard the patch? > > Best regards, > Marek Vasut Hello Marek, I re-submitted a new version as below, please review it. http://patchwork.ozlabs.org/patch/192178/ Thanks, Shengzhou ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when missing USB PHY clock
Hello guys, I didn't get an explicit list from silicon team to point out which platforms contain this PHY_CLK_VALID bit or not, Someone said all platforms have this bit, it's not true, at least we found P4080 and P1022 no this bit. I'll trace it later. This patch is not necessary for boards with USB PHY clock valid, just for those case of USB PHY clock invalid. Thanks, Shengzhou > -Original Message- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: Thursday, April 19, 2012 6:57 AM > To: Andy Fleming > Cc: Liu Shengzhou-B36685; u-boot@lists.denx.de > Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when missing > USB PHY clock > > Dear Andy Fleming, > > > Pinging you on this, again. Also, I've now moved the patch to Marek's > > queue, instead of mine. > > Thanks! Did the FSL silicon team respond already? > > > > > On Sun, Feb 26, 2012 at 8:44 PM, Liu Shengzhou-B36685 > > > > wrote: > > >> -Original Message- > > >> From: Marek Vasut [mailto:ma...@denx.de] > > >> Sent: Monday, February 27, 2012 7:13 AM > > >> To: u-boot@lists.denx.de > > >> Cc: Liu Shengzhou-B36685 > > >> Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when > > >> missing USB PHY clock > > >> > > >> > when missing USB PHY clock and issuing "usb start" at u-boot > > >> > prompt, writing to or_portsc register will cause CPU halt. We > > >> > should check USBGP[PHY_CLK_VALID] bit at the first time in > > >> > ehci_hcd_init() to > > >> > > >> avoid > > >> > > >> > CPU hang in this case. > > >> > > > >> > Signed-off-by: Shengzhou Liu > > >> > --- > > >> > drivers/usb/host/ehci-fsl.c | 22 +++--- > > >> > 1 files changed, 19 insertions(+), 3 deletions(-) > > >> > > >> Hi, > > >> > > >> what's the status of this patch/patchset? > > >> > > >> Thanks > > >> M > > > > > > Currently we found that usb CTRL_PHY_CLK_VALID bit breaks on P1022 > > > platform, which not contains this bit. - P1023/P3041/P5020 etc, have > > > this bit > > > - P3060/4080/PSC913x do have this bit, but not mentioned in RM. > > > - P1022(perhaps and other) has no this bit I'm waiting for the > > > response from FSL silicon team to confirm whether there is other > > > platform not including this bit or not, so this patch maybe have to > > > be pending until I get confirmation. > > > > > > Thanks, > > > Shengzhou > > > > > > > > > ___ > > > U-Boot mailing list > > > U-Boot@lists.denx.de > > > http://lists.denx.de/mailman/listinfo/u-boot > > Best regards, > Marek Vasut ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when missing USB PHY clock
> -Original Message- > From: Marek Vasut [mailto:ma...@denx.de] > Sent: Monday, February 27, 2012 7:13 AM > To: u-boot@lists.denx.de > Cc: Liu Shengzhou-B36685 > Subject: Re: [U-Boot] [PATCH] powerpc/usb: fix bug of CPU halt when > missing USB PHY clock > > > when missing USB PHY clock and issuing "usb start" at u-boot prompt, > > writing to or_portsc register will cause CPU halt. We should check > > USBGP[PHY_CLK_VALID] bit at the first time in ehci_hcd_init() to > avoid > > CPU hang in this case. > > > > Signed-off-by: Shengzhou Liu > > --- > > drivers/usb/host/ehci-fsl.c | 22 +++--- > > 1 files changed, 19 insertions(+), 3 deletions(-) > > > Hi, > > what's the status of this patch/patchset? > > Thanks > M Currently we found that usb CTRL_PHY_CLK_VALID bit breaks on P1022 platform, which not contains this bit. - P1023/P3041/P5020 etc, have this bit - P3060/4080/PSC913x do have this bit, but not mentioned in RM. - P1022(perhaps and other) has no this bit I'm waiting for the response from FSL silicon team to confirm whether there is other platform not including this bit or not, so this patch maybe have to be pending until I get confirmation. Thanks, Shengzhou ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] powerpc/usb: fix bug of CPU halt when missing USB PHY clock
> -Original Message- > From: Andy Fleming [mailto:aflem...@gmail.com] > Sent: Monday, February 13, 2012 4:14 PM > To: Liu Shengzhou-B36685; U-Boot list > Subject: Re: powerpc/usb: fix bug of CPU halt when missing USB PHY > clock > > You moved the USB_EN setting: > > > + /* Enable interface. */ > + setbits_be32(&ehci->control, USB_EN); > + > > [...] > > - /* Enable interface. */ > - setbits_be32(&ehci->control, USB_EN); > - > > > Should we clear this bit if we don't find a valid clock? The patch > description didn't say why you moved this write. > > Andy To read ehci->control[PHY_CLK_VALID], we have to first enable it, or it will hang when reading control[PHY_CLK_VALID]. -Shengzhou ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
