[U-Boot] [PATCH] Replace "extern inline" with "static inline"
A number of headers define functions as "extern inline" which is
causing problems with gcc5. The reason is that starting with
version 5.1, gcc defaults to the standard C99 semantics for the
inline keyword.
Under the traditional GNU inline semantics, an "extern inline"
function would never create an external definition, the same
as inline *without* extern in C99. In C99, and "extern inline"
definition is simply an external definition with an inline hint.
In short, the meanings of inline with and without extern are
swapped between GNU and C99.
The upshot is that all these definitions in header files create
an external definition wherever those headers are included,
resulting in multiple definition errors at link time.
Changing all these functions to "static inline" fixes the problem
since this works as desired in all gcc versions. Although the
semantics are slightly different (a static inline definition may
result in an actual function being emitted), it works as intended
in practice.
This patch also removes extern prototype declarations for the
changed functions where they existed.
Signed-off-by: Mans Rullgard
---
This is just a quick, automatic replace. I have not tested it.
I'm not sure I got all the extern prototypes. Microblaze not
included since someone already sent a patch for that.
---
arch/blackfin/include/asm/delay.h | 4 +--
arch/m68k/include/asm/bitops.h| 5 ++--
arch/m68k/include/asm/byteorder.h | 8 +++---
arch/m68k/include/asm/io.h| 40 ++---
arch/powerpc/include/asm/atomic.h | 8 +++---
arch/powerpc/include/asm/bitops.h | 35 ++---
arch/powerpc/include/asm/byteorder.h | 8 +++---
arch/powerpc/include/asm/io.h | 20 +++
arch/powerpc/include/asm/iopin_8260.h | 40 ++---
arch/powerpc/include/asm/iopin_8xx.h | 48 +--
arch/sparc/include/asm/irq.h | 4 +--
arch/sparc/include/asm/psr.h | 6 ++---
arch/sparc/include/asm/srmmu.h| 30 +++---
include/mpc8260.h | 2 +-
14 files changed, 125 insertions(+), 133 deletions(-)
diff --git a/arch/blackfin/include/asm/delay.h
b/arch/blackfin/include/asm/delay.h
index 97401a7..f146efd 100644
--- a/arch/blackfin/include/asm/delay.h
+++ b/arch/blackfin/include/asm/delay.h
@@ -16,7 +16,7 @@
* Delay routines, using a pre-computed "loops_per_second" value.
*/
-extern __inline__ void __delay(unsigned long loops)
+static __inline__ void __delay(unsigned long loops)
{
__asm__ __volatile__("1:\t%0 += -1;\n\t"
"cc = %0 == 0;\n\t"
@@ -31,7 +31,7 @@ extern __inline__ void __delay(unsigned long loops)
* first constant multiplications gets optimized away if the delay is
* a constant)
*/
-extern __inline__ void __udelay(unsigned long usecs)
+static __inline__ void __udelay(unsigned long usecs)
{
__delay(usecs);
}
diff --git a/arch/m68k/include/asm/bitops.h b/arch/m68k/include/asm/bitops.h
index f9c434b..6b79a0d 100644
--- a/arch/m68k/include/asm/bitops.h
+++ b/arch/m68k/include/asm/bitops.h
@@ -10,21 +10,20 @@
extern void set_bit(int nr, volatile void *addr);
extern void clear_bit(int nr, volatile void *addr);
extern void change_bit(int nr, volatile void *addr);
-extern int test_and_set_bit(int nr, volatile void *addr);
extern int test_and_clear_bit(int nr, volatile void *addr);
extern int test_and_change_bit(int nr, volatile void *addr);
#ifdef __KERNEL__
-extern inline int test_bit(int nr, __const__ volatile void *addr)
+static inline int test_bit(int nr, __const__ volatile void *addr)
{
__const__ unsigned int *p = (__const__ unsigned int *) addr;
return (p[nr >> 5] & (1UL << (nr & 31))) != 0;
}
-extern inline int test_and_set_bit(int nr, volatile void *vaddr)
+static inline int test_and_set_bit(int nr, volatile void *vaddr)
{
char retval;
diff --git a/arch/m68k/include/asm/byteorder.h
b/arch/m68k/include/asm/byteorder.h
index 908a99b..7244b75 100644
--- a/arch/m68k/include/asm/byteorder.h
+++ b/arch/m68k/include/asm/byteorder.h
@@ -22,25 +22,25 @@
(((__u32)(x) & (__u32)0x00ffUL) >> 8) | \
(((__u32)(x)) >> 24) ))
-extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+static __inline__ unsigned ld_le16(const volatile unsigned short *addr)
{
unsigned result = *addr;
return __sw16(result);
}
-extern __inline__ void st_le16(volatile unsigned short *addr,
+static __inline__ void st_le16(volatile unsigned short *addr,
const unsigned val)
{
*addr = __sw16(val);
}
-extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+static __inline__ unsigned ld_le32(const volatile unsigned *addr)
{
unsig
[U-Boot] [PATCH 2/2] net: fec_mxc: unregister mdio bus on probe error
If fecmxc_initialize_multi() fails, it frees but does not unregister
the mdio bus, causing subsequent uses of the "mii" command to crash.
Fix this by adding mdio_unregister() calls where needed.
Signed-off-by: Mans Rullgard
---
drivers/net/fec_mxc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 1250d2a..6c5e80b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -1109,6 +1109,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int
phy_id, uint32_t addr)
#ifdef CONFIG_PHYLIB
phydev = phy_find_by_mask(bus, 1 << phy_id, PHY_INTERFACE_MODE_RGMII);
if (!phydev) {
+ mdio_unregister(bus);
free(bus);
return -ENOMEM;
}
@@ -1120,6 +1121,7 @@ int fecmxc_initialize_multi(bd_t *bd, int dev_id, int
phy_id, uint32_t addr)
#ifdef CONFIG_PHYLIB
free(phydev);
#endif
+ mdio_unregister(bus);
free(bus);
}
return ret;
--
2.6.3
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[U-Boot] [PATCH 1/2] net: fec_mxc: configure MDIO hold time
If the host clock frequency is higher than 100 MHz, the MDIO hold
time needs to be increased from its current setting of one cycle in
order to meet the specified minium of 10 ns. Writing an appropriate
value to the HOLDTIME field of the MII_SPEED register achieves this.
Comment copied from Linux kernel.
Signed-off-by: Mans Rullgard
---
drivers/net/fec_mxc.c | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 79f6737..1250d2a 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -131,13 +131,25 @@ static void fec_mii_setspeed(struct ethernet_regs *eth)
/*
* Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
* and do not drop the Preamble.
+*
+* The i.MX28 and i.MX6 types have another filed in the MSCR (aka
+* MII_SPEED) register that defines the MDIO output hold time. Earlier
+* versions are RAZ there, so just ignore the difference and write the
+* register always.
+* The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
+* HOLDTIME + 1 is the number of clk cycles the fec is holding the
+* output.
+* The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
+* Given that ceil(clkrate / 500) <= 64, the calculation for
+* holdtime cannot result in a value greater than 3.
*/
- register u32 speed = DIV_ROUND_UP(imx_get_fecclk(), 500);
+ u32 pclk = imx_get_fecclk();
+ u32 speed = DIV_ROUND_UP(pclk, 500);
+ u32 hold = DIV_ROUND_UP(pclk, 1) - 1;
#ifdef FEC_QUIRK_ENET_MAC
speed--;
#endif
- speed <<= 1;
- writel(speed, ð->mii_speed);
+ writel(speed << 1 | hold << 8, ð->mii_speed);
debug("%s: mii_speed %08x\n", __func__, readl(ð->mii_speed));
}
--
2.6.3
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[U-Boot] [PATCH] gpio: mxs: add name_to_gpio() function
Override the default name_to_gpio() function with one that
accepts strings of the form bank:pin. If a colon is present
in the provided name, it behaves like the default version.
This lets the "gpio" command work with sane names rather than
requiring the user to enter the bank/pin composite in decimal.
Signed-off-by: Mans Rullgard
---
drivers/gpio/mxs_gpio.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c
index da0199b..b54a10b 100644
--- a/drivers/gpio/mxs_gpio.c
+++ b/drivers/gpio/mxs_gpio.c
@@ -114,3 +114,18 @@ int gpio_free(unsigned gpio)
{
return 0;
}
+
+int name_to_gpio(const char *name)
+{
+ unsigned bank, pin;
+ char *end;
+
+ bank = simple_strtoul(name, &end, 10);
+
+ if (!*end || *end != ':')
+ return bank;
+
+ pin = simple_strtoul(end + 1, NULL, 10);
+
+ return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT);
+}
--
2.6.3
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[U-Boot] [PATCH] OMAP3: set L1NEON bit in aux control register
This is required to work around ARM erratum 621766, affecting
Cortex-A8 r1p0-3:
When a sequence of Neon load instructions is intermixed with several
branches, some of which are mispredicted, it is possible for the
processor to deadlock due to Neon loads on the speculative path not
being properly flushed from the Neon load queue.
Signed-off-by: Mans Rullgard <[EMAIL PROTECTED]>
---
cpu/arm_cortexa8/omap3/board.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/cpu/arm_cortexa8/omap3/board.c b/cpu/arm_cortexa8/omap3/board.c
index 90809a6..7c2a7ea 100644
--- a/cpu/arm_cortexa8/omap3/board.c
+++ b/cpu/arm_cortexa8/omap3/board.c
@@ -139,6 +139,8 @@ void setup_auxcr()
__asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1");
/* Enabling ASA */
__asm__ __volatile__("orr r0, r0, #0x10");
+ /* Enable L1NEON */
+ __asm__ __volatile__("orr r0, r0, #1<<5");
/* SMI instruction to call ROM Code API */
__asm__ __volatile__(".word 0xE1600070");
__asm__ __volatile__("mov r0, %0":"=r"(i));
--
1.6.0.3
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[U-Boot] [PATCH 1/5] ARM: mxs: make lowlevel_init() weak
With the full SPL framework enabled, lowlevel_init() is required.
Make the empty stub weak so boards can override it.
Signed-off-by: Mans Rullgard
---
arch/arm/cpu/arm926ejs/mxs/mxs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 7a68a8f3ca74..5c7817074fd6 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -24,7 +24,7 @@
DECLARE_GLOBAL_DATA_PTR;
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
-void lowlevel_init(void) {}
+__weak void lowlevel_init(void) {}
void reset_cpu(ulong ignored) __attribute__((noreturn));
--
2.17.0
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[U-Boot] [PATCH 3/5] ARM: spl: include arm/thumb glue sections
When building in Thumb mode, the linker might generate mode switching stubs in .glue sections. Include these in the final link. Signed-off-by: Mans Rullgard --- arch/arm/cpu/u-boot-spl.lds | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/cpu/u-boot-spl.lds b/arch/arm/cpu/u-boot-spl.lds index 65f7b68861e2..38fc9b44c8c7 100644 --- a/arch/arm/cpu/u-boot-spl.lds +++ b/arch/arm/cpu/u-boot-spl.lds @@ -21,6 +21,7 @@ SECTIONS *(.vectors) CPUDIR/start.o (.text*) *(.text*) + *(.glue*) } . = ALIGN(4); -- 2.17.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/5] ARM: arm926ejs: fix lowlevel_init call
The code attempts to preserve the value of LR by storing it in R12/IP across the lowevel_init() call. However, this register is not saved by the callee. Use a register that guaranteed to be preserved instead. Signed-off-by: Mans Rullgard --- arch/arm/cpu/arm926ejs/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index 959d1ed86d8a..a6f0bdb70345 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -105,9 +105,9 @@ flush_dcache: /* * Go setup Memory and board specific bits prior to relocation. */ - mov ip, lr /* perserve link reg across call */ + mov r4, lr /* perserve link reg across call */ bl lowlevel_init /* go setup pll,mux,memory */ - mov lr, ip /* restore link */ + mov lr, r4 /* restore link */ #endif mov pc, lr /* back to my caller */ #endif /* CONFIG_SKIP_LOWLEVEL_INIT */ -- 2.17.0 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 4/5] ARM: mxs: move spl data
With full SPL enabled, the loaded image overwrites the mxs_spl_data
location. Moving it a slightly lower address fixes this.
Signed-off-by: Mans Rullgard
---
arch/arm/cpu/arm926ejs/mxs/mxs.c | 6 ++
arch/arm/cpu/arm926ejs/mxs/spl_boot.c | 3 +--
arch/arm/include/asm/arch-mxs/sys_proto.h | 2 ++
3 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxs.c b/arch/arm/cpu/arm926ejs/mxs/mxs.c
index 5c7817074fd6..09b5c04cc9d2 100644
--- a/arch/arm/cpu/arm926ejs/mxs/mxs.c
+++ b/arch/arm/cpu/arm926ejs/mxs/mxs.c
@@ -178,8 +178,7 @@ const char *get_imx_type(u32 imxtype)
int print_cpuinfo(void)
{
u32 cpurev;
- struct mxs_spl_data *data = (struct mxs_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+ struct mxs_spl_data *data = MXS_SPL_DATA;
cpurev = get_cpu_rev();
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
@@ -277,8 +276,7 @@ void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
int mxs_dram_init(void)
{
- struct mxs_spl_data *data = (struct mxs_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+ struct mxs_spl_data *data = MXS_SPL_DATA;
if (data->mem_dram_size == 0) {
printf("MXS:\n"
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index d9d1d73d1af4..0c3925640dc9 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -120,8 +120,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t
*resptr,
const iomux_cfg_t *iomux_setup,
const unsigned int iomux_size)
{
- struct mxs_spl_data *data = (struct mxs_spl_data *)
- ((CONFIG_SYS_TEXT_BASE - sizeof(struct mxs_spl_data)) & ~0xf);
+ struct mxs_spl_data *data = MXS_SPL_DATA;
uint8_t bootmode = mxs_get_bootmode_index();
gd = &gdata;
diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h
b/arch/arm/include/asm/arch-mxs/sys_proto.h
index 609676375b55..b23ee6d88768 100644
--- a/arch/arm/include/asm/arch-mxs/sys_proto.h
+++ b/arch/arm/include/asm/arch-mxs/sys_proto.h
@@ -85,6 +85,8 @@ static const struct mxs_pair mxs_boot_modes[] = {
#define MXS_BM_SDMMC1_3V3 0x0a
#define MXS_BM_SDMMC1_1V8 0x1a
+#define MXS_SPL_DATA ((struct mxs_spl_data *)(CONFIG_SYS_TEXT_BASE - 0x200))
+
struct mxs_spl_data {
uint8_t boot_mode_idx;
uint32_tmem_dram_size;
--
2.17.0
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[U-Boot] [PATCH 5/5] ARM: mxs: support full SPL framework
This allows using the full SPL framework on mxs devices. In this
mode, the u-boot.sb image loaded by the boot ROM contains only the
SPL which then loads U-Boot proper or a kernel in falcon mode.
Signed-off-by: Mans Rullgard
---
arch/arm/Kconfig | 2 +-
arch/arm/cpu/arm926ejs/mxs/Makefile | 4 ++--
arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg | 5 +
arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg | 6 ++
arch/arm/cpu/arm926ejs/mxs/spl_boot.c| 2 ++
include/configs/mxs.h| 2 ++
6 files changed, 18 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg
create mode 100644 arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 7212fc5afa72..0acdd162b4b3 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1352,7 +1352,7 @@ source "arch/arm/Kconfig.debug"
endmenu
config SPL_LDSCRIPT
-default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if ARCH_MX23 ||
ARCH_MX28
+default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 ||
ARCH_MX28) && !SPL_FRAMEWORK
default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile
b/arch/arm/cpu/arm926ejs/mxs/Makefile
index 71c2c0e7b40c..83b05acfa4eb 100644
--- a/arch/arm/cpu/arm926ejs/mxs/Makefile
+++ b/arch/arm/cpu/arm926ejs/mxs/Makefile
@@ -14,8 +14,8 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o
spl_power_init.o
endif
# Specify the target for use in elftosb call
-MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage.mx23.cfg
-MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage.mx28.cfg
+MKIMAGE_TARGET-$(CONFIG_MX23) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx23.cfg
+MKIMAGE_TARGET-$(CONFIG_MX28) = mxsimage$(CONFIG_SPL_FRAMEWORK:%=-spl).mx28.cfg
# Generate HAB-capable IVT
#
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg
b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg
new file mode 100644
index ..ab2183ed3795
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx23.cfg
@@ -0,0 +1,5 @@
+DISPLAYPROGRESS
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD 0x1000 spl/u-boot-spl.bin
+ CALL 0x1000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg
b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg
new file mode 100644
index ..0d95064ff7f1
--- /dev/null
+++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage-spl.mx28.cfg
@@ -0,0 +1,6 @@
+DISPLAYPROGRESS
+SECTION 0x0 BOOTABLE
+ TAG LAST
+ LOAD 0x1000 spl/u-boot-spl.bin
+ LOAD IVT 0x8000 0x1000
+ CALL HAB 0x8000 0x0
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
index 0c3925640dc9..bc39465fc4e0 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_boot.c
@@ -146,6 +146,7 @@ void mxs_common_spl_init(const uint32_t arg, const uint32_t
*resptr,
}
}
+#ifndef CONFIG_SPL_FRAMEWORK
/* Support aparatus */
inline void board_init_f(unsigned long bootflag)
{
@@ -158,3 +159,4 @@ inline void board_init_r(gd_t *id, ulong dest_addr)
for (;;)
;
}
+#endif
diff --git a/include/configs/mxs.h b/include/configs/mxs.h
index f07f81c8415c..0fe0770e13f0 100644
--- a/include/configs/mxs.h
+++ b/include/configs/mxs.h
@@ -44,8 +44,10 @@
/* Startup hooks */
/* SPL */
+#ifndef CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_NO_CPU_SUPPORT_CODE
#define CONFIG_SPL_START_S_PATH"arch/arm/cpu/arm926ejs/mxs"
+#endif
/* Memory sizes */
#define CONFIG_SYS_MALLOC_LEN 0x0040 /* 4 MB for malloc */
--
2.17.0
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[U-Boot] [PATCH] ARM: mxs: let boards override entire dram parameter table
If many values differ from the defaults, overriding the full table
is simpler and more space efficient than tweaking it through
mxs_adjust_memory_params().
Signed-off-by: Mans Rullgard
---
arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
index a744e5d4990a..a19cfc50449f 100644
--- a/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
+++ b/arch/arm/cpu/arm926ejs/mxs/spl_mem_init.c
@@ -16,7 +16,7 @@
#include "mxs_init.h"
-static uint32_t dram_vals[] = {
+__weak uint32_t mxs_dram_vals[] = {
/*
* i.MX28 DDR2 at 200MHz
*/
@@ -101,11 +101,11 @@ static void initialize_dram_values(void)
int i;
debug("SPL: Setting mx28 board specific SDRAM parameters\n");
- mxs_adjust_memory_params(dram_vals);
+ mxs_adjust_memory_params(mxs_dram_vals);
debug("SPL: Applying SDRAM parameters\n");
- for (i = 0; i < ARRAY_SIZE(dram_vals); i++)
- writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++)
+ writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
#else
static void initialize_dram_values(void)
@@ -113,7 +113,7 @@ static void initialize_dram_values(void)
int i;
debug("SPL: Setting mx23 board specific SDRAM parameters\n");
- mxs_adjust_memory_params(dram_vals);
+ mxs_adjust_memory_params(mxs_dram_vals);
/*
* HW_DRAM_CTL27, HW_DRAM_CTL28 and HW_DRAM_CTL35 are not initialized as
@@ -125,10 +125,10 @@ static void initialize_dram_values(void)
* So skip the initialization of these HW_DRAM_CTL registers.
*/
debug("SPL: Applying SDRAM parameters\n");
- for (i = 0; i < ARRAY_SIZE(dram_vals); i++) {
+ for (i = 0; i < ARRAY_SIZE(mxs_dram_vals); i++) {
if (i == 8 || i == 27 || i == 28 || i == 35)
continue;
- writel(dram_vals[i], MXS_DRAM_BASE + (4 * i));
+ writel(mxs_dram_vals[i], MXS_DRAM_BASE + (4 * i));
}
/*
--
2.17.0
___
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[U-Boot] [UNTESTED PATCH] ARM: orion5x: fix use of callee-saved registers in lowloevel_init
The lowlevel_init function uses r4 and r6 without preserving their values as required by the AAPCS. Use r0 and r2 instead as these are call-clobbered. Signed-off-by: Mans Rullgard --- arch/arm/mach-orion5x/lowlevel_init.S | 168 +- 1 file changed, 84 insertions(+), 84 deletions(-) diff --git a/arch/arm/mach-orion5x/lowlevel_init.S b/arch/arm/mach-orion5x/lowlevel_init.S index 3f38f36ff294..a4e113601013 100644 --- a/arch/arm/mach-orion5x/lowlevel_init.S +++ b/arch/arm/mach-orion5x/lowlevel_init.S @@ -72,67 +72,67 @@ lowlevel_init: #ifdef CONFIG_SPL_BUILD - /* Use 'r4 as the base for internal register accesses */ - ldr r4, =ORION5X_REGS_PHY_BASE + /* Use 'r2 as the base for internal register accesses */ + ldr r2, =ORION5X_REGS_PHY_BASE /* move internal registers from the default 0xD000 * to their intended location, defined by SoC */ ldr r3, =0xD000 add r3, r3, #0x2 - str r4, [r3, #0x80] + str r2, [r3, #0x80] /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r2, #0x01000 /*DDR SDRAM Initialization Control */ - ldr r6, =0x0001 - str r6, [r3, #0x480] + ldr r0, =0x0001 + str r0, [r3, #0x480] /* Use R3 as the base for PCI registers */ - add r3, r4, #0x31000 + add r3, r2, #0x31000 /* Disable arbiter */ - ldr r6, =0x0030 - str r6, [r3, #0xd00] + ldr r0, =0x0030 + str r0, [r3, #0xd00] /* Use R3 as the base for DRAM registers */ - add r3, r4, #0x01000 + add r3, r2, #0x01000 /* set all dram windows to 0 */ - mov r6, #0 - str r6, [r3, #0x504] - str r6, [r3, #0x50C] - str r6, [r3, #0x514] - str r6, [r3, #0x51C] + mov r0, #0 + str r0, [r3, #0x504] + str r0, [r3, #0x50C] + str r0, [r3, #0x514] + str r0, [r3, #0x51C] /* 1) Configure SDRAM */ - ldr r6, =SDRAM_CONFIG - str r6, [r3, #0x400] + ldr r0, =SDRAM_CONFIG + str r0, [r3, #0x400] /* 2) Set SDRAM Control reg */ - ldr r6, =SDRAM_CONTROL - str r6, [r3, #0x404] + ldr r0, =SDRAM_CONTROL + str r0, [r3, #0x404] /* 3) Write SDRAM address control register */ - ldr r6, =SDRAM_ADDR_CTRL - str r6, [r3, #0x410] + ldr r0, =SDRAM_ADDR_CTRL + str r0, [r3, #0x410] /* 4) Write SDRAM bank 0 size register */ - ldr r6, =SDRAM_BANK0_SIZE - str r6, [r3, #0x504] + ldr r0, =SDRAM_BANK0_SIZE + str r0, [r3, #0x504] /* keep other banks disabled */ /* 5) Write SDRAM open pages control register */ - ldr r6, =SDRAM_OPEN_PAGE_EN - str r6, [r3, #0x414] + ldr r0, =SDRAM_OPEN_PAGE_EN + str r0, [r3, #0x414] /* 6) Write SDRAM timing Low register */ - ldr r6, =SDRAM_TIME_CTRL_LOW - str r6, [r3, #0x408] + ldr r0, =SDRAM_TIME_CTRL_LOW + str r0, [r3, #0x408] /* 7) Write SDRAM timing High register */ - ldr r6, =SDRAM_TIME_CTRL_HI - str r6, [r3, #0x40C] + ldr r0, =SDRAM_TIME_CTRL_HI + str r0, [r3, #0x40C] /* 8) Write SDRAM mode register */ /* The CPU must not attempt to change the SDRAM Mode register setting */ @@ -143,73 +143,73 @@ lowlevel_init: /* and then sets SDRAM Mode register to its new value.*/ /* 8.1 write 'nop' to SDRAM operation */ - ldr r6, =SDRAM_OP_NOP - str r6, [r3, #0x418] + ldr r0, =SDRAM_OP_NOP + str r0, [r3, #0x418] /* 8.2 poll SDRAM operation until back in 'normal' mode. */ 1: - ldr r6, [r3, #0x418] - cmp r6, #0 + ldr r0, [r3, #0x418] + cmp r0, #0 bne 1b /* 8.3 Now its safe to write new value to SDRAM Mode register */ - ldr r6, =SDRAM_MODE - str r6, [r3, #0x41C] + ldr r0, =SDRAM_MODE + str r0, [r3, #0x41C] /* 8.4 Set new mode */ - ldr r6, =SDRAM_OP_SETMODE - str r6, [r3, #0x418] + ldr r0, =SDRAM_OP_SETMODE + str r0, [r3, #0x418] /* 8.5 poll SDRAM operation until back in 'normal' mode. */ 2: - ldr r6, [r3, #0x418] - cmp r6, #0 + ldr r0, [r3, #0x418] + cmp r0, #0 bne 2b /* DDR SDRAM Address/Control Pads Calibration */ - ldr r6, [r3, #0x4C0] + ldr r0, [r3, #0x4C0] /* Set Bit [31] to make the register writable */ - orr r6, r6, #SDRA
