Re: [U-Boot] [PATCH 10/11] evb-ast2500: Enable CONFIG_DM_MMC
Sounds good to me. Reviewed-by: Maksym Sloyko From: Simon Glass Date: Sat, May 11, 2019 at 12:26 PM To: U-Boot Mailing List Cc: Tom Rini, Marek Vasut, Simon Glass, Maxim Sloyko > This board builds with this option (although it may not work). Enable it > to stave off board removal for a bit. > > Signed-off-by: Simon Glass > --- > > configs/evb-ast2500_defconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig > index 7fb52d2732..bf630df565 100644 > --- a/configs/evb-ast2500_defconfig > +++ b/configs/evb-ast2500_defconfig > @@ -20,6 +20,7 @@ CONFIG_REGMAP=y > CONFIG_CLK=y > CONFIG_DM_I2C=y > CONFIG_SYS_I2C_ASPEED=y > +CONFIG_DM_MMC=y > CONFIG_PHY_REALTEK=y > CONFIG_DM_ETH=y > CONFIG_FTGMAC100=y > -- > 2.21.0.1020.gf2820cf01a-goog > -- Maxim Sloyko ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] aspeed: ast2500: Add AHB clock
On Tue, Sep 11, 2018 at 12:35 AM, Joel Stanley wrote:
> On Mon, 10 Sep 2018 at 23:48, Cédric Le Goater wrote:
> >
> > The AHB clock is used by the FMC/SPI controllers.
> >
> > Signed-off-by: Cédric Le Goater
> > ---
> > arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 2 ++
> > include/dt-bindings/clock/ast2500-scu.h| 1 +
> > drivers/clk/aspeed/clk_ast2500.c | 12
> > 3 files changed, 15 insertions(+)
> >
> > diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > index 4988ced7ddcc..6a90ded752ad 100644
> > --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > @@ -11,6 +11,8 @@
> > #define SCU_HWSTRAP_VGAMEM_MASK(3 <<
> SCU_HWSTRAP_VGAMEM_SHIFT)
> > #define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
> > #define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
> > +#define SCU_HWSTRAP_AXIAHB_DIV_SHIFT 9
> > +#define SCU_HWSTRAP_AXIAHB_DIV_MASK(0x7 <<
> SCU_HWSTRAP_AXIAHB_DIV_SHIFT)
> > #define SCU_HWSTRAP_DDR4 (1 << 24)
> > #define SCU_HWSTRAP_CLKIN_25MHZ(1 << 23)
> >
> > diff --git a/include/dt-bindings/clock/ast2500-scu.h
> b/include/dt-bindings/clock/ast2500-scu.h
> > index 4803abe9f628..03e6d16d3de0 100644
> > --- a/include/dt-bindings/clock/ast2500-scu.h
> > +++ b/include/dt-bindings/clock/ast2500-scu.h
> > @@ -17,6 +17,7 @@
> > #define BCLK_MACCLK103
> > #define BCLK_SDCLK 104
> > #define BCLK_ARMCLK105
> > +#define BCLK_HCLK 106
>
> I like how the clocks are grouped in this file. Are we confident that
> HCLK is going in the correct spot?
>
> > #define MCLK_DDR 201
> >
> > diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_
> ast2500.c
> > index 526470051c5d..c55f8d5ae30d 100644
> > --- a/drivers/clk/aspeed/clk_ast2500.c
> > +++ b/drivers/clk/aspeed/clk_ast2500.c
> > @@ -143,6 +143,18 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
> > rate = rate / apb_div;
> > }
> > break;
> > + case BCLK_HCLK:
> > + {
> > + ulong ahb_div = 1 + ((readl(&priv->scu->hwstrap)
> > + &
> SCU_HWSTRAP_AXIAHB_DIV_MASK)
> > +>>
> SCU_HWSTRAP_AXIAHB_DIV_SHIFT);
> > + ulong axi_div = 2;
> > +
> > + rate = ast2500_get_hpll_rate(
> > + clkin, readl(&priv->scu->h_pll_param));
> > + rate = rate / axi_div / ahb_div;
>
> In the kernel driver I wrote it as:
>
> rate / (axi_div + ahb_div)
>
These are two different formulae -- just want to make sure that the typo
only made it into an email :)
In any case, the exact right way to do this computation depends on how this
is implemented in the hardware itself. Most likely it's to dividers in
sequence, so dividing twice should be more accurate. Of course it would be
nice if somebody with hw design experience could comment.
If the datasheet has formula, I think the right way is to use it exactly as
stated.
>
> I know that the maths works, but do the numbers come out as we expect
> when doing integer division?
>
--
*M*axim *S*loyko
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Re: [U-Boot] License violations
Hi Jon, This looks like a good start: https://opensource.org/faq#copyleft-violation On Tue, Dec 19, 2017 at 9:21 PM, Jon 'jcase' Sawyer wrote: > I've been attempting to obtain source to the u boot implementation in a > tablet used to control DJI drones, called crystal sky. Today after many > games of chase the tail, DJI came back and told me they wouldn't release > it. > > Is there anyone more capable, who could help put some pressure on this > large corperation? > > > > JC > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot > -- *M*axim *S*loyko ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2] wdt: Update uclass to make clear that the timeout is in ms
On Fri, Aug 4, 2017 at 2:48 PM, Simon Glass wrote:
> From: Andy Shevchenko
>
> Convert name to show explicitly that we are using milliseconds. For a
> watchdog timer this is precise enough.
>
> No functional change intended.
>
> Signed-off-by: Andy Shevchenko
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2:
> - Use milliseconds since microseconds seems too fine a control
> - Update commit message to suit
>
> drivers/watchdog/wdt-uclass.c | 4 ++--
> include/wdt.h | 8
> 2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
> index bb9ae80866..8a30f024fd 100644
> --- a/drivers/watchdog/wdt-uclass.c
> +++ b/drivers/watchdog/wdt-uclass.c
> @@ -13,14 +13,14 @@
>
> DECLARE_GLOBAL_DATA_PTR;
>
> -int wdt_start(struct udevice *dev, u64 timeout, ulong flags)
> +int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
> {
> const struct wdt_ops *ops = device_get_ops(dev);
>
> if (!ops->start)
> return -ENOSYS;
>
> - return ops->start(dev, timeout, flags);
> + return ops->start(dev, timeout_ms, flags);
> }
>
> int wdt_stop(struct udevice *dev)
> diff --git a/include/wdt.h b/include/wdt.h
> index 0b5f05851a..9b90fbeeb3 100644
> --- a/include/wdt.h
> +++ b/include/wdt.h
> @@ -21,12 +21,12 @@
> * Start the timer
> *
> * @dev: WDT Device
> - * @timeout: Number of ticks before timer expires
> + * @timeout_ms: Number of ticks (milliseconds) before timer expires
These are not the same and this is definitely a functional change. The
length of a single tick depends on frequency of the clock that feeds
WDT. It might not be the same as 1/SYS_HZ. For example ast_wdt driver
uses 1MHz clock, so this parameter means microseconds for it.
> * @flags: Driver specific flags. This might be used to specify
> * which action needs to be executed when the timer expires
> * @return: 0 if OK, -ve on error
> */
> -int wdt_start(struct udevice *dev, u64 timeout, ulong flags);
> +int wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags);
>
> /*
> * Stop the timer, thus disabling the Watchdog. Use wdt_start to start it
> again.
> @@ -67,12 +67,12 @@ struct wdt_ops {
> * Start the timer
> *
> * @dev: WDT Device
> -* @timeout: Number of ticks before the timer expires
> +* @timeout_ms: Number of ticks (milliseconds) before the timer
> expires
> * @flags: Driver specific flags. This might be used to specify
> * which action needs to be executed when the timer expires
> * @return: 0 if OK, -ve on error
> */
> - int (*start)(struct udevice *dev, u64 timeout, ulong flags);
> + int (*start)(struct udevice *dev, u64 timeout_ms, ulong flags);
> /*
> * Stop the timer
> *
> --
> 2.14.0.rc1.383.gd1ce394fe2-goog
>
--
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[U-Boot] [PATCH v2 14/15] aspeed: Refactor SCU to use consistent mask & shift
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 12
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 5 ++--
drivers/clk/aspeed/clk_ast2500.c | 39 +-
3 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fe877b5430..590aed2f6c 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -8,8 +8,8 @@
#define SCU_UNLOCK_VALUE 0x1688a8a8
-#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_VGAMEM_MASK(3 << SCU_HWSTRAP_VGAMEM_SHIFT)
#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
@@ -18,17 +18,17 @@
#define SCU_MPLL_DENUM_SHIFT 0
#define SCU_MPLL_DENUM_MASK0x1f
#define SCU_MPLL_NUM_SHIFT 5
-#define SCU_MPLL_NUM_MASK 0xff
+#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
#define SCU_MPLL_POST_SHIFT13
-#define SCU_MPLL_POST_MASK 0x3f
+#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
#define SCU_PCLK_DIV_SHIFT 23
-#define SCU_PCLK_DIV_MASK 7
+#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK0x1f
#define SCU_HPLL_NUM_SHIFT 5
-#define SCU_HPLL_NUM_MASK 0xff
+#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
#define SCU_HPLL_POST_SHIFT13
-#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
#define SCU_MACCLK_SHIFT 16
#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index efcf452b17..6383f727f2 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -183,9 +183,8 @@ static int ast2500_sdrammc_ddr4_calibrate_vref(struct
dram_info *info)
static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
{
size_t vga_mem_size_base = 8 * 1024 * 1024;
- u32 vga_hwconf = (readl(&info->scu->hwstrap)
- >> SCU_HWSTRAP_VGAMEM_SHIFT)
- & SCU_HWSTRAP_VGAMEM_MASK;
+ u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
+ >> SCU_HWSTRAP_VGAMEM_SHIFT;
return vga_mem_size_base << vga_hwconf;
}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 7b4b5c64ac..ccf47a1da1 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -52,11 +52,11 @@ struct ast2500_div_config {
*/
static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
{
- const ulong num = (mpll_reg >> SCU_MPLL_NUM_SHIFT) & SCU_MPLL_NUM_MASK;
- const ulong denum = (mpll_reg >> SCU_MPLL_DENUM_SHIFT)
- & SCU_MPLL_DENUM_MASK;
- const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
- & SCU_MPLL_POST_MASK;
+ const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
+ const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
+ >> SCU_MPLL_DENUM_SHIFT;
+ const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
+ >> SCU_MPLL_POST_SHIFT;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
@@ -67,11 +67,11 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32
mpll_reg)
*/
static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
{
- const ulong num = (hpll_reg >> SCU_HPLL_NUM_SHIFT) & SCU_HPLL_NUM_MASK;
- const ulong denum = (hpll_reg >> SCU_HPLL_DENUM_SHIFT)
- & SCU_HPLL_DENUM_MASK;
- const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
- & SCU_HPLL_POST_MASK;
+ const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
+ const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
+ >> SCU_HPLL_DENUM_SHIFT;
+ const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
+ >> SCU_HPLL_
[U-Boot] [PATCH v2 13/15] aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.
The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.
So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1: None
arch/arm/dts/ast2500-u-boot.dtsi | 8 +
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 62 +-
drivers/clk/aspeed/clk_ast2500.c | 265 ++---
include/dt-bindings/clock/ast2500-scu.h| 2 +
4 files changed, 304 insertions(+), 33 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index faeeec1be4..f826646095 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -61,3 +61,11 @@
};
};
};
+
+&mac0 {
+ clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+};
+
+&mac1 {
+ clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+};
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 319d75e05c..fe877b5430 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -30,9 +30,36 @@
#define SCU_HPLL_POST_SHIFT13
#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_MACCLK_SHIFT 16
+#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
+
+#define SCU_MISC2_RGMII_HPLL (1 << 23)
+#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20
+#define SCU_MISC2_RGMII_CLKDIV_MASK(3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
+#define SCU_MISC2_RMII_MPLL(1 << 19)
+#define SCU_MISC2_RMII_CLKDIV_SHIFT16
+#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
#define SCU_MISC2_UARTCLK_SHIFT24
+#define SCU_MISC_D2PLL_OFF (1 << 4)
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+#define SCU_MISC_GCRT_USB20CLK (1 << 21)
+
+#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT0
+#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT6
+#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12
+#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18
+#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24)
+#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25)
+#define SCU_MICDS_RMII1_RCLKEN (1 << 29)
+#define SCU_MICDS_RMII2_RCLKEN (1 << 30)
+#define SCU_MICDS_RGMIIPLL (1 << 31)
/*
* SYSRESET is actually more like a Power register,
@@ -71,14 +98,45 @@
*/
#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
-#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
-#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
#define SCU_PIN_FUN_SCL1 (1 << 12)
#define SCU_PIN_FUN_SCL2 (1 << 14)
#define SCU_PIN_FUN_SDA1 (1 << 13)
#define SCU_PIN_FUN_SDA2 (1 << 15)
+#define SCU_CLKSTOP_MAC1 (1 << 20)
+#define SCU_CLKSTOP_MAC2 (1 << 21)
+
+#define SCU_D2PLL_EXT1_OFF (1 << 0)
+#define SCU_D2PLL_EXT1_BYPASS (1 << 1)
+#define SCU_D2PLL_EXT1_RESET (1 << 2)
+#define SCU_D2PLL_EXT1_MODE_SHIFT 3
+#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT)
+#define SCU_D2PLL_EXT1_PARAM_SHIFT 5
+#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
+
+#define SCU_D2PLL_NUM_SHIFT0
+#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT)
+#define SCU_D2PLL_DENUM_SHIFT 8
+#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT)
+#define SCU_D2PLL_POST_SHIFT 13
+#define SCU_D2PLL_POST_MASK(0x3f <<
[U-Boot] [PATCH v2 15/15] aspeed: Cleanup ast2500-u-boot.dtsi Device Tree
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1: None
---
arch/arm/dts/ast2500-u-boot.dtsi | 41
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index f826646095..7f80bad7d0 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -34,32 +34,33 @@
apb {
u-boot,dm-pre-reloc;
+ };
- timer: timer@1e782000 {
- u-boot,dm-pre-reloc;
- };
+ };
+};
- uart1: serial@1e783000 {
- clocks = <&scu PCLK_UART1>;
- };
+&uart1 {
+ clocks = <&scu PCLK_UART1>;
+};
- uart2: serial@1e78d000 {
- clocks = <&scu PCLK_UART2>;
- };
+&uart2 {
+ clocks = <&scu PCLK_UART2>;
+};
- uart3: serial@1e78e000 {
- clocks = <&scu PCLK_UART3>;
- };
+&uart3 {
+ clocks = <&scu PCLK_UART3>;
+};
- uart4: serial@1e78f000 {
- clocks = <&scu PCLK_UART4>;
- };
+&uart4 {
+ clocks = <&scu PCLK_UART4>;
+};
- uart5: serial@1e784000 {
- clocks = <&scu PCLK_UART5>;
- };
- };
- };
+&uart5 {
+ clocks = <&scu PCLK_UART5>;
+};
+
+&timer {
+ u-boot,dm-pre-reloc;
};
&mac0 {
--
2.13.0.rc1.294.g07d810a77f-goog
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[U-Boot] [PATCH v2 11/15] aspeed: Add I2C Driver
Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
Acked-by: Heiko Schocher
---
Changes in v2: None
Changes in v1:
- Style fixes
---
drivers/i2c/Kconfig | 9 ++
drivers/i2c/Makefile | 1 +
drivers/i2c/ast_i2c.c | 357 ++
drivers/i2c/ast_i2c.h | 132 +++
4 files changed, 499 insertions(+)
create mode 100644 drivers/i2c/ast_i2c.c
create mode 100644 drivers/i2c/ast_i2c.h
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 39f62daf5d..e661a308b0 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -100,6 +100,15 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
enable status register. This config option can be enabled in such
cases.
+config SYS_I2C_ASPEED
+ bool "Aspeed I2C Controller"
+ depends on DM_I2C && ARCH_ASPEED
+ help
+ Say yes here to select Aspeed I2C Host Controller. The driver
+ supports AST2500 and AST2400 controllers, but is very limited.
+ Only single master mode is supported and only byte-by-byte
+ synchronous reads and writes are supported, no Pool Buffers or DMA.
+
config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 7c86198863..229fd476db 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
new file mode 100644
index 00..16dfb57066
--- /dev/null
+++ b/drivers/i2c/ast_i2c.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ * Copyright 2016 IBM Corporation
+ * Copyright 2017 Google, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ast_i2c.h"
+
+#define I2C_TIMEOUT_US 10
+#define I2C_SLEEP_STEP_US 20
+
+#define HIGHSPEED_TTIMEOUT 3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Device private data
+ */
+struct ast_i2c_priv {
+ /* This device's clock */
+ struct clk clk;
+ /* Device registers */
+ struct ast_i2c_regs *regs;
+ /* I2C speed in Hz */
+ int speed;
+};
+
+/*
+ * Given desired divider ratio, return the value that needs to be set
+ * in Clock and AC Timing Control register
+ */
+static u32 get_clk_reg_val(ulong divider_ratio)
+{
+ ulong inc = 0, div;
+ ulong scl_low, scl_high, data;
+
+ for (div = 0; divider_ratio >= 16; div++) {
+ inc |= (divider_ratio & 1);
+ divider_ratio >>= 1;
+ }
+ divider_ratio += inc;
+ scl_low = (divider_ratio >> 1) - 1;
+ scl_high = divider_ratio - scl_low - 2;
+ data = I2CD_CACTC_BASE
+ | (scl_high << I2CD_TCKHIGH_SHIFT)
+ | (scl_low << I2CD_TCKLOW_SHIFT)
+ | (div << I2CD_BASE_DIV_SHIFT);
+
+ return data;
+}
+
+static void ast_i2c_clear_interrupts(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ writel(~0, &priv->regs->isr);
+}
+
+static void ast_i2c_init_bus(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ /* Reset device */
+ writel(0, &priv->regs->fcr);
+ /* Enable Master Mode. Assuming single-master */
+ writel(I2CD_MASTER_EN
+ | I2CD_M_SDA_LOCK_EN
+ | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
+ &priv->regs->fcr);
+ /* Enable Interrupts */
+ writel(I2CD_INTR_TX_ACK
+ | I2CD_INTR_TX_NAK
+ | I2CD_INTR_RX_DONE
+ | I2CD_INTR_BUS_RECOVER_DONE
+ | I2CD_INTR_NORMAL_STOP
+ | I2CD_INTR_ABNORMAL, &priv->regs->icr);
+}
+
+static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->regs = dev_get_addr_ptr(dev);
+ if (IS_ERR(priv->regs))
+ return PTR_ERR(priv->regs);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0) {
+ debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
+ ret);
+ return ret;
+
[U-Boot] [PATCH v2 06/15] aspeed: Device Tree configuration for Reset Driver
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1: None
arch/arm/dts/ast2500-evb.dts | 15 +++
arch/arm/dts/ast2500-u-boot.dtsi | 10 +++
include/dt-bindings/reset/ast2500-reset.h | 45 +++
3 files changed, 70 insertions(+)
create mode 100644 include/dt-bindings/reset/ast2500-reset.h
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index dc13952fb8..723941ac0b 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -21,3 +21,18 @@
&sdrammc {
clock-frequency = <4>;
};
+
+&wdt1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt2 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt3 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index c95a7ba835..faeeec1be4 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,5 @@
#include
+#include
#include "ast2500.dtsi"
@@ -11,12 +12,21 @@
#reset-cells = <1>;
};
+ rst: reset-controller {
+ u-boot,dm-pre-reloc;
+ compatible = "aspeed,ast2500-reset";
+ aspeed,wdt = <&wdt1>;
+ #reset-cells = <1>;
+ };
+
sdrammc: sdrammc@1e6e {
u-boot,dm-pre-reloc;
compatible = "aspeed,ast2500-sdrammc";
reg = <0x1e6e 0x174
0x1e6e0200 0x1d4 >;
+ #reset-cells = <1>;
clocks = <&scu PLL_MPLL>;
+ resets = <&rst AST_RESET_SDRAM>;
};
ahb {
diff --git a/include/dt-bindings/reset/ast2500-reset.h
b/include/dt-bindings/reset/ast2500-reset.h
new file mode 100644
index 00..eb5e1db97b
--- /dev/null
+++ b/include/dt-bindings/reset/ast2500-reset.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
+#define _ABI_MACH_ASPEED_AST2500_RESET_H_
+
+/*
+ * The values are intentionally layed out as flags in
+ * WDT reset parameter.
+ */
+
+#define AST_RESET_SOC 0
+#define AST_RESET_CHIP 1
+#define AST_RESET_CPU (1 << 1)
+#define AST_RESET_ARM (1 << 2)
+#define AST_RESET_COPROC (1 << 3)
+#define AST_RESET_SDRAM(1 << 4)
+#define AST_RESET_AHB (1 << 5)
+#define AST_RESET_I2C (1 << 6)
+#define AST_RESET_MAC1 (1 << 7)
+#define AST_RESET_MAC2 (1 << 8)
+#define AST_RESET_GCRT (1 << 9)
+#define AST_RESET_USB20(1 << 10)
+#define AST_RESET_USB11_HOST (1 << 11)
+#define AST_RESET_USB11_HID(1 << 12)
+#define AST_RESET_VIDEO(1 << 13)
+#define AST_RESET_HAC (1 << 14)
+#define AST_RESET_LPC (1 << 15)
+#define AST_RESET_SDIO (1 << 16)
+#define AST_RESET_MIC (1 << 17)
+#define AST_RESET_CRT2D(1 << 18)
+#define AST_RESET_PWM (1 << 19)
+#define AST_RESET_PECI (1 << 20)
+#define AST_RESET_JTAG (1 << 21)
+#define AST_RESET_ADC (1 << 22)
+#define AST_RESET_GPIO (1 << 23)
+#define AST_RESET_MCTP (1 << 24)
+#define AST_RESET_XDMA (1 << 25)
+#define AST_RESET_SPI (1 << 26)
+#define AST_RESET_MISC (1 << 27)
+
+#endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
--
2.13.0.rc1.294.g07d810a77f-goog
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[U-Boot] [PATCH v2 04/15] aspeed: Make SCU lock/unlock functions part of SCU API
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 14 ++
arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 +++
drivers/clk/aspeed/clk_ast2500.c | 18 ++
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fc0c01ae33..0fa3ecb9b9 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -120,6 +120,20 @@ int ast_get_clk(struct udevice **devp);
*/
void *ast_get_scu(void);
+/**
+ * ast_scu_unlock() - unlock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_unlock(struct ast2500_scu *scu);
+
+/**
+ * ast_scu_lock() - lock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_lock(struct ast2500_scu *scu);
+
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
index 079909fa64..30cfac1af0 100644
--- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
int ast_get_clk(struct udevice **devp)
@@ -28,3 +29,17 @@ void *ast_get_scu(void)
return priv->scu;
}
+
+void ast_scu_unlock(struct ast2500_scu *scu)
+{
+ writel(SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (!readl(&scu->protection_key))
+ ;
+}
+
+void ast_scu_lock(struct ast2500_scu *scu)
+{
+ writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (readl(&scu->protection_key))
+ ;
+}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 26a5e58221..504731271c 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -132,20 +132,6 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
return rate;
}
-static void ast2500_scu_unlock(struct ast2500_scu *scu)
-{
- writel(SCU_UNLOCK_VALUE, &scu->protection_key);
- while (!readl(&scu->protection_key))
- ;
-}
-
-static void ast2500_scu_lock(struct ast2500_scu *scu)
-{
- writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
- while (readl(&scu->protection_key))
- ;
-}
-
static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
{
ulong clkin = ast2500_get_clkin(scu);
@@ -197,9 +183,9 @@ static ulong ast2500_configure_ddr(struct ast2500_scu *scu,
ulong rate)
| (best_num << SCU_MPLL_NUM_SHIFT)
| (best_denum << SCU_MPLL_DENUM_SHIFT);
- ast2500_scu_unlock(scu);
+ ast_scu_unlock(scu);
writel(mpll_reg, &scu->m_pll_param);
- ast2500_scu_lock(scu);
+ ast_scu_lock(scu);
return ast2500_get_mpll_rate(clkin, mpll_reg);
}
--
2.13.0.rc1.294.g07d810a77f-goog
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[U-Boot] [PATCH v2 12/15] aspeed: Enable I2C in EVB defconfig
Enable I2C driver in ast2500 Eval Board defconfig. Also enable i2c command. Signed-off-by: Maxim Sloyko Reviewed-by: Simon Glass --- Changes in v2: None Changes in v1: None configs/evb-ast2500_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index f8ef9b779c..08b5f85a34 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -18,3 +18,6 @@ CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y CONFIG_PINCTRL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_ASPEED=y +CONFIG_CMD_I2C=y -- 2.13.0.rc1.294.g07d810a77f-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 10/15] aspeed: Add P-Bus clock in ast2500 clock driver
Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 ++-
drivers/clk/aspeed/clk_ast2500.c | 11 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 1cdd3b9198..319d75e05c 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -21,7 +21,8 @@
#define SCU_MPLL_NUM_MASK 0xff
#define SCU_MPLL_POST_SHIFT13
#define SCU_MPLL_POST_MASK 0x3f
-
+#define SCU_PCLK_DIV_SHIFT 23
+#define SCU_PCLK_DIV_MASK 7
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK0x1f
#define SCU_HPLL_NUM_SHIFT 5
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 504731271c..9e4c66ea85 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -110,6 +110,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_mpll_rate(clkin,
readl(&priv->scu->m_pll_param));
break;
+ case BCLK_PCLK:
+ {
+ ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
+ >> SCU_PCLK_DIV_SHIFT) &
+SCU_PCLK_DIV_MASK);
+ rate = ast2500_get_hpll_rate(clkin,
+readl(&priv->scu->
+ h_pll_param));
+ rate = rate / apb_div;
+ }
+ break;
case PCLK_UART1:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
--
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[U-Boot] [PATCH v2 09/15] aspeed: Enable Pinctrl Driver in AST2500 EVB
Enable Pinctrl Driver in AST2500 Eval Board's defconfig Signed-off-by: Maxim Sloyko Reviewed-by: Simon Glass --- Changes in v2: None Changes in v1: None configs/evb-ast2500_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 74808a71ee..f8ef9b779c 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -17,3 +17,4 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y +CONFIG_PINCTRL=y -- 2.13.0.rc1.294.g07d810a77f-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 07/15] aspeed: Refactor AST2500 RAM Driver and Sysreset Driver
This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.
To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.
Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.
These were the only users of the old Watchdog API, so that API is
removed.
This all is done in one change to avoid having to maintain dual API for
watchdog in between.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1:
- Rename wdt_reset call to wdt_expire_now
---
arch/arm/include/asm/arch-aspeed/wdt.h | 39 -
arch/arm/mach-aspeed/Kconfig | 8 +
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 12 +--
arch/arm/mach-aspeed/ast_wdt.c | 51
configs/evb-ast2500_defconfig| 2 ++
drivers/sysreset/sysreset_ast.c | 24 ++---
6 files changed, 24 insertions(+), 112 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index 981fa05a56..db8ecbcbe4 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -100,45 +100,6 @@ u32 ast_reset_mask_from_flags(ulong flags);
* @reset_mask: Reset Mask
*/
ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
-
-#ifndef CONFIG_WDT
-/**
- * Stop WDT
- *
- * @wdt: watchdog to stop
- *
- * When using driver model this function has different signature
- */
-void wdt_stop(struct ast_wdt *wdt);
-
-/**
- * Stop WDT
- *
- * @wdt: watchdog to start
- * @timeoutwatchdog timeout in number of clock ticks
- *
- * When using driver model this function has different signature
- */
-void wdt_start(struct ast_wdt *wdt, u32 timeout);
-#endif /* CONFIG_WDT */
-
-/**
- * Reset peripherals specified by mask
- *
- * Note, that this is only supported by ast2500 SoC
- *
- * @wdt: watchdog to use for this reset
- * @mask: reset mask.
- */
-int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask);
-
-/**
- * ast_get_wdt() - get a pointer to watchdog registers
- *
- * @wdt_number: 0-based WDT peripheral number
- * @return pointer to registers or -ve error on error
- */
-struct ast_wdt *ast_get_wdt(u8 wdt_number);
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_WDT_H */
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index c5b90bd96a..4f021baa06 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -11,19 +11,13 @@ config SYS_TEXT_BASE
config ASPEED_AST2500
bool "Support Aspeed AST2500 SoC"
+ depends on DM_RESET
select CPU_ARM1176
help
The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
It is used as Board Management Controller on many server boards,
which is enabled by support of LPC and eSPI peripherals.
-config WDT_NUM
- int "Number of Watchdog Timers"
- default 3 if ASPEED_AST2500
- help
- The number of Watchdot Timers on a SoC.
- AST2500 has three WDTsk earlier versions have two or fewer.
-
source "arch/arm/mach-aspeed/ast2500/Kconfig"
endif
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index cb6e03fa34..efcf452b17 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -328,6 +329,7 @@ static void ast2500_sdrammc_lock(struct dram_info *info)
static int ast2500_sdrammc_probe(struct udevice *dev)
{
+ struct reset_ctl reset_ctl;
struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
struct ast2500_sdrammc_regs *regs = priv->regs;
int i;
@@ -345,9 +347,15 @@ static int ast2500_sdrammc_probe(struct udevice *dev)
}
clk_set_rate(&priv->ddr_clk, priv->clock_rate);
- ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM);
+ ret = reset_get_by_index(dev, 0, &reset_ctl);
if (ret) {
- debug("%s(): SDRAM reset failed\n", __func__);
+ debug("%s(): Failed to get reset signal\n", __func__);
+ return ret;
+ }
+
+ ret = reset_assert(&reset_ctl);
+ if (ret) {
+ debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
return ret;
}
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 895fba3366..1a858b1020 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -28,54 +28,3 @@ ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32
reset_mask)
[U-Boot] [PATCH v2 08/15] aspeed: AST2500 Pinctrl Driver
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.
Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1: None
arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 19
drivers/pinctrl/Kconfig| 9 ++
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/aspeed/Makefile| 1 +
drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 +
6 files changed, 209 insertions(+)
create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h
create mode 100644 drivers/pinctrl/aspeed/Makefile
create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c
diff --git a/arch/arm/include/asm/arch-aspeed/pinctrl.h
b/arch/arm/include/asm/arch-aspeed/pinctrl.h
new file mode 100644
index 00..365dc21dbc
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/pinctrl.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * Peripherals supported by the hardware.
+ * These are used to specify pinctrl settings.
+ */
+
+enum periph_id {
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_UART4,
+ PERIPH_ID_LPC,
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_PWM5,
+ PERIPH_ID_PWM6,
+ PERIPH_ID_PWM7,
+ PERIPH_ID_PWM8,
+ PERIPH_ID_MAC1,
+ PERIPH_ID_MAC2,
+ PERIPH_ID_VIDEO,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_I2C8,
+ PERIPH_ID_I2C9,
+ PERIPH_ID_I2C10,
+ PERIPH_ID_I2C11,
+ PERIPH_ID_I2C12,
+ PERIPH_ID_I2C13,
+ PERIPH_ID_I2C14,
+ PERIPH_ID_SD1,
+ PERIPH_ID_SD2,
+};
+
+#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index e2556f920d..1cdd3b9198 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -10,6 +10,8 @@
#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
+#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
#define SCU_HWSTRAP_CLKIN_25MHZ(1 << 23)
@@ -59,6 +61,23 @@
#define SCU_SYSRESET_AHB (1 << 1)
#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
+#define SCU_PINMUX_CTRL5_I2C (1 << 16)
+
+/*
+ * The values are grouped by function, not by register.
+ * They are actually scattered across multiple loosely related registers.
+ */
+#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
+#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_SCL1 (1 << 12)
+#define SCU_PIN_FUN_SCL2 (1 << 14)
+#define SCU_PIN_FUN_SDA1 (1 << 13)
+#define SCU_PIN_FUN_SDA2 (1 << 15)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index efcb4c0003..3b7dd5f0c5 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -175,6 +175,15 @@ config PIC32_PINCTRL
by a device tree node which contains both GPIO defintion and pin
control
functions.
+config ASPEED_AST2500_PINCTRL
+ bool "Aspeed AST2500 pin control driver"
+ depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
+ default y
+ help
+Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses
+ Generic Pinctrl framework and is compatible with the Linux driver,
+ i.e. it uses the same device tree configuration.
+
endif
source "drivers/pinctrl/meson/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 512112af64..5392c3ed45 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
obj-$(CONFIG_PINCTR
[U-Boot] [PATCH v2 05/15] aspeed: Reset Driver
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:
rst: reset-controller {
compatible = "aspeed,ast2500-reset";
aspeed,wdt = <&wdt1>;
}
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1:
- Remove unnecessary check for error in dev_get_priv
- Fix comment
- Rename wdt_reset call to wdt_expire_now
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 28 +++
drivers/reset/Kconfig | 10 +++
drivers/reset/Makefile | 1 +
drivers/reset/ast2500-reset.c | 106 +
4 files changed, 145 insertions(+)
create mode 100644 drivers/reset/ast2500-reset.c
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 0fa3ecb9b9..e2556f920d 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -31,6 +31,34 @@
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+/*
+ * SYSRESET is actually more like a Power register,
+ * except that corresponding bit set to 1 means that
+ * the peripheral is off.
+ */
+#define SCU_SYSRESET_XDMA (1 << 25)
+#define SCU_SYSRESET_MCTP (1 << 24)
+#define SCU_SYSRESET_ADC (1 << 23)
+#define SCU_SYSRESET_JTAG (1 << 22)
+#define SCU_SYSRESET_MIC (1 << 18)
+#define SCU_SYSRESET_SDIO (1 << 16)
+#define SCU_SYSRESET_USB11HOST (1 << 15)
+#define SCU_SYSRESET_USBHUB(1 << 14)
+#define SCU_SYSRESET_CRT (1 << 13)
+#define SCU_SYSRESET_MAC2 (1 << 12)
+#define SCU_SYSRESET_MAC1 (1 << 11)
+#define SCU_SYSRESET_PECI (1 << 10)
+#define SCU_SYSRESET_PWM (1 << 9)
+#define SCU_SYSRESET_PCI_VGA (1 << 8)
+#define SCU_SYSRESET_2D(1 << 7)
+#define SCU_SYSRESET_VIDEO (1 << 6)
+#define SCU_SYSRESET_LPC (1 << 5)
+#define SCU_SYSRESET_HAC (1 << 4)
+#define SCU_SYSRESET_USBHID(1 << 3)
+#define SCU_SYSRESET_I2C (1 << 2)
+#define SCU_SYSRESET_AHB (1 << 1)
+#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c42b0bcf0e..eb54189d4b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -43,4 +43,14 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
+config AST2500_RESET
+ bool "Reset controller driver for AST2500 SoCs"
+ depends on DM_RESET && WDT_ASPEED
+ default y if ASPEED_AST2500
+ help
+ Support for reset controller on AST2500 SoC. This controller uses
+ watchdog to reset different peripherals and thus only supports
+ resets that are supported by watchdog. The main limitation though
+ is that some reset signals, like I2C or MISC reset multiple devices.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 5c4305cc1d..16ad7eed5b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
+obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
new file mode 100644
index 00..b2c89e1f1e
--- /dev/null
+++ b/drivers/reset/ast2500-reset.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ast2500_reset_priv {
+ /* WDT used to perform resets. */
+ struct udevice *wdt;
+ struct ast2500_scu *scu;
+};
+
+static int ast2500_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
+ &priv->wdt);
+ if (ret) {
+ debug("%s: can't find WDT for reset controller", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ast2500_reset_assert(struct reset_ctl *reset
[U-Boot] [PATCH v2 03/15] aspeed: Watchdog Timer Driver
This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1:
- Rename reset to expire_now
- Rename restart to reset
---
arch/arm/include/asm/arch-aspeed/wdt.h | 53 --
arch/arm/mach-aspeed/ast_wdt.c | 40 ---
drivers/watchdog/Kconfig | 11 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/ast_wdt.c | 125 +
5 files changed, 217 insertions(+), 13 deletions(-)
create mode 100644 drivers/watchdog/ast_wdt.c
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index b292a0e67b..981fa05a56 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -67,15 +67,60 @@ struct ast_wdt {
u32 timeout_status;
u32 clr_timeout_status;
u32 reset_width;
-#ifdef CONFIG_ASPEED_AST2500
+ /* On pre-ast2500 SoCs this register is reserved. */
u32 reset_mask;
-#else
- u32 reserved0;
-#endif
};
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mode value from it.
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mode value
+ */
+u32 ast_reset_mode_from_flags(ulong flags);
+
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mask value from it. Reset Mask is only supported on ast2500
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mask value
+ */
+u32 ast_reset_mask_from_flags(ulong flags);
+
+/**
+ * Given Reset Mask and Reset Mode values, converts them to flags,
+ * suitable for passing into wdt_start or wdt_reset uclass functions.
+ *
+ * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
+ * can both be packed into single 32 bits wide value.
+ *
+ * @reset_mode: Reset Mode
+ * @reset_mask: Reset Mask
+ */
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
+
+#ifndef CONFIG_WDT
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to stop
+ *
+ * When using driver model this function has different signature
+ */
void wdt_stop(struct ast_wdt *wdt);
+
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to start
+ * @timeoutwatchdog timeout in number of clock ticks
+ *
+ * When using driver model this function has different signature
+ */
void wdt_start(struct ast_wdt *wdt, u32 timeout);
+#endif /* CONFIG_WDT */
/**
* Reset peripherals specified by mask
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 22481ab7ea..895fba3366 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -9,6 +9,27 @@
#include
#include
+u32 ast_reset_mode_from_flags(ulong flags)
+{
+ return flags & WDT_CTRL_RESET_MASK;
+}
+
+u32 ast_reset_mask_from_flags(ulong flags)
+{
+ return flags >> 2;
+}
+
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask)
+{
+ ulong ret = reset_mode & WDT_CTRL_RESET_MASK;
+
+ if (ret == WDT_CTRL_RESET_SOC)
+ ret |= (reset_mask << 2);
+
+ return ret;
+}
+
+#ifndef CONFIG_WDT
void wdt_stop(struct ast_wdt *wdt)
{
clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
@@ -26,15 +47,7 @@ void wdt_start(struct ast_wdt *wdt, u32 timeout)
setbits_le32(&wdt->ctrl,
WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
}
-
-struct ast_wdt *ast_get_wdt(u8 wdt_number)
-{
- if (wdt_number > CONFIG_WDT_NUM - 1)
- return ERR_PTR(-EINVAL);
-
- return (struct ast_wdt *)(WDT_BASE +
- sizeof(struct ast_wdt) * wdt_number);
-}
+#endif /* CONFIG_WDT */
int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
{
@@ -57,3 +70,12 @@ int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
return -EINVAL;
#endif
}
+
+struct ast_wdt *ast_get_wdt(u8 wdt_number)
+{
+ if (wdt_number > CONFIG_WDT_NUM - 1)
+ return ERR_PTR(-EINVAL);
+
+ return (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) * wdt_number);
+}
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 7a725f1e6d..fab8dc9034 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -18,4 +18,15 @@ config WDT_SANDBOX
can be probed and supports all of the methods of WDT, but does
not
really do anything.
+config WDT_ASPEED
+ bool "Aspeed ast2400/ast2500 watchdog timer support"
+ depends on WDT
+ default y if ARCH_ASPEED
+ help
+ Select this to enable watchdog timer for Aspeed ast2500/ast2400
devices.
+ The watchdog timer is stopped when initialized. It performs
[U-Boot] [PATCH v2 02/15] dm: Simple Watchdog uclass
This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2:
- Remove "probe" function from sandbox wdt driver
- Fix include order
Changes in v1:
- Rename wdt_reset to wdt_expire_now
- Rename wdt_restart to wdt_reset
- Clarified function documentation in few cases
- Add Sandbox WDT driver and unit tests
---
arch/sandbox/dts/test.dts| 4 ++
arch/sandbox/include/asm/state.h | 9
configs/sandbox_defconfig| 2 +
drivers/watchdog/Kconfig | 21
drivers/watchdog/Makefile| 2 +
drivers/watchdog/sandbox_wdt.c | 66
drivers/watchdog/wdt-uclass.c| 72 ++
include/dm/uclass-id.h | 1 +
include/wdt.h| 107 +++
test/dm/Makefile | 1 +
test/dm/wdt.c| 40 +++
11 files changed, 325 insertions(+)
create mode 100644 drivers/watchdog/sandbox_wdt.c
create mode 100644 drivers/watchdog/wdt-uclass.c
create mode 100644 include/wdt.h
create mode 100644 test/dm/wdt.c
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index fff175d1b7..e04ecc64cc 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -418,6 +418,10 @@
};
};
};
+
+ wdt0: wdt@0 {
+ compatible = "sandbox,wdt";
+ };
};
#include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 149f28d873..987cc7b49d 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -39,6 +39,12 @@ struct sandbox_spi_info {
struct udevice *emul;
};
+struct sandbox_wdt_info {
+ unsigned long long counter;
+ uint reset_count;
+ bool running;
+};
+
/* The complete state of the test system */
struct sandbox_state {
const char *cmd;/* Command to execute */
@@ -69,6 +75,9 @@ struct sandbox_state {
/* Pointer to information for each SPI bus/cs */
struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
[CONFIG_SANDBOX_SPI_MAX_CS];
+
+ /* Information about Watchdog */
+ struct sandbox_wdt_info wdt;
};
/* Minimum space we guarantee in the state FDT when calling read/write*/
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 01f6f5d5c6..a5f63e027f 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -171,3 +171,5 @@ CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
+CONFIG_WDT=y
+CONFIG_WDT_SANDBOX=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e69de29bb2..7a725f1e6d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -0,0 +1,21 @@
+menu "Watchdog Timer Support"
+
+config WDT
+ bool "Enable driver model for watchdog timer drivers"
+ depends on DM
+ help
+ Enable driver model for watchdog timer. At the moment the API
+ is very simple and only supports four operations:
+ start, restart, stop and reset (expire immediately).
+ What exactly happens when the timer expires is up to a particular
+ device/driver.
+
+config WDT_SANDBOX
+ bool "Enable Watchdog Timer support for Sandbox"
+ depends on SANDBOX && WDT
+ help
+ Enable Watchdog Timer support in Sandbox. This is a dummy
device that
+ can be probed and supports all of the methods of WDT, but does
not
+ really do anything.
+
+endmenu
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a007ae8234..f523d34d57 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,5 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_WDT) += wdt-uclass.o
+obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
diff --git a/drivers/watchdog/sandbox_wdt.c b/drivers/watchdog/sandbox_wdt.c
new file mode 100644
index 00..02b57f3986
--- /dev/null
+++ b/drivers/watchdog/sandbox_wdt.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct sandbox_state *state = state_get_current();
+
+ state->wdt.counter = timeout;
+ state->w
[U-Boot] [PATCH v2 01/15] aspeed: Update ast2500 Device Tree
Pull in the Device Tree for ast2500 from the mainline Linux kernel.
The file is copied from
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
Signed-off-by: Maxim Sloyko
Reviewed-by: Simon Glass
---
Changes in v2: None
Changes in v1:
- Added link to the original version to commit message
---
arch/arm/dts/ast2500.dtsi | 881 +-
1 file changed, 880 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 97fac69d11..7e0ad3a41a 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -1,6 +1,6 @@
/*
* This device tree is copied from
- * https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/
+ *
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
*/
#include "skeleton.dtsi"
@@ -36,6 +36,22 @@
reg = <0x1e6c0080 0x80>;
};
+ mac0: ethernet@1e66 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e66 0x180>;
+ interrupts = <2>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
+ mac1: ethernet@1e68 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e68 0x180>;
+ interrupts = <3>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -48,6 +64,822 @@
reg = <0x1e6e2070 0x04>;
};
+ syscon: syscon@1e6e2000 {
+ compatible = "aspeed,g5-scu", "syscon",
"simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g5-pinctrl";
+ aspeed,external-nodes = <&gfx &lhc>;
+
+ pinctrl_acpi_default: acpi_default {
+ function = "ACPI";
+ groups = "ACPI";
+ };
+
+ pinctrl_adc0_default: adc0_default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
+
+ pinctrl_adc1_default: adc1_default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
+
+ pinctrl_adc10_default: adc10_default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
+
+ pinctrl_adc11_default: adc11_default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
+
+ pinctrl_adc12_default: adc12_default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
+
+ pinctrl_adc13_default: adc13_default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
+
+ pinctrl_adc14_default: adc14_default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
+
+ pinctrl_adc15_default: adc15_default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
+
+ pinctrl_adc2_default: adc2_default {
+
[U-Boot] [PATCH v2 00/15] Expand Aspeed AST2500 Support
This series expands support for Aspeed AST2500 SoC, commonly used as Board Management Controller in many servers. The main goal of this series is I2C driver, the rest are either cleanups or supporting patches. Most notable among them is addition of Watchdog uclass, so that watchdog drivers can now use Driver Model. One notable thing that is *missing* from this series is Device Tree configuration for I2C driver. The Linux Kernel I2C driver is still under review and it may affect the details of how devices need to be configured in the Device Tree. So, I decided to wait until it will show up in Linux Kernel DT and then pull it into U-Boot. I removed Network driver from this series. I will work on it separately and will make it compatible with existing Faraday devices, but that is a work better done outside of this already long series. Also, sorry for taking long time to respond, I had to take care of some more pressing, non-U-Boot-related issues. I can assure you that I'm still committed to continue to work on Aspeed in U-Boot. Changes in v2: - Remove "probe" function from sandbox wdt driver - Fix include order Changes in v1: - Added link to the original version to commit message - Rename wdt_reset to wdt_expire_now - Rename wdt_restart to wdt_reset - Clarified function documentation in few cases - Add Sandbox WDT driver and unit tests - Rename reset to expire_now - Rename restart to reset - Remove unnecessary check for error in dev_get_priv - Fix comment - Rename wdt_reset call to wdt_expire_now - Rename wdt_reset call to wdt_expire_now - Style fixes Maxim Sloyko (15): aspeed: Update ast2500 Device Tree dm: Simple Watchdog uclass aspeed: Watchdog Timer Driver aspeed: Make SCU lock/unlock functions part of SCU API aspeed: Reset Driver aspeed: Device Tree configuration for Reset Driver aspeed: Refactor AST2500 RAM Driver and Sysreset Driver aspeed: AST2500 Pinctrl Driver aspeed: Enable Pinctrl Driver in AST2500 EVB aspeed: Add P-Bus clock in ast2500 clock driver aspeed: Add I2C Driver aspeed: Enable I2C in EVB defconfig aspeed: Add support for Clocks needed by MACs aspeed: Refactor SCU to use consistent mask & shift aspeed: Cleanup ast2500-u-boot.dtsi Device Tree arch/arm/dts/ast2500-evb.dts | 15 + arch/arm/dts/ast2500-u-boot.dtsi | 59 +- arch/arm/dts/ast2500.dtsi | 881 - arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++ arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 132 +++- arch/arm/include/asm/arch-aspeed/wdt.h | 38 +- arch/arm/mach-aspeed/Kconfig | 8 +- arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 + arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 17 +- arch/arm/mach-aspeed/ast_wdt.c | 47 +- arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/state.h | 9 + configs/evb-ast2500_defconfig | 6 + configs/sandbox_defconfig | 2 + drivers/clk/aspeed/clk_ast2500.c | 321 +++-- drivers/i2c/Kconfig| 9 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 357 ++ drivers/i2c/ast_i2c.h | 132 drivers/pinctrl/Kconfig| 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/aspeed/Makefile| 1 + drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 drivers/reset/Kconfig | 10 + drivers/reset/Makefile | 1 + drivers/reset/ast2500-reset.c | 106 +++ drivers/sysreset/sysreset_ast.c| 24 +- drivers/watchdog/Kconfig | 32 + drivers/watchdog/Makefile | 3 + drivers/watchdog/ast_wdt.c | 125 drivers/watchdog/sandbox_wdt.c | 66 ++ drivers/watchdog/wdt-uclass.c | 72 ++ include/dm/uclass-id.h | 1 + include/dt-bindings/clock/ast2500-scu.h| 2 + include/dt-bindings/reset/ast2500-reset.h | 45 ++ include/wdt.h | 107 +++ test/dm/Makefile | 1 + test/dm/wdt.c | 40 ++ 38 files changed, 2711 insertions(+), 167 deletions(-) create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h create mode 100644 drivers/pinctrl/aspeed/Makefile create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c create mode 100644 drivers/reset/ast2500-reset.c create mode 100644 drivers/watchdog/ast_wdt.c create mode 100644 drivers/watchdog/sandbox_wdt.c create mode 100644 drivers/watchdog/wdt-uclass.c create mode 100644 includ
Re: [U-Boot] [PATCH v1 11/15] aspeed: Add I2C Driver
On Tue, Apr 18, 2017 at 5:12 PM, Simon Glass wrote:
> On 17 April 2017 at 13:00, Maxim Sloyko wrote:
> > Add Device Model based I2C driver for ast2500/ast2400 SoCs.
> > The driver is very limited, it only supports master mode and
> > synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.
> >
> > Signed-off-by: Maxim Sloyko
> >
> > ---
> >
> > Changes in v1:
> > - Style fixes
> >
> >
> > ---
> > drivers/i2c/Kconfig | 9 ++
> > drivers/i2c/Makefile | 1 +
> > drivers/i2c/ast_i2c.c | 357 ++
>
> > drivers/i2c/ast_i2c.h | 132 +++
> > 4 files changed, 499 insertions(+)
> > create mode 100644 drivers/i2c/ast_i2c.c
> > create mode 100644 drivers/i2c/ast_i2c.h
>
> Reviewed-by: Simon Glass
>
> nit below
>
> [..]
> > +static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
> > +{
> > + struct ast_i2c_priv *priv = dev_get_priv(dev);
> > + int ret;
> > +
> > + priv->regs = dev_get_addr_ptr(dev);
> > + if (IS_ERR(priv->regs))
> > + return PTR_ERR(priv->regs);
>
> Should be
>
> if (!priv->regs)
>
> I think
>
Looks like dev_get_addr_ptr returns FDT_ADDR_T_NONE (cast to void*) in case
of error. FDT_ADDR_T_NONE is -1, so simple !priv->regs check would be
incorrect, as far as I understand.
>
> > +
> > + ret = clk_get_by_index(dev, 0, &priv->clk);
> > + if (ret < 0) {
> > + debug("%s: Can't get clock for %s: %d\n", __func__,
> dev->name,
> > + ret);
> > + return ret;
>
> Regards,
> Simon
>
--
*M*axim *S*loyko
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Re: [U-Boot] [PATCH v1 11/15] aspeed: Add I2C Driver
On Wed, Apr 19, 2017 at 4:58 AM, Heiko Schocher wrote:
> Hello Maxim,
>
> Am 17.04.2017 um 21:00 schrieb Maxim Sloyko:
>>
>> Add Device Model based I2C driver for ast2500/ast2400 SoCs.
>> The driver is very limited, it only supports master mode and
>> synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.
>>
>> Signed-off-by: Maxim Sloyko
>>
>> ---
>>
>> Changes in v1:
>> - Style fixes
>>
>>
>> ---
>> drivers/i2c/Kconfig | 9 ++
>> drivers/i2c/Makefile | 1 +
>> drivers/i2c/ast_i2c.c | 357
>> ++
>> drivers/i2c/ast_i2c.h | 132 +++
>> 4 files changed, 499 insertions(+)
>> create mode 100644 drivers/i2c/ast_i2c.c
>> create mode 100644 drivers/i2c/ast_i2c.h
>
>
> Is this "version 2" from the patch you posted in march?
Yes, sorry, I think I forgot to add proper "In-Reply-To" header.
>
> Acked-by: Heiko Schocher
>
> bye,
> Heiko
>
>>
>> diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
>> index 39f62daf5d..e661a308b0 100644
>> --- a/drivers/i2c/Kconfig
>> +++ b/drivers/i2c/Kconfig
>> @@ -100,6 +100,15 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
>> enable status register. This config option can be enabled in
>> such
>> cases.
>>
>> +config SYS_I2C_ASPEED
>> + bool "Aspeed I2C Controller"
>> + depends on DM_I2C && ARCH_ASPEED
>> + help
>> + Say yes here to select Aspeed I2C Host Controller. The driver
>> + supports AST2500 and AST2400 controllers, but is very limited.
>> + Only single master mode is supported and only byte-by-byte
>> + synchronous reads and writes are supported, no Pool Buffers or
>> DMA.
>> +
>> config SYS_I2C_INTEL
>> bool "Intel I2C/SMBUS driver"
>> depends on DM_I2C
>> diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
>> index 7c86198863..229fd476db 100644
>> --- a/drivers/i2c/Makefile
>> +++ b/drivers/i2c/Makefile
>> @@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
>> obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
>> obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
>> obj-$(CONFIG_SYS_I2C) += i2c_core.o
>> +obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
>> obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
>> obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
>> obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
>> diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
>> new file mode 100644
>> index 00..16dfb57066
>> --- /dev/null
>> +++ b/drivers/i2c/ast_i2c.c
>> @@ -0,0 +1,357 @@
>> +/*
>> + * Copyright (C) 2012-2020 ASPEED Technology Inc.
>> + * Copyright 2016 IBM Corporation
>> + * Copyright 2017 Google, Inc.
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +#include
>> +
>> +#include "ast_i2c.h"
>> +
>> +#define I2C_TIMEOUT_US 10
>> +#define I2C_SLEEP_STEP_US 20
>> +
>> +#define HIGHSPEED_TTIMEOUT 3
>> +
>> +DECLARE_GLOBAL_DATA_PTR;
>> +
>> +/*
>> + * Device private data
>> + */
>> +struct ast_i2c_priv {
>> + /* This device's clock */
>> + struct clk clk;
>> + /* Device registers */
>> + struct ast_i2c_regs *regs;
>> + /* I2C speed in Hz */
>> + int speed;
>> +};
>> +
>> +/*
>> + * Given desired divider ratio, return the value that needs to be set
>> + * in Clock and AC Timing Control register
>> + */
>> +static u32 get_clk_reg_val(ulong divider_ratio)
>> +{
>> + ulong inc = 0, div;
>> + ulong scl_low, scl_high, data;
>> +
>> + for (div = 0; divider_ratio >= 16; div++) {
>> + inc |= (divider_ratio & 1);
>> + divider_ratio >>= 1;
>> + }
>> + divider_ratio += inc;
>> + scl_low = (divider_ratio >> 1) - 1;
>> + scl_high = divider_ratio - scl_low - 2;
>> + data = I2CD_CACTC_BASE
>> + | (scl_high << I2CD_TCKHIGH_SHIFT)
>> + | (scl_low << I2CD_TCKLOW_SHIFT)
>> + | (div << I2CD_BASE_DIV_SHIFT);
>> +
>> +
[U-Boot] [PATCH v1 10/15] aspeed: Add P-Bus clock in ast2500 clock driver
Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 ++-
drivers/clk/aspeed/clk_ast2500.c | 11 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 1cdd3b9198..319d75e05c 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -21,7 +21,8 @@
#define SCU_MPLL_NUM_MASK 0xff
#define SCU_MPLL_POST_SHIFT13
#define SCU_MPLL_POST_MASK 0x3f
-
+#define SCU_PCLK_DIV_SHIFT 23
+#define SCU_PCLK_DIV_MASK 7
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK0x1f
#define SCU_HPLL_NUM_SHIFT 5
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 504731271c..9e4c66ea85 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -110,6 +110,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_mpll_rate(clkin,
readl(&priv->scu->m_pll_param));
break;
+ case BCLK_PCLK:
+ {
+ ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
+ >> SCU_PCLK_DIV_SHIFT) &
+SCU_PCLK_DIV_MASK);
+ rate = ast2500_get_hpll_rate(clkin,
+readl(&priv->scu->
+ h_pll_param));
+ rate = rate / apb_div;
+ }
+ break;
case PCLK_UART1:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
--
2.12.2.762.g0e3151a226-goog
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[U-Boot] [PATCH v1 14/15] aspeed: Refactor SCU to use consistent mask & shift
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 12
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 5 ++--
drivers/clk/aspeed/clk_ast2500.c | 39 +-
3 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fe877b5430..590aed2f6c 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -8,8 +8,8 @@
#define SCU_UNLOCK_VALUE 0x1688a8a8
-#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_VGAMEM_MASK(3 << SCU_HWSTRAP_VGAMEM_SHIFT)
#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
@@ -18,17 +18,17 @@
#define SCU_MPLL_DENUM_SHIFT 0
#define SCU_MPLL_DENUM_MASK0x1f
#define SCU_MPLL_NUM_SHIFT 5
-#define SCU_MPLL_NUM_MASK 0xff
+#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
#define SCU_MPLL_POST_SHIFT13
-#define SCU_MPLL_POST_MASK 0x3f
+#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
#define SCU_PCLK_DIV_SHIFT 23
-#define SCU_PCLK_DIV_MASK 7
+#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK0x1f
#define SCU_HPLL_NUM_SHIFT 5
-#define SCU_HPLL_NUM_MASK 0xff
+#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
#define SCU_HPLL_POST_SHIFT13
-#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
#define SCU_MACCLK_SHIFT 16
#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index efcf452b17..6383f727f2 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -183,9 +183,8 @@ static int ast2500_sdrammc_ddr4_calibrate_vref(struct
dram_info *info)
static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
{
size_t vga_mem_size_base = 8 * 1024 * 1024;
- u32 vga_hwconf = (readl(&info->scu->hwstrap)
- >> SCU_HWSTRAP_VGAMEM_SHIFT)
- & SCU_HWSTRAP_VGAMEM_MASK;
+ u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
+ >> SCU_HWSTRAP_VGAMEM_SHIFT;
return vga_mem_size_base << vga_hwconf;
}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 7b4b5c64ac..ccf47a1da1 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -52,11 +52,11 @@ struct ast2500_div_config {
*/
static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
{
- const ulong num = (mpll_reg >> SCU_MPLL_NUM_SHIFT) & SCU_MPLL_NUM_MASK;
- const ulong denum = (mpll_reg >> SCU_MPLL_DENUM_SHIFT)
- & SCU_MPLL_DENUM_MASK;
- const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
- & SCU_MPLL_POST_MASK;
+ const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
+ const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
+ >> SCU_MPLL_DENUM_SHIFT;
+ const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
+ >> SCU_MPLL_POST_SHIFT;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
@@ -67,11 +67,11 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32
mpll_reg)
*/
static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
{
- const ulong num = (hpll_reg >> SCU_HPLL_NUM_SHIFT) & SCU_HPLL_NUM_MASK;
- const ulong denum = (hpll_reg >> SCU_HPLL_DENUM_SHIFT)
- & SCU_HPLL_DENUM_MASK;
- const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
- & SCU_HPLL_POST_MASK;
+ const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
+ const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
+ >> SCU_HPLL_DENUM_SHIFT;
+ const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
+ >> SCU_HPLL_POST_SHIFT;
return (clkin *
[U-Boot] [PATCH v1 05/15] aspeed: Reset Driver
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:
rst: reset-controller {
compatible = "aspeed,ast2500-reset";
aspeed,wdt = <&wdt1>;
}
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Remove unnecessary check for error in dev_get_priv
- Fix comment
- Rename wdt_reset call to wdt_expire_now
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 28 +++
drivers/reset/Kconfig | 10 +++
drivers/reset/Makefile | 1 +
drivers/reset/ast2500-reset.c | 106 +
4 files changed, 145 insertions(+)
create mode 100644 drivers/reset/ast2500-reset.c
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 0fa3ecb9b9..e2556f920d 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -31,6 +31,34 @@
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+/*
+ * SYSRESET is actually more like a Power register,
+ * except that corresponding bit set to 1 means that
+ * the peripheral is off.
+ */
+#define SCU_SYSRESET_XDMA (1 << 25)
+#define SCU_SYSRESET_MCTP (1 << 24)
+#define SCU_SYSRESET_ADC (1 << 23)
+#define SCU_SYSRESET_JTAG (1 << 22)
+#define SCU_SYSRESET_MIC (1 << 18)
+#define SCU_SYSRESET_SDIO (1 << 16)
+#define SCU_SYSRESET_USB11HOST (1 << 15)
+#define SCU_SYSRESET_USBHUB(1 << 14)
+#define SCU_SYSRESET_CRT (1 << 13)
+#define SCU_SYSRESET_MAC2 (1 << 12)
+#define SCU_SYSRESET_MAC1 (1 << 11)
+#define SCU_SYSRESET_PECI (1 << 10)
+#define SCU_SYSRESET_PWM (1 << 9)
+#define SCU_SYSRESET_PCI_VGA (1 << 8)
+#define SCU_SYSRESET_2D(1 << 7)
+#define SCU_SYSRESET_VIDEO (1 << 6)
+#define SCU_SYSRESET_LPC (1 << 5)
+#define SCU_SYSRESET_HAC (1 << 4)
+#define SCU_SYSRESET_USBHID(1 << 3)
+#define SCU_SYSRESET_I2C (1 << 2)
+#define SCU_SYSRESET_AHB (1 << 1)
+#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c42b0bcf0e..eb54189d4b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -43,4 +43,14 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
+config AST2500_RESET
+ bool "Reset controller driver for AST2500 SoCs"
+ depends on DM_RESET && WDT_ASPEED
+ default y if ASPEED_AST2500
+ help
+ Support for reset controller on AST2500 SoC. This controller uses
+ watchdog to reset different peripherals and thus only supports
+ resets that are supported by watchdog. The main limitation though
+ is that some reset signals, like I2C or MISC reset multiple devices.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 5c4305cc1d..16ad7eed5b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
+obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
new file mode 100644
index 00..b2c89e1f1e
--- /dev/null
+++ b/drivers/reset/ast2500-reset.c
@@ -0,0 +1,106 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ast2500_reset_priv {
+ /* WDT used to perform resets. */
+ struct udevice *wdt;
+ struct ast2500_scu *scu;
+};
+
+static int ast2500_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
+ &priv->wdt);
+ if (ret) {
+ debug("%s: can't find WDT for reset controller", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct ast2500_reset_priv *priv
[U-Boot] [PATCH v1 08/15] aspeed: AST2500 Pinctrl Driver
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.
Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 19
drivers/pinctrl/Kconfig| 9 ++
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/aspeed/Makefile| 1 +
drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 +
6 files changed, 209 insertions(+)
create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h
create mode 100644 drivers/pinctrl/aspeed/Makefile
create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c
diff --git a/arch/arm/include/asm/arch-aspeed/pinctrl.h
b/arch/arm/include/asm/arch-aspeed/pinctrl.h
new file mode 100644
index 00..365dc21dbc
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/pinctrl.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * Peripherals supported by the hardware.
+ * These are used to specify pinctrl settings.
+ */
+
+enum periph_id {
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_UART4,
+ PERIPH_ID_LPC,
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_PWM5,
+ PERIPH_ID_PWM6,
+ PERIPH_ID_PWM7,
+ PERIPH_ID_PWM8,
+ PERIPH_ID_MAC1,
+ PERIPH_ID_MAC2,
+ PERIPH_ID_VIDEO,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_I2C8,
+ PERIPH_ID_I2C9,
+ PERIPH_ID_I2C10,
+ PERIPH_ID_I2C11,
+ PERIPH_ID_I2C12,
+ PERIPH_ID_I2C13,
+ PERIPH_ID_I2C14,
+ PERIPH_ID_SD1,
+ PERIPH_ID_SD2,
+};
+
+#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index e2556f920d..1cdd3b9198 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -10,6 +10,8 @@
#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
+#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
#define SCU_HWSTRAP_CLKIN_25MHZ(1 << 23)
@@ -59,6 +61,23 @@
#define SCU_SYSRESET_AHB (1 << 1)
#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
+#define SCU_PINMUX_CTRL5_I2C (1 << 16)
+
+/*
+ * The values are grouped by function, not by register.
+ * They are actually scattered across multiple loosely related registers.
+ */
+#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
+#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_SCL1 (1 << 12)
+#define SCU_PIN_FUN_SCL2 (1 << 14)
+#define SCU_PIN_FUN_SDA1 (1 << 13)
+#define SCU_PIN_FUN_SDA2 (1 << 15)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index efcb4c0003..3b7dd5f0c5 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -175,6 +175,15 @@ config PIC32_PINCTRL
by a device tree node which contains both GPIO defintion and pin
control
functions.
+config ASPEED_AST2500_PINCTRL
+ bool "Aspeed AST2500 pin control driver"
+ depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
+ default y
+ help
+Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses
+ Generic Pinctrl framework and is compatible with the Linux driver,
+ i.e. it uses the same device tree configuration.
+
endif
source "drivers/pinctrl/meson/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 512112af64..5392c3ed45 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MES
[U-Boot] [PATCH v1 04/15] aspeed: Make SCU lock/unlock functions part of SCU API
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 14 ++
arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 +++
drivers/clk/aspeed/clk_ast2500.c | 18 ++
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fc0c01ae33..0fa3ecb9b9 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -120,6 +120,20 @@ int ast_get_clk(struct udevice **devp);
*/
void *ast_get_scu(void);
+/**
+ * ast_scu_unlock() - unlock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_unlock(struct ast2500_scu *scu);
+
+/**
+ * ast_scu_lock() - lock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_lock(struct ast2500_scu *scu);
+
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
index 079909fa64..30cfac1af0 100644
--- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
int ast_get_clk(struct udevice **devp)
@@ -28,3 +29,17 @@ void *ast_get_scu(void)
return priv->scu;
}
+
+void ast_scu_unlock(struct ast2500_scu *scu)
+{
+ writel(SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (!readl(&scu->protection_key))
+ ;
+}
+
+void ast_scu_lock(struct ast2500_scu *scu)
+{
+ writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (readl(&scu->protection_key))
+ ;
+}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 26a5e58221..504731271c 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -132,20 +132,6 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
return rate;
}
-static void ast2500_scu_unlock(struct ast2500_scu *scu)
-{
- writel(SCU_UNLOCK_VALUE, &scu->protection_key);
- while (!readl(&scu->protection_key))
- ;
-}
-
-static void ast2500_scu_lock(struct ast2500_scu *scu)
-{
- writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
- while (readl(&scu->protection_key))
- ;
-}
-
static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
{
ulong clkin = ast2500_get_clkin(scu);
@@ -197,9 +183,9 @@ static ulong ast2500_configure_ddr(struct ast2500_scu *scu,
ulong rate)
| (best_num << SCU_MPLL_NUM_SHIFT)
| (best_denum << SCU_MPLL_DENUM_SHIFT);
- ast2500_scu_unlock(scu);
+ ast_scu_unlock(scu);
writel(mpll_reg, &scu->m_pll_param);
- ast2500_scu_lock(scu);
+ ast_scu_lock(scu);
return ast2500_get_mpll_rate(clkin, mpll_reg);
}
--
2.12.2.762.g0e3151a226-goog
___
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 12/15] aspeed: Enable I2C in EVB defconfig
Enable I2C driver in ast2500 Eval Board defconfig. Also enable i2c command. Signed-off-by: Maxim Sloyko --- Changes in v1: None configs/evb-ast2500_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index f8ef9b779c..08b5f85a34 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -18,3 +18,6 @@ CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y CONFIG_PINCTRL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_ASPEED=y +CONFIG_CMD_I2C=y -- 2.12.2.762.g0e3151a226-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 01/15] aspeed: Update ast2500 Device Tree
Pull in the Device Tree for ast2500 from the mainline Linux kernel.
The file is copied from
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Added link to the original version to commit message
---
arch/arm/dts/ast2500.dtsi | 881 +-
1 file changed, 880 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 97fac69d11..7e0ad3a41a 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -1,6 +1,6 @@
/*
* This device tree is copied from
- * https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/
+ *
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
*/
#include "skeleton.dtsi"
@@ -36,6 +36,22 @@
reg = <0x1e6c0080 0x80>;
};
+ mac0: ethernet@1e66 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e66 0x180>;
+ interrupts = <2>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
+ mac1: ethernet@1e68 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e68 0x180>;
+ interrupts = <3>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -48,6 +64,822 @@
reg = <0x1e6e2070 0x04>;
};
+ syscon: syscon@1e6e2000 {
+ compatible = "aspeed,g5-scu", "syscon",
"simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g5-pinctrl";
+ aspeed,external-nodes = <&gfx &lhc>;
+
+ pinctrl_acpi_default: acpi_default {
+ function = "ACPI";
+ groups = "ACPI";
+ };
+
+ pinctrl_adc0_default: adc0_default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
+
+ pinctrl_adc1_default: adc1_default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
+
+ pinctrl_adc10_default: adc10_default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
+
+ pinctrl_adc11_default: adc11_default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
+
+ pinctrl_adc12_default: adc12_default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
+
+ pinctrl_adc13_default: adc13_default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
+
+ pinctrl_adc14_default: adc14_default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
+
+ pinctrl_adc15_default: adc15_default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
+
+ pinctrl_adc2_default: adc2_default {
+
[U-Boot] [PATCH v1 02/15] dm: Simple Watchdog uclass
This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Rename wdt_reset to wdt_expire_now
- Rename wdt_restart to wdt_reset
- Clarified function documentation in few cases
- Add Sandbox WDT driver and unit tests
---
arch/sandbox/dts/test.dts| 4 ++
arch/sandbox/include/asm/state.h | 9
configs/sandbox_defconfig| 2 +
drivers/watchdog/Kconfig | 21
drivers/watchdog/Makefile| 2 +
drivers/watchdog/sandbox_wdt.c | 76 +++
drivers/watchdog/wdt-uclass.c| 72 ++
include/dm/uclass-id.h | 1 +
include/wdt.h| 107 +++
test/dm/Makefile | 1 +
test/dm/wdt.c| 40 +++
11 files changed, 335 insertions(+)
create mode 100644 drivers/watchdog/sandbox_wdt.c
create mode 100644 drivers/watchdog/wdt-uclass.c
create mode 100644 include/wdt.h
create mode 100644 test/dm/wdt.c
diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index fff175d1b7..e04ecc64cc 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -418,6 +418,10 @@
};
};
};
+
+ wdt0: wdt@0 {
+ compatible = "sandbox,wdt";
+ };
};
#include "sandbox_pmic.dtsi"
diff --git a/arch/sandbox/include/asm/state.h b/arch/sandbox/include/asm/state.h
index 149f28d873..987cc7b49d 100644
--- a/arch/sandbox/include/asm/state.h
+++ b/arch/sandbox/include/asm/state.h
@@ -39,6 +39,12 @@ struct sandbox_spi_info {
struct udevice *emul;
};
+struct sandbox_wdt_info {
+ unsigned long long counter;
+ uint reset_count;
+ bool running;
+};
+
/* The complete state of the test system */
struct sandbox_state {
const char *cmd;/* Command to execute */
@@ -69,6 +75,9 @@ struct sandbox_state {
/* Pointer to information for each SPI bus/cs */
struct sandbox_spi_info spi[CONFIG_SANDBOX_SPI_MAX_BUS]
[CONFIG_SANDBOX_SPI_MAX_CS];
+
+ /* Information about Watchdog */
+ struct sandbox_wdt_info wdt;
};
/* Minimum space we guarantee in the state FDT when calling read/write*/
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 01f6f5d5c6..a5f63e027f 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -171,3 +171,5 @@ CONFIG_UNIT_TEST=y
CONFIG_UT_TIME=y
CONFIG_UT_DM=y
CONFIG_UT_ENV=y
+CONFIG_WDT=y
+CONFIG_WDT_SANDBOX=y
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e69de29bb2..7a725f1e6d 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -0,0 +1,21 @@
+menu "Watchdog Timer Support"
+
+config WDT
+ bool "Enable driver model for watchdog timer drivers"
+ depends on DM
+ help
+ Enable driver model for watchdog timer. At the moment the API
+ is very simple and only supports four operations:
+ start, restart, stop and reset (expire immediately).
+ What exactly happens when the timer expires is up to a particular
+ device/driver.
+
+config WDT_SANDBOX
+ bool "Enable Watchdog Timer support for Sandbox"
+ depends on SANDBOX && WDT
+ help
+ Enable Watchdog Timer support in Sandbox. This is a dummy
device that
+ can be probed and supports all of the methods of WDT, but does
not
+ really do anything.
+
+endmenu
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a007ae8234..f523d34d57 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,5 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_WDT) += wdt-uclass.o
+obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
diff --git a/drivers/watchdog/sandbox_wdt.c b/drivers/watchdog/sandbox_wdt.c
new file mode 100644
index 00..34d90bee7e
--- /dev/null
+++ b/drivers/watchdog/sandbox_wdt.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static int sandbox_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ struct sandbox_state *state = state_get_current();
+
+ state->wdt.counter = timeout;
+ state->wdt.running = true;
+
+ return 0;
+}
+
+static int sandbox_wdt_stop(struct udevice *dev)
+{
+ struct sandbox_sta
[U-Boot] [PATCH v1 03/15] aspeed: Watchdog Timer Driver
This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Rename reset to expire_now
- Rename restart to reset
---
arch/arm/include/asm/arch-aspeed/wdt.h | 53 --
arch/arm/mach-aspeed/ast_wdt.c | 40 ---
drivers/watchdog/Kconfig | 11 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/ast_wdt.c | 125 +
5 files changed, 217 insertions(+), 13 deletions(-)
create mode 100644 drivers/watchdog/ast_wdt.c
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index b292a0e67b..981fa05a56 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -67,15 +67,60 @@ struct ast_wdt {
u32 timeout_status;
u32 clr_timeout_status;
u32 reset_width;
-#ifdef CONFIG_ASPEED_AST2500
+ /* On pre-ast2500 SoCs this register is reserved. */
u32 reset_mask;
-#else
- u32 reserved0;
-#endif
};
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mode value from it.
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mode value
+ */
+u32 ast_reset_mode_from_flags(ulong flags);
+
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mask value from it. Reset Mask is only supported on ast2500
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mask value
+ */
+u32 ast_reset_mask_from_flags(ulong flags);
+
+/**
+ * Given Reset Mask and Reset Mode values, converts them to flags,
+ * suitable for passing into wdt_start or wdt_reset uclass functions.
+ *
+ * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
+ * can both be packed into single 32 bits wide value.
+ *
+ * @reset_mode: Reset Mode
+ * @reset_mask: Reset Mask
+ */
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
+
+#ifndef CONFIG_WDT
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to stop
+ *
+ * When using driver model this function has different signature
+ */
void wdt_stop(struct ast_wdt *wdt);
+
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to start
+ * @timeoutwatchdog timeout in number of clock ticks
+ *
+ * When using driver model this function has different signature
+ */
void wdt_start(struct ast_wdt *wdt, u32 timeout);
+#endif /* CONFIG_WDT */
/**
* Reset peripherals specified by mask
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 22481ab7ea..895fba3366 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -9,6 +9,27 @@
#include
#include
+u32 ast_reset_mode_from_flags(ulong flags)
+{
+ return flags & WDT_CTRL_RESET_MASK;
+}
+
+u32 ast_reset_mask_from_flags(ulong flags)
+{
+ return flags >> 2;
+}
+
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask)
+{
+ ulong ret = reset_mode & WDT_CTRL_RESET_MASK;
+
+ if (ret == WDT_CTRL_RESET_SOC)
+ ret |= (reset_mask << 2);
+
+ return ret;
+}
+
+#ifndef CONFIG_WDT
void wdt_stop(struct ast_wdt *wdt)
{
clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
@@ -26,15 +47,7 @@ void wdt_start(struct ast_wdt *wdt, u32 timeout)
setbits_le32(&wdt->ctrl,
WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
}
-
-struct ast_wdt *ast_get_wdt(u8 wdt_number)
-{
- if (wdt_number > CONFIG_WDT_NUM - 1)
- return ERR_PTR(-EINVAL);
-
- return (struct ast_wdt *)(WDT_BASE +
- sizeof(struct ast_wdt) * wdt_number);
-}
+#endif /* CONFIG_WDT */
int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
{
@@ -57,3 +70,12 @@ int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
return -EINVAL;
#endif
}
+
+struct ast_wdt *ast_get_wdt(u8 wdt_number)
+{
+ if (wdt_number > CONFIG_WDT_NUM - 1)
+ return ERR_PTR(-EINVAL);
+
+ return (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) * wdt_number);
+}
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 7a725f1e6d..fab8dc9034 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -18,4 +18,15 @@ config WDT_SANDBOX
can be probed and supports all of the methods of WDT, but does
not
really do anything.
+config WDT_ASPEED
+ bool "Aspeed ast2400/ast2500 watchdog timer support"
+ depends on WDT
+ default y if ARCH_ASPEED
+ help
+ Select this to enable watchdog timer for Aspeed ast2500/ast2400
devices.
+ The watchdog timer is stopped when initialized. It performs reset,
either
+ full SoC reset o
[U-Boot] [PATCH v1 15/15] aspeed: Cleanup ast2500-u-boot.dtsi Device Tree
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
---
arch/arm/dts/ast2500-u-boot.dtsi | 41
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index f826646095..7f80bad7d0 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -34,32 +34,33 @@
apb {
u-boot,dm-pre-reloc;
+ };
- timer: timer@1e782000 {
- u-boot,dm-pre-reloc;
- };
+ };
+};
- uart1: serial@1e783000 {
- clocks = <&scu PCLK_UART1>;
- };
+&uart1 {
+ clocks = <&scu PCLK_UART1>;
+};
- uart2: serial@1e78d000 {
- clocks = <&scu PCLK_UART2>;
- };
+&uart2 {
+ clocks = <&scu PCLK_UART2>;
+};
- uart3: serial@1e78e000 {
- clocks = <&scu PCLK_UART3>;
- };
+&uart3 {
+ clocks = <&scu PCLK_UART3>;
+};
- uart4: serial@1e78f000 {
- clocks = <&scu PCLK_UART4>;
- };
+&uart4 {
+ clocks = <&scu PCLK_UART4>;
+};
- uart5: serial@1e784000 {
- clocks = <&scu PCLK_UART5>;
- };
- };
- };
+&uart5 {
+ clocks = <&scu PCLK_UART5>;
+};
+
+&timer {
+ u-boot,dm-pre-reloc;
};
&mac0 {
--
2.12.2.762.g0e3151a226-goog
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[U-Boot] [PATCH v1 13/15] aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.
The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.
So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/dts/ast2500-u-boot.dtsi | 8 +
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 62 +-
drivers/clk/aspeed/clk_ast2500.c | 265 ++---
include/dt-bindings/clock/ast2500-scu.h| 2 +
4 files changed, 304 insertions(+), 33 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index faeeec1be4..f826646095 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -61,3 +61,11 @@
};
};
};
+
+&mac0 {
+ clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+};
+
+&mac1 {
+ clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+};
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 319d75e05c..fe877b5430 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -30,9 +30,36 @@
#define SCU_HPLL_POST_SHIFT13
#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_MACCLK_SHIFT 16
+#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
+
+#define SCU_MISC2_RGMII_HPLL (1 << 23)
+#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20
+#define SCU_MISC2_RGMII_CLKDIV_MASK(3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
+#define SCU_MISC2_RMII_MPLL(1 << 19)
+#define SCU_MISC2_RMII_CLKDIV_SHIFT16
+#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
#define SCU_MISC2_UARTCLK_SHIFT24
+#define SCU_MISC_D2PLL_OFF (1 << 4)
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+#define SCU_MISC_GCRT_USB20CLK (1 << 21)
+
+#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT0
+#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT6
+#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12
+#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18
+#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24)
+#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25)
+#define SCU_MICDS_RMII1_RCLKEN (1 << 29)
+#define SCU_MICDS_RMII2_RCLKEN (1 << 30)
+#define SCU_MICDS_RGMIIPLL (1 << 31)
/*
* SYSRESET is actually more like a Power register,
@@ -71,14 +98,45 @@
*/
#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
-#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
-#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
#define SCU_PIN_FUN_SCL1 (1 << 12)
#define SCU_PIN_FUN_SCL2 (1 << 14)
#define SCU_PIN_FUN_SDA1 (1 << 13)
#define SCU_PIN_FUN_SDA2 (1 << 15)
+#define SCU_CLKSTOP_MAC1 (1 << 20)
+#define SCU_CLKSTOP_MAC2 (1 << 21)
+
+#define SCU_D2PLL_EXT1_OFF (1 << 0)
+#define SCU_D2PLL_EXT1_BYPASS (1 << 1)
+#define SCU_D2PLL_EXT1_RESET (1 << 2)
+#define SCU_D2PLL_EXT1_MODE_SHIFT 3
+#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT)
+#define SCU_D2PLL_EXT1_PARAM_SHIFT 5
+#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
+
+#define SCU_D2PLL_NUM_SHIFT0
+#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT)
+#define SCU_D2PLL_DENUM_SHIFT 8
+#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT)
+#define SCU_D2PLL_POST_SHIFT 13
+#define SCU_D2PLL_POST_MASK(0x3f << SCU_D2PLL_POST_SHIFT)
+#define SCU_D2PLL
[U-Boot] [PATCH v1 11/15] aspeed: Add I2C Driver
Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Style fixes
---
drivers/i2c/Kconfig | 9 ++
drivers/i2c/Makefile | 1 +
drivers/i2c/ast_i2c.c | 357 ++
drivers/i2c/ast_i2c.h | 132 +++
4 files changed, 499 insertions(+)
create mode 100644 drivers/i2c/ast_i2c.c
create mode 100644 drivers/i2c/ast_i2c.h
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 39f62daf5d..e661a308b0 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -100,6 +100,15 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
enable status register. This config option can be enabled in such
cases.
+config SYS_I2C_ASPEED
+ bool "Aspeed I2C Controller"
+ depends on DM_I2C && ARCH_ASPEED
+ help
+ Say yes here to select Aspeed I2C Host Controller. The driver
+ supports AST2500 and AST2400 controllers, but is very limited.
+ Only single master mode is supported and only byte-by-byte
+ synchronous reads and writes are supported, no Pool Buffers or DMA.
+
config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 7c86198863..229fd476db 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
new file mode 100644
index 00..16dfb57066
--- /dev/null
+++ b/drivers/i2c/ast_i2c.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ * Copyright 2016 IBM Corporation
+ * Copyright 2017 Google, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ast_i2c.h"
+
+#define I2C_TIMEOUT_US 10
+#define I2C_SLEEP_STEP_US 20
+
+#define HIGHSPEED_TTIMEOUT 3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Device private data
+ */
+struct ast_i2c_priv {
+ /* This device's clock */
+ struct clk clk;
+ /* Device registers */
+ struct ast_i2c_regs *regs;
+ /* I2C speed in Hz */
+ int speed;
+};
+
+/*
+ * Given desired divider ratio, return the value that needs to be set
+ * in Clock and AC Timing Control register
+ */
+static u32 get_clk_reg_val(ulong divider_ratio)
+{
+ ulong inc = 0, div;
+ ulong scl_low, scl_high, data;
+
+ for (div = 0; divider_ratio >= 16; div++) {
+ inc |= (divider_ratio & 1);
+ divider_ratio >>= 1;
+ }
+ divider_ratio += inc;
+ scl_low = (divider_ratio >> 1) - 1;
+ scl_high = divider_ratio - scl_low - 2;
+ data = I2CD_CACTC_BASE
+ | (scl_high << I2CD_TCKHIGH_SHIFT)
+ | (scl_low << I2CD_TCKLOW_SHIFT)
+ | (div << I2CD_BASE_DIV_SHIFT);
+
+ return data;
+}
+
+static void ast_i2c_clear_interrupts(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ writel(~0, &priv->regs->isr);
+}
+
+static void ast_i2c_init_bus(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ /* Reset device */
+ writel(0, &priv->regs->fcr);
+ /* Enable Master Mode. Assuming single-master */
+ writel(I2CD_MASTER_EN
+ | I2CD_M_SDA_LOCK_EN
+ | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
+ &priv->regs->fcr);
+ /* Enable Interrupts */
+ writel(I2CD_INTR_TX_ACK
+ | I2CD_INTR_TX_NAK
+ | I2CD_INTR_RX_DONE
+ | I2CD_INTR_BUS_RECOVER_DONE
+ | I2CD_INTR_NORMAL_STOP
+ | I2CD_INTR_ABNORMAL, &priv->regs->icr);
+}
+
+static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->regs = dev_get_addr_ptr(dev);
+ if (IS_ERR(priv->regs))
+ return PTR_ERR(priv->regs);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0) {
+ debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ast_i2c_probe(struct udevice *dev)
+{
+
[U-Boot] [PATCH v1 06/15] aspeed: Device Tree configuration for Reset Driver
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko
---
Changes in v1: None
arch/arm/dts/ast2500-evb.dts | 15 +++
arch/arm/dts/ast2500-u-boot.dtsi | 10 +++
include/dt-bindings/reset/ast2500-reset.h | 45 +++
3 files changed, 70 insertions(+)
create mode 100644 include/dt-bindings/reset/ast2500-reset.h
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index dc13952fb8..723941ac0b 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -21,3 +21,18 @@
&sdrammc {
clock-frequency = <4>;
};
+
+&wdt1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt2 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt3 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index c95a7ba835..faeeec1be4 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,5 @@
#include
+#include
#include "ast2500.dtsi"
@@ -11,12 +12,21 @@
#reset-cells = <1>;
};
+ rst: reset-controller {
+ u-boot,dm-pre-reloc;
+ compatible = "aspeed,ast2500-reset";
+ aspeed,wdt = <&wdt1>;
+ #reset-cells = <1>;
+ };
+
sdrammc: sdrammc@1e6e {
u-boot,dm-pre-reloc;
compatible = "aspeed,ast2500-sdrammc";
reg = <0x1e6e 0x174
0x1e6e0200 0x1d4 >;
+ #reset-cells = <1>;
clocks = <&scu PLL_MPLL>;
+ resets = <&rst AST_RESET_SDRAM>;
};
ahb {
diff --git a/include/dt-bindings/reset/ast2500-reset.h
b/include/dt-bindings/reset/ast2500-reset.h
new file mode 100644
index 00..eb5e1db97b
--- /dev/null
+++ b/include/dt-bindings/reset/ast2500-reset.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
+#define _ABI_MACH_ASPEED_AST2500_RESET_H_
+
+/*
+ * The values are intentionally layed out as flags in
+ * WDT reset parameter.
+ */
+
+#define AST_RESET_SOC 0
+#define AST_RESET_CHIP 1
+#define AST_RESET_CPU (1 << 1)
+#define AST_RESET_ARM (1 << 2)
+#define AST_RESET_COPROC (1 << 3)
+#define AST_RESET_SDRAM(1 << 4)
+#define AST_RESET_AHB (1 << 5)
+#define AST_RESET_I2C (1 << 6)
+#define AST_RESET_MAC1 (1 << 7)
+#define AST_RESET_MAC2 (1 << 8)
+#define AST_RESET_GCRT (1 << 9)
+#define AST_RESET_USB20(1 << 10)
+#define AST_RESET_USB11_HOST (1 << 11)
+#define AST_RESET_USB11_HID(1 << 12)
+#define AST_RESET_VIDEO(1 << 13)
+#define AST_RESET_HAC (1 << 14)
+#define AST_RESET_LPC (1 << 15)
+#define AST_RESET_SDIO (1 << 16)
+#define AST_RESET_MIC (1 << 17)
+#define AST_RESET_CRT2D(1 << 18)
+#define AST_RESET_PWM (1 << 19)
+#define AST_RESET_PECI (1 << 20)
+#define AST_RESET_JTAG (1 << 21)
+#define AST_RESET_ADC (1 << 22)
+#define AST_RESET_GPIO (1 << 23)
+#define AST_RESET_MCTP (1 << 24)
+#define AST_RESET_XDMA (1 << 25)
+#define AST_RESET_SPI (1 << 26)
+#define AST_RESET_MISC (1 << 27)
+
+#endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
--
2.12.2.762.g0e3151a226-goog
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[U-Boot] [PATCH v1 07/15] aspeed: Refactor AST2500 RAM Driver and Sysreset Driver
This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.
To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.
Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.
These were the only users of the old Watchdog API, so that API is
removed.
This all is done in one change to avoid having to maintain dual API for
watchdog in between.
Signed-off-by: Maxim Sloyko
---
Changes in v1:
- Rename wdt_reset call to wdt_expire_now
---
arch/arm/include/asm/arch-aspeed/wdt.h | 39 -
arch/arm/mach-aspeed/Kconfig | 8 +
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 12 +--
arch/arm/mach-aspeed/ast_wdt.c | 51
configs/evb-ast2500_defconfig| 2 ++
drivers/sysreset/sysreset_ast.c | 24 ++---
6 files changed, 24 insertions(+), 112 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index 981fa05a56..db8ecbcbe4 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -100,45 +100,6 @@ u32 ast_reset_mask_from_flags(ulong flags);
* @reset_mask: Reset Mask
*/
ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
-
-#ifndef CONFIG_WDT
-/**
- * Stop WDT
- *
- * @wdt: watchdog to stop
- *
- * When using driver model this function has different signature
- */
-void wdt_stop(struct ast_wdt *wdt);
-
-/**
- * Stop WDT
- *
- * @wdt: watchdog to start
- * @timeoutwatchdog timeout in number of clock ticks
- *
- * When using driver model this function has different signature
- */
-void wdt_start(struct ast_wdt *wdt, u32 timeout);
-#endif /* CONFIG_WDT */
-
-/**
- * Reset peripherals specified by mask
- *
- * Note, that this is only supported by ast2500 SoC
- *
- * @wdt: watchdog to use for this reset
- * @mask: reset mask.
- */
-int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask);
-
-/**
- * ast_get_wdt() - get a pointer to watchdog registers
- *
- * @wdt_number: 0-based WDT peripheral number
- * @return pointer to registers or -ve error on error
- */
-struct ast_wdt *ast_get_wdt(u8 wdt_number);
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_WDT_H */
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index c5b90bd96a..4f021baa06 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -11,19 +11,13 @@ config SYS_TEXT_BASE
config ASPEED_AST2500
bool "Support Aspeed AST2500 SoC"
+ depends on DM_RESET
select CPU_ARM1176
help
The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
It is used as Board Management Controller on many server boards,
which is enabled by support of LPC and eSPI peripherals.
-config WDT_NUM
- int "Number of Watchdog Timers"
- default 3 if ASPEED_AST2500
- help
- The number of Watchdot Timers on a SoC.
- AST2500 has three WDTsk earlier versions have two or fewer.
-
source "arch/arm/mach-aspeed/ast2500/Kconfig"
endif
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index cb6e03fa34..efcf452b17 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -328,6 +329,7 @@ static void ast2500_sdrammc_lock(struct dram_info *info)
static int ast2500_sdrammc_probe(struct udevice *dev)
{
+ struct reset_ctl reset_ctl;
struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
struct ast2500_sdrammc_regs *regs = priv->regs;
int i;
@@ -345,9 +347,15 @@ static int ast2500_sdrammc_probe(struct udevice *dev)
}
clk_set_rate(&priv->ddr_clk, priv->clock_rate);
- ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM);
+ ret = reset_get_by_index(dev, 0, &reset_ctl);
if (ret) {
- debug("%s(): SDRAM reset failed\n", __func__);
+ debug("%s(): Failed to get reset signal\n", __func__);
+ return ret;
+ }
+
+ ret = reset_assert(&reset_ctl);
+ if (ret) {
+ debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
return ret;
}
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 895fba3366..1a858b1020 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -28,54 +28,3 @@ ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32
reset_mask)
return ret;
}
-
-#ifndef CONFIG_WDT
-v
[U-Boot] [PATCH v1 09/15] aspeed: Enable Pinctrl Driver in AST2500 EVB
Enable Pinctrl Driver in AST2500 Eval Board's defconfig Signed-off-by: Maxim Sloyko --- Changes in v1: None configs/evb-ast2500_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 74808a71ee..f8ef9b779c 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -17,3 +17,4 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y +CONFIG_PINCTRL=y -- 2.12.2.762.g0e3151a226-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v1 00/15] Expand Aspeed AST2500 Support
This series expands support for Aspeed AST2500 SoC, commonly used as Board Management Controller in many servers. The main goal of this series is I2C driver, the rest are either cleanups or supporting patches. Most notable among them is addition of Watchdog uclass, so that watchdog drivers can now use Driver Model. One notable thing that is *missing* from this series is Device Tree configuration for I2C driver. The Linux Kernel I2C driver is still under review and it may affect the details of how devices need to be configured in the Device Tree. So, I decided to wait until it will show up in Linux Kernel DT and then pull it into U-Boot. I removed Network driver from this series. I will work on it separately and will make it compatible with existing Faraday devices, but that is a work better done outside of this already long series. Changes in v1: - Added link to the original version to commit message - Rename wdt_reset to wdt_expire_now - Rename wdt_restart to wdt_reset - Clarified function documentation in few cases - Add Sandbox WDT driver and unit tests - Rename reset to expire_now - Rename restart to reset - Remove unnecessary check for error in dev_get_priv - Fix comment - Rename wdt_reset call to wdt_expire_now - Rename wdt_reset call to wdt_expire_now - Style fixes Maxim Sloyko (15): aspeed: Update ast2500 Device Tree dm: Simple Watchdog uclass aspeed: Watchdog Timer Driver aspeed: Make SCU lock/unlock functions part of SCU API aspeed: Reset Driver aspeed: Device Tree configuration for Reset Driver aspeed: Refactor AST2500 RAM Driver and Sysreset Driver aspeed: AST2500 Pinctrl Driver aspeed: Enable Pinctrl Driver in AST2500 EVB aspeed: Add P-Bus clock in ast2500 clock driver aspeed: Add I2C Driver aspeed: Enable I2C in EVB defconfig aspeed: Add support for Clocks needed by MACs aspeed: Refactor SCU to use consistent mask & shift aspeed: Cleanup ast2500-u-boot.dtsi Device Tree arch/arm/dts/ast2500-evb.dts | 15 + arch/arm/dts/ast2500-u-boot.dtsi | 59 +- arch/arm/dts/ast2500.dtsi | 881 - arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++ arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 132 +++- arch/arm/include/asm/arch-aspeed/wdt.h | 38 +- arch/arm/mach-aspeed/Kconfig | 8 +- arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 + arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 17 +- arch/arm/mach-aspeed/ast_wdt.c | 47 +- arch/sandbox/dts/test.dts | 4 + arch/sandbox/include/asm/state.h | 9 + configs/evb-ast2500_defconfig | 6 + configs/sandbox_defconfig | 2 + drivers/clk/aspeed/clk_ast2500.c | 321 +++-- drivers/i2c/Kconfig| 9 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 357 ++ drivers/i2c/ast_i2c.h | 132 drivers/pinctrl/Kconfig| 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/aspeed/Makefile| 1 + drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 drivers/reset/Kconfig | 10 + drivers/reset/Makefile | 1 + drivers/reset/ast2500-reset.c | 106 +++ drivers/sysreset/sysreset_ast.c| 24 +- drivers/watchdog/Kconfig | 32 + drivers/watchdog/Makefile | 3 + drivers/watchdog/ast_wdt.c | 125 drivers/watchdog/sandbox_wdt.c | 76 +++ drivers/watchdog/wdt-uclass.c | 72 ++ include/dm/uclass-id.h | 1 + include/dt-bindings/clock/ast2500-scu.h| 2 + include/dt-bindings/reset/ast2500-reset.h | 45 ++ include/wdt.h | 107 +++ test/dm/Makefile | 1 + test/dm/wdt.c | 40 ++ 38 files changed, 2721 insertions(+), 167 deletions(-) create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h create mode 100644 drivers/pinctrl/aspeed/Makefile create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c create mode 100644 drivers/reset/ast2500-reset.c create mode 100644 drivers/watchdog/ast_wdt.c create mode 100644 drivers/watchdog/sandbox_wdt.c create mode 100644 drivers/watchdog/wdt-uclass.c create mode 100644 include/dt-bindings/reset/ast2500-reset.h create mode 100644 include/wdt.h create mode 100644 test/dm/wdt.c -- 2.12.2.762.g0e3151a226-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 05/17] aspeed: Reset Driver
On Tue, Mar 21, 2017 at 4:22 PM, Simon Glass wrote:
>
> Hi Maxim,
>
> On 16 March 2017 at 15:36, Maxim Sloyko wrote:
> > Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
> > perform resets and thus depends on it. The actual Watchdog device used
> > needs to be configured in Device Tree using "aspeed,wdt" property, which
> > must be WDT phandle, for example:
> >
> > rst: reset-controller {
> > compatible = "aspeed,ast2500-reset";
> > aspeed,wdt = <&wdt1>;
> > }
> >
> > Signed-off-by: Maxim Sloyko
> > ---
> >
> > arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 28 +++
> > drivers/reset/Kconfig | 10 +++
> > drivers/reset/Makefile | 1 +
> > drivers/reset/ast2500-reset.c | 109
> > +
> > 4 files changed, 148 insertions(+)
> > create mode 100644 drivers/reset/ast2500-reset.c
> >
>
> Reviewed-by: Simon Glass
>
> Nits below.
>
> > diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > index 0fa3ecb9b9..e2556f920d 100644
> > --- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > @@ -31,6 +31,34 @@
> >
> > #define SCU_MISC_UARTCLK_DIV13 (1 << 12)
> >
> > +/*
> > + * SYSRESET is actually more like a Power register,
> > + * except that corresponding bit set to 1 means that
> > + * the peripheral is off.
> > + */
> > +#define SCU_SYSRESET_XDMA (1 << 25)
> > +#define SCU_SYSRESET_MCTP (1 << 24)
> > +#define SCU_SYSRESET_ADC (1 << 23)
> > +#define SCU_SYSRESET_JTAG (1 << 22)
> > +#define SCU_SYSRESET_MIC (1 << 18)
> > +#define SCU_SYSRESET_SDIO (1 << 16)
> > +#define SCU_SYSRESET_USB11HOST (1 << 15)
> > +#define SCU_SYSRESET_USBHUB(1 << 14)
> > +#define SCU_SYSRESET_CRT (1 << 13)
> > +#define SCU_SYSRESET_MAC2 (1 << 12)
> > +#define SCU_SYSRESET_MAC1 (1 << 11)
> > +#define SCU_SYSRESET_PECI (1 << 10)
> > +#define SCU_SYSRESET_PWM (1 << 9)
> > +#define SCU_SYSRESET_PCI_VGA (1 << 8)
> > +#define SCU_SYSRESET_2D(1 << 7)
> > +#define SCU_SYSRESET_VIDEO (1 << 6)
> > +#define SCU_SYSRESET_LPC (1 << 5)
> > +#define SCU_SYSRESET_HAC (1 << 4)
> > +#define SCU_SYSRESET_USBHID(1 << 3)
> > +#define SCU_SYSRESET_I2C (1 << 2)
> > +#define SCU_SYSRESET_AHB (1 << 1)
> > +#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
> > +
> > #ifndef __ASSEMBLY__
> >
> > struct ast2500_clk_priv {
> > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> > index c42b0bcf0e..eb54189d4b 100644
> > --- a/drivers/reset/Kconfig
> > +++ b/drivers/reset/Kconfig
> > @@ -43,4 +43,14 @@ config RESET_UNIPHIER
> > Say Y if you want to control reset signals provided by System
> > Control
> > block, Media I/O block, Peripheral Block.
> >
> > +config AST2500_RESET
> > + bool "Reset controller driver for AST2500 SoCs"
> > + depends on DM_RESET && WDT_ASPEED
> > + default y if ASPEED_AST2500
> > + help
> > + Support for reset controller on AST2500 SoC. This controller uses
> > + watchdog to reset different peripherals and thus only supports
> > + resets that are supported by watchdog. The main limitation though
> > + is that some reset signals, like I2C or MISC reset multiple
> > devices.
> > +
> > endmenu
> > diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
> > index 5c4305cc1d..16ad7eed5b 100644
> > --- a/drivers/reset/Makefile
> > +++ b/drivers/reset/Makefile
> > @@ -8,3 +8,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
> > obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
> > obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
> > obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
> > +obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
> > diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
> > new file mode 100644
> > index 00.
Re: [U-Boot] [PATCH 16/17] aspeed: Add AST2500/AST2400 compatible NIC Driver
On Wed, Mar 22, 2017 at 6:06 AM, Simon Glass wrote: > Hi Maxim, > > On 21 March 2017 at 17:44, Maxim Sloyko wrote: > > Hi Joe, > > > > Please see responses inline, simply ACK'ed comments will be addressed > > in the next version. > > > > On Tue, Mar 21, 2017 at 12:32 PM, Joe Hershberger > > wrote: > >> On Thu, Mar 16, 2017 at 4:36 PM, Maxim Sloyko > wrote: > >>> The device that Aspeed uses is basically Faraday FTGMAC100, but with > >>> some differences here and there. Since I don't have access to a > properly > >>> implemented FTGMAC100 though, I can't really test it and so I don't > >>> feel comfortable claiming compatibility, even though I reused a lot of > >>> FTGMAC100 driver code. > >> > >> I think it would be better to attempt to integrate this driver with > >> the FTGMAC driver and ask others on the list who have that HW to test > >> your changes to ensure no regressions. I prefer we have fewer drivers > >> to maintain. > > > > One concern: this driver also performs its clock configuration, which > > I believe is very specific to the SoC, so to have that compatibility > > clock configuration needs to be externalized somehow. I don't know > > what is the best way to do it. > > Generally the clock is defined by a DT property in the node, so this > should work out OK. > Well, this device on this SoC needs two different clocks configured, one for all devices and one device specific. The device speed is also hardware strapped, so it reads the unrelated register to figure out which rate to enable. Not to mention, it's still unclear how it's going to be done in Linux, so somewhere else in this review Tom actually suggested to go non-DT way with this. Anyway, I'm going to drop this driver from this series and work this out separately, just to keep things moving, because it looks like it raises the largest number of concerns. > > Regards, > Simon > -- *M*axim *S*loyko ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 16/17] aspeed: Add AST2500/AST2400 compatible NIC Driver
Hi Joe,
Please see responses inline, simply ACK'ed comments will be addressed
in the next version.
On Tue, Mar 21, 2017 at 12:32 PM, Joe Hershberger
wrote:
> On Thu, Mar 16, 2017 at 4:36 PM, Maxim Sloyko wrote:
>> The device that Aspeed uses is basically Faraday FTGMAC100, but with
>> some differences here and there. Since I don't have access to a properly
>> implemented FTGMAC100 though, I can't really test it and so I don't
>> feel comfortable claiming compatibility, even though I reused a lot of
>> FTGMAC100 driver code.
>
> I think it would be better to attempt to integrate this driver with
> the FTGMAC driver and ask others on the list who have that HW to test
> your changes to ensure no regressions. I prefer we have fewer drivers
> to maintain.
One concern: this driver also performs its clock configuration, which
I believe is very specific to the SoC, so to have that compatibility
clock configuration needs to be externalized somehow. I don't know
what is the best way to do it.
>
> I'll review what you've got here, and presumably the comments apply to
> either your changes or the FTGMAC driver.
>
>> Signed-off-by: Maxim Sloyko
>> ---
>>
>> drivers/net/Kconfig | 8 +
>> drivers/net/Makefile | 1 +
>> drivers/net/ast_nic.c | 584
>> ++
>> drivers/net/ast_nic.h | 198 +
>> 4 files changed, 791 insertions(+)
>> create mode 100644 drivers/net/ast_nic.c
>> create mode 100644 drivers/net/ast_nic.h
>>
>> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
>> index 70e36611ea..6de8b35d9f 100644
>> --- a/drivers/net/Kconfig
>> +++ b/drivers/net/Kconfig
>> @@ -208,4 +208,12 @@ config GMAC_ROCKCHIP
>> This driver provides Rockchip SoCs network support based on the
>> Synopsys Designware driver.
>>
>> +config AST_NIC
>> + bool "Support Aspeed ast2500/ast2400 NIC"
>> + depends on DM_ETH
>> + help
>> + This driver provides support for ast2500/ast2400 network devices.
>> + It uses Driver Model and so can support multiple devices on the
>> same SoC.
>> + The device itself is basically a variation of Faraday FTGMAC100.
>> +
>> endif # NETDEVICES
>> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
>> index 2493a48b88..792bebb9cc 100644
>> --- a/drivers/net/Makefile
>> +++ b/drivers/net/Makefile
>> @@ -78,3 +78,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
>> obj-$(CONFIG_VSC9953) += vsc9953.o
>> obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
>> obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
>> +obj-$(CONFIG_AST_NIC) += ast_nic.o
>> diff --git a/drivers/net/ast_nic.c b/drivers/net/ast_nic.c
>> new file mode 100644
>> index 00..881d20151c
>> --- /dev/null
>> +++ b/drivers/net/ast_nic.c
>> @@ -0,0 +1,584 @@
>> +/*
>> + * (C) Copyright 2009 Faraday Technology
>> + * Po-Yu Chuang
>> + *
>> + * (C) Copyright 2010 Andes Technology
>> + * Macpaul Lin
>> + *
>> + * Copyright 2017 Google Inc
>> + *
>> + * SPDX-License-Identifier:GPL-2.0+
>> + */
>> +
>> +/*
>> + * This device is basically Faraday FTGMAC100, with some differences,
>> + * which do not seem to be very big, but are in very random places, like
>> + * some registers removed and completely different ones put in their place.
>> + */
>> +
>> +#include
>> +#include
>> +#include
>> +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
>> +#include
>> +#endif
>> +#include
>> +#include
>> +#include
>> +#include "ast_nic.h"
>> +
>> +#define ETH_ZLEN 60
>> +#define RBSR_DEFAULT_VALUE 0x640
>> +
>> +#define PKTBUFSTX 4
>> +
>> +#define MAX_PHY_ADDR 32
>> +
>> +struct ast_nic_xdes {
>> + u32 des[4];
>> +} __aligned(16);
>
> Can you use a constant for this, like ARCH_DMA_MINALIGN?
Ack
>
>> +
>> +struct ast_nic_xdes ast_txdes[PKTBUFSTX];
>> +struct ast_nic_xdes ast_rxdes[PKTBUFSRX];
>
> Any reason these are not static? Also, why globals instead of allocated?
These should be static, yes. The reason for globals is that I could
not get them properly aligned, when I put them into ast_nic_priv
structure.
>
>> +
>> +struct ast_nic_priv {
>> + struct ast_nic_xdes *txdes;
>> + struct ast_nic_xdes *rxdes;
>> + struct ast_nic_regs *regs;
>> + int tx_index;
>> + int r
Re: [U-Boot] [PATCH 13/17] aspeed: Add support for Clocks needed by MACs
On Mon, Mar 20, 2017 at 12:48 PM, Tom Rini wrote:
>
> On Mon, Mar 20, 2017 at 10:52:12AM -0700, Maxim Sloyko wrote:
> > On Mon, Mar 20, 2017 at 10:30 AM, Tom Rini wrote:
> >
> > > On Mon, Mar 20, 2017 at 10:24:20AM -0700, Maxim Sloyko wrote:
> > > > On Sun, Mar 19, 2017 at 9:42 AM, Tom Rini wrote:
> > > >
> > > > > On Thu, Mar 16, 2017 at 02:36:20PM -0700, Maxim Sloyko wrote:
> > > > > > Add support for clocks needed by MACs to ast2500 clock driver.
> > > > > > The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
> > > > > > PCLK_MAC2 for MAC1 and MAC2 respectively.
> > > > > >
> > > > > > The rate of D2-PLL is hardcoded to 250MHz -- the value used in
> > > > > > Aspeed
> > > > > > SDK. It is not entirely clear from the datasheet how this clock is
> > > used
> > > > > > by MACs, so not clear if the rate would ever need to be different.
> > > So,
> > > > > > for now, hardcoding it is probably safer.
> > > > > >
> > > > > > The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected
> > > through
> > > > > > hardware strapping.
> > > > > >
> > > > > > So, the network driver would only need to enable these clocks, no
> > > need
> > > > > > to configure the rate.
> > > > > >
> > > > > > Signed-off-by: Maxim Sloyko
> > > > > > ---
> > > > > >
> > > > > > arch/arm/dts/ast2500-u-boot.dtsi | 8 +
> > > > > > arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 62 +-
> > > > > > drivers/clk/aspeed/clk_ast2500.c | 265
> > > > > ++---
> > > > > > include/dt-bindings/clock/ast2500-scu.h| 2 +
> > > > > > 4 files changed, 304 insertions(+), 33 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm/dts/ast2500-u-boot.dtsi
> > > > > b/arch/arm/dts/ast2500-u-boot.dtsi
> > > > > > index faeeec1be4..f826646095 100644
> > > > > > --- a/arch/arm/dts/ast2500-u-boot.dtsi
> > > > > > +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> > > > > > @@ -61,3 +61,11 @@
> > > > > > };
> > > > > > };
> > > > > > };
> > > > > > +
> > > > > > +&mac0 {
> > > > > > + clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
> > > > > > +};
> > > > > > +
> > > > > > +&mac1 {
> > > > > > + clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
> > > > > > +};
> > > > >
> > > > > Why is this here and not in the main dts file? The -u-boot.dtsi is
> > > > > for
> > > > > stuff that's not appropriate in the upstream dts file. Thanks!
> > > >
> > > > There is no clock driver for this part in mainline Linux Kernel yet and
> > > > I
> > > > don't know how it will end up being configured. I suspect that they
> > > > might
> > > > not use the same bindings though.
> > > >
> > > > Should I put this into board specific dts?
> > >
> > > So this applies to a lot of parts of the series here. What we don't
> > > want to do is have places where the DTS here diverges from the Linux
> > > kernel DTS and we don't reconcile them. If the relevant Linux drivers
> > > are not in mainline, are they at least in linux-next or otherwise
> > > submitted to the relevant subtrees?
> > >
> >
> > No, as far as I know, maybe Rick (cc'ed) knows what is the plan there.
> >
> > I'm not really working on the linux driver and it's outside of my control.
> >
> > I can change network driver, so that it does not use this DT configuration
> > and either hard code clock config into it, or configure it's clocks in
> > board specific file -- would that be more acceptable?
>
> For all the cases where you don't have the DT portion itself upstream
> yet, go with platdata instead for now. Unless I'm mis-recalling things
> that is.
Sorry, I don't quite follow.
My understanding is that platdata is supposed to be used as a
substitute for DT nodes, but in this case there is a node for MAC
present in upstream linux device tree, it's just that one specific
option that needs to be different. Is there an overwrite mechanism
that is platdata based?
What I was thinking about is changing the driver so that instead of
reading the clock configuration from DT it would use clock ids based
on device's sequence number, i.e. mac0 would use PCLK_MAC0, mac1 would
use PCLK_MAC1. Same for I2C.
>
>
> --
> Tom
--
Maxim Sloyko
___
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Re: [U-Boot] [PATCH 13/17] aspeed: Add support for Clocks needed by MACs
On Mon, Mar 20, 2017 at 10:30 AM, Tom Rini wrote:
> On Mon, Mar 20, 2017 at 10:24:20AM -0700, Maxim Sloyko wrote:
> > On Sun, Mar 19, 2017 at 9:42 AM, Tom Rini wrote:
> >
> > > On Thu, Mar 16, 2017 at 02:36:20PM -0700, Maxim Sloyko wrote:
> > > > Add support for clocks needed by MACs to ast2500 clock driver.
> > > > The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
> > > > PCLK_MAC2 for MAC1 and MAC2 respectively.
> > > >
> > > > The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
> > > > SDK. It is not entirely clear from the datasheet how this clock is
> used
> > > > by MACs, so not clear if the rate would ever need to be different.
> So,
> > > > for now, hardcoding it is probably safer.
> > > >
> > > > The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected
> through
> > > > hardware strapping.
> > > >
> > > > So, the network driver would only need to enable these clocks, no
> need
> > > > to configure the rate.
> > > >
> > > > Signed-off-by: Maxim Sloyko
> > > > ---
> > > >
> > > > arch/arm/dts/ast2500-u-boot.dtsi | 8 +
> > > > arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 62 +-
> > > > drivers/clk/aspeed/clk_ast2500.c | 265
> > > ++---
> > > > include/dt-bindings/clock/ast2500-scu.h| 2 +
> > > > 4 files changed, 304 insertions(+), 33 deletions(-)
> > > >
> > > > diff --git a/arch/arm/dts/ast2500-u-boot.dtsi
> > > b/arch/arm/dts/ast2500-u-boot.dtsi
> > > > index faeeec1be4..f826646095 100644
> > > > --- a/arch/arm/dts/ast2500-u-boot.dtsi
> > > > +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> > > > @@ -61,3 +61,11 @@
> > > > };
> > > > };
> > > > };
> > > > +
> > > > +&mac0 {
> > > > + clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
> > > > +};
> > > > +
> > > > +&mac1 {
> > > > + clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
> > > > +};
> > >
> > > Why is this here and not in the main dts file? The -u-boot.dtsi is for
> > > stuff that's not appropriate in the upstream dts file. Thanks!
> >
> > There is no clock driver for this part in mainline Linux Kernel yet and I
> > don't know how it will end up being configured. I suspect that they might
> > not use the same bindings though.
> >
> > Should I put this into board specific dts?
>
> So this applies to a lot of parts of the series here. What we don't
> want to do is have places where the DTS here diverges from the Linux
> kernel DTS and we don't reconcile them. If the relevant Linux drivers
> are not in mainline, are they at least in linux-next or otherwise
> submitted to the relevant subtrees?
>
No, as far as I know, maybe Rick (cc'ed) knows what is the plan there.
I'm not really working on the linux driver and it's outside of my control.
I can change network driver, so that it does not use this DT configuration
and either hard code clock config into it, or configure it's clocks in
board specific file -- would that be more acceptable?
>
> --
> Tom
>
--
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Re: [U-Boot] [PATCH 13/17] aspeed: Add support for Clocks needed by MACs
On Sun, Mar 19, 2017 at 9:42 AM, Tom Rini wrote:
> On Thu, Mar 16, 2017 at 02:36:20PM -0700, Maxim Sloyko wrote:
> > Add support for clocks needed by MACs to ast2500 clock driver.
> > The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
> > PCLK_MAC2 for MAC1 and MAC2 respectively.
> >
> > The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
> > SDK. It is not entirely clear from the datasheet how this clock is used
> > by MACs, so not clear if the rate would ever need to be different. So,
> > for now, hardcoding it is probably safer.
> >
> > The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
> > hardware strapping.
> >
> > So, the network driver would only need to enable these clocks, no need
> > to configure the rate.
> >
> > Signed-off-by: Maxim Sloyko
> > ---
> >
> > arch/arm/dts/ast2500-u-boot.dtsi | 8 +
> > arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 62 +-
> > drivers/clk/aspeed/clk_ast2500.c | 265
> ++---
> > include/dt-bindings/clock/ast2500-scu.h| 2 +
> > 4 files changed, 304 insertions(+), 33 deletions(-)
> >
> > diff --git a/arch/arm/dts/ast2500-u-boot.dtsi
> b/arch/arm/dts/ast2500-u-boot.dtsi
> > index faeeec1be4..f826646095 100644
> > --- a/arch/arm/dts/ast2500-u-boot.dtsi
> > +++ b/arch/arm/dts/ast2500-u-boot.dtsi
> > @@ -61,3 +61,11 @@
> > };
> > };
> > };
> > +
> > +&mac0 {
> > + clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
> > +};
> > +
> > +&mac1 {
> > + clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
> > +};
>
> Why is this here and not in the main dts file? The -u-boot.dtsi is for
> stuff that's not appropriate in the upstream dts file. Thanks!
>
There is no clock driver for this part in mainline Linux Kernel yet and I
don't know how it will end up being configured. I suspect that they might
not use the same bindings though.
Should I put this into board specific dts?
>
> --
> Tom
>
--
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[U-Boot] [PATCH 17/17] aspeed: Network Driver configuration for EVB
Enable Network Driver along with network related commands -- ping, dhcp,
mii -- in ast2500 Eval Board's defconfig.
Add MAC devices' configuration to Eval Board Device Tree.
Signed-off-by: Maxim Sloyko
---
---
arch/arm/dts/ast2500-evb.dts | 14 ++
configs/evb-ast2500_defconfig | 7 +++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index 723941ac0b..c47ad684a5 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -36,3 +36,17 @@
u-boot,dm-pre-reloc;
status = "okay";
};
+
+&mac0 {
+ compatible = "aspeed,ast2500-nic";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mac1link_default>, <&pinctrl_mdio1_default>;
+};
+
+&mac1 {
+ compatible = "aspeed,ast2500-nic";
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_mac2link_default>, <&pinctrl_mdio2_default>;
+};
diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index 08b5f85a34..d1548f7f3c 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -21,3 +21,10 @@ CONFIG_PINCTRL=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_ASPEED=y
CONFIG_CMD_I2C=y
+CONFIG_DM_ETH=y
+CONFIG_AST_NIC=y
+CONFIG_CMD_NET=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_MII=y
+CONFIG_CMD_MII=y
--
2.12.0.367.g23dc2f6d3c-goog
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[U-Boot] [PATCH 14/17] aspeed: Refactor SCU to use consistent mask & shift
Refactor SCU header to use consistent Mask & Shift values.
Now, consistently, to read value from SCU register, mask needs
to be applied before shift.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 12
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 5 ++--
drivers/clk/aspeed/clk_ast2500.c | 39 +-
3 files changed, 27 insertions(+), 29 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fe877b5430..590aed2f6c 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -8,8 +8,8 @@
#define SCU_UNLOCK_VALUE 0x1688a8a8
-#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_VGAMEM_MASK(3 << SCU_HWSTRAP_VGAMEM_SHIFT)
#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
@@ -18,17 +18,17 @@
#define SCU_MPLL_DENUM_SHIFT 0
#define SCU_MPLL_DENUM_MASK0x1f
#define SCU_MPLL_NUM_SHIFT 5
-#define SCU_MPLL_NUM_MASK 0xff
+#define SCU_MPLL_NUM_MASK (0xff << SCU_MPLL_NUM_SHIFT)
#define SCU_MPLL_POST_SHIFT13
-#define SCU_MPLL_POST_MASK 0x3f
+#define SCU_MPLL_POST_MASK (0x3f << SCU_MPLL_POST_SHIFT)
#define SCU_PCLK_DIV_SHIFT 23
-#define SCU_PCLK_DIV_MASK 7
+#define SCU_PCLK_DIV_MASK (7 << SCU_PCLK_DIV_SHIFT)
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK0x1f
#define SCU_HPLL_NUM_SHIFT 5
-#define SCU_HPLL_NUM_MASK 0xff
+#define SCU_HPLL_NUM_MASK (0xff << SCU_HPLL_NUM_SHIFT)
#define SCU_HPLL_POST_SHIFT13
-#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_HPLL_POST_MASK (0x3f << SCU_HPLL_POST_SHIFT)
#define SCU_MACCLK_SHIFT 16
#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index efcf452b17..6383f727f2 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -183,9 +183,8 @@ static int ast2500_sdrammc_ddr4_calibrate_vref(struct
dram_info *info)
static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
{
size_t vga_mem_size_base = 8 * 1024 * 1024;
- u32 vga_hwconf = (readl(&info->scu->hwstrap)
- >> SCU_HWSTRAP_VGAMEM_SHIFT)
- & SCU_HWSTRAP_VGAMEM_MASK;
+ u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
+ >> SCU_HWSTRAP_VGAMEM_SHIFT;
return vga_mem_size_base << vga_hwconf;
}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 7b4b5c64ac..ccf47a1da1 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -52,11 +52,11 @@ struct ast2500_div_config {
*/
static ulong ast2500_get_mpll_rate(ulong clkin, u32 mpll_reg)
{
- const ulong num = (mpll_reg >> SCU_MPLL_NUM_SHIFT) & SCU_MPLL_NUM_MASK;
- const ulong denum = (mpll_reg >> SCU_MPLL_DENUM_SHIFT)
- & SCU_MPLL_DENUM_MASK;
- const ulong post_div = (mpll_reg >> SCU_MPLL_POST_SHIFT)
- & SCU_MPLL_POST_MASK;
+ const ulong num = (mpll_reg & SCU_MPLL_NUM_MASK) >> SCU_MPLL_NUM_SHIFT;
+ const ulong denum = (mpll_reg & SCU_MPLL_DENUM_MASK)
+ >> SCU_MPLL_DENUM_SHIFT;
+ const ulong post_div = (mpll_reg & SCU_MPLL_POST_MASK)
+ >> SCU_MPLL_POST_SHIFT;
return (clkin * ((num + 1) / (denum + 1))) / (post_div + 1);
}
@@ -67,11 +67,11 @@ static ulong ast2500_get_mpll_rate(ulong clkin, u32
mpll_reg)
*/
static ulong ast2500_get_hpll_rate(ulong clkin, u32 hpll_reg)
{
- const ulong num = (hpll_reg >> SCU_HPLL_NUM_SHIFT) & SCU_HPLL_NUM_MASK;
- const ulong denum = (hpll_reg >> SCU_HPLL_DENUM_SHIFT)
- & SCU_HPLL_DENUM_MASK;
- const ulong post_div = (hpll_reg >> SCU_HPLL_POST_SHIFT)
- & SCU_HPLL_POST_MASK;
+ const ulong num = (hpll_reg & SCU_HPLL_NUM_MASK) >> SCU_HPLL_NUM_SHIFT;
+ const ulong denum = (hpll_reg & SCU_HPLL_DENUM_MASK)
+ >> SCU_HPLL_DENUM_SHIFT;
+ const ulong post_div = (hpll_reg & SCU_HPLL_POST_MASK)
+ >> SCU_HPLL_POST_SHIFT;
return (clkin * ((num + 1
[U-Boot] [PATCH 15/17] aspeed: Cleanup ast2500-u-boot.dtsi Device Tree
Remove unnecessary apb and ahb nodes and just override necessary
nodes/values.
Signed-off-by: Maxim Sloyko
---
arch/arm/dts/ast2500-u-boot.dtsi | 41
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index f826646095..7f80bad7d0 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -34,32 +34,33 @@
apb {
u-boot,dm-pre-reloc;
+ };
- timer: timer@1e782000 {
- u-boot,dm-pre-reloc;
- };
+ };
+};
- uart1: serial@1e783000 {
- clocks = <&scu PCLK_UART1>;
- };
+&uart1 {
+ clocks = <&scu PCLK_UART1>;
+};
- uart2: serial@1e78d000 {
- clocks = <&scu PCLK_UART2>;
- };
+&uart2 {
+ clocks = <&scu PCLK_UART2>;
+};
- uart3: serial@1e78e000 {
- clocks = <&scu PCLK_UART3>;
- };
+&uart3 {
+ clocks = <&scu PCLK_UART3>;
+};
- uart4: serial@1e78f000 {
- clocks = <&scu PCLK_UART4>;
- };
+&uart4 {
+ clocks = <&scu PCLK_UART4>;
+};
- uart5: serial@1e784000 {
- clocks = <&scu PCLK_UART5>;
- };
- };
- };
+&uart5 {
+ clocks = <&scu PCLK_UART5>;
+};
+
+&timer {
+ u-boot,dm-pre-reloc;
};
&mac0 {
--
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[U-Boot] [PATCH 16/17] aspeed: Add AST2500/AST2400 compatible NIC Driver
The device that Aspeed uses is basically Faraday FTGMAC100, but with
some differences here and there. Since I don't have access to a properly
implemented FTGMAC100 though, I can't really test it and so I don't
feel comfortable claiming compatibility, even though I reused a lot of
FTGMAC100 driver code.
Signed-off-by: Maxim Sloyko
---
drivers/net/Kconfig | 8 +
drivers/net/Makefile | 1 +
drivers/net/ast_nic.c | 584 ++
drivers/net/ast_nic.h | 198 +
4 files changed, 791 insertions(+)
create mode 100644 drivers/net/ast_nic.c
create mode 100644 drivers/net/ast_nic.h
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 70e36611ea..6de8b35d9f 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -208,4 +208,12 @@ config GMAC_ROCKCHIP
This driver provides Rockchip SoCs network support based on the
Synopsys Designware driver.
+config AST_NIC
+ bool "Support Aspeed ast2500/ast2400 NIC"
+ depends on DM_ETH
+ help
+ This driver provides support for ast2500/ast2400 network devices.
+ It uses Driver Model and so can support multiple devices on the same
SoC.
+ The device itself is basically a variation of Faraday FTGMAC100.
+
endif # NETDEVICES
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 2493a48b88..792bebb9cc 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -78,3 +78,4 @@ obj-$(CONFIG_FSL_MEMAC) += fm/memac_phy.o
obj-$(CONFIG_VSC9953) += vsc9953.o
obj-$(CONFIG_PIC32_ETH) += pic32_mdio.o pic32_eth.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
+obj-$(CONFIG_AST_NIC) += ast_nic.o
diff --git a/drivers/net/ast_nic.c b/drivers/net/ast_nic.c
new file mode 100644
index 00..881d20151c
--- /dev/null
+++ b/drivers/net/ast_nic.c
@@ -0,0 +1,584 @@
+/*
+ * (C) Copyright 2009 Faraday Technology
+ * Po-Yu Chuang
+ *
+ * (C) Copyright 2010 Andes Technology
+ * Macpaul Lin
+ *
+ * Copyright 2017 Google Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+/*
+ * This device is basically Faraday FTGMAC100, with some differences,
+ * which do not seem to be very big, but are in very random places, like
+ * some registers removed and completely different ones put in their place.
+ */
+
+#include
+#include
+#include
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#include
+#endif
+#include
+#include
+#include
+#include "ast_nic.h"
+
+#define ETH_ZLEN 60
+#define RBSR_DEFAULT_VALUE 0x640
+
+#define PKTBUFSTX 4
+
+#define MAX_PHY_ADDR 32
+
+struct ast_nic_xdes {
+ u32 des[4];
+} __aligned(16);
+
+struct ast_nic_xdes ast_txdes[PKTBUFSTX];
+struct ast_nic_xdes ast_rxdes[PKTBUFSRX];
+
+struct ast_nic_priv {
+ struct ast_nic_xdes *txdes;
+ struct ast_nic_xdes *rxdes;
+ struct ast_nic_regs *regs;
+ int tx_index;
+ int rx_index;
+ int phy_addr;
+};
+
+static int ast_nic_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast_nic_priv *priv = dev_get_priv(dev);
+ struct eth_pdata *platdata = dev_get_platdata(dev);
+
+ priv->regs = dev_get_addr_ptr(dev);
+ priv->txdes = ast_txdes;
+ priv->rxdes = ast_rxdes;
+ platdata->iobase = (phys_addr_t)priv->regs;
+
+ return 0;
+}
+
+static void ast_nic_reset(struct udevice *dev)
+{
+ struct ast_nic_priv *priv = dev_get_priv(dev);
+
+ setbits_le32(&priv->regs->maccr, MAC_MACCR_SW_RST);
+ while (readl(&priv->regs->maccr) & MAC_MACCR_SW_RST)
+ ;
+ /*
+* Only needed for ast2400, for ast2500 this is the no-op,
+* because the register is marked read-only.
+*/
+ setbits_le32(&priv->regs->fear0, MAC_FEAR_NEW_MD_IFACE);
+}
+
+static int ast_nic_phy_read(struct udevice *dev, int phy_addr,
+ int regnum, u16 *value)
+{
+ struct ast_nic_priv *priv = dev_get_priv(dev);
+ int phycr;
+ int i;
+
+ phycr = MAC_PHYCR_FIRE | MAC_PHYCR_ST_22 | MAC_PHYCR_READ |
+ (phy_addr << MAC_PHYCR_PHYAD_SHIFT) |
+ (regnum << MAC_PHYCR_REGAD_SHIFT);
+
+ writel(phycr, &priv->regs->phycr);
+
+ for (i = 0; i < 10; i++) {
+ phycr = readl(&priv->regs->phycr);
+
+ if ((phycr & MAC_PHYCR_FIRE) == 0) {
+ int data;
+
+ data = readl(&priv->regs->phydata);
+ *value = (data & MAC_PHYDATA_MIIRDATA_MASK) >>
+ MAC_PHYDATA_MIIRDATA_SHIFT;
+
+ return 0;
+ }
+
+ mdelay(10);
+ }
+
+ debug("mdio read timed out\n");
+ return -ETIMEDOUT;
+}
+
+static int ast_nic_phy_write(struct udevice *dev, int phy_addr,
+ int regnum, u16
[U-Boot] [PATCH 12/17] aspeed: Enable I2C in EVB defconfig
Enable I2C driver in ast2500 Eval Board defconfig. Also enable i2c command. Signed-off-by: Maxim Sloyko --- configs/evb-ast2500_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index f8ef9b779c..08b5f85a34 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -18,3 +18,6 @@ CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y CONFIG_PINCTRL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_ASPEED=y +CONFIG_CMD_I2C=y -- 2.12.0.367.g23dc2f6d3c-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 11/17] aspeed: Add I2C Driver
Add Device Model based I2C driver for ast2500/ast2400 SoCs.
The driver is very limited, it only supports master mode and
synchronous byte-by-byte reads/writes, no DMA or Pool Buffers.
Signed-off-by: Maxim Sloyko
---
drivers/i2c/Kconfig | 9 ++
drivers/i2c/Makefile | 1 +
drivers/i2c/ast_i2c.c | 355 ++
drivers/i2c/ast_i2c.h | 132 +++
4 files changed, 497 insertions(+)
create mode 100644 drivers/i2c/ast_i2c.c
create mode 100644 drivers/i2c/ast_i2c.h
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index 39f62daf5d..e661a308b0 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -100,6 +100,15 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
enable status register. This config option can be enabled in such
cases.
+config SYS_I2C_ASPEED
+ bool "Aspeed I2C Controller"
+ depends on DM_I2C && ARCH_ASPEED
+ help
+ Say yes here to select Aspeed I2C Host Controller. The driver
+ supports AST2500 and AST2400 controllers, but is very limited.
+ Only single master mode is supported and only byte-by-byte
+ synchronous reads and writes are supported, no Pool Buffers or DMA.
+
config SYS_I2C_INTEL
bool "Intel I2C/SMBUS driver"
depends on DM_I2C
diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile
index 7c86198863..229fd476db 100644
--- a/drivers/i2c/Makefile
+++ b/drivers/i2c/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o
obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o
obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o
obj-$(CONFIG_SYS_I2C) += i2c_core.o
+obj-$(CONFIG_SYS_I2C_ASPEED) += ast_i2c.o
obj-$(CONFIG_SYS_I2C_AT91) += at91_i2c.o
obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o
diff --git a/drivers/i2c/ast_i2c.c b/drivers/i2c/ast_i2c.c
new file mode 100644
index 00..0b60b08cf2
--- /dev/null
+++ b/drivers/i2c/ast_i2c.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ * Copyright 2016 IBM Corporation
+ * Copyright 2017 Google, Inc.
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "ast_i2c.h"
+
+#define I2C_TIMEOUT_US 10
+#define I2C_SLEEP_STEP_US 20
+
+#define HIGHSPEED_TTIMEOUT 3
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Device private data
+ */
+struct ast_i2c_priv {
+ /* This device's clock */
+ struct clk clk;
+ /* Device registers */
+ struct ast_i2c_regs *regs;
+ /* I2C speed in Hz */
+ int speed;
+};
+
+/*
+ * Given desired divider ratio, return the value that needs to be set
+ * in Clock and AC Timing Control register
+ */
+static u32 get_clk_reg_val(ulong divider_ratio)
+{
+ ulong inc = 0, div;
+ ulong scl_low, scl_high, data;
+
+ for (div = 0; divider_ratio >= 16; div++) {
+ inc |= (divider_ratio & 1);
+ divider_ratio >>= 1;
+ }
+ divider_ratio += inc;
+ scl_low = (divider_ratio >> 1) - 1;
+ scl_high = divider_ratio - scl_low - 2;
+ data = I2CD_CACTC_BASE
+ | (scl_high << I2CD_TCKHIGH_SHIFT)
+ | (scl_low << I2CD_TCKLOW_SHIFT)
+ | (div << I2CD_BASE_DIV_SHIFT);
+
+ return data;
+}
+
+static void ast_i2c_clear_interrupts(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ writel(~0, &priv->regs->isr);
+}
+
+static void ast_i2c_init_bus(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+
+ /* Reset device */
+ writel(0, &priv->regs->fcr);
+ /* Enable Master Mode. Assuming single-master */
+ writel(I2CD_MASTER_EN
+ | I2CD_M_SDA_LOCK_EN
+ | I2CD_MULTI_MASTER_DIS | I2CD_M_SCL_DRIVE_EN,
+ &priv->regs->fcr);
+ /* Enable Interrupts */
+ writel(I2CD_INTR_TX_ACK
+ | I2CD_INTR_TX_NAK
+ | I2CD_INTR_RX_DONE
+ | I2CD_INTR_BUS_RECOVER_DONE
+ | I2CD_INTR_NORMAL_STOP
+ | I2CD_INTR_ABNORMAL, &priv->regs->icr);
+}
+
+static int ast_i2c_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast_i2c_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ priv->regs = dev_get_addr_ptr(dev);
+ if (IS_ERR(priv->regs))
+ return PTR_ERR(priv->regs);
+
+ ret = clk_get_by_index(dev, 0, &priv->clk);
+ if (ret < 0) {
+ debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
+ ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ast_i2c_probe(struct udevice *dev)
+{
+ struct ast2500_scu *scu;
+
+
[U-Boot] [PATCH 08/17] aspeed: AST2500 Pinctrl Driver
This driver uses Generic Pinctrl framework and is compatible with
the Linux driver for ast2500: it uses the same device tree
configuration.
Not all pins are supported by the driver at the moment, so it actually
compatible with ast2400. In general, however, there are differences that
in the future would be easier to maintain separately.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 19
drivers/pinctrl/Kconfig| 9 ++
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/aspeed/Makefile| 1 +
drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 +
6 files changed, 209 insertions(+)
create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h
create mode 100644 drivers/pinctrl/aspeed/Makefile
create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c
diff --git a/arch/arm/include/asm/arch-aspeed/pinctrl.h
b/arch/arm/include/asm/arch-aspeed/pinctrl.h
new file mode 100644
index 00..365dc21dbc
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/pinctrl.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef _ASM_ARCH_PERIPH_H
+#define _ASM_ARCH_PERIPH_H
+
+/*
+ * Peripherals supported by the hardware.
+ * These are used to specify pinctrl settings.
+ */
+
+enum periph_id {
+ PERIPH_ID_UART1,
+ PERIPH_ID_UART2,
+ PERIPH_ID_UART3,
+ PERIPH_ID_UART4,
+ PERIPH_ID_LPC,
+ PERIPH_ID_PWM0,
+ PERIPH_ID_PWM1,
+ PERIPH_ID_PWM2,
+ PERIPH_ID_PWM3,
+ PERIPH_ID_PWM4,
+ PERIPH_ID_PWM5,
+ PERIPH_ID_PWM6,
+ PERIPH_ID_PWM7,
+ PERIPH_ID_PWM8,
+ PERIPH_ID_MAC1,
+ PERIPH_ID_MAC2,
+ PERIPH_ID_VIDEO,
+ PERIPH_ID_SPI1,
+ PERIPH_ID_SPI2,
+ PERIPH_ID_I2C1,
+ PERIPH_ID_I2C2,
+ PERIPH_ID_I2C3,
+ PERIPH_ID_I2C4,
+ PERIPH_ID_I2C5,
+ PERIPH_ID_I2C6,
+ PERIPH_ID_I2C7,
+ PERIPH_ID_I2C8,
+ PERIPH_ID_I2C9,
+ PERIPH_ID_I2C10,
+ PERIPH_ID_I2C11,
+ PERIPH_ID_I2C12,
+ PERIPH_ID_I2C13,
+ PERIPH_ID_I2C14,
+ PERIPH_ID_SD1,
+ PERIPH_ID_SD2,
+};
+
+#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index e2556f920d..1cdd3b9198 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -10,6 +10,8 @@
#define SCU_HWSTRAP_VGAMEM_MASK3
#define SCU_HWSTRAP_VGAMEM_SHIFT 2
+#define SCU_HWSTRAP_MAC1_RGMII (1 << 6)
+#define SCU_HWSTRAP_MAC2_RGMII (1 << 7)
#define SCU_HWSTRAP_DDR4 (1 << 24)
#define SCU_HWSTRAP_CLKIN_25MHZ(1 << 23)
@@ -59,6 +61,23 @@
#define SCU_SYSRESET_AHB (1 << 1)
#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+/* Bits 16-27 in the register control pin functions for I2C devices 3-14 */
+#define SCU_PINMUX_CTRL5_I2C (1 << 16)
+
+/*
+ * The values are grouped by function, not by register.
+ * They are actually scattered across multiple loosely related registers.
+ */
+#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
+#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_SCL1 (1 << 12)
+#define SCU_PIN_FUN_SCL2 (1 << 14)
+#define SCU_PIN_FUN_SDA1 (1 << 13)
+#define SCU_PIN_FUN_SDA2 (1 << 15)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index efcb4c0003..3b7dd5f0c5 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -175,6 +175,15 @@ config PIC32_PINCTRL
by a device tree node which contains both GPIO defintion and pin
control
functions.
+config ASPEED_AST2500_PINCTRL
+ bool "Aspeed AST2500 pin control driver"
+ depends on DM && PINCTRL_GENERIC && ASPEED_AST2500
+ default y
+ help
+Support pin multiplexing control on Aspeed ast2500 SoC. The driver uses
+ Generic Pinctrl framework and is compatible with the Linux driver,
+ i.e. it uses the same device tree configuration.
+
endif
source "drivers/pinctrl/meson/Kconfig"
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 512112af64..5392c3ed45 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_PIC32_PINCTRL) += pinctrl_pic32.o
obj-$(CONFIG_PINCTRL_EXYNOS) += exynos/
obj-$(CONFIG_PINCTRL_MESON)+= meson/
o
[U-Boot] [PATCH 07/17] aspeed: Refactor AST2500 RAM Driver and Sysreset Driver
This change switches all existing users of ast2500 Watchdog to Driver
Model based Watchdog driver.
To perform system reset Sysreset Driver uses first Watchdog device found
via uclass_first_device call. Since the system is going to be reset
anyway it does not make much difference which watchdog is used.
Instead of using Watchdog to reset itself, SDRAM driver now uses Reset
driver to do that.
These were the only users of the old Watchdog API, so that API is
removed.
This all is done in one change to avoid having to maintain dual API for
watchdog in between.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/wdt.h | 39 -
arch/arm/mach-aspeed/Kconfig | 8 +
arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 12 +--
arch/arm/mach-aspeed/ast_wdt.c | 51
configs/evb-ast2500_defconfig| 2 ++
drivers/sysreset/sysreset_ast.c | 24 ++---
6 files changed, 24 insertions(+), 112 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index 981fa05a56..db8ecbcbe4 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -100,45 +100,6 @@ u32 ast_reset_mask_from_flags(ulong flags);
* @reset_mask: Reset Mask
*/
ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
-
-#ifndef CONFIG_WDT
-/**
- * Stop WDT
- *
- * @wdt: watchdog to stop
- *
- * When using driver model this function has different signature
- */
-void wdt_stop(struct ast_wdt *wdt);
-
-/**
- * Stop WDT
- *
- * @wdt: watchdog to start
- * @timeoutwatchdog timeout in number of clock ticks
- *
- * When using driver model this function has different signature
- */
-void wdt_start(struct ast_wdt *wdt, u32 timeout);
-#endif /* CONFIG_WDT */
-
-/**
- * Reset peripherals specified by mask
- *
- * Note, that this is only supported by ast2500 SoC
- *
- * @wdt: watchdog to use for this reset
- * @mask: reset mask.
- */
-int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask);
-
-/**
- * ast_get_wdt() - get a pointer to watchdog registers
- *
- * @wdt_number: 0-based WDT peripheral number
- * @return pointer to registers or -ve error on error
- */
-struct ast_wdt *ast_get_wdt(u8 wdt_number);
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_WDT_H */
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index c5b90bd96a..4f021baa06 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -11,19 +11,13 @@ config SYS_TEXT_BASE
config ASPEED_AST2500
bool "Support Aspeed AST2500 SoC"
+ depends on DM_RESET
select CPU_ARM1176
help
The Aspeed AST2500 is a ARM-based SoC with arm1176 CPU.
It is used as Board Management Controller on many server boards,
which is enabled by support of LPC and eSPI peripherals.
-config WDT_NUM
- int "Number of Watchdog Timers"
- default 3 if ASPEED_AST2500
- help
- The number of Watchdot Timers on a SoC.
- AST2500 has three WDTsk earlier versions have two or fewer.
-
source "arch/arm/mach-aspeed/ast2500/Kconfig"
endif
diff --git a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
index cb6e03fa34..efcf452b17 100644
--- a/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/sdram_ast2500.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -328,6 +329,7 @@ static void ast2500_sdrammc_lock(struct dram_info *info)
static int ast2500_sdrammc_probe(struct udevice *dev)
{
+ struct reset_ctl reset_ctl;
struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
struct ast2500_sdrammc_regs *regs = priv->regs;
int i;
@@ -345,9 +347,15 @@ static int ast2500_sdrammc_probe(struct udevice *dev)
}
clk_set_rate(&priv->ddr_clk, priv->clock_rate);
- ret = ast_wdt_reset_masked(ast_get_wdt(0), WDT_RESET_SDRAM);
+ ret = reset_get_by_index(dev, 0, &reset_ctl);
if (ret) {
- debug("%s(): SDRAM reset failed\n", __func__);
+ debug("%s(): Failed to get reset signal\n", __func__);
+ return ret;
+ }
+
+ ret = reset_assert(&reset_ctl);
+ if (ret) {
+ debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
return ret;
}
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 895fba3366..1a858b1020 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -28,54 +28,3 @@ ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32
reset_mask)
return ret;
}
-
-#ifndef CONFIG_WDT
-void wdt_stop(struct ast_wdt *wdt)
-{
- clrbits_le3
[U-Boot] [PATCH 13/17] aspeed: Add support for Clocks needed by MACs
Add support for clocks needed by MACs to ast2500 clock driver.
The clocks are D2-PLL, which is used by both MACs and PCLK_MAC1 and
PCLK_MAC2 for MAC1 and MAC2 respectively.
The rate of D2-PLL is hardcoded to 250MHz -- the value used in Aspeed
SDK. It is not entirely clear from the datasheet how this clock is used
by MACs, so not clear if the rate would ever need to be different. So,
for now, hardcoding it is probably safer.
The rate of PCLK_MAC{1,2} is chosen based on MAC speed selected through
hardware strapping.
So, the network driver would only need to enable these clocks, no need
to configure the rate.
Signed-off-by: Maxim Sloyko
---
arch/arm/dts/ast2500-u-boot.dtsi | 8 +
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 62 +-
drivers/clk/aspeed/clk_ast2500.c | 265 ++---
include/dt-bindings/clock/ast2500-scu.h| 2 +
4 files changed, 304 insertions(+), 33 deletions(-)
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index faeeec1be4..f826646095 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -61,3 +61,11 @@
};
};
};
+
+&mac0 {
+ clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+};
+
+&mac1 {
+ clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+};
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 319d75e05c..fe877b5430 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -30,9 +30,36 @@
#define SCU_HPLL_POST_SHIFT13
#define SCU_HPLL_POST_MASK 0x3f
+#define SCU_MACCLK_SHIFT 16
+#define SCU_MACCLK_MASK(7 << SCU_MACCLK_SHIFT)
+
+#define SCU_MISC2_RGMII_HPLL (1 << 23)
+#define SCU_MISC2_RGMII_CLKDIV_SHIFT 20
+#define SCU_MISC2_RGMII_CLKDIV_MASK(3 << SCU_MISC2_RGMII_CLKDIV_SHIFT)
+#define SCU_MISC2_RMII_MPLL(1 << 19)
+#define SCU_MISC2_RMII_CLKDIV_SHIFT16
+#define SCU_MISC2_RMII_CLKDIV_MASK (3 << SCU_MISC2_RMII_CLKDIV_SHIFT)
#define SCU_MISC2_UARTCLK_SHIFT24
+#define SCU_MISC_D2PLL_OFF (1 << 4)
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+#define SCU_MISC_GCRT_USB20CLK (1 << 21)
+
+#define SCU_MICDS_MAC1RGMII_TXDLY_SHIFT0
+#define SCU_MICDS_MAC1RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC1RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC2RGMII_TXDLY_SHIFT6
+#define SCU_MICDS_MAC2RGMII_TXDLY_MASK (0x3f\
+<< SCU_MICDS_MAC2RGMII_TXDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_RDLY_SHIFT 12
+#define SCU_MICDS_MAC1RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC1RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC2RMII_RDLY_SHIFT 18
+#define SCU_MICDS_MAC2RMII_RDLY_MASK (0x3f << SCU_MICDS_MAC2RMII_RDLY_SHIFT)
+#define SCU_MICDS_MAC1RMII_TXFALL (1 << 24)
+#define SCU_MICDS_MAC2RMII_TXFALL (1 << 25)
+#define SCU_MICDS_RMII1_RCLKEN (1 << 29)
+#define SCU_MICDS_RMII2_RCLKEN (1 << 30)
+#define SCU_MICDS_RGMIIPLL (1 << 31)
/*
* SYSRESET is actually more like a Power register,
@@ -71,14 +98,45 @@
*/
#define SCU_PIN_FUN_MAC1_MDC (1 << 30)
#define SCU_PIN_FUN_MAC1_MDIO (1 << 31)
-#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
+#define SCU_PIN_FUN_MAC1_PHY_LINK (1 << 0)
#define SCU_PIN_FUN_MAC2_MDIO (1 << 2)
-#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
+#define SCU_PIN_FUN_MAC2_PHY_LINK (1 << 1)
#define SCU_PIN_FUN_SCL1 (1 << 12)
#define SCU_PIN_FUN_SCL2 (1 << 14)
#define SCU_PIN_FUN_SDA1 (1 << 13)
#define SCU_PIN_FUN_SDA2 (1 << 15)
+#define SCU_CLKSTOP_MAC1 (1 << 20)
+#define SCU_CLKSTOP_MAC2 (1 << 21)
+
+#define SCU_D2PLL_EXT1_OFF (1 << 0)
+#define SCU_D2PLL_EXT1_BYPASS (1 << 1)
+#define SCU_D2PLL_EXT1_RESET (1 << 2)
+#define SCU_D2PLL_EXT1_MODE_SHIFT 3
+#define SCU_D2PLL_EXT1_MODE_MASK (3 << SCU_D2PLL_EXT1_MODE_SHIFT)
+#define SCU_D2PLL_EXT1_PARAM_SHIFT 5
+#define SCU_D2PLL_EXT1_PARAM_MASK (0x1ff << SCU_D2PLL_EXT1_PARAM_SHIFT)
+
+#define SCU_D2PLL_NUM_SHIFT0
+#define SCU_D2PLL_NUM_MASK (0xff << SCU_D2PLL_NUM_SHIFT)
+#define SCU_D2PLL_DENUM_SHIFT 8
+#define SCU_D2PLL_DENUM_MASK (0x1f << SCU_D2PLL_DENUM_SHIFT)
+#define SCU_D2PLL_POST_SHIFT 13
+#define SCU_D2PLL_POST_MASK(0x3f << SCU_D2PLL_POST_SHIFT)
+#define SCU_D2PLL_ODIV_SHIFT
[U-Boot] [PATCH 03/17] aspeed: Watchdog Timer Driver
This driver supports ast2500 and ast2400 SoCs.
Only ast2500 supports reset_mask and thus the option of resettting
individual peripherals using WDT.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/wdt.h | 53 --
arch/arm/mach-aspeed/ast_wdt.c | 40 ---
drivers/watchdog/Kconfig | 13
drivers/watchdog/Makefile | 1 +
drivers/watchdog/ast_wdt.c | 125 +
5 files changed, 219 insertions(+), 13 deletions(-)
create mode 100644 drivers/watchdog/ast_wdt.c
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
index b292a0e67b..981fa05a56 100644
--- a/arch/arm/include/asm/arch-aspeed/wdt.h
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -67,15 +67,60 @@ struct ast_wdt {
u32 timeout_status;
u32 clr_timeout_status;
u32 reset_width;
-#ifdef CONFIG_ASPEED_AST2500
+ /* On pre-ast2500 SoCs this register is reserved. */
u32 reset_mask;
-#else
- u32 reserved0;
-#endif
};
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mode value from it.
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mode value
+ */
+u32 ast_reset_mode_from_flags(ulong flags);
+
+/**
+ * Given flags parameter passed to wdt_reset or wdt_start uclass functions,
+ * gets Reset Mask value from it. Reset Mask is only supported on ast2500
+ *
+ * @flags: flags parameter passed into wdt_reset or wdt_start
+ * @return Reset Mask value
+ */
+u32 ast_reset_mask_from_flags(ulong flags);
+
+/**
+ * Given Reset Mask and Reset Mode values, converts them to flags,
+ * suitable for passing into wdt_start or wdt_reset uclass functions.
+ *
+ * On ast2500 Reset Mask is 25 bits wide and Reset Mode is 2 bits wide, so they
+ * can both be packed into single 32 bits wide value.
+ *
+ * @reset_mode: Reset Mode
+ * @reset_mask: Reset Mask
+ */
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask);
+
+#ifndef CONFIG_WDT
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to stop
+ *
+ * When using driver model this function has different signature
+ */
void wdt_stop(struct ast_wdt *wdt);
+
+/**
+ * Stop WDT
+ *
+ * @wdt: watchdog to start
+ * @timeoutwatchdog timeout in number of clock ticks
+ *
+ * When using driver model this function has different signature
+ */
void wdt_start(struct ast_wdt *wdt, u32 timeout);
+#endif /* CONFIG_WDT */
/**
* Reset peripherals specified by mask
diff --git a/arch/arm/mach-aspeed/ast_wdt.c b/arch/arm/mach-aspeed/ast_wdt.c
index 22481ab7ea..895fba3366 100644
--- a/arch/arm/mach-aspeed/ast_wdt.c
+++ b/arch/arm/mach-aspeed/ast_wdt.c
@@ -9,6 +9,27 @@
#include
#include
+u32 ast_reset_mode_from_flags(ulong flags)
+{
+ return flags & WDT_CTRL_RESET_MASK;
+}
+
+u32 ast_reset_mask_from_flags(ulong flags)
+{
+ return flags >> 2;
+}
+
+ulong ast_flags_from_reset_mode_mask(u32 reset_mode, u32 reset_mask)
+{
+ ulong ret = reset_mode & WDT_CTRL_RESET_MASK;
+
+ if (ret == WDT_CTRL_RESET_SOC)
+ ret |= (reset_mask << 2);
+
+ return ret;
+}
+
+#ifndef CONFIG_WDT
void wdt_stop(struct ast_wdt *wdt)
{
clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
@@ -26,15 +47,7 @@ void wdt_start(struct ast_wdt *wdt, u32 timeout)
setbits_le32(&wdt->ctrl,
WDT_CTRL_EN | WDT_CTRL_RESET | WDT_CTRL_CLK1MHZ);
}
-
-struct ast_wdt *ast_get_wdt(u8 wdt_number)
-{
- if (wdt_number > CONFIG_WDT_NUM - 1)
- return ERR_PTR(-EINVAL);
-
- return (struct ast_wdt *)(WDT_BASE +
- sizeof(struct ast_wdt) * wdt_number);
-}
+#endif /* CONFIG_WDT */
int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
{
@@ -57,3 +70,12 @@ int ast_wdt_reset_masked(struct ast_wdt *wdt, u32 mask)
return -EINVAL;
#endif
}
+
+struct ast_wdt *ast_get_wdt(u8 wdt_number)
+{
+ if (wdt_number > CONFIG_WDT_NUM - 1)
+ return ERR_PTR(-EINVAL);
+
+ return (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) * wdt_number);
+}
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 0d7366f3df..10f34f5efa 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -9,3 +9,16 @@ config WDT
start, restart, stop and reset (expire immediately).
What exactly happens when the timer expires is up to a particular
device/driver.
+
+config WDT_ASPEED
+ bool "Aspeed ast2400/ast2500 watchdog timer support"
+ depends on WDT
+ default y if ARCH_ASPEED
+ help
+ Select this to enable watchdog timer for Aspeed ast2500/ast2400
devices.
+ The watchdog timer is stopped when initialized. It performs reset,
either
+ full SoC reset or CPU or just some peripherals, based on the f
[U-Boot] [PATCH 10/17] aspeed: Add P-Bus clock in ast2500 clock driver
Add P-Bus Clock support to ast2500 clock driver.
This is the clock used by I2C devices.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 3 ++-
drivers/clk/aspeed/clk_ast2500.c | 11 +++
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 1cdd3b9198..319d75e05c 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -21,7 +21,8 @@
#define SCU_MPLL_NUM_MASK 0xff
#define SCU_MPLL_POST_SHIFT13
#define SCU_MPLL_POST_MASK 0x3f
-
+#define SCU_PCLK_DIV_SHIFT 23
+#define SCU_PCLK_DIV_MASK 7
#define SCU_HPLL_DENUM_SHIFT 0
#define SCU_HPLL_DENUM_MASK0x1f
#define SCU_HPLL_NUM_SHIFT 5
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 504731271c..9e4c66ea85 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -110,6 +110,17 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_mpll_rate(clkin,
readl(&priv->scu->m_pll_param));
break;
+ case BCLK_PCLK:
+ {
+ ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
+ >> SCU_PCLK_DIV_SHIFT) &
+SCU_PCLK_DIV_MASK);
+ rate = ast2500_get_hpll_rate(clkin,
+readl(&priv->scu->
+ h_pll_param));
+ rate = rate / apb_div;
+ }
+ break;
case PCLK_UART1:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
--
2.12.0.367.g23dc2f6d3c-goog
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[U-Boot] [PATCH 09/17] aspeed: Enable Pinctrl Driver in AST2500 EVB
Enable Pinctrl Driver in AST2500 Eval Board's defconfig Signed-off-by: Maxim Sloyko --- configs/evb-ast2500_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig index 74808a71ee..f8ef9b779c 100644 --- a/configs/evb-ast2500_defconfig +++ b/configs/evb-ast2500_defconfig @@ -17,3 +17,4 @@ CONFIG_SYSRESET=y CONFIG_TIMER=y CONFIG_WDT=y CONFIG_DM_RESET=y +CONFIG_PINCTRL=y -- 2.12.0.367.g23dc2f6d3c-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 04/17] aspeed: Make SCU lock/unlock functions part of SCU API
Make functions for locking and unlocking SCU part of SCU API.
Many drivers need to modify settings in SCU and thus need to unlock it
first. This change makes it possible.
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 14 ++
arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 +++
drivers/clk/aspeed/clk_ast2500.c | 18 ++
3 files changed, 31 insertions(+), 16 deletions(-)
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index fc0c01ae33..0fa3ecb9b9 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -120,6 +120,20 @@ int ast_get_clk(struct udevice **devp);
*/
void *ast_get_scu(void);
+/**
+ * ast_scu_unlock() - unlock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_unlock(struct ast2500_scu *scu);
+
+/**
+ * ast_scu_lock() - lock protected registers
+ *
+ * @scu, pointer to ast2500_scu
+ */
+void ast_scu_lock(struct ast2500_scu *scu);
+
#endif /* __ASSEMBLY__ */
#endif /* _ASM_ARCH_SCU_AST2500_H */
diff --git a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
index 079909fa64..30cfac1af0 100644
--- a/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
+++ b/arch/arm/mach-aspeed/ast2500/clk_ast2500.c
@@ -6,6 +6,7 @@
#include
#include
+#include
#include
int ast_get_clk(struct udevice **devp)
@@ -28,3 +29,17 @@ void *ast_get_scu(void)
return priv->scu;
}
+
+void ast_scu_unlock(struct ast2500_scu *scu)
+{
+ writel(SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (!readl(&scu->protection_key))
+ ;
+}
+
+void ast_scu_lock(struct ast2500_scu *scu)
+{
+ writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
+ while (readl(&scu->protection_key))
+ ;
+}
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 26a5e58221..504731271c 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -132,20 +132,6 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
return rate;
}
-static void ast2500_scu_unlock(struct ast2500_scu *scu)
-{
- writel(SCU_UNLOCK_VALUE, &scu->protection_key);
- while (!readl(&scu->protection_key))
- ;
-}
-
-static void ast2500_scu_lock(struct ast2500_scu *scu)
-{
- writel(~SCU_UNLOCK_VALUE, &scu->protection_key);
- while (readl(&scu->protection_key))
- ;
-}
-
static ulong ast2500_configure_ddr(struct ast2500_scu *scu, ulong rate)
{
ulong clkin = ast2500_get_clkin(scu);
@@ -197,9 +183,9 @@ static ulong ast2500_configure_ddr(struct ast2500_scu *scu,
ulong rate)
| (best_num << SCU_MPLL_NUM_SHIFT)
| (best_denum << SCU_MPLL_DENUM_SHIFT);
- ast2500_scu_unlock(scu);
+ ast_scu_unlock(scu);
writel(mpll_reg, &scu->m_pll_param);
- ast2500_scu_lock(scu);
+ ast_scu_lock(scu);
return ast2500_get_mpll_rate(clkin, mpll_reg);
}
--
2.12.0.367.g23dc2f6d3c-goog
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[U-Boot] [PATCH 06/17] aspeed: Device Tree configuration for Reset Driver
Add Reset Driver configuration to ast2500 SoC Device Tree and bindings
for various reset signals
Signed-off-by: Maxim Sloyko
---
arch/arm/dts/ast2500-evb.dts | 15 +++
arch/arm/dts/ast2500-u-boot.dtsi | 10 +++
include/dt-bindings/reset/ast2500-reset.h | 45 +++
3 files changed, 70 insertions(+)
create mode 100644 include/dt-bindings/reset/ast2500-reset.h
diff --git a/arch/arm/dts/ast2500-evb.dts b/arch/arm/dts/ast2500-evb.dts
index dc13952fb8..723941ac0b 100644
--- a/arch/arm/dts/ast2500-evb.dts
+++ b/arch/arm/dts/ast2500-evb.dts
@@ -21,3 +21,18 @@
&sdrammc {
clock-frequency = <4>;
};
+
+&wdt1 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt2 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+&wdt3 {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index c95a7ba835..faeeec1be4 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -1,4 +1,5 @@
#include
+#include
#include "ast2500.dtsi"
@@ -11,12 +12,21 @@
#reset-cells = <1>;
};
+ rst: reset-controller {
+ u-boot,dm-pre-reloc;
+ compatible = "aspeed,ast2500-reset";
+ aspeed,wdt = <&wdt1>;
+ #reset-cells = <1>;
+ };
+
sdrammc: sdrammc@1e6e {
u-boot,dm-pre-reloc;
compatible = "aspeed,ast2500-sdrammc";
reg = <0x1e6e 0x174
0x1e6e0200 0x1d4 >;
+ #reset-cells = <1>;
clocks = <&scu PLL_MPLL>;
+ resets = <&rst AST_RESET_SDRAM>;
};
ahb {
diff --git a/include/dt-bindings/reset/ast2500-reset.h
b/include/dt-bindings/reset/ast2500-reset.h
new file mode 100644
index 00..eb5e1db97b
--- /dev/null
+++ b/include/dt-bindings/reset/ast2500-reset.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _ABI_MACH_ASPEED_AST2500_RESET_H_
+#define _ABI_MACH_ASPEED_AST2500_RESET_H_
+
+/*
+ * The values are intentionally layed out as flags in
+ * WDT reset parameter.
+ */
+
+#define AST_RESET_SOC 0
+#define AST_RESET_CHIP 1
+#define AST_RESET_CPU (1 << 1)
+#define AST_RESET_ARM (1 << 2)
+#define AST_RESET_COPROC (1 << 3)
+#define AST_RESET_SDRAM(1 << 4)
+#define AST_RESET_AHB (1 << 5)
+#define AST_RESET_I2C (1 << 6)
+#define AST_RESET_MAC1 (1 << 7)
+#define AST_RESET_MAC2 (1 << 8)
+#define AST_RESET_GCRT (1 << 9)
+#define AST_RESET_USB20(1 << 10)
+#define AST_RESET_USB11_HOST (1 << 11)
+#define AST_RESET_USB11_HID(1 << 12)
+#define AST_RESET_VIDEO(1 << 13)
+#define AST_RESET_HAC (1 << 14)
+#define AST_RESET_LPC (1 << 15)
+#define AST_RESET_SDIO (1 << 16)
+#define AST_RESET_MIC (1 << 17)
+#define AST_RESET_CRT2D(1 << 18)
+#define AST_RESET_PWM (1 << 19)
+#define AST_RESET_PECI (1 << 20)
+#define AST_RESET_JTAG (1 << 21)
+#define AST_RESET_ADC (1 << 22)
+#define AST_RESET_GPIO (1 << 23)
+#define AST_RESET_MCTP (1 << 24)
+#define AST_RESET_XDMA (1 << 25)
+#define AST_RESET_SPI (1 << 26)
+#define AST_RESET_MISC (1 << 27)
+
+#endif /* _ABI_MACH_ASPEED_AST2500_RESET_H_ */
--
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[U-Boot] [PATCH 05/17] aspeed: Reset Driver
Add Reset Driver for ast2500 SoC. This driver uses Watchdog Timer to
perform resets and thus depends on it. The actual Watchdog device used
needs to be configured in Device Tree using "aspeed,wdt" property, which
must be WDT phandle, for example:
rst: reset-controller {
compatible = "aspeed,ast2500-reset";
aspeed,wdt = <&wdt1>;
}
Signed-off-by: Maxim Sloyko
---
arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 28 +++
drivers/reset/Kconfig | 10 +++
drivers/reset/Makefile | 1 +
drivers/reset/ast2500-reset.c | 109 +
4 files changed, 148 insertions(+)
create mode 100644 drivers/reset/ast2500-reset.c
diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
index 0fa3ecb9b9..e2556f920d 100644
--- a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
+++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
@@ -31,6 +31,34 @@
#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
+/*
+ * SYSRESET is actually more like a Power register,
+ * except that corresponding bit set to 1 means that
+ * the peripheral is off.
+ */
+#define SCU_SYSRESET_XDMA (1 << 25)
+#define SCU_SYSRESET_MCTP (1 << 24)
+#define SCU_SYSRESET_ADC (1 << 23)
+#define SCU_SYSRESET_JTAG (1 << 22)
+#define SCU_SYSRESET_MIC (1 << 18)
+#define SCU_SYSRESET_SDIO (1 << 16)
+#define SCU_SYSRESET_USB11HOST (1 << 15)
+#define SCU_SYSRESET_USBHUB(1 << 14)
+#define SCU_SYSRESET_CRT (1 << 13)
+#define SCU_SYSRESET_MAC2 (1 << 12)
+#define SCU_SYSRESET_MAC1 (1 << 11)
+#define SCU_SYSRESET_PECI (1 << 10)
+#define SCU_SYSRESET_PWM (1 << 9)
+#define SCU_SYSRESET_PCI_VGA (1 << 8)
+#define SCU_SYSRESET_2D(1 << 7)
+#define SCU_SYSRESET_VIDEO (1 << 6)
+#define SCU_SYSRESET_LPC (1 << 5)
+#define SCU_SYSRESET_HAC (1 << 4)
+#define SCU_SYSRESET_USBHID(1 << 3)
+#define SCU_SYSRESET_I2C (1 << 2)
+#define SCU_SYSRESET_AHB (1 << 1)
+#define SCU_SYSRESET_SDRAM_WDT (1 << 0)
+
#ifndef __ASSEMBLY__
struct ast2500_clk_priv {
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c42b0bcf0e..eb54189d4b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -43,4 +43,14 @@ config RESET_UNIPHIER
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
+config AST2500_RESET
+ bool "Reset controller driver for AST2500 SoCs"
+ depends on DM_RESET && WDT_ASPEED
+ default y if ASPEED_AST2500
+ help
+ Support for reset controller on AST2500 SoC. This controller uses
+ watchdog to reset different peripherals and thus only supports
+ resets that are supported by watchdog. The main limitation though
+ is that some reset signals, like I2C or MISC reset multiple devices.
+
endmenu
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 5c4305cc1d..16ad7eed5b 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -8,3 +8,4 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
+obj-$(CONFIG_AST2500_RESET) += ast2500-reset.o
diff --git a/drivers/reset/ast2500-reset.c b/drivers/reset/ast2500-reset.c
new file mode 100644
index 00..0afa4bd01a
--- /dev/null
+++ b/drivers/reset/ast2500-reset.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct ast2500_reset_priv {
+ /* WDT used to perform resets. */
+ struct udevice *wdt;
+ struct ast2500_scu *scu;
+};
+
+static int ast2500_ofdata_to_platdata(struct udevice *dev)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = uclass_get_device_by_phandle(UCLASS_WDT, dev, "aspeed,wdt",
+ &priv->wdt);
+ if (ret) {
+ debug("%s: can't find WDT for reset controller", __func__);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ast2500_reset_assert(struct reset_ctl *reset_ctl)
+{
+ struct ast2500_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+ u32 reset_mode, reset_mask;
+ bool reset_sdram;
+ int ret;
+
+ if (I
[U-Boot] [PATCH 02/17] dm: Simple Watchdog uclass
This is a simple uclass for Watchdog Timers. It has four operations:
start, restart, reset, stop. Drivers must implement start, restart and
stop operations, while implementing reset is optional: It's default
implementation expires watchdog timer in one clock tick.
Signed-off-by: Maxim Sloyko
---
drivers/watchdog/Kconfig | 11 +
drivers/watchdog/Makefile | 1 +
drivers/watchdog/wdt-uclass.c | 79 +++
include/dm/uclass-id.h| 1 +
include/wdt.h | 97 +++
5 files changed, 189 insertions(+)
create mode 100644 drivers/watchdog/wdt-uclass.c
create mode 100644 include/wdt.h
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index e69de29bb2..0d7366f3df 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -0,0 +1,11 @@
+menu "Watchdog Timer Support"
+
+config WDT
+ bool "Enable driver model for watchdog timer drivers"
+ depends on DM
+ help
+ Enable driver model for watchdog timer. At the moment the API
+ is very simple and only supports four operations:
+ start, restart, stop and reset (expire immediately).
+ What exactly happens when the timer expires is up to a particular
+ device/driver.
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index a007ae8234..1aabcb97ae 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -15,3 +15,4 @@ obj-$(CONFIG_XILINX_TB_WATCHDOG) += xilinx_tb_wdt.o
obj-$(CONFIG_BFIN_WATCHDOG) += bfin_wdt.o
obj-$(CONFIG_OMAP_WATCHDOG) += omap_wdt.o
obj-$(CONFIG_DESIGNWARE_WATCHDOG) += designware_wdt.o
+obj-$(CONFIG_WDT) += wdt-uclass.o
diff --git a/drivers/watchdog/wdt-uclass.c b/drivers/watchdog/wdt-uclass.c
new file mode 100644
index 00..98a8b529f9
--- /dev/null
+++ b/drivers/watchdog/wdt-uclass.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Implement a simple watchdog uclass. Watchdog is basically a timer that
+ * is used to detect or recover from malfunction. During normal operation
+ * the watchdog would be regularly reset to prevent it from timing out.
+ * If, due to a hardware fault or program error, the computer fails to reset
+ * the watchdog, the timer will elapse and generate a timeout signal.
+ * The timeout signal is used to initiate corrective action or actions,
+ * which typically include placing the system in a safe, known state.
+ */
+
+int wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+{
+ const struct wdt_ops *ops = device_get_ops(dev);
+
+ if (!ops->start)
+ return -ENOSYS;
+
+ return ops->start(dev, timeout, flags);
+}
+
+int wdt_stop(struct udevice *dev)
+{
+ const struct wdt_ops *ops = device_get_ops(dev);
+
+ if (!ops->stop)
+ return -ENOSYS;
+
+ return ops->stop(dev);
+}
+
+int wdt_restart(struct udevice *dev)
+{
+ const struct wdt_ops *ops = device_get_ops(dev);
+
+ if (!ops->restart)
+ return -ENOSYS;
+
+ return ops->restart(dev);
+}
+
+int wdt_reset(struct udevice *dev, ulong flags)
+{
+ const struct wdt_ops *ops;
+
+ debug("WDT Resettting: %lu\n", flags);
+ ops = device_get_ops(dev);
+ if (ops->reset) {
+ return ops->reset(dev, flags);
+ } else {
+ if (!ops->start)
+ return -ENOSYS;
+
+ ops->start(dev, 1, flags);
+ while (1)
+ ;
+ }
+
+ return 0;
+}
+
+UCLASS_DRIVER(wdt) = {
+ .id = UCLASS_WDT,
+ .name = "wdt",
+};
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index 8c92d0b030..b73a7fd436 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -83,6 +83,7 @@ enum uclass_id {
UCLASS_VIDEO, /* Video or LCD device */
UCLASS_VIDEO_BRIDGE,/* Video bridge, e.g. DisplayPort to LVDS */
UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */
+ UCLASS_WDT, /* Watchdot Timer driver */
UCLASS_COUNT,
UCLASS_INVALID = -1,
diff --git a/include/wdt.h b/include/wdt.h
new file mode 100644
index 00..1da5a962df
--- /dev/null
+++ b/include/wdt.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright 2017 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _WDT_H_
+#define _WDT_H_
+
+/*
+ * Start the timer
+ *
+ * @dev: WDT Device
+ * @timeout: Number of ticks before timer expires
+ * @flags: Driver specific flags. This might be used to specify
+ * which action needs to be executed when the timer expires
+ * @return: 0 if OK, -ve on error
+ */
+int wdt_start(struct udevice *dev, u64 timeout, ulong fla
[U-Boot] [PATCH 01/17] aspeed: Update ast2500 Device Tree
Pull in the Device Tree for ast2500 from the mainline Linux kernel
Signed-off-by: Maxim Sloyko
---
arch/arm/dts/ast2500.dtsi | 881 +-
1 file changed, 880 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi
index 97fac69d11..7e0ad3a41a 100644
--- a/arch/arm/dts/ast2500.dtsi
+++ b/arch/arm/dts/ast2500.dtsi
@@ -1,6 +1,6 @@
/*
* This device tree is copied from
- * https://raw.githubusercontent.com/torvalds/linux/02440622/arch/arm/boot/dts/
+ *
https://raw.githubusercontent.com/torvalds/linux/34ea5c9d/arch/arm/boot/dts/aspeed-g5.dtsi
*/
#include "skeleton.dtsi"
@@ -36,6 +36,22 @@
reg = <0x1e6c0080 0x80>;
};
+ mac0: ethernet@1e66 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e66 0x180>;
+ interrupts = <2>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
+ mac1: ethernet@1e68 {
+ compatible = "faraday,ftgmac100";
+ reg = <0x1e68 0x180>;
+ interrupts = <3>;
+ no-hw-checksum;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -48,6 +64,822 @@
reg = <0x1e6e2070 0x04>;
};
+ syscon: syscon@1e6e2000 {
+ compatible = "aspeed,g5-scu", "syscon",
"simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g5-pinctrl";
+ aspeed,external-nodes = <&gfx &lhc>;
+
+ pinctrl_acpi_default: acpi_default {
+ function = "ACPI";
+ groups = "ACPI";
+ };
+
+ pinctrl_adc0_default: adc0_default {
+ function = "ADC0";
+ groups = "ADC0";
+ };
+
+ pinctrl_adc1_default: adc1_default {
+ function = "ADC1";
+ groups = "ADC1";
+ };
+
+ pinctrl_adc10_default: adc10_default {
+ function = "ADC10";
+ groups = "ADC10";
+ };
+
+ pinctrl_adc11_default: adc11_default {
+ function = "ADC11";
+ groups = "ADC11";
+ };
+
+ pinctrl_adc12_default: adc12_default {
+ function = "ADC12";
+ groups = "ADC12";
+ };
+
+ pinctrl_adc13_default: adc13_default {
+ function = "ADC13";
+ groups = "ADC13";
+ };
+
+ pinctrl_adc14_default: adc14_default {
+ function = "ADC14";
+ groups = "ADC14";
+ };
+
+ pinctrl_adc15_default: adc15_default {
+ function = "ADC15";
+ groups = "ADC15";
+ };
+
+ pinctrl_adc2_default: adc2_default {
+ function = "ADC2";
+ groups = "ADC2";
+ };
+
+ pinctrl_adc3_default: adc3_default {
+
[U-Boot] [PATCH 00/17] Expand Aspeed AST2500 Support
This series expands support for Aspeed AST2500 SoC, commonly used as Board Management Controller in many servers, to the point where it can actually be useful. The main goal of this series is I2C and Network drivers, the rest are either cleanups or supporting patches. Most notable among them is addition of Watchdog Uclass, so that watchdog drivers can now use Driver Model. One notable thing that is *missing* from this series is Device Tree configuration for I2C driver. The Linux Kernel I2C driver is still under review and it may affect the details of how devices need to be configured in the Device Tree. So, I decided to wait until it will show up in Linux Kernel DT and then pull it into U-Boot. Maxim Sloyko (17): aspeed: Update ast2500 Device Tree dm: Simple Watchdog uclass aspeed: Watchdog Timer Driver aspeed: Make SCU lock/unlock functions part of SCU API aspeed: Reset Driver aspeed: Device Tree configuration for Reset Driver aspeed: Refactor AST2500 RAM Driver and Sysreset Driver aspeed: AST2500 Pinctrl Driver aspeed: Enable Pinctrl Driver in AST2500 EVB aspeed: Add P-Bus clock in ast2500 clock driver aspeed: Add I2C Driver aspeed: Enable I2C in EVB defconfig aspeed: Add support for Clocks needed by MACs aspeed: Refactor SCU to use consistent mask & shift aspeed: Cleanup ast2500-u-boot.dtsi Device Tree aspeed: Add AST2500/AST2400 compatible NIC Driver aspeed: Network Driver configuration for EVB arch/arm/dts/ast2500-evb.dts | 29 + arch/arm/dts/ast2500-u-boot.dtsi | 59 +- arch/arm/dts/ast2500.dtsi | 881 - arch/arm/include/asm/arch-aspeed/pinctrl.h | 52 ++ arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 132 +++- arch/arm/include/asm/arch-aspeed/wdt.h | 38 +- arch/arm/mach-aspeed/Kconfig | 8 +- arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 15 + arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 17 +- arch/arm/mach-aspeed/ast_wdt.c | 47 +- configs/evb-ast2500_defconfig | 13 + drivers/clk/aspeed/clk_ast2500.c | 321 +++-- drivers/i2c/Kconfig| 9 + drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 355 ++ drivers/i2c/ast_i2c.h | 132 drivers/net/Kconfig| 8 + drivers/net/Makefile | 1 + drivers/net/ast_nic.c | 584 drivers/net/ast_nic.h | 198 ++ drivers/pinctrl/Kconfig| 9 + drivers/pinctrl/Makefile | 1 + drivers/pinctrl/aspeed/Makefile| 1 + drivers/pinctrl/aspeed/pinctrl_ast2500.c | 127 drivers/reset/Kconfig | 10 + drivers/reset/Makefile | 1 + drivers/reset/ast2500-reset.c | 109 +++ drivers/sysreset/sysreset_ast.c| 24 +- drivers/watchdog/Kconfig | 24 + drivers/watchdog/Makefile | 2 + drivers/watchdog/ast_wdt.c | 125 drivers/watchdog/wdt-uclass.c | 79 +++ include/dm/uclass-id.h | 1 + include/dt-bindings/clock/ast2500-scu.h| 2 + include/dt-bindings/reset/ast2500-reset.h | 45 ++ include/wdt.h | 97 +++ 36 files changed, 3390 insertions(+), 167 deletions(-) create mode 100644 arch/arm/include/asm/arch-aspeed/pinctrl.h create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h create mode 100644 drivers/net/ast_nic.c create mode 100644 drivers/net/ast_nic.h create mode 100644 drivers/pinctrl/aspeed/Makefile create mode 100644 drivers/pinctrl/aspeed/pinctrl_ast2500.c create mode 100644 drivers/reset/ast2500-reset.c create mode 100644 drivers/watchdog/ast_wdt.c create mode 100644 drivers/watchdog/wdt-uclass.c create mode 100644 include/dt-bindings/reset/ast2500-reset.h create mode 100644 include/wdt.h -- 2.12.0.367.g23dc2f6d3c-goog ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] STM32F429 u-boot
Hi Bruno, Your email did reach the mailing list, it's just looks like, unfortunately, nobody can help you with this at the moment. Try Cc'ing or directly emailing somebody who works on U-Boot for STM32 SoCs, I definitely saw some patches recently. On Sun, Mar 5, 2017 at 11:21 PM, bruno schwander wrote: > Anyway I can ask this on the list ? My message is still awaiting moderation > or fell in the spam folder... > > > Hi all, > > > > I am bringing up u-boot on a new custom board with STM32F429 cpu. To > start, I modified the stm32f429 discovery board files by adding the proper > gpio, size and address for the external DRAM, also the dram timings and > USART gpio pins used > > I use the "bare" gcc 5.4 toolchain from ARM from > https://developer.arm.com/open-source/gnu-toolchain/gnu-rm/downloads > > > > I am able to load u-boot in flash with openocd, and I am able to debug > with a jtag adapter and gdb. I am able to step through the initial > functions of u-boot, set breakpoints and examine memory. Until I hit > strange things. > > > > I can step into arch_cpu_init () at arch/arm/mach-stm32/stm32f4/soc.c, > then into configure_clocks () at arch/arm/mach-stm32/stm32f4/clock.c . At > that point, the clocks are setup by writing a few registers, and as soon as > I leave this function, instead of returning to arch_cpu_init() I end up in > mAlloc() in dlmalloc.c . > > > > Anybody has some clue about what could be going on ? Any hint or > suggestion on how to figure this out would be welcome. > > > > Cheers, > > > > Bruno > ___ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot > -- *M*axim *S*loyko ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 06/12] aspeed/ast2500: Add Clock Driver
On Sat, Jan 14, 2017 at 9:14 AM, Simon Glass wrote:
> Hi Maxim,
>
> On 4 January 2017 at 12:46, Maxim Sloyko wrote:
> > This driver is ast2500 specific and is not compatible with earlier
>
> ast2500-specific
>
> > versions of this chip. The differences are not that large, but they are
> > in somewhat random places, so making it compatible with ast2400 is not
> > worth the effort at the moment.
> >
> > Signed-off-by: Maxim Sloyko
> > ---
> >
> > arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 108 +++
> > drivers/clk/Makefile | 2 +
> > drivers/clk/aspeed/Makefile| 7 +
> > drivers/clk/aspeed/clk_ast2500.c | 255
> +
> > 4 files changed, 372 insertions(+)
> > create mode 100644 arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > create mode 100644 drivers/clk/aspeed/Makefile
> > create mode 100644 drivers/clk/aspeed/clk_ast2500.c
> >
> > diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > new file mode 100644
> > index 00..febff9d2d3
> > --- /dev/null
> > +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2500.h
> > @@ -0,0 +1,108 @@
> > +#ifndef _ASM_ARCH_SCU_AST2500_H
> > +#define _ASM_ARCH_SCU_AST2500_H
> > +
> > +#define SCU_UNLOCK_VALUE 0x1688a8a8
> > +
> > +#define SCU_HWSTRAP_VGAMEM_MASK3
> > +#define SCU_HWSTRAP_VGAMEM_SHIFT 2
> > +#define SCU_HWSTRAP_DDR4 (1 << 24)
> > +#define SCU_HWSTRAP_CLKIN_25MHZ(1 << 23)
> > +
> > +#define SCU_MPLL_DENUM_SHIFT 0
> > +#define SCU_MPLL_DENUM_MASK0x1f
> > +#define SCU_MPLL_NUM_SHIFT 5
> > +#define SCU_MPLL_NUM_MASK 0xff
> > +#define SCU_MPLL_POST_SHIFT13
> > +#define SCU_MPLL_POST_MASK 0x3f
> > +
> > +#define SCU_HPLL_DENUM_SHIFT 0
> > +#define SCU_HPLL_DENUM_MASK0x1f
> > +#define SCU_HPLL_NUM_SHIFT 5
> > +#define SCU_HPLL_NUM_MASK 0xff
> > +#define SCU_HPLL_POST_SHIFT13
> > +#define SCU_HPLL_POST_MASK 0x3f
> > +
> > +#define SCU_MISC2_UARTCLK_SHIFT24
> > +
> > +#define SCU_MISC_UARTCLK_DIV13 (1 << 12)
> > +
> > +#ifndef __ASSEMBLY__
> > +
> > +struct ast2500_clk_priv {
> > + struct ast2500_scu *scu;
> > +};
> > +
> > +struct ast2500_scu {
> > + u32 protection_key;
> > + u32 sysreset_ctrl1;
> > + u32 clk_sel1;
> > + u32 clk_stop_ctrl1;
> > + u32 freq_counter_ctrl;
> > + u32 freq_counter_cmp;
> > + u32 intr_ctrl;
> > + u32 d2_pll_param;
> > + u32 m_pll_param;
> > + u32 h_pll_param;
> > + u32 d_pll_param;
> > + u32 misc_ctrl1;
> > + u32 pci_config[3];
> > + u32 sysreset_status;
> > + u32 vga_handshake[2];
> > + u32 mac_clk_delay;
> > + u32 misc_ctrl2;
> > + u32 vga_scratch[8];
> > + u32 hwstrap;
> > + u32 rng_ctrl;
> > + u32 rng_data;
> > + u32 rev_id;
> > + u32 pinmux_ctrl[6];
> > + u32 reserved0;
> > + u32 extrst_sel;
> > + u32 pinmux_ctrl1[4];
> > + u32 reserved1[2];
> > + u32 mac_clk_delay_100M;
> > + u32 mac_clk_delay_10M;
> > + u32 wakeup_enable;
> > + u32 wakeup_control;
> > + u32 reserved2[3];
> > + u32 sysreset_ctrl2;
> > + u32 clk_sel2;
> > + u32 clk_stop_ctrl2;
> > + u32 freerun_counter;
> > + u32 freerun_counter_ext;
> > + u32 clk_duty_meas_ctrl;
> > + u32 clk_duty_meas_res;
> > + u32 reserved3[4];
> > + /* The next registers are not key protected */
>
> key-protected
>
Fixed.
>
> > + struct ast2500_cpu2 {
> > + u32 ctrl;
> > + u32 base_addr[9];
> > + u32 cache_ctrl;
> > + } cpu2;
> > + u32 reserved4;
> > + u32 d_pll_ext_param[3];
> > + u32 d2_pll_ext_param[3];
> > + u32 mh_pll_ext_param;
> > + u32 reserved5;
> > + u32 chip_id[2];
> > + u32 reserved6[2];
> > + u32 uart_clk_ctrl;
> > + u32 reserved7[7];
> > + u32 pcie_config;
> > + u32 mmio_decode;
>
[U-Boot] [PATCH v3 0/4] arm: aspeed: Basic support for Aspeed AST2500 part and eval board
This series adds minimal support for AST2500 part and eval board, enough to boot EVB into prompt. It contains WDT, Timer, Sysreset, Clock (very basic) and SDRAM MC drivers, all written from scratch, using AST2500 datasheet. Aspeed's SDK was used only for reference. Given very limited documentation provided by Aspeed, some parts of SDRAM init sequence were basically rewritten to do the same thing that is done in Aspeed SDK, without real understanding of what is going on. The file layout closely follows the example of rk3288 chip and firefly-rk3288 board. Changes in v3: - Added SYS_TEXT_BASE as Kconfig option - Removed CONFIG_SYS_TEXT_BASE in favor of Kconfig option - In aspeed-common.h changed some options from define CONFIG_FOO 1 to define CONFIG_FOO - In evb_ast2500.h fixed some options to define CONFIG_FOO instead of define CONFIG_FOO 1 Changes in v2: - Moved number of WDTs to a Kconfig option Changes in v1: - Merged together the patches related to aspeed common drivers and configuration - Fixed timer driver name (was sandbox_timer) - Removed yet nonexistent files from mach-aspeed/Makefile - Merge together all patches related to ast2500 specific drivers - Add Copyright statement to all c/h files - Use DT include from Linux Kernel, Add U-Boot specific modifications in ast2500-u-boot.dtsi - Merge together all patches related to ast2500 boards common functions/configs - Add copyright statement to ast2500-board.c - Merge together patches related to ast2500 eval board configuration - Add Copyright statement to evb_ast2500.c - Use ast2500-u-boot.dtsi instead of ast2500.dtsi, which is now Linux Kernel DT Include Maxim Sloyko (4): aspeed: Add drivers common to all Aspeed SoCs aspeed: Add basic ast2500 specific drivers and configuration aspeed: Board init functions and common configs for ast2500 based boards aspeed: Support for ast2500 Eval Board arch/arm/Kconfig | 7 + arch/arm/Makefile| 1 + arch/arm/dts/Makefile| 2 + arch/arm/dts/ast2500-evb.dts | 23 ++ arch/arm/dts/ast2500-u-boot.dtsi | 53 +++ arch/arm/dts/ast2500.dtsi| 174 + arch/arm/include/asm/arch-aspeed/scu_ast2500.h | 113 ++ arch/arm/include/asm/arch-aspeed/sdram_ast2500.h | 138 +++ arch/arm/include/asm/arch-aspeed/timer.h | 54 +++ arch/arm/include/asm/arch-aspeed/wdt.h | 89 + arch/arm/mach-aspeed/Kconfig | 27 ++ arch/arm/mach-aspeed/Makefile| 8 + arch/arm/mach-aspeed/ast2500-board.c | 78 arch/arm/mach-aspeed/ast2500/Kconfig | 13 + arch/arm/mach-aspeed/ast2500/Makefile| 1 + arch/arm/mach-aspeed/ast2500/clk_ast2500.c | 30 ++ arch/arm/mach-aspeed/ast2500/sdram_ast2500.c | 443 +++ arch/arm/mach-aspeed/ast_wdt.c | 37 ++ board/aspeed/evb_ast2500/Kconfig | 12 + board/aspeed/evb_ast2500/Makefile| 1 + board/aspeed/evb_ast2500/evb_ast2500.c | 6 + configs/evb-ast2500_defconfig| 21 ++ drivers/clk/Makefile | 2 + drivers/clk/aspeed/Makefile | 7 + drivers/clk/aspeed/clk_ast2500.c | 255 + drivers/sysreset/Makefile| 1 + drivers/sysreset/sysreset_ast.c | 55 +++ drivers/timer/Kconfig| 7 + drivers/timer/Makefile | 1 + drivers/timer/ast_timer.c| 96 + include/configs/aspeed-common.h | 82 + include/configs/evb_ast2500.h| 30 ++ include/dt-bindings/clock/ast2500-scu.h | 29 ++ 33 files changed, 1896 insertions(+) create mode 100644 arch/arm/dts/ast2500-evb.dts create mode 100644 arch/arm/dts/ast2500-u-boot.dtsi create mode 100644 arch/arm/dts/ast2500.dtsi create mode 100644 arch/arm/include/asm/arch-aspeed/scu_ast2500.h create mode 100644 arch/arm/include/asm/arch-aspeed/sdram_ast2500.h create mode 100644 arch/arm/include/asm/arch-aspeed/timer.h create mode 100644 arch/arm/include/asm/arch-aspeed/wdt.h create mode 100644 arch/arm/mach-aspeed/Kconfig create mode 100644 arch/arm/mach-aspeed/Makefile create mode 100644 arch/arm/mach-aspeed/ast2500-board.c create mode 100644 arch/arm/mach-aspeed/ast2500/Kconfig create mode 100644 arch/arm/mach-aspeed/ast2500/Makefile create mode 100644 arch/arm/mach-aspeed/ast2500/clk_ast2500.c create mode 100644 arch/arm/mach-aspeed/ast2500/sdram_ast2500.c create mode 100644 arch/arm/mach-aspeed/ast_wdt.c create mode 100644 board/aspeed/evb_ast2500/Kconfig create mode 100644 board/aspeed/evb_ast2500/Makefile create mode 100644 board/aspeed/evb_ast2500/evb_ast2500.c create mode 100644 config
Re: [U-Boot] [PATCH v2 3/4] aspeed: Board init functions and common configs for ast2500 based boards
On Tue, Jan 10, 2017 at 7:20 PM, Tom Rini wrote:
> On Mon, Jan 09, 2017 at 05:50:39PM -0800, Maxim Sloyko wrote:
>
> [snip]
>> +#define CONFIG_CMDLINE_EDITING 1
>
> In general, we just do '#define CONFIG_FOO'.
Fixed several defines in aspeed-common.h and evb_ast2500.h
>
>> +#define CONFIG_SYS_TEXT_BASE 0x
>
> This one at least is in Kconfig now. Please check for anything else
> that has also been migrated, thanks!
This seems to be the only one. Checked by grepping all Kconfigs for
all options in aspeed-common.h, basically by running
for v in $(cat include/configs/aspeed-common.h | awk '/^#define
CONFIG/ { print gensub("CONFIG_", "", 1, $2) }'); do find . -name
Kconfig -exec grep -Hn $v {} \; ; done
The fix still ended up being spread around three patches from this
series, so I'm copying Revewed-by to only one of those that was left
untouched.
>
> --
> Tom
--
Maxim Sloyko
___
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[U-Boot] [PATCH v2 1/4] aspeed: Add drivers common to all Aspeed SoCs
Add support for Watchdog Timer, which is compatible with AST2400 and
AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver
does not follow the driver model. It also uses fixed clock, so no clock
driver is needed.
Add support for timer for Aspeed ast2400/ast2500 devices.
The driver actually controls several devices, but because all devices
share the same Control Register, it is somewhat difficult to completely
decouple them. Since only one timer is needed at the moment, this should
be OK. The timer uses fixed clock, so does not rely on a clock driver.
Add sysreset driver, which uses watchdog timer to do resets and particular
watchdog device to use is hardcoded (0)
---
Changes in v2:
- Moved number of WDTs to a Kconfig option
Changes in v1:
- Merged together the patches related to aspeed common drivers and
configuration
- Fixed timer driver name (was sandbox_timer)
- Removed yet nonexistent files from mach-aspeed/Makefile
Signed-off-by: Maxim Sloyko
---
arch/arm/Kconfig | 7 +++
arch/arm/Makefile| 1 +
arch/arm/include/asm/arch-aspeed/timer.h | 54 ++
arch/arm/include/asm/arch-aspeed/wdt.h | 89 +
arch/arm/mach-aspeed/Kconfig | 22
arch/arm/mach-aspeed/Makefile| 7 +++
arch/arm/mach-aspeed/ast_wdt.c | 37
drivers/sysreset/Makefile| 1 +
drivers/sysreset/sysreset_ast.c | 55 ++
drivers/timer/Kconfig| 7 +++
drivers/timer/Makefile | 1 +
drivers/timer/ast_timer.c| 96
12 files changed, 377 insertions(+)
create mode 100644 arch/arm/include/asm/arch-aspeed/timer.h
create mode 100644 arch/arm/include/asm/arch-aspeed/wdt.h
create mode 100644 arch/arm/mach-aspeed/Kconfig
create mode 100644 arch/arm/mach-aspeed/Makefile
create mode 100644 arch/arm/mach-aspeed/ast_wdt.c
create mode 100644 drivers/sysreset/sysreset_ast.c
create mode 100644 drivers/timer/ast_timer.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 714dd8b514..135c544335 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -882,8 +882,15 @@ config TARGET_THUNDERX_88XX
select OF_CONTROL
select SYS_CACHE_SHIFT_7
+config ARCH_ASPEED
+ bool "Support Aspeed SoCs"
+ select OF_CONTROL
+ select DM
+
endchoice
+source "arch/arm/mach-aspeed/Kconfig"
+
source "arch/arm/mach-at91/Kconfig"
source "arch/arm/mach-bcm283x/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 236debb452..cc73e1038e 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -50,6 +50,7 @@ PLATFORM_CPPFLAGS += $(arch-y) $(tune-y)
# Machine directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
+machine-$(CONFIG_ARCH_ASPEED) += aspeed
machine-$(CONFIG_ARCH_AT91)+= at91
machine-$(CONFIG_ARCH_BCM283X) += bcm283x
machine-$(CONFIG_ARCH_DAVINCI) += davinci
diff --git a/arch/arm/include/asm/arch-aspeed/timer.h
b/arch/arm/include/asm/arch-aspeed/timer.h
new file mode 100644
index 00..87c5b354ec
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/timer.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#ifndef _ASM_ARCH_TIMER_H
+#define _ASM_ARCH_TIMER_H
+
+/* Each timer has 4 control bits in ctrl1 register.
+ * Timer1 uses bits 0:3, Timer2 uses bits 4:7 and so on,
+ * such that timer X uses bits (4 * X - 4):(4 * X - 1)
+ * If the timer does not support PWM, bit 4 is reserved.
+ */
+#define AST_TMC_EN (1 << 0)
+#define AST_TMC_1MHZ (1 << 1)
+#define AST_TMC_OVFINTR(1 << 2)
+#define AST_TMC_PWM(1 << 3)
+
+/* Timers are counted from 1 in the datasheet. */
+#define AST_TMC_CTRL1_SHIFT(n) (4 * ((n) - 1))
+
+#define AST_TMC_RATE (1000*1000)
+
+#ifndef __ASSEMBLY__
+
+/*
+ * All timers share control registers, which makes it harder to make them
+ * separate devices. Since only one timer is needed at the moment, making
+ * it this just one device.
+ */
+
+struct ast_timer_counter {
+ u32 status;
+ u32 reload_val;
+ u32 match1;
+ u32 match2;
+};
+
+struct ast_timer {
+ struct ast_timer_counter timers1[3];
+ u32 ctrl1;
+ u32 ctrl2;
+#ifdef CONFIG_ASPEED_AST2500
+ u32 ctrl3;
+ u32 ctrl1_clr;
+#else
+ u32 reserved[2];
+#endif
+ struct ast_timer_counter timers2[5];
+};
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_ARCH_TIMER_H */
diff --git a/arch/arm/include/asm/arch-aspeed/wdt.h
b/arch/arm/include/asm/arch-aspeed/wdt.h
new file mode 100644
index 00..32774b1a70
--- /dev/null
+++ b/arch/arm/include/asm/arch-aspeed/wdt.h
@@ -0,0 +1,89 @@
+/*
+ * (C) Copyrig
[U-Boot] [PATCH v2 3/4] aspeed: Board init functions and common configs for ast2500 based boards
---
Changes in v2: None
Changes in v1:
- Merge together all patches related to ast2500 boards common
functions/configs
- Add copyright statement to ast2500-board.c
Signed-off-by: Maxim Sloyko
---
arch/arm/mach-aspeed/Makefile| 2 +-
arch/arm/mach-aspeed/ast2500-board.c | 78 +
include/configs/aspeed-common.h | 84
3 files changed, 163 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/mach-aspeed/ast2500-board.c
create mode 100644 include/configs/aspeed-common.h
diff --git a/arch/arm/mach-aspeed/Makefile b/arch/arm/mach-aspeed/Makefile
index 1f7af71b03..9d29ff7f6f 100644
--- a/arch/arm/mach-aspeed/Makefile
+++ b/arch/arm/mach-aspeed/Makefile
@@ -5,4 +5,4 @@
#
obj-$(CONFIG_ARCH_ASPEED) += ast_wdt.o
-obj-$(CONFIG_ASPEED_AST2500) += ast2500/
+obj-$(CONFIG_ASPEED_AST2500) += ast2500/ ast2500-board.o
diff --git a/arch/arm/mach-aspeed/ast2500-board.c
b/arch/arm/mach-aspeed/ast2500-board.c
new file mode 100644
index 00..6ff74f0a1f
--- /dev/null
+++ b/arch/arm/mach-aspeed/ast2500-board.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2016 Google, Inc
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+/* Second Watchdog Timer by default is configured
+ * to trigger secondary boot source.
+ */
+#define AST_2ND_BOOT_WDT (1)
+
+/* Third Watchdog Timer by default is configured
+ * to toggle Flash address mode switch before reset.
+ */
+#define AST_FLASH_ADDR_DETECT_WDT (2)
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void lowlevel_init(void)
+{
+ /*
+* These two watchdogs need to be stopped as soon as possible,
+* otherwise the board might hang. By default they are set to
+* a very short timeout and even simple debug write to serial
+* console early in the init process might cause them to fire.
+*/
+ struct ast_wdt *flash_addr_wdt =
+ (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) *
+ AST_FLASH_ADDR_DETECT_WDT);
+
+ clrbits_le32(&flash_addr_wdt->ctrl, WDT_CTRL_EN);
+
+#ifndef CONFIG_FIRMWARE_2ND_BOOT
+ struct ast_wdt *sec_boot_wdt =
+ (struct ast_wdt *)(WDT_BASE +
+ sizeof(struct ast_wdt) *
+ AST_2ND_BOOT_WDT);
+
+ clrbits_le32(&sec_boot_wdt->ctrl, WDT_CTRL_EN);
+#endif
+}
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+int dram_init(void)
+{
+ struct udevice *dev;
+ int ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+ if (ret) {
+ debug("DRAM FAIL1\r\n");
+ return ret;
+ }
+
+ struct ram_info ram;
+ ret = ram_get_info(dev, &ram);
+ if (ret) {
+ debug("DRAM FAIL2\r\n");
+ return ret;
+ }
+
+
+ gd->ram_size = ram.size;
+ return 0;
+}
diff --git a/include/configs/aspeed-common.h b/include/configs/aspeed-common.h
new file mode 100644
index 00..c125e39e3f
--- /dev/null
+++ b/include/configs/aspeed-common.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (C) 2012-2020 ASPEED Technology Inc.
+ * Ryan Chen
+ *
+ * Copyright 2016 IBM Corporation
+ * (C) Copyright 2016 Google, Inc
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __AST_COMMON_CONFIG_H
+#define __AST_COMMON_CONFIG_H
+
+/* Misc CPU related */
+#define CONFIG_CMDLINE_TAG
+#define CONFIG_SETUP_MEMORY_TAGS
+#define CONFIG_INITRD_TAG
+
+#define CONFIG_CMDLINE_EDITING 1
+
+/* Enable cache controller */
+#define CONFIG_SYS_DCACHE_OFF 1
+
+#ifdef CONFIG_PRE_CON_BUF_SZ
+#define PRE_CON_RAM_SZ CONFIG_PRE_CON_BUF_SZ
+#else
+#define PRE_CON_RAM_SZ 0
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE 0x8000
+#define CONFIG_SYS_INIT_RAM_ADDR (0x1e72 + PRE_CON_RAM_SZ)
+#define CONFIG_SYS_INIT_RAM_SIZE (36*1024 - PRE_CON_RAM_SZ)
+#define SYS_INIT_RAM_END (CONFIG_SYS_INIT_RAM_ADDR \
++ CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_ADDR(SYS_INIT_RAM_END \
+- GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \
+- GENERATED_GBL_DATA_SIZE)
+
+#define CONFIG_NR_DRAM_BANKS 1
+
+#define CONFIG_SYS_TEXT_BASE 0x
+
+#define CONFIG_SYS_MALLOC_LEN (32 << 20)
+
+/*
+ * NS16550 Configuration
+ */
+#define CONFIG_BAUDRATE115200
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_SUBNETMASK
+
+/*
+ * Miscellaneo
Re: [U-Boot] [PATCH 05/12] aspeed/ast2500: Device Tree and bindings for some of the clocks
On Wed, Jan 4, 2017 at 7:26 PM, Tom Rini wrote: > On Wed, Jan 04, 2017 at 05:18:42PM -0800, Maxim Sloyko wrote: >> On Wed, Jan 4, 2017 at 12:58 PM, Tom Rini wrote: >> > On Wed, Jan 04, 2017 at 11:46:49AM -0800, Maxim Sloyko wrote: >> > >> >> Signed-off-by: Maxim Sloyko >> >> --- >> >> >> >> arch/arm/dts/ast2500.dtsi | 423 >> >> >> >> include/dt-bindings/clock/ast2500-scu.h | 29 +++ >> >> 2 files changed, 452 insertions(+) >> >> create mode 100644 arch/arm/dts/ast2500.dtsi >> >> create mode 100644 include/dt-bindings/clock/ast2500-scu.h >> >> >> >> diff --git a/arch/arm/dts/ast2500.dtsi b/arch/arm/dts/ast2500.dtsi >> >> new file mode 100644 >> >> index 00..1a2a3f7ee3 >> >> --- /dev/null >> >> +++ b/arch/arm/dts/ast2500.dtsi >> >> @@ -0,0 +1,423 @@ >> >> +/* This device tree is copied from >> >> + * >> >> https://github.com/openbmc/linux/blob/c5682cb/arch/arm/boot/dts/aspeed-g5.dtsi >> > >> > Is this also found in the Linux kernel or not yet? Thanks! >> >> Yes, this is also in in main Linux kernel now, as I've found out, but >> actually there is a number of differences, most notably there is no >> pin configuration in this device tree, because there is no pinctrl >> driver. Actually, I take that back, I was looking at the wrong linux Linux kernel tree still... Only basic version of device tree has made it to mainline kernel, but it's enough at the moment, so I used that instead. >> >> Should I remove this reference or modify it? > > Ideally, we will take the kernel dts files and then add what we need on > top of that in one of CONFIG_SYS_CPU/CONFIG_SYS_SOC/CONFIG_SYS_VENDOR > -u-boot.dtsi files, see for example arch/arm/dts/sunxi-u-boot.dtsi or > arch/arm/dts/tegra124-nyan-big-u-boot.dtsi OK, so I took the device tree from the Linux kernel, (ast2500.dtsi), added modifications in ast2500-u-boot.dtsi and now include ast2500-u-boot.dtsi in ast2500-evb.dts. Let me know if I misunderstood you. Thanks! > > -- > Tom -- Maxim Sloyko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 00/12] arm: aspeed: Basic support for Aspeed AST2500 part and eval board
On Wed, Jan 4, 2017 at 12:26 PM, Tom Rini wrote: > On Wed, Jan 04, 2017 at 11:46:44AM -0800, Maxim Sloyko wrote: > >> This series adds minimal support for AST2500 part and eval board, >> enough to boot EVB into prompt. It contains WDT, Timer, Sysreset, >> Clock (very basic) and SDRAM MC drivers, all written from scratch, >> using AST2500 datasheet. Aspeed's SDK was used only for reference. >> Given very limited documentation provided by Aspeed, some parts of SDRAM >> init sequence were basically rewritten to do the same thing that is done >> in Aspeed SDK, without real understanding of what is going on. >> >> The file layout closely follows the example of rk3288 chip and firefly-rk3288 >> board. >> >> For the first round of reviews I'm mostly looking for a nod to add >> mach-aspeed and arch-aspeed directories, as well as for feedback >> on naming, file locations and overall approach. > > Thanks for doing this. I'll review the individual patches for other > changes but in general: > >> Maxim Sloyko (12): >> aspeed: Add mach-aspeed directory and basic Kconfig >> aspeed: Add support for Watchdot Timer >> aspeed: Add Timer Support >> aspeed: Add sysreset driver >> aspeed/ast2500: Device Tree and bindings for some of the clocks >> aspeed/ast2500: Add Clock Driver >> aspeed/ast2500: Helper function to get access to SCU >> aspeed/ast2500: Add SDRAM MC driver >> aspeed/ast2500: Common board init functions for ast2500 based boards > > This can really be one patch. Or maybe 2-3 (wdt, timer, sysreset, > everything else). The stuff that one could lump together and say "this > must be here for the SoC to build and have minimal functionality" is one > patch. The changes that adds useful functionality is a patch each. Well, the review would certainly be easier for me, if this was just one patch, so I would gladly merge them. > >> aspeed: Common configuration parameters for aspeed boards >> aspeed: Device Tree for ast2500 Eval Board >> aspeed: Configuration for ast2500 eval board > > Adding the ast2500 EVB would be another single patch. Sounds good to me. > > -- > Tom -- Maxim Sloyko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Problem: the build does not recurse into subdirectory
On Sat, Dec 17, 2016 at 2:46 PM, Simon Glass wrote: > Hi Maxim, > > On 16 December 2016 at 17:18, Maxim Sloyko wrote: >> Greetings, >> >> I'm working on adding new platform to U-Boot and right now I'm trying >> to clean up the directory structure, but running into a problem of >> Make not recursing into a subdirectory that I've created. >> >> in my arch/arm/mach-aspeed/Makefile I have this: >> >> obj-$(CONFIG_ASPEED_AST2500) += ast2500/ ast2500-board.o >> >> and then in arch/arm/mach-aspeed/ast2500/Makefile: >> >> $obj-y += clk_ast2500.o sdram_ast2500.o > > What is the $ for? I don't think you want that. Oh my, I can't believe I was that stupid :) Thanks for the help, that's what the problem was. > >> >> When I try to build everything, I get this error: >> >> arm-linux-gnueabi-ld.bfd: cannot find >> arch/arm/mach-aspeed/ast2500/built-in.o: No such file or directory >> >> If instead in arch/arm/mach-aspeed/Makefile I specify: >> >> obj-$(CONFIG_ASPEED_AST2500) += ast2500/clk_ast2500.o >> ast2500/sdram_ast2500.o ast2500-board.o >> >> (That is, I just added binaries from the lower level dir explicitly) >> >> everything builds fine, which means that CONFIG_ASPEED_AST2500 is defined. >> >> Any ideas what might be the problem here? >> >> If you need more details, you can see the code here >> https://github.com/maksymko/u-boot/tree/aspeed_ast2500_evb/arch/arm/mach-aspeed >> >> Many thanks for the help! >> >> -- >> Maxim Sloyko > > Regards, > Simon -- Maxim Sloyko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] U-Boot memory allocation problems with ast2500
Hi all, First, disclaimer: this is the first time I'm doing something with U-Boot or the part (ast2500), so any claim I make below can be false or just plain nonsense. I'm working on expanding support of Aspeed ast2500 part in U-Boot. I ran into some problems, when I tried to use Linux Kernel device tree for this part in U-Boot. Looking at diagnostic messages ( http://pastebin.ca/3713876) I figured out that the problem is that U-Boot continues to use malloc_simple, even after it has been relocated to RAM. As a result, it fails to allocate 130k needed for environment, because it is larger than the configured size of a memory chunk for simple malloc. I suspect that this has something to do with memory configuration, do you know what I may be missing? Also, it looks like lowlevel_init has been called twice, i.e. again after relocation -- is this expected? This might be what is causing the problem, because lowlevel_init does a lot of RAM related configuration, but I don't know what to do about it. There is some very basic support for this part in U-Boot, provided by manufacturer, but it is basically a single platform.S assembly file that does everything, like RAM configuration and some other peripherals support in lowlevel_init procedure. So, if I want to add proper support for this part, i.e. with device tree and all, is there a way to make this a gradual process? I mean, is it possible to leave existing RAM initialization procedure in lowlevel_init and just add new drivers for something I'm interested in or is this all or nothing kind of thing? Thank you. -- *M*axim *S*loyko ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
