Re: [U-Boot] mx6qp sabreauto hangs after saveenv/reset

[Nitin Garg]

On 10/09/2015 09:59 AM, Fabio Estevam wrote:
> Hi Peng,
> 
> On Thu, Oct 8, 2015 at 11:12 PM, Peng Fan  wrote:
> 
>> Whether plugging nand chip into the socket or without nand chip, the board 
>> reboot
>> well in my side. I did not do stress test, only do a few test, and each time
>> 'reset', it can boot fine.
> 
> Thanks for testing it.
> 
> Maybe it is an issue with the board I have. I should receive a new one
> next week and will test it.
> 
> By the way, does your board work standalone (without the base board)?
> Mine only works when it is connected to the base board and in this
> case I need to supply 12V.
> 
> Thanks
> 
There is a jumper (J2) to change it to standalone. 
Mine works without baseboard and 5V supply.

-Nitin
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Re: [U-Boot] [PATCH 02/11] imx: power: add pmic pfuze300 support

[Nitin Garg]

On 07/15/2015 05:49 PM, Adrian Alonso wrote:
 * Add pmic pfuze300 support for imx7 and iMX6 DL/SL/SX SoC's
 * Implement power_pfuze300_init to be used in power_init_board
   callback function.
 
 Signed-off-by: Adrian Alonso aalo...@freescale.com
 Signed-off-by: Peng Fan peng@freescale.com
 ---
  drivers/power/pmic/Makefile|  1 +
  drivers/power/pmic/pmic_pfuze300.c | 32 
  include/power/pfuze300_pmic.h  | 78 
 ++
  3 files changed, 111 insertions(+)
  create mode 100644 drivers/power/pmic/pmic_pfuze300.c
  create mode 100644 include/power/pfuze300_pmic.h
 
 diff --git a/drivers/power/pmic/Makefile b/drivers/power/pmic/Makefile
 index ae86f04..43040ff 100644
 --- a/drivers/power/pmic/Makefile
 +++ b/drivers/power/pmic/Makefile
 @@ -14,6 +14,7 @@ obj-$(CONFIG_POWER_MAX8997) += pmic_max8997.o
  obj-$(CONFIG_POWER_MUIC_MAX8997) += muic_max8997.o
  obj-$(CONFIG_POWER_MAX77686) += pmic_max77686.o
  obj-$(CONFIG_POWER_PFUZE100) += pmic_pfuze100.o
 +obj-$(CONFIG_POWER_PFUZE300) += pmic_pfuze300.o
  obj-$(CONFIG_POWER_TPS65090_I2C) += pmic_tps65090.o
  obj-$(CONFIG_POWER_TPS65090_EC) += pmic_tps65090_ec.o
  obj-$(CONFIG_POWER_TPS65217) += pmic_tps65217.o
 diff --git a/drivers/power/pmic/pmic_pfuze300.c 
 b/drivers/power/pmic/pmic_pfuze300.c
 new file mode 100644
 index 000..4304ddd
 --- /dev/null
 +++ b/drivers/power/pmic/pmic_pfuze300.c
 @@ -0,0 +1,32 @@
 +/*
 + * Copyright (C) 2015 Freescale Semiconductor, Inc.
 + * Peng Fan peng@freescale.com
 + *
 + * SPDX-License-Identifier:  GPL-2.0+
 + */
 +
 +#include common.h
 +#include errno.h
 +#include i2c.h
 +#include power/pmic.h
 +#include power/pfuze300_pmic.h
 +
 +int power_pfuze300_init(unsigned char bus)
 +{
 + static const char name[] = PFUZE300;
 + struct pmic *p = pmic_alloc();
 +
 + if (!p) {
 + printf(%s: POWER allocation error!\n, __func__);
 + return -ENOMEM;
 + }
 +
 + p-name = name;
 + p-interface = PMIC_I2C;
 + p-number_of_regs = PMIC_NUM_OF_REGS;
 + p-hw.i2c.addr = CONFIG_POWER_PFUZE300_I2C_ADDR;
 + p-hw.i2c.tx_num = 1;
 + p-bus = bus;
 +
 + return 0;
 +}
 diff --git a/include/power/pfuze300_pmic.h b/include/power/pfuze300_pmic.h
 new file mode 100644
 index 000..c7ec5ce
 --- /dev/null
 +++ b/include/power/pfuze300_pmic.h
 @@ -0,0 +1,78 @@
 +/*
 + *  Copyright (C) 2015 Freescale Semiconductor, Inc
 + *  Peng Fan peng@freescale.com
 + *
 + * SPDX-License-Identifier: GPL-2.0+
 + */
 +#ifndef __PFUZE300_PMIC_H_
 +#define __PFUZE300_PMIC_H_
 +
 +/* PFUZE300 registers */
 +enum {
 + PFUZE300_DEVICEID   = 0x00,
 +
 + PFUZE300_REVID  = 0x03,
 + PFUZE300_FABID  = 0x04,
 + PFUZE300_INTSTAT0   = 0x05,
 + PFUZE300_INTMASK0   = 0x06,
 + PFUZE300_INTSENSE0  = 0x07,
 + PFUZE300_INTSTAT1   = 0x08,
 + PFUZE300_INTMASK1   = 0x09,
 + PFUZE300_INTSENSE1  = 0x0A,
 +
 + PFUZE300_INTSTAT3   = 0x0E,
 + PFUZE300_INTMASK3   = 0x0F,
 + PFUZE300_INTSENSE3  = 0x10,
 + PFUZE300_INTSTAT4   = 0x11,
 + PFUZE300_INTMASK4   = 0x12,
 + PFUZE300_INTSENSE4  = 0x13,
 +
 + PFUZE300_COINCTL= 0x1A,
 + PFUZE300_PWRCTL = 0x1B,
 + PFUZE300_MEMA   = 0x1C,
 + PFUZE300_MEMB   = 0x1D,
 + PFUZE300_MEMC   = 0x1E,
 + PFUZE300_MEMD   = 0x1F,
 +
 + PFUZE300_SW1AVOLT   = 0x20,
 + PFUZE300_SW1ASTBY   = 0x21,
 + PFUZE300_SW1AOFF= 0x22,
 + PFUZE300_SW1AMODE   = 0x23,
 + PFUZE300_SW1ACONF   = 0x24,
 +
 + PFUZE300_SW1BVOLT   = 0x2E,
 + PFUZE300_SW1BSTBY   = 0x2F,
 + PFUZE300_SW1BOFF= 0x30,
 + PFUZE300_SW1BMODE   = 0x31,
 + PFUZE300_SW1BCONF   = 0x32,
 +
 + PFUZE300_SW2VOLT= 0x35,
 + PFUZE300_SW2STBY= 0x36,
 + PFUZE300_SW2OFF = 0x37,
 + PFUZE300_SW2MODE= 0x38,
 + PFUZE300_SW2CONF= 0x39,
 +
 + PFUZE300_SW3VOLT= 0x3C,
 + PFUZE300_SW3STBY= 0x3D,
 + PFUZE300_SW3OFF = 0x3E,
 + PFUZE300_SW3MODE= 0x3F,
 + PFUZE300_SW3CONF= 0x40,
 +
 + PFUZE300_SWBSTCTL   = 0x66,
 +
 + PFUZE300_LDOGCTL= 0x69,
 + PFUZE300_VREFDDRCTL = 0x6A,
 + PFUZE300_VSNVSCTL   = 0x6B,
 + PFUZE300_VLDO1CTL   = 0x6C,
 + PFUZE300_VLDO2CTL   = 0x6D,
 + PFUZE300_VCC_SDCTL  = 0x6E,
 + PFUZE300_V33CTL = 0x6F,
 + PFUZE300_VLDO3CTL   = 0x70,
 + PFUZE300_VLD4CTL= 0x71,
 +
 + PMIC_NUM_OF_REGS= 0x7F,
 +};
 +
 +int power_pfuze300_init(unsigned char bus);
 +
 +#endif
 

I think the PMIC name is pfuze3000 not pfuse300.

Regards,
Nitin
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Re: [U-Boot] [PATCH] imx: imximage: add new CHECK/CLR BIT command

[Nitin Garg]

On 06/30/2015 03:02 AM, Peng Fan wrote:
 Hi Stefano,
 
 On Sun, Jun 28, 2015 at 01:00:07PM +0200, Stefano Babic wrote:
 Hi Peng,

 On 14/06/2015 11:38, Peng Fan wrote:
 Since rom code supports the following commands, add new commands support in
 imximage.


 It is better to explain here which i.MX are supporting this ROM (i.MX6
 and i.MX7).
 
 Ok. Will fix this.
 
Just to make sure; i.MX6 and i.MX7 support these commands.



 1. CHECK_BITS_SET 4 [address] [mask bit]
means:
while ((*address  mask) != mask);

 2. CHECK_BITS_CLR 4 [address] [mask bit]
means:
while ((*address  ~mask) != 0);

 2. CLR_BIT 4 [address] [mask bit]
means:
*address = *address  ~mask;

 I understand that the command to be added is CHECK_DATA_COMMAND, as
 reported by manual. The TAG for the command is the same (0xCF), that
 means we have a single command with different parameters.
 It is better to follow the same approach in the code, because it is easy
 to find the relatd documentation in manual. In this patch, it looks like
 we have different commands, but this is not true: there is one command
 with different parameters.
 
 Yeah, you are right. CHECK_BITS_SET/CLR corresponds to CHECK_DATA_COMMAND.
 CLR_BIT corresponds to WRITE_DATA_COMMAND, with mask=1, set=0.
 
 The reason to add different commands but not one CHECK_DATA_COMMAND is that
 compatible with current implementation.
 Current DCD supports DATA 4 addr value. If want to use one 
 CHECK_DATA_COMMAND
 to cover CHECK_BITS_SET/CLR, we need another entry, then commands like this:
 CHECK_DATA 4 addr mask [SET or CLR], which will make code more complex. So,
 I choose to make CHECK_BITS_SET/CLR different commands, but not one CHECK_DATA
 command.
 
 Since 4 is not used for V2, how about CHECK_DATA SET addr mask and
 CHECK_DATA CLR addr mask?
 


 dcd_v2_t is redefined, because there may not be only one write data command,
 there may be many different commands like CHECK_BITS_SET, CHECK_BITS_CLR and
 CLR_BIT.

 I disagree or maybe this is related to i.MX7, where I could not check
 the documentation. Please explain here: I see only one command
 (CHECK_DATA_COMMAND, Chapter 8.7.2.2 in i.MX6Q).
 
 i.MX7 needs CHECK_DATA_COMMAND to wait some bits set, because CHECK_BITS_SET
 is implemented, so I call it a command:)
 Yeah, there is only one CHECK_DATA_COMMAND. I'll refine this piece commit msg.
 


 dcd_len is still leaved there, since changing it needs changes for dcd v1.
 For v2, we check whether dcd size is larger than MAX_DCD_SIZE_V2, but not
 dcd_len.

 It is just a bit confusing, and these are details in implementation -
 they are not related to the commit where you explain the new feature.
 Move these comments inside the code where they belong to.
 
 Ok. Will do.
 


 Signed-off-by: Peng Fan peng@freescale.com
 ---
  tools/imximage.c | 129 
 ++-
  tools/imximage.h |  24 +--
  2 files changed, 119 insertions(+), 34 deletions(-)

 diff --git a/tools/imximage.c b/tools/imximage.c
 index 6f469ae..1c0225d 100644
 --- a/tools/imximage.c
 +++ b/tools/imximage.c
 @@ -22,6 +22,9 @@ static table_entry_t imximage_cmds[] = {
 {CMD_BOOT_FROM, BOOT_FROM,boot command,   },
 {CMD_BOOT_OFFSET,   BOOT_OFFSET,  Boot offset,},
 {CMD_DATA,  DATA, Reg Write Data, },
 +   {CMD_CLR_BIT,   CLR_BIT,  Reg clear bit,  },
 +   {CMD_CHECK_BITS_SET,CHECK_BITS_SET,   Reg Check bits set, },
 +   {CMD_CHECK_BITS_CLR,CHECK_BITS_CLR,   Reg Check bits clr, },

 The table reflects Freescale's documentation. This has the big advantage
 because there is no need to explain which command is supposed to do
 because this is really well done by Freescale in the manuals. Here we
 should have only an additional entry due to CHECK_DATA_COMMAND, exactly
 what the SOC is able to do.
 
 Back to the question, why I implemented CHECK_BITS_SET/CLR, but not
 CHECK_DATA_COMMAND. I do not want to introduce more entry in one DCD entry
 such as CHECK_DATA 4 addr mask [CLR/SET], so I use two software commands
 to cover CHECK_DATA_COMMAND.
 

 {CMD_CSF,   CSF,   Command Sequence File, },
 {CMD_IMAGE_VERSION, IMAGE_VERSION,image version,  },
 {-1,, ,   },
 @@ -84,6 +87,7 @@ static set_imx_hdr_t set_imx_hdr;
  static uint32_t max_dcd_entries;
  static uint32_t *header_size_ptr;
  static uint32_t *csf_ptr;
 +static uint32_t dataindex;
  
  static uint32_t get_cfg_value(char *token, char *name,  int linenr)
  {
 @@ -129,7 +133,7 @@ static void err_imximage_version(int version)
  }
  
  static void set_dcd_val_v1(struct imx_header *imxhdr, char *name, int 
 lineno,
 -   int fld, uint32_t value, uint32_t off)
 +  int fld, int cmd, uint32_t value, uint32_t off)
  {

 Parameter list is becoming very long 

Re: [U-Boot] arm: imx: Kernel not booting when environment is in QSPI

[Nitin Garg]

On 06/09/2015 10:02 AM, Fabio Estevam wrote:
 Adding some FSL folks in case they have some suggestions.
 
 Regards,
 
 Fabio Estevam
 
 On Tue, Jun 9, 2015 at 11:41 AM, Matthias Weißer m.weisse...@gmail.com 
 wrote:
 Hi

 I work with an imx6sx sdb. I observed that placing u-boot in QSPI
 flash and also having the environment in QSPI the linux kernel doesn't
 boot. The backtrace from the kernel contains 'fsl_qspi_probe'. If only
 u-boot resides in QSPI and the environment is on mmc then the kernel
 boots successfully.

 Some more investigation showed that even when u-boot and the
 environment is on mmc a simple
 = sf probe 1:0
 causing the kernel not to boot.

 So I suspect a problem with u-boot not leaving the QSPI hardware in a
 sane state for the kernel driver to take over control. If no serial
 flash operations are executed in u-boot I can access the flash in
 linux via mtd.

 Kernel and u-boot are both current git HEAD with minor changes. Anyone
 with an idea?

 Regards
 Matthias

 Kernel output:
 Starting kernel ...

 [0.00] Booting Linux on physical CPU 0x0
 [0.00] Linux version 4.1.0-rc7-00047-g5879ae5-dirty
 (mweisser@ldev) (gcc version 4.9.2 (crosstool-NG 1.20.0) ) #2 Tue Jun
 9 09:40:49 CEST 2015
 [0.00] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), 
 cr=10c53c7d
 [0.00] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing
 instruction cache
 [0.00] Machine model: Freescale i.MX6 SoloX SDB RevB Board
 [0.00] cma: Reserved 16 MiB at 0xbf00
 [0.00] Memory policy: Data cache writeback
 [0.00] CPU: All CPU(s) started in SVC mode.
 [0.00] Built 1 zonelists in Zone order, mobility grouping on.
 Total pages: 260096
 [0.00] Kernel command line: console=ttymxc0,115200 ip=dhcp
 root=/dev/nfs nfsroot=192.168.1.60:/data/users/mweisser/tgt-fs/linux-fs
 consoleblank=0
 [0.00] PID hash table entries: 4096 (order: 2, 16384 bytes)
 [0.00] Dentry cache hash table entries: 131072 (order: 7, 524288 
 bytes)
 [0.00] Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
 [0.00] Memory: 1006056K/1048576K available (6035K kernel code,
 321K rwdata, 1960K rodata, 232K init, 8310K bss, 26136K reserved,
 16384K cma-reserved, 0K highmem)
 [0.00] Virtual kernel memory layout:
 [0.00] vector  : 0x - 0x1000   (   4 kB)
 [0.00] fixmap  : 0xffc0 - 0xfff0   (3072 kB)
 [0.00] vmalloc : 0xc080 - 0xff00   (1000 MB)
 [0.00] lowmem  : 0x8000 - 0xc000   (1024 MB)
 [0.00] pkmap   : 0x7fe0 - 0x8000   (   2 MB)
 [0.00] modules : 0x7f00 - 0x7fe0   (  14 MB)
 [0.00]   .text : 0x80008000 - 0x807d7044   (7997 kB)
 [0.00]   .init : 0x807d8000 - 0x80812000   ( 232 kB)
 [0.00]   .data : 0x80812000 - 0x808624e0   ( 322 kB)
 [0.00].bss : 0x808624e0 - 0x8107ff88   (8311 kB)
 [0.00] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
 [0.00] Running RCU self tests
 [0.00] NR_IRQS:16 nr_irqs:16 16
 [0.00] L2C-310 erratum 769419 enabled
 [0.00] L2C-310 enabling early BRESP for Cortex-A9
 [0.00] L2C-310 full line of zeros enabled for Cortex-A9
 [0.00] L2C-310 ID prefetch enabled, offset 1 lines
 [0.00] L2C-310 dynamic clock gating enabled, standby mode enabled
 [0.00] L2C-310 cache controller enabled, 16 ways, 256 kB
 [0.00] L2C-310: CACHE_ID 0x41c8, AUX_CTRL 0x76430001
 [0.00] Switching to timer-based delay loop, resolution 333ns
 [0.07] sched_clock: 32 bits at 3000kHz, resolution 333ns,
 wraps every 715827882841ns
 [0.35] clocksource mxc_timer1: mask: 0x max_cycles:
 0x, max_idle_ns: 637086815595 ns
 [0.000888] Console: colour dummy device 80x30
 [0.000918] Lock dependency validator: Copyright (c) 2006 Red Hat,
 Inc., Ingo Molnar
 [0.000927] ... MAX_LOCKDEP_SUBCLASSES:  8
 [0.000934] ... MAX_LOCK_DEPTH:  48
 [0.000941] ... MAX_LOCKDEP_KEYS:8191
 [0.000948] ... CLASSHASH_SIZE:  4096
 [0.000955] ... MAX_LOCKDEP_ENTRIES: 32768
 [0.000961] ... MAX_LOCKDEP_CHAINS:  65536
 [0.000968] ... CHAINHASH_SIZE:  32768
 [0.000975]  memory used by lock dependency info: 5167 kB
 [0.000983]  per task-struct memory footprint: 1152 bytes
 [0.001006] Calibrating delay loop (skipped), value calculated
 using timer frequency.. 6.00 BogoMIPS (lpj=3)
 [0.001023] pid_max: default: 32768 minimum: 301
 [0.001180] Mount-cache hash table entries: 2048 (order: 1, 8192 bytes)
 [0.001196] Mountpoint-cache hash table entries: 2048 (order: 1, 8192 
 bytes)
 [0.002704] CPU: Testing write buffer coherency: ok
 [0.003382] Setting up static identity map for 0x80008200 - 0x80008258
 [0.006410] devtmpfs: initialized
 [0.028795] VFP 

Re: [U-Boot] bootcount: Add dcache flush to bootcount_store()

[Nitin Garg]

Hi Stefan,
On 03/27/2015 08:18 AM, Stefan Roese wrote:
 Hi!
 
 (added a few more people to the Cc list)
 
 On 17.03.2015 10:00, Holger Brunck wrote:
 Hi Tom,

 On 03/13/2015 03:34 PM, Tom Rini wrote:
 On Fri, Mar 13, 2015 at 09:48:56AM -0400, Tom Rini wrote:
 On Wed, Mar 11, 2015 at 09:51:38AM +0100, Stefan Roese wrote:

 Without this dcache_flush the updated bootcounter may not be saved to
 its location.

 This was detected on an iMX.6 platform using the OCRAM (internal SRAM)
 as bootcounter storage area. And issuing reset from within U-Boot
 cause the bootcounter to stay on its initial value.

 Signed-off-by: Stefan Roese s...@denx.de
 Reviewed-by: Tom Rini tr...@konsulko.com

 OK, this breaks some platforms:
 powerpc:  +   TQM850L
 +(TQM850L) drivers/built-in.o: In function `bootcount_store':
 +(TQM850L) build/../drivers/bootcount/bootcount.c:64: undefined reference 
 to `flush_dcache_range'
 +(TQM850L) make[1]: *** [u-boot] Error 1
 +(TQM850L) make: *** [sub-make] Error 2

 We'll see how many others have the same problem soon and then I'll
 decide on nuking the old platforms of holding off on this change.

 Aside from the TQM 8xx family that Wolfgang owns we have mgcoge and
 mgcoge3ne also breaking from this
 (http://patchwork.ozlabs.org/patch/448849/) change.  Wolfgang, Holger,
 how do you want to proceed?  We either need cache operations or dropping
 bootcount from the platforms or dropping the platforms.


 we still would like to keep mgcoge and mgcoge3ne support. These boards are 
 still
 in maintenance. Unfortunately this week we are very busy. Next week Valentin 
 or
 myself have planned to find some time to look at this.
 
 I just yesterday noticed this code for mx6:
 
 - arch/arm/cpu/armv7/mx6/soc.c 
 -
 void enable_caches(void)
 {
   ...
   /* Enable caching on OCRAM and ROM */
   mmu_set_region_dcache_behaviour(ROMCP_ARB_BASE_ADDR,
   ROMCP_ARB_END_ADDR,
   option);
   mmu_set_region_dcache_behaviour(IRAM_BASE_ADDR,
   IRAM_SIZE,
   option);
 
 So we definitely have the dcache enabled on mx6 in the OCRAM. And this
 of course explains, why I need the cache flush operations in the
 bootcounter code.
 
 I'm not really sure if we want this area to be cached though. This got
 introduced with this patch:
 
 Author: Nitin Garg nitin.g...@freescale.com  2014-09-16 20:33:25
 Committer: Stefano Babic sba...@denx.de  2014-09-22 16:21:04
 
 imx: Support i.MX6 High Assurance Boot authentication
 
 When CONFIG_SECURE_BOOT is enabled, the signed images
 like kernel and dtb can be authenticated using iMX6 CAAM.
 The added command hab_auth_img can be used for HAB
 authentication of images. The command takes the image
 DDR location, IVT (Image Vector Table) offset inside
 image as parameters. Detailed info about signing images
 can be found in Freescale AppNote AN4581.
 
 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 
 The cache stuff is not mentioned here in this commit log.
 Nitin, why did you enable the cache here? Performance reason
 only?
Seems like I missed mentioning this in the commit log, sorry.
We enabled the OCRAM d-cache since it helped HAB to
execute faster when authenticating OS image. The time taken 
to complete HAB improved by 3 times with d-cache enabled
for ROM and OCRAM. This is because the HAB uses various
regions of the OCRAM for data.

 
 If the OCRAM was uncached (again), we could really drop my patch
 (this mail thread) with those flush calls. So how should we proceed?
 Make this OCRAM area uncached again?
 
 Comments welcome...
 
 Thanks,
 Stefan
 
 BTW: I'm on vacation now until 8th April, so please don't expect
 any replies in this time.
 
Regards,
Nitin
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Re: [U-Boot] [PATCH v6 0/5] add i.MX6 thermal sensor driver

[Nitin Garg]

On 11/15/2014 06:34 AM, Albert ARIBAUD wrote:
 Hello nitin.g...@freescale.com,
 
 On Fri, 14 Nov 2014 14:13:02 -0600, nitin.g...@freescale.com
 nitin.g...@freescale.com wrote:
 From: Nitin Garg nitin.g...@freescale.com

 This patch set adds i.MX6 thermal sensor driver
 and enables it for mx6sabre boards. Also adds
 various anadig bit definitions as required for
 upcoming drivers.

 Changes in v6:
 -Aligned imx thermal driver macro defines with kernel

 Changes in v5:
 -Don't modify the copyright of cpu.c and crm_regs.h file

 Changes in v4:
 -Added imx6 thermal sensor as a driver
 -Renamed the config define to be more meaningful
 -Move the clock code to clock.c
 -Reusing ocotp driver for reading fuse
 -Fix check for calibration fuse not programmed
 -Aligned the slope computation with kernel
 -Added Anadig register defines as seperate commit

 Changes in v3:
 -adds the mx6 thermal driver support
 -adds the mx6 thermal support to mx6sabresd board.

 Changes in v2:
 -run checkpatch and fix reported issues

 Nitin Garg (4):
   mx6: clock: Add api to enable pll3
   mx6: thermal: Add i.MX6 CPU thermal sensor support
   mx6: thermal: Check cpu temperature via thermal sensor
   mx6: thermal: Enable thermal sensor for mx6 sabre boards.
 
 So, is it 5 as the cover letter says, or 4 as the patches say? If
 actually 4 and only the cover letter is wrong, then there's no need to
 repost. If actually 5, then please repost them all, renumbered
 accordingly.
 
 Amicalement,
 

Just the cover subject is wrong (0/5 should be 0/4). Thanks,
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Re: [U-Boot] [PATCH v4 1/5] mx6: crm_regs: Add bit definitions for anadig registers

[Nitin Garg]

Hi Stefano,
On 10/01/2014 02:21 AM, Stefano Babic wrote:
 Hi Nitin, Tom, Wolfgang,
 
 On 16/09/2014 18:48, Nitin Garg wrote:
 Add bit definitons for various anadig registers as
 required by various drivers.

 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 ---

 Changes in v4: None
 Changes in v3: None
 Changes in v2: None

  arch/arm/include/asm/arch-mx6/crm_regs.h |  543 
 +-
  1 file changed, 542 insertions(+), 1 deletion(-)

 diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h 
 b/arch/arm/include/asm/arch-mx6/crm_regs.h
 index e67b5b9..66a7cea 100644
 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h
 +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
 @@ -1,5 +1,5 @@
  /*
 - * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
 + * Copyright 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
 
 This is a legal issue. I guess some changes like this one have already
 flown into mainline, but I am quite unsure that this is legally correct.
 Originally, when the file was introduced, it had Freescale's Copyright -
 fine.
 
 Of course, this header file was changed several times, and not only by
 Freescale or Freescale's employers. Is it then correct to update the
 copyright now, extending the datum ? I doubt this is ok.
 
 Thanks for clarification,
 Stefano Babic
 

Shall I remove it and resend? Or shall I change it to 2011,2014?
Pls suggest.

Regards,
Nitin
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[U-Boot] [PATCH v5] mx6: thermal: Check cpu temperature via thermal sensor

[Nitin Garg]

read cpu temperature using the onchip thermal
sensor.

Signed-off-by: Nitin Garg nitin.g...@freescale.com

---

Changes in v5:
-Don't modify the copyright of cpu.c file

Changes in v4:
-Added imx6 thermal sensor as a driver
-Renamed the config define to be more meaningful
-Move the clock code to clock.c
-Reusing ocotp driver for reading fuse
-Fix check for calibration fuse not programmed
-Aligned the slope computation with kernel
-Added Anadig register defines as seperate commit

Changes in v3:
-adds the mx6 temperature support
-adds the mx6 temperature support to mx6sabresd board.

Changes in v2:
-run checkpatch and fix reported issues

 arch/arm/imx-common/cpu.c |6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index ed826a0..a7b49bd 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -15,6 +15,7 @@
 #include asm/arch/sys_proto.h
 #include asm/arch/crm_regs.h
 #include ipu_pixfmt.h
+#include imx_thermal.h
 
 #ifdef CONFIG_FSL_ESDHC
 #include fsl_esdhc.h
@@ -139,6 +140,11 @@ int print_cpuinfo(void)
(cpurev  0x000F0)  4,
(cpurev  0xF)  0,
mxc_get_clock(MXC_ARM_CLK) / 100);
+
+#if defined(CONFIG_MX6)  defined(CONFIG_IMX6_THERMAL)
+   check_cpu_temperature();
+#endif
+
printf(Reset cause: %s\n, get_reset_cause());
return 0;
 }
-- 
1.7.9.5

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[U-Boot] [PATCH v5] mx6: crm_regs: Add bit definitions for anadig registers

[Nitin Garg]

Add bit definitons for various anadig registers as
required by various drivers.

Signed-off-by: Nitin Garg nitin.g...@freescale.com

---

Changes in v5:
-Don't modify the copyright of crm_regs.h file

Changes in v4:
-Added imx6 thermal sensor as a driver
-Renamed the config define to be more meaningful
-Move the clock code to clock.c
-Reusing ocotp driver for reading fuse
-Fix check for calibration fuse not programmed
-Aligned the slope computation with kernel
-Added Anadig register defines as seperate commit

Changes in v3:
-adds the mx6 temperature support
-adds the mx6 temperature support to mx6sabresd board.

Changes in v2:
-run checkpatch and fix reported issues

 arch/arm/include/asm/arch-mx6/crm_regs.h |  541 ++
 1 file changed, 541 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h 
b/arch/arm/include/asm/arch-mx6/crm_regs.h
index e67b5b9..5c79d0f 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1061,4 +1061,545 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
(((v)  0)  BM_ANADIG_PFD_528_PFD0_FRAC)
 
+#define HW_ANADIG_REG_1P1  (0x0110)
+#define HW_ANADIG_REG_1P1_SET  (0x0114)
+#define HW_ANADIG_REG_1P1_CLR  (0x0118)
+#define HW_ANADIG_REG_1P1_TOG  (0x011c)
+
+#define BP_ANADIG_REG_1P1_RSVD2  18
+#define BM_ANADIG_REG_1P1_RSVD2 0xFFFC
+#define BF_ANADIG_REG_1P1_RSVD2(v) \
+   (((v)  18)  BM_ANADIG_REG_1P1_RSVD2)
+#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x0002
+#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x0001
+#define BP_ANADIG_REG_1P1_RSVD1  13
+#define BM_ANADIG_REG_1P1_RSVD1 0xE000
+#define BF_ANADIG_REG_1P1_RSVD1(v)  \
+   (((v)  13)  BM_ANADIG_REG_1P1_RSVD1)
+#define BP_ANADIG_REG_1P1_OUTPUT_TRG  8
+#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x1F00
+#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v)  \
+   (((v)  8)  BM_ANADIG_REG_1P1_OUTPUT_TRG)
+#define BM_ANADIG_REG_1P1_RSVD0 0x0080
+#define BP_ANADIG_REG_1P1_BO_OFFSET  4
+#define BM_ANADIG_REG_1P1_BO_OFFSET 0x0070
+#define BF_ANADIG_REG_1P1_BO_OFFSET(v)  \
+   (((v)  4)  BM_ANADIG_REG_1P1_BO_OFFSET)
+#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x0008
+#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x0004
+#define BM_ANADIG_REG_1P1_ENABLE_BO 0x0002
+#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x0001
+
+#define HW_ANADIG_REG_3P0  (0x0120)
+#define HW_ANADIG_REG_3P0_SET  (0x0124)
+#define HW_ANADIG_REG_3P0_CLR  (0x0128)
+#define HW_ANADIG_REG_3P0_TOG  (0x012c)
+
+#define BP_ANADIG_REG_3P0_RSVD2  18
+#define BM_ANADIG_REG_3P0_RSVD2 0xFFFC
+#define BF_ANADIG_REG_3P0_RSVD2(v) \
+   (((v)  18)  BM_ANADIG_REG_3P0_RSVD2)
+#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x0002
+#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x0001
+#define BP_ANADIG_REG_3P0_RSVD1  13
+#define BM_ANADIG_REG_3P0_RSVD1 0xE000
+#define BF_ANADIG_REG_3P0_RSVD1(v)  \
+   (((v)  13)  BM_ANADIG_REG_3P0_RSVD1)
+#define BP_ANADIG_REG_3P0_OUTPUT_TRG  8
+#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x1F00
+#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v)  \
+   (((v)  8)  BM_ANADIG_REG_3P0_OUTPUT_TRG)
+#define BM_ANADIG_REG_3P0_VBUS_SEL 0x0080
+#define BP_ANADIG_REG_3P0_BO_OFFSET  4
+#define BM_ANADIG_REG_3P0_BO_OFFSET 0x0070
+#define BF_ANADIG_REG_3P0_BO_OFFSET(v)  \
+   (((v)  4)  BM_ANADIG_REG_3P0_BO_OFFSET)
+#define BM_ANADIG_REG_3P0_RSVD0 0x0008
+#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x0004
+#define BM_ANADIG_REG_3P0_ENABLE_BO 0x0002
+#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x0001
+
+#define HW_ANADIG_REG_2P5  (0x0130)
+#define HW_ANADIG_REG_2P5_SET  (0x0134)
+#define HW_ANADIG_REG_2P5_CLR  (0x0138)
+#define HW_ANADIG_REG_2P5_TOG  (0x013c)
+
+#define BP_ANADIG_REG_2P5_RSVD2  19
+#define BM_ANADIG_REG_2P5_RSVD2 0xFFF8
+#define BF_ANADIG_REG_2P5_RSVD2(v) \
+   (((v)  19)  BM_ANADIG_REG_2P5_RSVD2)
+#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x0004
+#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x0002
+#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x0001
+#define BP_ANADIG_REG_2P5_RSVD1  13
+#define BM_ANADIG_REG_2P5_RSVD1 0xE000
+#define BF_ANADIG_REG_2P5_RSVD1(v)  \
+   (((v)  13)  BM_ANADIG_REG_2P5_RSVD1)
+#define BP_ANADIG_REG_2P5_OUTPUT_TRG  8
+#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x1F00
+#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v)  \
+   (((v)  8)  BM_ANADIG_REG_2P5_OUTPUT_TRG)
+#define BM_ANADIG_REG_2P5_RSVD0 0x0080
+#define BP_ANADIG_REG_2P5_BO_OFFSET  4
+#define BM_ANADIG_REG_2P5_BO_OFFSET 0x0070
+#define BF_ANADIG_REG_2P5_BO_OFFSET(v)  \
+   (((v)  4)  BM_ANADIG_REG_2P5_BO_OFFSET)
+#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x0008
+#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x0004
+#define BM_ANADIG_REG_2P5_ENABLE_BO 0x0002
+#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x0001
+
+#define HW_ANADIG_REG_CORE (0x0140)
+#define HW_ANADIG_REG_CORE_SET

Re: [U-Boot] [PATCH v5] mx6: crm_regs: Add bit definitions for anadig registers

[Nitin Garg]

On 10/01/2014 07:26 AM, Fabio Estevam wrote:
 Hi Nitin,
 
 On Wed, Oct 1, 2014 at 9:19 AM, Nitin Garg nitin.g...@freescale.com wrote:
 Add bit definitons for various anadig registers as
 required by various drivers.

 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 
 In the previous v4 version this was a patch series 1/4.
 
 Now it is a single patch. What about the other patches?
 

I will resend the whole series. Thanks for pointing out.
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[U-Boot] [PATCH v5 0/5] add i.MX6 thermal sensor driver

[Nitin Garg]

This patch set adds i.MX6 thermal sensor driver
and enables it for mx6sabre boards. Also adds
various anadig bit definitions as required for
upcoming drivers.

Changes in v5:
-Don't modify the copyright of cpu.c and crm_regs.h file

Changes in v4:
-Added imx6 thermal sensor as a driver
-Renamed the config define to be more meaningful
-Move the clock code to clock.c
-Reusing ocotp driver for reading fuse
-Fix check for calibration fuse not programmed
-Aligned the slope computation with kernel
-Added Anadig register defines as seperate commit

Changes in v3:
-adds the mx6 thermal driver support
-adds the mx6 thermal support to mx6sabresd board.

Changes in v2:
-run checkpatch and fix reported issues

Nitin Garg (5):
  mx6: crm_regs: Add bit definitions for anadig registers
  mx6: clock: Add api to enable pll3
  mx6: thermal: Add i.MX6 CPU thermal sensor support
  mx6: thermal: Check cpu temperature via thermal sensor
  mx6: thermal: Enable thermal sensor for mx6 sabre boards.

 arch/arm/cpu/armv7/mx6/clock.c   |   25 ++
 arch/arm/imx-common/cpu.c|6 +
 arch/arm/include/asm/arch-mx6/clock.h|1 +
 arch/arm/include/asm/arch-mx6/crm_regs.h |  541 ++
 drivers/Makefile |1 +
 drivers/thermal/Makefile |8 +
 drivers/thermal/imx_thermal.c|  137 
 include/configs/mx6sabre_common.h|3 +-
 include/imx_thermal.h|   15 +
 9 files changed, 736 insertions(+), 1 deletion(-)
 create mode 100644 drivers/thermal/Makefile
 create mode 100644 drivers/thermal/imx_thermal.c
 create mode 100644 include/imx_thermal.h

-- 
1.7.9.5

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[U-Boot] [PATCH v5 4/5] mx6: thermal: Check cpu temperature via thermal sensor

[Nitin Garg]

read cpu temperature using the onchip thermal
sensor.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

 arch/arm/imx-common/cpu.c |6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index ed826a0..a7b49bd 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -15,6 +15,7 @@
 #include asm/arch/sys_proto.h
 #include asm/arch/crm_regs.h
 #include ipu_pixfmt.h
+#include imx_thermal.h
 
 #ifdef CONFIG_FSL_ESDHC
 #include fsl_esdhc.h
@@ -139,6 +140,11 @@ int print_cpuinfo(void)
(cpurev  0x000F0)  4,
(cpurev  0xF)  0,
mxc_get_clock(MXC_ARM_CLK) / 100);
+
+#if defined(CONFIG_MX6)  defined(CONFIG_IMX6_THERMAL)
+   check_cpu_temperature();
+#endif
+
printf(Reset cause: %s\n, get_reset_cause());
return 0;
 }
-- 
1.7.9.5

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[U-Boot] [PATCH v5 2/5] mx6: clock: Add api to enable pll3

[Nitin Garg]

Add api to check and enable pll3 as required
for thermal sensor driver.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

 arch/arm/cpu/armv7/mx6/clock.c|   25 +
 arch/arm/include/asm/arch-mx6/clock.h |1 +
 2 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 336e557..04273bb 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -642,6 +642,31 @@ int enable_pcie_clock(void)
   BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
 
+void enable_pll3(void)
+{
+   struct anatop_regs __iomem *anatop =
+   (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+   /* make sure pll3 is enabled */
+   if ((readl(anatop-usb1_pll_480_ctrl) 
+   BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
+   /* enable pll's power */
+   writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
+  anatop-usb1_pll_480_ctrl_set);
+   writel(0x80, anatop-ana_misc2_clr);
+   /* wait for pll lock */
+   while ((readl(anatop-usb1_pll_480_ctrl) 
+   BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
+   ;
+   /* disable bypass */
+   writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
+  anatop-usb1_pll_480_ctrl_clr);
+   /* enable pll output */
+   writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
+  anatop-usb1_pll_480_ctrl_set);
+   }
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
switch (clk) {
diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index c11674f..c40abc4 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -65,4 +65,5 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
 void enable_enet_clk(unsigned char enable);
+void enable_pll3(void);
 #endif /* __ASM_ARCH_CLOCK_H */
-- 
1.7.9.5

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[U-Boot] [PATCH v5 1/5] mx6: crm_regs: Add bit definitions for anadig registers

[Nitin Garg]

Add bit definitons for various anadig registers as
required by various drivers.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

 arch/arm/include/asm/arch-mx6/crm_regs.h |  541 ++
 1 file changed, 541 insertions(+)

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h 
b/arch/arm/include/asm/arch-mx6/crm_regs.h
index e67b5b9..5c79d0f 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1061,4 +1061,545 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
(((v)  0)  BM_ANADIG_PFD_528_PFD0_FRAC)
 
+#define HW_ANADIG_REG_1P1  (0x0110)
+#define HW_ANADIG_REG_1P1_SET  (0x0114)
+#define HW_ANADIG_REG_1P1_CLR  (0x0118)
+#define HW_ANADIG_REG_1P1_TOG  (0x011c)
+
+#define BP_ANADIG_REG_1P1_RSVD2  18
+#define BM_ANADIG_REG_1P1_RSVD2 0xFFFC
+#define BF_ANADIG_REG_1P1_RSVD2(v) \
+   (((v)  18)  BM_ANADIG_REG_1P1_RSVD2)
+#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x0002
+#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x0001
+#define BP_ANADIG_REG_1P1_RSVD1  13
+#define BM_ANADIG_REG_1P1_RSVD1 0xE000
+#define BF_ANADIG_REG_1P1_RSVD1(v)  \
+   (((v)  13)  BM_ANADIG_REG_1P1_RSVD1)
+#define BP_ANADIG_REG_1P1_OUTPUT_TRG  8
+#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x1F00
+#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v)  \
+   (((v)  8)  BM_ANADIG_REG_1P1_OUTPUT_TRG)
+#define BM_ANADIG_REG_1P1_RSVD0 0x0080
+#define BP_ANADIG_REG_1P1_BO_OFFSET  4
+#define BM_ANADIG_REG_1P1_BO_OFFSET 0x0070
+#define BF_ANADIG_REG_1P1_BO_OFFSET(v)  \
+   (((v)  4)  BM_ANADIG_REG_1P1_BO_OFFSET)
+#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x0008
+#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x0004
+#define BM_ANADIG_REG_1P1_ENABLE_BO 0x0002
+#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x0001
+
+#define HW_ANADIG_REG_3P0  (0x0120)
+#define HW_ANADIG_REG_3P0_SET  (0x0124)
+#define HW_ANADIG_REG_3P0_CLR  (0x0128)
+#define HW_ANADIG_REG_3P0_TOG  (0x012c)
+
+#define BP_ANADIG_REG_3P0_RSVD2  18
+#define BM_ANADIG_REG_3P0_RSVD2 0xFFFC
+#define BF_ANADIG_REG_3P0_RSVD2(v) \
+   (((v)  18)  BM_ANADIG_REG_3P0_RSVD2)
+#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x0002
+#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x0001
+#define BP_ANADIG_REG_3P0_RSVD1  13
+#define BM_ANADIG_REG_3P0_RSVD1 0xE000
+#define BF_ANADIG_REG_3P0_RSVD1(v)  \
+   (((v)  13)  BM_ANADIG_REG_3P0_RSVD1)
+#define BP_ANADIG_REG_3P0_OUTPUT_TRG  8
+#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x1F00
+#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v)  \
+   (((v)  8)  BM_ANADIG_REG_3P0_OUTPUT_TRG)
+#define BM_ANADIG_REG_3P0_VBUS_SEL 0x0080
+#define BP_ANADIG_REG_3P0_BO_OFFSET  4
+#define BM_ANADIG_REG_3P0_BO_OFFSET 0x0070
+#define BF_ANADIG_REG_3P0_BO_OFFSET(v)  \
+   (((v)  4)  BM_ANADIG_REG_3P0_BO_OFFSET)
+#define BM_ANADIG_REG_3P0_RSVD0 0x0008
+#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x0004
+#define BM_ANADIG_REG_3P0_ENABLE_BO 0x0002
+#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x0001
+
+#define HW_ANADIG_REG_2P5  (0x0130)
+#define HW_ANADIG_REG_2P5_SET  (0x0134)
+#define HW_ANADIG_REG_2P5_CLR  (0x0138)
+#define HW_ANADIG_REG_2P5_TOG  (0x013c)
+
+#define BP_ANADIG_REG_2P5_RSVD2  19
+#define BM_ANADIG_REG_2P5_RSVD2 0xFFF8
+#define BF_ANADIG_REG_2P5_RSVD2(v) \
+   (((v)  19)  BM_ANADIG_REG_2P5_RSVD2)
+#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x0004
+#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x0002
+#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x0001
+#define BP_ANADIG_REG_2P5_RSVD1  13
+#define BM_ANADIG_REG_2P5_RSVD1 0xE000
+#define BF_ANADIG_REG_2P5_RSVD1(v)  \
+   (((v)  13)  BM_ANADIG_REG_2P5_RSVD1)
+#define BP_ANADIG_REG_2P5_OUTPUT_TRG  8
+#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x1F00
+#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v)  \
+   (((v)  8)  BM_ANADIG_REG_2P5_OUTPUT_TRG)
+#define BM_ANADIG_REG_2P5_RSVD0 0x0080
+#define BP_ANADIG_REG_2P5_BO_OFFSET  4
+#define BM_ANADIG_REG_2P5_BO_OFFSET 0x0070
+#define BF_ANADIG_REG_2P5_BO_OFFSET(v)  \
+   (((v)  4)  BM_ANADIG_REG_2P5_BO_OFFSET)
+#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x0008
+#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x0004
+#define BM_ANADIG_REG_2P5_ENABLE_BO 0x0002
+#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x0001
+
+#define HW_ANADIG_REG_CORE (0x0140)
+#define HW_ANADIG_REG_CORE_SET (0x0144)
+#define HW_ANADIG_REG_CORE_CLR (0x0148)
+#define HW_ANADIG_REG_CORE_TOG (0x014c)
+
+#define BM_ANADIG_REG_CORE_REF_SHIFT 0x8000
+#define BM_ANADIG_REG_CORE_RSVD0 0x4000
+#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x2000
+#define BP_ANADIG_REG_CORE_RAMP_RATE  27
+#define BM_ANADIG_REG_CORE_RAMP_RATE 0x1800
+#define BF_ANADIG_REG_CORE_RAMP_RATE(v)  \
+   (((v)  27)  BM_ANADIG_REG_CORE_RAMP_RATE)
+#define BP_ANADIG_REG_CORE_REG2_ADJ  23
+#define BM_ANADIG_REG_CORE_REG2_ADJ 0x0780
+#define

[U-Boot] [PATCH v5 3/5] mx6: thermal: Add i.MX6 CPU thermal sensor support

[Nitin Garg]

i.MX6 SoC has onchip temperature sensor. Add driver
for this sensor.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

 drivers/Makefile  |1 +
 drivers/thermal/Makefile  |8 +++
 drivers/thermal/imx_thermal.c |  137 +
 include/imx_thermal.h |   15 +
 4 files changed, 161 insertions(+)
 create mode 100644 drivers/thermal/Makefile
 create mode 100644 drivers/thermal/imx_thermal.c
 create mode 100644 include/imx_thermal.h

diff --git a/drivers/Makefile b/drivers/Makefile
index d8361d9..2792acd 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -19,3 +19,4 @@ obj-$(CONFIG_QE) += qe/
 obj-y += memory/
 obj-y += pwm/
 obj-y += input/
+obj-y += thermal/
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
new file mode 100644
index 000..04ae395
--- /dev/null
+++ b/drivers/thermal/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+# Author: Nitin Garg nitin.g...@freescale.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
new file mode 100644
index 000..3b53b61
--- /dev/null
+++ b/drivers/thermal/imx_thermal.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Nitin Garg nitin.g...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include config.h
+#include common.h
+#include div64.h
+#include fuse.h
+#include asm/io.h
+#include asm/arch/crm_regs.h
+#include asm/arch/clock.h
+
+#define TEMPERATURE_MIN-40
+#define TEMPERATURE_HOT80
+#define TEMPERATURE_MAX125
+#define FACTOR01000
+#define FACTOR115976
+#define FACTOR24297157
+#define MEASURE_FREQ   327
+
+static int read_cpu_temperature(u32 fuse)
+{
+   int temperature;
+   unsigned int reg, n_meas;
+   struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+   int t1, n1;
+   u32 c1, c2;
+   u64 temp64;
+
+   /* make sure pll3 is enabled for thermal sensor */
+   enable_pll3();
+
+   /*
+* Sensor data layout:
+*   [31:20] - sensor value @ 25C
+* We use universal formula now and only need sensor value @ 25C
+* slope = 0.4297157 - (0.0015976 * 25C fuse)
+*/
+   n1 = fuse  20;
+   t1 = 25; /* t1 always 25C */
+
+   /*
+* Derived from linear interpolation:
+* slope = 0.4297157 - (0.0015976 * 25C fuse)
+* slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
+* (Nmeas - n1) / (Tmeas - t1) = slope
+* We want to reduce this down to the minimum computation necessary
+* for each temperature read.  Also, we want Tmeas in millicelsius
+* and we don't want to lose precision from integer division. So...
+* Tmeas = (Nmeas - n1) / slope + t1
+* milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
+* milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
+* Let constant c1 = (-1000 / slope)
+* milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
+* Let constant c2 = n1 *c1 + 1000 * t1
+* milli_Tmeas = c2 - Nmeas * c1
+*/
+   temp64 = FACTOR0;
+   temp64 *= 1000;
+   do_div(temp64, FACTOR1 * n1 - FACTOR2);
+   c1 = temp64;
+   c2 = n1 * c1 + 1000 * t1;
+
+   /*
+* now we only use single measure, every time we read
+* the temperature, we will power on/down anadig thermal
+* module
+*/
+   writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, anatop-tempsense0_clr);
+   writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, anatop-ana_misc0_set);
+
+   /* setup measure freq */
+   reg = readl(anatop-tempsense1);
+   reg = ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ;
+   reg |= MEASURE_FREQ;
+   writel(reg, anatop-tempsense1);
+
+   /* start the measurement process */
+   writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, anatop-tempsense0_clr);
+   writel(BM_ANADIG_TEMPSENSE0_FINISHED, anatop-tempsense0_clr);
+   writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, anatop-tempsense0_set);
+
+   /* make sure that the latest temp is valid */
+   while ((readl(anatop-tempsense0) 
+   BM_ANADIG_TEMPSENSE0_FINISHED) == 0)
+   udelay(1);
+
+   /* read temperature count */
+   reg = readl(anatop-tempsense0);
+   n_meas = (reg  BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
+BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
+   writel(BM_ANADIG_TEMPSENSE0_FINISHED, anatop-tempsense0_clr);
+
+   /* milli_Tmeas = c2 - Nmeas * c1 */
+   temperature = (c2 - n_meas * c1)/1000;
+
+   /* power down anatop thermal sensor */
+   writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, anatop-tempsense0_set);
+   writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, anatop

[U-Boot] [PATCH v5 5/5] mx6: thermal: Enable thermal sensor for mx6 sabre boards.

[Nitin Garg]

Add CONFIG_IMX6_THERMAL to mx6sabre_common.h file. Since
thermal driver depends on ocotp, make sure to enable
CONFIG_MXC_OCOTP when CONFIG_IMX6_THERMAL is slected.

Signed-off-by: Nitin Garg nitin.g...@freescale.com

---

Changes in v5:
-Don't modify the copyright of cpu.c and crm_regs.h file

Changes in v4:
-Added imx6 thermal sensor as a driver
-Renamed the config define to be more meaningful
-Move the clock code to clock.c
-Reusing ocotp driver for reading fuse
-Fix check for calibration fuse not programmed
-Aligned the slope computation with kernel
-Added Anadig register defines as seperate commit

Changes in v3:
-adds the mx6 thermal driver support
-adds the mx6 thermal support to mx6sabresd board.

Changes in v2:
-run checkpatch and fix reported issues

 include/configs/mx6sabre_common.h |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/configs/mx6sabre_common.h 
b/include/configs/mx6sabre_common.h
index 2d93d6c..b3e6071 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -24,6 +24,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
+#define CONFIG_IMX6_THERMAL
 
 #define CONFIG_SYS_GENERIC_BOARD
 
@@ -37,7 +38,7 @@
 #define CONFIG_MXC_UART
 
 #define CONFIG_CMD_FUSE
-#ifdef CONFIG_CMD_FUSE
+#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
 #define CONFIG_MXC_OCOTP
 #endif
 
-- 
1.7.9.5

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[U-Boot] [PATCH v1] imx6sx: Fix i.MX6SX HAB api function table offset

[Nitin Garg]

i.MX6SX ROM implements unified table sections.
The HAB function table is at offset 0x100. Update
the HAB function pointers accordingly.

Signed-off-by: Nitin Garg nitin.g...@freescale.com

---

 arch/arm/include/asm/arch-mx6/hab.h |   33 +++--
 include/configs/mx6sxsabresd.h  |1 +
 2 files changed, 24 insertions(+), 10 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/hab.h 
b/arch/arm/include/asm/arch-mx6/hab.h
index 1f12695..4c9734e 100644
--- a/arch/arm/include/asm/arch-mx6/hab.h
+++ b/arch/arm/include/asm/arch-mx6/hab.h
@@ -53,17 +53,30 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, 
ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 
-#define HAB_RVT_REPORT_EVENT   (*(uint32_t *)0x00B4)
-#define HAB_RVT_REPORT_STATUS  (*(uint32_t *)0x00B8)
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x00A4)
-#define HAB_RVT_ENTRY  (*(uint32_t *)0x0098)
-#define HAB_RVT_EXIT   (*(uint32_t *)0x009C)
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
 
-#define HAB_RVT_REPORT_EVENT_NEW   (*(uint32_t *)0x00B8)
-#define HAB_RVT_REPORT_STATUS_NEW  (*(uint32_t *)0x00BC)
-#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x00A8)
-#define HAB_RVT_ENTRY_NEW  (*(uint32_t *)0x009C)
-#define HAB_RVT_EXIT_NEW   (*(uint32_t *)0x00A0)
+#define HAB_RVT_BASE   0x0100
+#define HAB_RVT_ENTRY  (*(uint32_t *)(HAB_RVT_BASE + 0x04))
+#define HAB_RVT_EXIT   (*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
+#define HAB_RVT_REPORT_EVENT   (*(uint32_t *)(HAB_RVT_BASE + 0x20))
+#define HAB_RVT_REPORT_STATUS  (*(uint32_t *)(HAB_RVT_BASE + 0x24))
+
+#else
+
+#define HAB_RVT_REPORT_EVENT   (*(uint32_t *)0x00B4)
+#define HAB_RVT_REPORT_STATUS  (*(uint32_t *)0x00B8)
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x00A4)
+#define HAB_RVT_ENTRY  (*(uint32_t *)0x0098)
+#define HAB_RVT_EXIT   (*(uint32_t *)0x009C)
+
+#endif
+
+#define HAB_RVT_REPORT_EVENT_NEW   (*(uint32_t *)0x00B8)
+#define HAB_RVT_REPORT_STATUS_NEW  (*(uint32_t *)0x00BC)
+#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x00A8)
+#define HAB_RVT_ENTRY_NEW  (*(uint32_t *)0x009C)
+#define HAB_RVT_EXIT_NEW   (*(uint32_t *)0x00A0)
 
 #define HAB_CID_ROM 0 /** ROM Caller ID */
 #define HAB_CID_UBOOT 1 /** UBOOT Caller ID*/
diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h
index 1eda65e..6394667 100644
--- a/include/configs/mx6sxsabresd.h
+++ b/include/configs/mx6sxsabresd.h
@@ -15,6 +15,7 @@
 #include mx6_common.h
 
 #define CONFIG_MX6
+#define CONFIG_ROM_UNIFIED_SECTIONS
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 
-- 
1.7.9.5

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Re: [U-Boot] [PATCH v4] imx: Support i.MX6 High Assurance Boot authentication

[Nitin Garg]

Hi Fabio,

On 09/30/2014 08:44 AM, Fabio Estevam wrote:
 Hi Nitin,
 
 On Tue, Sep 16, 2014 at 3:33 PM, Nitin Garg nitin.g...@freescale.com wrote:
 When CONFIG_SECURE_BOOT is enabled, the signed images
 like kernel and dtb can be authenticated using iMX6 CAAM.
 The added command hab_auth_img can be used for HAB
 authentication of images. The command takes the image
 DDR location, IVT (Image Vector Table) offset inside
 image as parameters. Detailed info about signing images
 can be found in Freescale AppNote AN4581.

 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 
 I have just tested the 'hab_status' command and it hangs my mx6sxsabresd 
 board:
 
 U-Boot 2014.10-rc2-16959-g6eb2f0d-dirty (Sep 30 2014 - 10:28:19)
 
 CPU:   Freescale i.MX6SX rev1.0 at 792 MHz
 Reset cause: POR
 Board: MX6SX SABRE SDB
 I2C:   ready
 DRAM:  1 GiB
 MMC:   FSL_SDHC: 0
 In:serial
 Out:   serial
 Err:   serial
 PMIC:  PFUZE100 ID=0x10
 Net:   FEC [PRIME]
 Hit any key to stop autoboot:  0
 = hab_status
 
 Secure boot disabled
 
 (hangs the system)
 
 Could you please take a look at this issue?
 

I found the reason for the hang. The HAB api table was not
updated for i.MX6SX. Since i.MX6SX ROM implements unified
sections in ROM, the HAP function pointers needs to be
updated. I have sent a patch for the same.

-Nitin

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[U-Boot] [PATCH v1] imx6sx: Fix i.MX6SX HAB api function table offset

[Nitin Garg]

i.MX6SX ROM implements unified table sections.
The HAB function table is at offset 0x100. Update
the HAB function pointers accordingly.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
Tested-by: Fabio Estevam fabio.este...@freescale.com

---

 arch/arm/include/asm/arch-mx6/hab.h |   16 +++-
 include/configs/mx6_common.h|4 
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/hab.h 
b/arch/arm/include/asm/arch-mx6/hab.h
index 1f12695..c53709b 100644
--- a/arch/arm/include/asm/arch-mx6/hab.h
+++ b/arch/arm/include/asm/arch-mx6/hab.h
@@ -53,11 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, 
ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 
-#define HAB_RVT_REPORT_EVENT   (*(uint32_t *)0x00B4)
-#define HAB_RVT_REPORT_STATUS  (*(uint32_t *)0x00B8)
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x00A4)
-#define HAB_RVT_ENTRY  (*(uint32_t *)0x0098)
-#define HAB_RVT_EXIT   (*(uint32_t *)0x009C)
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
+#define HAB_RVT_BASE   0x0100
+#else
+#define HAB_RVT_BASE   0x0094
+#endif
+
+#define HAB_RVT_ENTRY  (*(uint32_t *)(HAB_RVT_BASE + 0x04))
+#define HAB_RVT_EXIT   (*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
+#define HAB_RVT_REPORT_EVENT   (*(uint32_t *)(HAB_RVT_BASE + 0x20))
+#define HAB_RVT_REPORT_STATUS  (*(uint32_t *)(HAB_RVT_BASE + 0x24))
 
 #define HAB_RVT_REPORT_EVENT_NEW   (*(uint32_t *)0x00B8)
 #define HAB_RVT_REPORT_STATUS_NEW  (*(uint32_t *)0x00BC)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 135a3f5..824e73f 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -30,4 +30,8 @@
 
 #define CONFIG_MP
 
+#ifdef CONFIG_MX6SX
+#define CONFIG_ROM_UNIFIED_SECTIONS
+#endif
+
 #endif
-- 
1.7.9.5

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[U-Boot] [PATCH v2] imx6sx: Fix i.MX6SX HAB api function table offset

[Nitin Garg]

i.MX6SX ROM implements unified table sections.
The HAB function table is at offset 0x100. Update
the HAB function pointers accordingly.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
Tested-by: Fabio Estevam fabio.este...@freescale.com

---

Changes in v2:
-Moved CONFIG_ROM_UNIFIED_SECTIONS to mx6_common.h
-Simplified hab.h changes
-Added Fabio as Tested-by

 arch/arm/include/asm/arch-mx6/hab.h |   16 +++-
 include/configs/mx6_common.h|4 
 2 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/hab.h 
b/arch/arm/include/asm/arch-mx6/hab.h
index 1f12695..c53709b 100644
--- a/arch/arm/include/asm/arch-mx6/hab.h
+++ b/arch/arm/include/asm/arch-mx6/hab.h
@@ -53,11 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, 
ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 
-#define HAB_RVT_REPORT_EVENT   (*(uint32_t *)0x00B4)
-#define HAB_RVT_REPORT_STATUS  (*(uint32_t *)0x00B8)
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x00A4)
-#define HAB_RVT_ENTRY  (*(uint32_t *)0x0098)
-#define HAB_RVT_EXIT   (*(uint32_t *)0x009C)
+#ifdef CONFIG_ROM_UNIFIED_SECTIONS
+#define HAB_RVT_BASE   0x0100
+#else
+#define HAB_RVT_BASE   0x0094
+#endif
+
+#define HAB_RVT_ENTRY  (*(uint32_t *)(HAB_RVT_BASE + 0x04))
+#define HAB_RVT_EXIT   (*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
+#define HAB_RVT_REPORT_EVENT   (*(uint32_t *)(HAB_RVT_BASE + 0x20))
+#define HAB_RVT_REPORT_STATUS  (*(uint32_t *)(HAB_RVT_BASE + 0x24))
 
 #define HAB_RVT_REPORT_EVENT_NEW   (*(uint32_t *)0x00B8)
 #define HAB_RVT_REPORT_STATUS_NEW  (*(uint32_t *)0x00BC)
diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h
index 135a3f5..824e73f 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -30,4 +30,8 @@
 
 #define CONFIG_MP
 
+#ifdef CONFIG_MX6SX
+#define CONFIG_ROM_UNIFIED_SECTIONS
+#endif
+
 #endif
-- 
1.7.9.5

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[U-Boot] [PATCH v3] imx6sx: Fix i.MX6SX HAB api function table offset

[Nitin Garg]

i.MX6SX ROM implements unified table sections.
The HAB function table is at offset 0x100. Update
the HAB function pointers accordingly.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
Tested-by: Fabio Estevam fabio.este...@freescale.com

---

Changes in v3:
-Removed CONFIG_ROM_UNIFIED_SECTIONS instead use
CONFIG_MX6SX

Changes in v2:
-Moved CONFIG_ROM_UNIFIED_SECTIONS to mx6_common.h
-Simplified hab.h changes
-Added Fabio as Tested-by

 arch/arm/include/asm/arch-mx6/hab.h |   16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/arch-mx6/hab.h 
b/arch/arm/include/asm/arch-mx6/hab.h
index 1f12695..c9e5318 100644
--- a/arch/arm/include/asm/arch-mx6/hab.h
+++ b/arch/arm/include/asm/arch-mx6/hab.h
@@ -53,11 +53,17 @@ typedef void *hab_rvt_authenticate_image_t(uint8_t, 
ptrdiff_t,
void **, size_t *, hab_loader_callback_f_t);
 typedef void hapi_clock_init_t(void);
 
-#define HAB_RVT_REPORT_EVENT   (*(uint32_t *)0x00B4)
-#define HAB_RVT_REPORT_STATUS  (*(uint32_t *)0x00B8)
-#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)0x00A4)
-#define HAB_RVT_ENTRY  (*(uint32_t *)0x0098)
-#define HAB_RVT_EXIT   (*(uint32_t *)0x009C)
+#ifdef CONFIG_MX6SX
+#define HAB_RVT_BASE   0x0100
+#else
+#define HAB_RVT_BASE   0x0094
+#endif
+
+#define HAB_RVT_ENTRY  (*(uint32_t *)(HAB_RVT_BASE + 0x04))
+#define HAB_RVT_EXIT   (*(uint32_t *)(HAB_RVT_BASE + 0x08))
+#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10))
+#define HAB_RVT_REPORT_EVENT   (*(uint32_t *)(HAB_RVT_BASE + 0x20))
+#define HAB_RVT_REPORT_STATUS  (*(uint32_t *)(HAB_RVT_BASE + 0x24))
 
 #define HAB_RVT_REPORT_EVENT_NEW   (*(uint32_t *)0x00B8)
 #define HAB_RVT_REPORT_STATUS_NEW  (*(uint32_t *)0x00BC)
-- 
1.7.9.5

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Re: [U-Boot] [PATCH v4] imx: Support i.MX6 High Assurance Boot authentication

[Nitin Garg]

Hi Stefano,

On 09/22/2014 09:07 AM, Stefano Babic wrote:
 Hi Nitin,
 
 On 16/09/2014 20:33, Nitin Garg wrote:
 When CONFIG_SECURE_BOOT is enabled, the signed images
 like kernel and dtb can be authenticated using iMX6 CAAM.
 The added command hab_auth_img can be used for HAB
 authentication of images. The command takes the image
 DDR location, IVT (Image Vector Table) offset inside
 image as parameters. Detailed info about signing images
 can be found in Freescale AppNote AN4581.

 Signed-off-by: Nitin Garg nitin.g...@freescale.com

 ---

 
 I wanted to apply it on current tree, but it seems it depends on
 mx6: clock: Add api to enable pll3. Or better, it seems in your tree
 on top the the patch for pll3. It is not an issue and I solve it myself,
 but can you confim that or do you prefer that I apply this one only
 after the thermal series will be merged ?
 
 Best regards,
 Stefano Babic
 
 

Yes you are correct, in my tree I did HAB patch on top of
temperature sensor patch. Pls resolve it or I can help if needed.
I do not have any preference with ordering of HAB and temperature patch.

Thanks,
Nitin Garg
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[U-Boot] [PATCH v4 1/5] mx6: crm_regs: Add bit definitions for anadig registers

[Nitin Garg]

Add bit definitons for various anadig registers as
required by various drivers.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/include/asm/arch-mx6/crm_regs.h |  543 +-
 1 file changed, 542 insertions(+), 1 deletion(-)

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h 
b/arch/arm/include/asm/arch-mx6/crm_regs.h
index e67b5b9..66a7cea 100644
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011-2014 Freescale Semiconductor, Inc. All Rights Reserved.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -1061,4 +1061,545 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
(((v)  0)  BM_ANADIG_PFD_528_PFD0_FRAC)
 
+#define HW_ANADIG_REG_1P1  (0x0110)
+#define HW_ANADIG_REG_1P1_SET  (0x0114)
+#define HW_ANADIG_REG_1P1_CLR  (0x0118)
+#define HW_ANADIG_REG_1P1_TOG  (0x011c)
+
+#define BP_ANADIG_REG_1P1_RSVD2  18
+#define BM_ANADIG_REG_1P1_RSVD2 0xFFFC
+#define BF_ANADIG_REG_1P1_RSVD2(v) \
+   (((v)  18)  BM_ANADIG_REG_1P1_RSVD2)
+#define BM_ANADIG_REG_1P1_OK_VDD1P1 0x0002
+#define BM_ANADIG_REG_1P1_BO_VDD1P1 0x0001
+#define BP_ANADIG_REG_1P1_RSVD1  13
+#define BM_ANADIG_REG_1P1_RSVD1 0xE000
+#define BF_ANADIG_REG_1P1_RSVD1(v)  \
+   (((v)  13)  BM_ANADIG_REG_1P1_RSVD1)
+#define BP_ANADIG_REG_1P1_OUTPUT_TRG  8
+#define BM_ANADIG_REG_1P1_OUTPUT_TRG 0x1F00
+#define BF_ANADIG_REG_1P1_OUTPUT_TRG(v)  \
+   (((v)  8)  BM_ANADIG_REG_1P1_OUTPUT_TRG)
+#define BM_ANADIG_REG_1P1_RSVD0 0x0080
+#define BP_ANADIG_REG_1P1_BO_OFFSET  4
+#define BM_ANADIG_REG_1P1_BO_OFFSET 0x0070
+#define BF_ANADIG_REG_1P1_BO_OFFSET(v)  \
+   (((v)  4)  BM_ANADIG_REG_1P1_BO_OFFSET)
+#define BM_ANADIG_REG_1P1_ENABLE_PULLDOWN 0x0008
+#define BM_ANADIG_REG_1P1_ENABLE_ILIMIT 0x0004
+#define BM_ANADIG_REG_1P1_ENABLE_BO 0x0002
+#define BM_ANADIG_REG_1P1_ENABLE_LINREG 0x0001
+
+#define HW_ANADIG_REG_3P0  (0x0120)
+#define HW_ANADIG_REG_3P0_SET  (0x0124)
+#define HW_ANADIG_REG_3P0_CLR  (0x0128)
+#define HW_ANADIG_REG_3P0_TOG  (0x012c)
+
+#define BP_ANADIG_REG_3P0_RSVD2  18
+#define BM_ANADIG_REG_3P0_RSVD2 0xFFFC
+#define BF_ANADIG_REG_3P0_RSVD2(v) \
+   (((v)  18)  BM_ANADIG_REG_3P0_RSVD2)
+#define BM_ANADIG_REG_3P0_OK_VDD3P0 0x0002
+#define BM_ANADIG_REG_3P0_BO_VDD3P0 0x0001
+#define BP_ANADIG_REG_3P0_RSVD1  13
+#define BM_ANADIG_REG_3P0_RSVD1 0xE000
+#define BF_ANADIG_REG_3P0_RSVD1(v)  \
+   (((v)  13)  BM_ANADIG_REG_3P0_RSVD1)
+#define BP_ANADIG_REG_3P0_OUTPUT_TRG  8
+#define BM_ANADIG_REG_3P0_OUTPUT_TRG 0x1F00
+#define BF_ANADIG_REG_3P0_OUTPUT_TRG(v)  \
+   (((v)  8)  BM_ANADIG_REG_3P0_OUTPUT_TRG)
+#define BM_ANADIG_REG_3P0_VBUS_SEL 0x0080
+#define BP_ANADIG_REG_3P0_BO_OFFSET  4
+#define BM_ANADIG_REG_3P0_BO_OFFSET 0x0070
+#define BF_ANADIG_REG_3P0_BO_OFFSET(v)  \
+   (((v)  4)  BM_ANADIG_REG_3P0_BO_OFFSET)
+#define BM_ANADIG_REG_3P0_RSVD0 0x0008
+#define BM_ANADIG_REG_3P0_ENABLE_ILIMIT 0x0004
+#define BM_ANADIG_REG_3P0_ENABLE_BO 0x0002
+#define BM_ANADIG_REG_3P0_ENABLE_LINREG 0x0001
+
+#define HW_ANADIG_REG_2P5  (0x0130)
+#define HW_ANADIG_REG_2P5_SET  (0x0134)
+#define HW_ANADIG_REG_2P5_CLR  (0x0138)
+#define HW_ANADIG_REG_2P5_TOG  (0x013c)
+
+#define BP_ANADIG_REG_2P5_RSVD2  19
+#define BM_ANADIG_REG_2P5_RSVD2 0xFFF8
+#define BF_ANADIG_REG_2P5_RSVD2(v) \
+   (((v)  19)  BM_ANADIG_REG_2P5_RSVD2)
+#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x0004
+#define BM_ANADIG_REG_2P5_OK_VDD2P5 0x0002
+#define BM_ANADIG_REG_2P5_BO_VDD2P5 0x0001
+#define BP_ANADIG_REG_2P5_RSVD1  13
+#define BM_ANADIG_REG_2P5_RSVD1 0xE000
+#define BF_ANADIG_REG_2P5_RSVD1(v)  \
+   (((v)  13)  BM_ANADIG_REG_2P5_RSVD1)
+#define BP_ANADIG_REG_2P5_OUTPUT_TRG  8
+#define BM_ANADIG_REG_2P5_OUTPUT_TRG 0x1F00
+#define BF_ANADIG_REG_2P5_OUTPUT_TRG(v)  \
+   (((v)  8)  BM_ANADIG_REG_2P5_OUTPUT_TRG)
+#define BM_ANADIG_REG_2P5_RSVD0 0x0080
+#define BP_ANADIG_REG_2P5_BO_OFFSET  4
+#define BM_ANADIG_REG_2P5_BO_OFFSET 0x0070
+#define BF_ANADIG_REG_2P5_BO_OFFSET(v)  \
+   (((v)  4)  BM_ANADIG_REG_2P5_BO_OFFSET)
+#define BM_ANADIG_REG_2P5_ENABLE_PULLDOWN 0x0008
+#define BM_ANADIG_REG_2P5_ENABLE_ILIMIT 0x0004
+#define BM_ANADIG_REG_2P5_ENABLE_BO 0x0002
+#define BM_ANADIG_REG_2P5_ENABLE_LINREG 0x0001
+
+#define HW_ANADIG_REG_CORE (0x0140)
+#define HW_ANADIG_REG_CORE_SET (0x0144)
+#define HW_ANADIG_REG_CORE_CLR (0x0148)
+#define HW_ANADIG_REG_CORE_TOG (0x014c)
+
+#define BM_ANADIG_REG_CORE_REF_SHIFT 0x8000
+#define BM_ANADIG_REG_CORE_RSVD0 0x4000
+#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x2000

[U-Boot] [PATCH v4 3/5] mx6: thermal: Add i.MX6 CPU thermal sensor support

[Nitin Garg]

i.MX6 SoC has onchip temperature sensor. Add driver
for this sensor.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/Makefile  |1 +
 drivers/thermal/Makefile  |8 +++
 drivers/thermal/imx_thermal.c |  137 +
 include/imx_thermal.h |   15 +
 4 files changed, 161 insertions(+)
 create mode 100644 drivers/thermal/Makefile
 create mode 100644 drivers/thermal/imx_thermal.c
 create mode 100644 include/imx_thermal.h

diff --git a/drivers/Makefile b/drivers/Makefile
index b22b109..fc57e49 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -16,3 +16,4 @@ obj-y += watchdog/
 obj-$(CONFIG_QE) += qe/
 obj-y += memory/
 obj-y += pwm/
+obj-y += thermal/
diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile
new file mode 100644
index 000..04ae395
--- /dev/null
+++ b/drivers/thermal/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014 Freescale Semiconductor, Inc.
+# Author: Nitin Garg nitin.g...@freescale.com
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-$(CONFIG_IMX6_THERMAL) += imx_thermal.o
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
new file mode 100644
index 000..3b53b61
--- /dev/null
+++ b/drivers/thermal/imx_thermal.c
@@ -0,0 +1,137 @@
+/*
+ * (C) Copyright 2014 Freescale Semiconductor, Inc.
+ * Author: Nitin Garg nitin.g...@freescale.com
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#include config.h
+#include common.h
+#include div64.h
+#include fuse.h
+#include asm/io.h
+#include asm/arch/crm_regs.h
+#include asm/arch/clock.h
+
+#define TEMPERATURE_MIN-40
+#define TEMPERATURE_HOT80
+#define TEMPERATURE_MAX125
+#define FACTOR01000
+#define FACTOR115976
+#define FACTOR24297157
+#define MEASURE_FREQ   327
+
+static int read_cpu_temperature(u32 fuse)
+{
+   int temperature;
+   unsigned int reg, n_meas;
+   struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+   int t1, n1;
+   u32 c1, c2;
+   u64 temp64;
+
+   /* make sure pll3 is enabled for thermal sensor */
+   enable_pll3();
+
+   /*
+* Sensor data layout:
+*   [31:20] - sensor value @ 25C
+* We use universal formula now and only need sensor value @ 25C
+* slope = 0.4297157 - (0.0015976 * 25C fuse)
+*/
+   n1 = fuse  20;
+   t1 = 25; /* t1 always 25C */
+
+   /*
+* Derived from linear interpolation:
+* slope = 0.4297157 - (0.0015976 * 25C fuse)
+* slope = (FACTOR2 - FACTOR1 * n1) / FACTOR0
+* (Nmeas - n1) / (Tmeas - t1) = slope
+* We want to reduce this down to the minimum computation necessary
+* for each temperature read.  Also, we want Tmeas in millicelsius
+* and we don't want to lose precision from integer division. So...
+* Tmeas = (Nmeas - n1) / slope + t1
+* milli_Tmeas = 1000 * (Nmeas - n1) / slope + 1000 * t1
+* milli_Tmeas = -1000 * (n1 - Nmeas) / slope + 1000 * t1
+* Let constant c1 = (-1000 / slope)
+* milli_Tmeas = (n1 - Nmeas) * c1 + 1000 * t1
+* Let constant c2 = n1 *c1 + 1000 * t1
+* milli_Tmeas = c2 - Nmeas * c1
+*/
+   temp64 = FACTOR0;
+   temp64 *= 1000;
+   do_div(temp64, FACTOR1 * n1 - FACTOR2);
+   c1 = temp64;
+   c2 = n1 * c1 + 1000 * t1;
+
+   /*
+* now we only use single measure, every time we read
+* the temperature, we will power on/down anadig thermal
+* module
+*/
+   writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, anatop-tempsense0_clr);
+   writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, anatop-ana_misc0_set);
+
+   /* setup measure freq */
+   reg = readl(anatop-tempsense1);
+   reg = ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ;
+   reg |= MEASURE_FREQ;
+   writel(reg, anatop-tempsense1);
+
+   /* start the measurement process */
+   writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, anatop-tempsense0_clr);
+   writel(BM_ANADIG_TEMPSENSE0_FINISHED, anatop-tempsense0_clr);
+   writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, anatop-tempsense0_set);
+
+   /* make sure that the latest temp is valid */
+   while ((readl(anatop-tempsense0) 
+   BM_ANADIG_TEMPSENSE0_FINISHED) == 0)
+   udelay(1);
+
+   /* read temperature count */
+   reg = readl(anatop-tempsense0);
+   n_meas = (reg  BM_ANADIG_TEMPSENSE0_TEMP_VALUE)
+BP_ANADIG_TEMPSENSE0_TEMP_VALUE;
+   writel(BM_ANADIG_TEMPSENSE0_FINISHED, anatop-tempsense0_clr);
+
+   /* milli_Tmeas = c2 - Nmeas * c1 */
+   temperature = (c2 - n_meas * c1)/1000;
+
+   /* power down anatop thermal sensor */
+   writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, anatop-tempsense0_set

[U-Boot] [PATCH v4 2/5] mx6: clock: Add api to enable pll3

[Nitin Garg]

Add api to check and enable pll3 as required
for thermal sensor driver.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/cpu/armv7/mx6/clock.c|   25 +
 arch/arm/include/asm/arch-mx6/clock.h |1 +
 2 files changed, 26 insertions(+)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5..8a0 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -543,6 +543,31 @@ int enable_pcie_clock(void)
   BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
 
+void enable_pll3(void)
+{
+   struct anatop_regs __iomem *anatop =
+   (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
+
+   /* make sure pll3 is enabled */
+   if ((readl(anatop-usb1_pll_480_ctrl) 
+   BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
+   /* enable pll's power */
+   writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
+  anatop-usb1_pll_480_ctrl_set);
+   writel(0x80, anatop-ana_misc2_clr);
+   /* wait for pll lock */
+   while ((readl(anatop-usb1_pll_480_ctrl) 
+   BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
+   ;
+   /* disable bypass */
+   writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
+  anatop-usb1_pll_480_ctrl_clr);
+   /* enable pll output */
+   writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
+  anatop-usb1_pll_480_ctrl_set);
+   }
+}
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
switch (clk) {
diff --git a/arch/arm/include/asm/arch-mx6/clock.h 
b/arch/arm/include/asm/arch-mx6/clock.h
index 339c789..fd4b860 100644
--- a/arch/arm/include/asm/arch-mx6/clock.h
+++ b/arch/arm/include/asm/arch-mx6/clock.h
@@ -60,4 +60,5 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
 int enable_spi_clk(unsigned char enable, unsigned spi_num);
 void enable_ipu_clock(void);
 int enable_fec_anatop_clock(enum enet_freq freq);
+void enable_pll3(void);
 #endif /* __ASM_ARCH_CLOCK_H */
-- 
1.7.9.5

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[U-Boot] [PATCH v4 0/5] add i.MX6 thermal sensor driver

[Nitin Garg]

This patch set adds i.MX6 thermal sensor driver
and enables it for mx6sabre boards. Also adds
various anadig bit definitions as required for
upcoming drivers.

Changes in v4:
-Added imx6 thermal sensor as a driver
-Renamed the config define to be more meaningful
-Move the clock code to clock.c
-Reusing ocotp driver for reading fuse
-Fix check for calibration fuse not programmed
-Aligned the slope computation with kernel
-Added Anadig register defines as seperate commit

Changes in v3:
-adds the mx6 temperature support
-adds the mx6 temperature support to mx6sabresd board.

Changes in v2:
-run checkpatch and fix reported issues

Nitin Garg (5):
  mx6: crm_regs: Add bit definitions for anadig registers
  mx6: clock: Add api to enable pll3
  mx6: thermal: Add i.MX6 CPU thermal sensor support
  mx6: thermal: Check cpu temperature via thermal sensor
  mx6: thermal: Enable thermal sensor for mx6 sabre boards.

 arch/arm/cpu/armv7/mx6/clock.c   |   25 ++
 arch/arm/imx-common/cpu.c|8 +-
 arch/arm/include/asm/arch-mx6/clock.h|1 +
 arch/arm/include/asm/arch-mx6/crm_regs.h |  543 +-
 drivers/Makefile |1 +
 drivers/thermal/Makefile |8 +
 drivers/thermal/imx_thermal.c|  137 
 include/configs/mx6sabre_common.h|3 +-
 include/imx_thermal.h|   15 +
 9 files changed, 738 insertions(+), 3 deletions(-)
 create mode 100644 drivers/thermal/Makefile
 create mode 100644 drivers/thermal/imx_thermal.c
 create mode 100644 include/imx_thermal.h

-- 
1.7.9.5

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[U-Boot] [PATCH v4 5/5] mx6: thermal: Enable thermal sensor for mx6 sabre boards.

[Nitin Garg]

Add CONFIG_IMX6_THERMAL to mx6sabre_common.h file. Since
thermal driver depends on ocotp, make sure to enable
CONFIG_MXC_OCOTP when CONFIG_IMX6_THERMAL is slected.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

Changes in v4:
-Added imx6 thermal sensor as a driver
-Renamed the config define to be more meaningful
-Move the clock code to clock.c
-Reusing ocotp driver for reading fuse
-Fix check for calibration fuse not programmed
-Aligned the slope computation with kernel
-Added Anadig register defines as seperate commit

Changes in v3:
-adds the mx6 temperature support
-adds the mx6 temperature support to mx6sabresd board.

Changes in v2:
-run checkpatch and fix reported issues

 include/configs/mx6sabre_common.h |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/configs/mx6sabre_common.h 
b/include/configs/mx6sabre_common.h
index e59a3b4..4297596 100644
--- a/include/configs/mx6sabre_common.h
+++ b/include/configs/mx6sabre_common.h
@@ -24,6 +24,7 @@
 #define CONFIG_SETUP_MEMORY_TAGS
 #define CONFIG_INITRD_TAG
 #define CONFIG_REVISION_TAG
+#define CONFIG_IMX6_THERMAL
 
 #define CONFIG_SYS_GENERIC_BOARD
 
@@ -37,7 +38,7 @@
 #define CONFIG_MXC_UART
 
 #define CONFIG_CMD_FUSE
-#ifdef CONFIG_CMD_FUSE
+#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL)
 #define CONFIG_MXC_OCOTP
 #endif
 
-- 
1.7.9.5

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[U-Boot] [PATCH v4 4/5] mx6: thermal: Check cpu temperature via thermal sensor

[Nitin Garg]

read cpu temperature using the onchip thermal
sensor.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

Changes in v4: None
Changes in v3: None
Changes in v2: None

 arch/arm/imx-common/cpu.c |8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/arch/arm/imx-common/cpu.c b/arch/arm/imx-common/cpu.c
index ed826a0..10e1b05 100644
--- a/arch/arm/imx-common/cpu.c
+++ b/arch/arm/imx-common/cpu.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2007
  * Sascha Hauer, Pengutronix
  *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2009-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -15,6 +15,7 @@
 #include asm/arch/sys_proto.h
 #include asm/arch/crm_regs.h
 #include ipu_pixfmt.h
+#include imx_thermal.h
 
 #ifdef CONFIG_FSL_ESDHC
 #include fsl_esdhc.h
@@ -139,6 +140,11 @@ int print_cpuinfo(void)
(cpurev  0x000F0)  4,
(cpurev  0xF)  0,
mxc_get_clock(MXC_ARM_CLK) / 100);
+
+#if defined(CONFIG_MX6)  defined(CONFIG_IMX6_THERMAL)
+   check_cpu_temperature();
+#endif
+
printf(Reset cause: %s\n, get_reset_cause());
return 0;
 }
-- 
1.7.9.5

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[U-Boot] [PATCH v4] imx: Support i.MX6 High Assurance Boot authentication

[Nitin Garg]

When CONFIG_SECURE_BOOT is enabled, the signed images
like kernel and dtb can be authenticated using iMX6 CAAM.
The added command hab_auth_img can be used for HAB
authentication of images. The command takes the image
DDR location, IVT (Image Vector Table) offset inside
image as parameters. Detailed info about signing images
can be found in Freescale AppNote AN4581.

Signed-off-by: Nitin Garg nitin.g...@freescale.com

---

Changes in v4:
- Use single hab_caam_clock_enable api for en/disable
- Remove unused DEBUG_AUTHENTICATE_IMAGE
- Use DEBUG instead of DEBUG_AUTHENTICATE_IMAGE
- Add defined for pu_irom_mmu_enabled var location
- Add MMU check before setting ROM variable
- Replace printf with puts where applicable

Changes in v3:
- Remove typecast of get_cpu_rev since its not required

Changes in v2:
- Cleaned up clock code as per review comments
- Removed dead code as per review comments
- Re-written commit log as per review comments

 arch/arm/cpu/armv7/mx6/clock.c|   27 ++
 arch/arm/cpu/armv7/mx6/hab.c  |  169 -
 arch/arm/cpu/armv7/mx6/soc.c  |   15 +++
 arch/arm/include/asm/arch-mx6/clock.h |1 +
 4 files changed, 211 insertions(+), 1 deletion(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 8a0..48f0bdd 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -568,6 +568,33 @@ void enable_pll3(void)
}
 }
 
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(unsigned char enable)
+{
+   u32 reg;
+
+   /* CG4 ~ CG6, CAAM clocks */
+   reg = __raw_readl(imx_ccm-CCGR0);
+   if (enable)
+   reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+   MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+   MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+   else
+   reg = ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+   MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+   MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+   __raw_writel(reg, imx_ccm-CCGR0);
+
+   /* EMI slow clk */
+   reg = __raw_readl(imx_ccm-CCGR6);
+   if (enable)
+   reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+   else
+   reg = ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+   __raw_writel(reg, imx_ccm-CCGR6);
+}
+#endif
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
switch (clk) {
diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c
index f6810a6..8dee595 100644
--- a/arch/arm/cpu/armv7/mx6/hab.c
+++ b/arch/arm/cpu/armv7/mx6/hab.c
@@ -1,12 +1,14 @@
 /*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
 
 #include common.h
 #include asm/io.h
+#include asm/system.h
 #include asm/arch/hab.h
+#include asm/arch/clock.h
 #include asm/arch/sys_proto.h
 
 /*  start of HAB API updates */
@@ -71,6 +73,44 @@
((hab_rvt_exit_t *)HAB_RVT_EXIT)\
 )
 
+#define IVT_SIZE   0x20
+#define ALIGN_SIZE 0x1000
+#define CSF_PAD_SIZE   0x2000
+#define MX6DQ_PU_IROM_MMU_EN_VAR   0x009024a8
+#define MX6DLS_PU_IROM_MMU_EN_VAR  0x00901dd0
+#define MX6SL_PU_IROM_MMU_EN_VAR   0x00900a18
+
+/*
+ * ++  0x0 (DDR_UIMAGE_START) -
+ * |   Header   |  |
+ * ++  0x40|
+ * ||  |
+ * ||  |
+ * ||  |
+ * ||  |
+ * | Image Data |  |
+ * .|  |
+ * .|Stuff to be authenticated +
+ * .|  ||
+ * ||  ||
+ * ||  ||
+ * ++  ||
+ * ||  ||
+ * | Fill Data  |  ||
+ * ||  ||
+ * ++ Align to ALIGN_SIZE  ||
+ * |IVT |  ||
+ * ++ + IVT_SIZE  - |
+ * ||   |
+ * |  CSF DATA  | -+
+ * ||
+ * ++
+ * ||
+ * | Fill Data  |
+ * ||
+ * ++ + CSF_PAD_SIZE
+ */
+
 bool is_hab_enabled(void)
 {
struct ocotp_regs *ocotp

Re: [U-Boot] [PATCH v3] imx: Support i.MX6 High Assurance Boot authentication

[Nitin Garg]

Hi Stefano,

On 09/12/2014 03:46 AM, Stefano Babic wrote:
 Hi Nitin,
 
 On 04/09/2014 03:18, Nitin Garg wrote:
 When CONFIG_SECURE_BOOT is enabled, the signed images
 like kernel and dtb can be authenticated using iMX6 CAAM.
 The added command hab_auth_img can be used for HAB
 authentication of images. The command takes the image
 DDR location, IVT (Image Vector Table) offset inside
 image as parameters. Detailed info about signing images
 can be found in Freescale AppNote AN4581.

 Signed-off-by: Nitin Garg nitin.g...@freescale.com

 ---

 Changes in v3:
 - Remove typecast of get_cpu_rev since its not required

 Changes in v2:
 - Cleaned up clock code as per review comments
 - Removed dead code as per review comments
 - Re-written commit log as per review comments

  arch/arm/cpu/armv7/mx6/clock.c|   32 ++-
  arch/arm/cpu/armv7/mx6/hab.c  |  165 
 -
  arch/arm/cpu/armv7/mx6/soc.c  |   15 +++
  arch/arm/include/asm/arch-mx6/clock.h |4 +
  4 files changed, 214 insertions(+), 2 deletions(-)

 diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
 index 820b8d5..db6a8fc 100644
 --- a/arch/arm/cpu/armv7/mx6/clock.c
 +++ b/arch/arm/cpu/armv7/mx6/clock.c
 @@ -1,5 +1,5 @@
  /*
 - * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
 + * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
   *
   * SPDX-License-Identifier: GPL-2.0+
   */
 @@ -543,6 +543,36 @@ int enable_pcie_clock(void)
 BM_ANADIG_PLL_ENET_ENABLE_PCIE);
  }
  
 +#ifdef CONFIG_SECURE_BOOT
 +void hab_caam_clock_enable(void)
 +{
 +struct mxc_ccm_reg *const imx_ccm =
 +(struct mxc_ccm_reg *)CCM_BASE_ADDR;
 +
 +/*CG4 ~ CG6, enable CAAM clocks*/
 +setbits_le32(imx_ccm-CCGR0, MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 + MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 +
 +/* Enable EMI slow clk */
 +setbits_le32(imx_ccm-CCGR6, MXC_CCM_CCGR6_EMI_SLOW_MASK);
 +}
 +
 +void hab_caam_clock_disable(void)
 +{
 +struct mxc_ccm_reg *const imx_ccm =
 +(struct mxc_ccm_reg *)CCM_BASE_ADDR;
 +
 +/*CG4 ~ CG6, disable CAAM clocks*/
 +clrbits_le32(imx_ccm-CCGR0, MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
 + MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
 + MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
 +
 +/* Disable EMI slow clk */
 +clrbits_le32(imx_ccm-CCGR6, MXC_CCM_CCGR6_EMI_SLOW_MASK);
 +}
 +#endif
 
 
 Generally, we have in clock.c one function per clock, getting as
 enable_uart_clkparameter a boolean for enabling/disabling (i.e.
 enable_ocotp_clk(), enable_uart_clk(),...)
 
 Please stick with the same rule.
Accepted. Rework in v4.

 
 +
  unsigned int mxc_get_clock(enum mxc_clock clk)
  {
  switch (clk) {
 diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c
 index f6810a6..61a94a1 100644
 --- a/arch/arm/cpu/armv7/mx6/hab.c
 +++ b/arch/arm/cpu/armv7/mx6/hab.c
 @@ -1,5 +1,5 @@
  /*
 - * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
 + * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
   *
   * SPDX-License-Identifier:GPL-2.0+
   */
 @@ -7,8 +7,12 @@
  #include common.h
  #include asm/io.h
  #include asm/arch/hab.h
 +#include asm/arch/clock.h
  #include asm/arch/sys_proto.h
  
 +/* HAB (High Assurance Boot) debug */
 +#undef DEBUG_AUTHENTICATE_IMAGE
 
 This is never defined, you do not need to undefine it.
Accepted. Rework in v4.

 
 +
  /*  start of HAB API updates */
  
  #define hab_rvt_report_event_p  \
 @@ -71,6 +75,41 @@
  ((hab_rvt_exit_t *)HAB_RVT_EXIT)\
  )
  
 +#define IVT_SIZE0x20
 +#define ALIGN_SIZE  0x1000
 +#define CSF_PAD_SIZE0x2000
 +
 +/*
 + * ++  0x0 (DDR_UIMAGE_START) -
 + * |   Header   |  |
 + * ++  0x40|
 + * ||  |
 + * ||  |
 + * ||  |
 + * ||  |
 + * | Image Data |  |
 + * .|  |
 + * .|Stuff to be authenticated 
 +
 + * .|  |
 |
 + * ||  |
 |
 + * ||  |
 |
 + * ++  |
 |
 + * ||  |
 |
 + * | Fill Data  |  |
 |
 + * ||  |
 |
 + * ++ Align to ALIGN_SIZE

Re: [U-Boot] [PATCH 1/2 v3] Add i.MX6 CPU temperature sensor support

[Nitin Garg]

Hi Stefano,

On 09/11/2014 04:01 AM, Stefano Babic wrote:
 Hi Nitin,
 
 
 On 02/09/2014 00:48, nitin.g...@freescale.com wrote:
 From: Nitin Garg nitin.g...@freescale.com

 i.MX6 SoC has onChip temperature sensor. Add support
 for this sensor.

 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 ---
  arch/arm/cpu/armv7/mx6/soc.c |  138 +++-
  arch/arm/imx-common/cpu.c|7 +-
  arch/arm/include/asm/arch-mx6/crm_regs.h |  543 
 +-
  arch/arm/include/asm/arch-mx6/imx-regs.h |9 +-
  4 files changed, 693 insertions(+), 4 deletions(-)

 
 I tend to consider this as a driver instead of a couple of functions to
 read/check temperature. Hiding this code inside cpu code does not get an
 overview about which API is used. If another SOC (not necessarily
 Freescale) will add such kind of functionality, we will have probably a
 different API.
 
 I would prefer, without reinventing the wheel, to follow the kernel
 approach and move this code into a driver, let's say into
 drivers/thermal. Feel free to add this directory to u-boot tree. A name
 as imx-thermal as in kernel looks to me appropriate for your code.
Accepted. Reworked in v4.

 
 diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
 index ac84a1f..b0c1306 100644
 --- a/arch/arm/cpu/armv7/mx6/soc.c
 +++ b/arch/arm/cpu/armv7/mx6/soc.c
 @@ -2,7 +2,7 @@
   * (C) Copyright 2007
   * Sascha Hauer, Pengutronix
   *
 - * (C) Copyright 2009 Freescale Semiconductor, Inc.
 + * (C) Copyright 2009-2014 Freescale Semiconductor, Inc.
   *
   * SPDX-License-Identifier: GPL-2.0+
   */
 @@ -35,6 +35,16 @@ struct scu_regs {
  u32 fpga_rev;
  };
  
 +#define TEMPERATURE_MIN -40
 +#define TEMPERATURE_HOT 80
 +#define TEMPERATURE_MAX 125
 +#define FACTOR1 15976
 +#define FACTOR2 4297157
 +#define MEASURE_FREQ327
 +
 +#define REG_VALUE_TO_CEL(ratio, raw) \
 +((raw_n40c - raw) * 100 / ratio - 40)
 +
  u32 get_nr_cpus(void)
  {
  struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
 @@ -218,6 +228,132 @@ static void imx_set_wdog_powerdown(bool enable)
  writew(enable, wdog2-wmcr);
  }
  
 +#ifdef CONFIG_IMX6_TEMP_SENSOR
 
 TEMP is rather a misleading name. It can be confused with temporary.
 Maybe CONFIG_IMX_THERMAL or CONFIG_IMX_THERMAL_SENSOR ?
 
Accepted. Reworked in v4.

 +static int read_cpu_temperature(u32 *fuse)
 +{
 +int temperature;
 +unsigned int ccm_ccgr2;
 +unsigned int reg, tmp;
 +unsigned int raw_25c, raw_n40c, ratio;
 +struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 +struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 +struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
 +struct fuse_bank *bank = ocotp-bank[1];
 +struct fuse_bank1_regs *fuse_bank1 =
 +(struct fuse_bank1_regs *)bank-fuse_regs;
 +
 +/* need to make sure pll3 is enabled for thermal sensor */
 
 The code to enable a clock should go into armv7/mx6/clock.c.
 
Accepted. Reworked in v4.

 +if ((readl(anatop-usb1_pll_480_ctrl) 
 +BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
 +/* enable pll's power */
 +writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
 +   anatop-usb1_pll_480_ctrl_set);
 +writel(0x80, anatop-ana_misc2_clr);
 +/* wait for pll lock */
 +while ((readl(anatop-usb1_pll_480_ctrl) 
 +BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
 +;
 +/* disable bypass */
 +writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
 +   anatop-usb1_pll_480_ctrl_clr);
 +/* enable pll output */
 +writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
 +   anatop-usb1_pll_480_ctrl_set);
 +}
 +
 +ccm_ccgr2 = readl(mxc_ccm-CCGR2);
 +/* enable OCOTP_CTRL clock in CCGR2 */
 +writel(ccm_ccgr2 | MXC_CCM_CCGR2_OCOTP_CTRL_MASK, mxc_ccm-CCGR2);
 
 You are readding the same code we have already merged. We have a ocotp
 driver in u-boot, and this uses enable_ocotp_clk() to enable and disable
 the clock. Please use also the functions provide by the ocotp driver. I
 suggest you add a Kconfig rule to make this driver dependend on ocotp.
 
Since OCOTP in not in Kconfig (instead in header), I have added a rule in
config header to enable OCOTP when IMX6_THERMAL is enabled. Pls accept.


 +*fuse = readl(fuse_bank1-ana1);
 +
 +/* restore CCGR2 */
 +writel(ccm_ccgr2, mxc_ccm-CCGR2);
 +
 +if (*fuse == 0 || *fuse == 0x || (*fuse  0xfff0) == 0)
 +return TEMPERATURE_MIN;
 +
 
 Does it mean invalid values ? According to manual, the register is split
 into three different regions (Room, Hot_count, Hot_temp) and I am
 wondering we can simply compare the whole register. If your check means
 that you are reading

Re: [U-Boot] [PATCH 2/2] iMX6SLEVK: Change to use generic board

[Nitin Garg]

On 09/03/2014 04:43 AM, Ye.Li wrote:
 Enable CONFIG_SYS_GENERIC_BOARD for imx6slevk to use generic board.
 
 Signed-off-by: Ye.Li b37...@freescale.com
 ---
  include/configs/mx6slevk.h |2 ++
  1 files changed, 2 insertions(+), 0 deletions(-)
 
 diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h
 index 3d05a64..194d7bd 100644
 --- a/include/configs/mx6slevk.h
 +++ b/include/configs/mx6slevk.h
 @@ -26,6 +26,8 @@
  #define CONFIG_INITRD_TAG
  #define CONFIG_REVISION_TAG
  
 +#define CONFIG_SYS_GENERIC_BOARD
 +
  /* Size of malloc() pool */
  #define CONFIG_SYS_MALLOC_LEN(3 * SZ_1M)
  
 

Acked-by: Nitin Garg nitin.g...@freescale.com
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Re: [U-Boot] [PATCH 1/2] iMX6Q/DL:ARM2: Change to use generic board

[Nitin Garg]

On 09/03/2014 04:43 AM, Ye.Li wrote:
 Enable the CONFIG_SYS_GENERIC_BOARD for imx6q/dl arm2 board to
 use generic board.
 
 Signed-off-by: Ye.Li b37...@freescale.com
 ---
  include/configs/mx6qarm2.h |2 ++
  1 files changed, 2 insertions(+), 0 deletions(-)
 
 diff --git a/include/configs/mx6qarm2.h b/include/configs/mx6qarm2.h
 index f314b31..3566b15 100644
 --- a/include/configs/mx6qarm2.h
 +++ b/include/configs/mx6qarm2.h
 @@ -22,6 +22,8 @@
  #define CONFIG_SETUP_MEMORY_TAGS
  #define CONFIG_INITRD_TAG
  
 +#define CONFIG_SYS_GENERIC_BOARD
 +
  /* Size of malloc() pool */
  #define CONFIG_SYS_MALLOC_LEN(CONFIG_ENV_SIZE + 2 * 1024 * 
 1024)
  
 

Acked-by: Nitin Garg nitin.g...@freescale.com
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Re: [U-Boot] [PATCH] Support i.MX6 High Assurance Boot (HAB) authentication of images

[Nitin Garg]

On 09/03/2014 07:10 PM, Fabio Estevam wrote:
 On Tue, Sep 2, 2014 at 10:55 PM, Nitin Garg nitin.g...@freescale.com wrote:
 
 In the macros of HAB, like:
 hab_rvt_report_event_p

 The compiler generates bhi instead of bgt.
 
 hab_rvt_report_event_p exists prior to this patch. Is the issue
 present in current code then?
 
 If so, it should be handled on a separate patch.
 
I will remove the typecast as its not essential (I stepped
through the code today and its fine).
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[U-Boot] [PATCH v3] imx: Support i.MX6 High Assurance Boot authentication

[Nitin Garg]

When CONFIG_SECURE_BOOT is enabled, the signed images
like kernel and dtb can be authenticated using iMX6 CAAM.
The added command hab_auth_img can be used for HAB
authentication of images. The command takes the image
DDR location, IVT (Image Vector Table) offset inside
image as parameters. Detailed info about signing images
can be found in Freescale AppNote AN4581.

Signed-off-by: Nitin Garg nitin.g...@freescale.com

---

Changes in v3:
- Remove typecast of get_cpu_rev since its not required

Changes in v2:
- Cleaned up clock code as per review comments
- Removed dead code as per review comments
- Re-written commit log as per review comments

 arch/arm/cpu/armv7/mx6/clock.c|   32 ++-
 arch/arm/cpu/armv7/mx6/hab.c  |  165 -
 arch/arm/cpu/armv7/mx6/soc.c  |   15 +++
 arch/arm/include/asm/arch-mx6/clock.h |4 +
 4 files changed, 214 insertions(+), 2 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5..db6a8fc 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -543,6 +543,36 @@ int enable_pcie_clock(void)
   BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
 
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(void)
+{
+   struct mxc_ccm_reg *const imx_ccm =
+   (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   /*CG4 ~ CG6, enable CAAM clocks*/
+   setbits_le32(imx_ccm-CCGR0, MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+
+   /* Enable EMI slow clk */
+   setbits_le32(imx_ccm-CCGR6, MXC_CCM_CCGR6_EMI_SLOW_MASK);
+}
+
+void hab_caam_clock_disable(void)
+{
+   struct mxc_ccm_reg *const imx_ccm =
+   (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   /*CG4 ~ CG6, disable CAAM clocks*/
+   clrbits_le32(imx_ccm-CCGR0, MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+
+   /* Disable EMI slow clk */
+   clrbits_le32(imx_ccm-CCGR6, MXC_CCM_CCGR6_EMI_SLOW_MASK);
+}
+#endif
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
switch (clk) {
diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c
index f6810a6..61a94a1 100644
--- a/arch/arm/cpu/armv7/mx6/hab.c
+++ b/arch/arm/cpu/armv7/mx6/hab.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,8 +7,12 @@
 #include common.h
 #include asm/io.h
 #include asm/arch/hab.h
+#include asm/arch/clock.h
 #include asm/arch/sys_proto.h
 
+/* HAB (High Assurance Boot) debug */
+#undef DEBUG_AUTHENTICATE_IMAGE
+
 /*  start of HAB API updates */
 
 #define hab_rvt_report_event_p \
@@ -71,6 +75,41 @@
((hab_rvt_exit_t *)HAB_RVT_EXIT)\
 )
 
+#define IVT_SIZE   0x20
+#define ALIGN_SIZE 0x1000
+#define CSF_PAD_SIZE   0x2000
+
+/*
+ * ++  0x0 (DDR_UIMAGE_START) -
+ * |   Header   |  |
+ * ++  0x40|
+ * ||  |
+ * ||  |
+ * ||  |
+ * ||  |
+ * | Image Data |  |
+ * .|  |
+ * .|Stuff to be authenticated +
+ * .|  ||
+ * ||  ||
+ * ||  ||
+ * ++  ||
+ * ||  ||
+ * | Fill Data  |  ||
+ * ||  ||
+ * ++ Align to ALIGN_SIZE  ||
+ * |IVT |  ||
+ * ++ + IVT_SIZE  - |
+ * ||   |
+ * |  CSF DATA  | -+
+ * ||
+ * ++
+ * ||
+ * | Fill Data  |
+ * ||
+ * ++ + CSF_PAD_SIZE
+ */
+
 bool is_hab_enabled(void

Re: [U-Boot] [PATCH 4/4] iMX6Q/DL:arm2: Add support for i.MX6Q/DL arm2 LPDDR2 boards

[Nitin Garg]

Hi Ye,

On 09/03/2014 03:34 AM, Ye.Li wrote:
 diff --git a/board/freescale/mx6qarm2/mx6qarm2.c 
 b/board/freescale/mx6qarm2/mx6qarm2.c
 index f2e577d..090f3a8 100644
 --- a/board/freescale/mx6qarm2/mx6qarm2.c
 +++ b/board/freescale/mx6qarm2/mx6qarm2.c
 @@ -32,7 +32,11 @@ DECLARE_GLOBAL_DATA_PTR;
  
  int dram_init(void)
  {
 - gd-ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
 +#ifdef CONFIG_DDR_32BIT
 + gd-ram_size = (phys_size_t)CONFIG_DDR_MB * 512 * 1024;
 +#else
 + gd-ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;
 +#endif
  
   return 0;
  }

I thought this (CONFIG_DDR_32BIT) is true only for mx6dlarm2
DDR3 board.

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Re: [U-Boot] [PATCH] tools: imximage: Fix the maximum DCD size for mx53/mx6

[Nitin Garg]

On 09/01/2014 07:56 AM, Fabio Estevam wrote:
 According to mx53 and mx6 reference manuals:
 
 The maximum size of the DCD limited to 1768 bytes.
 
 As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and
 excluding the first entry, which is the header leads to 220 as the maximum
 number for DCD size.
 
 Reported-by: Jonas Karlsson jonas.d.karls...@gmail.com 
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---
  tools/imximage.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/tools/imximage.h b/tools/imximage.h
 index 01f861e..5b5ad0e 100644
 --- a/tools/imximage.h
 +++ b/tools/imximage.h
 @@ -8,7 +8,7 @@
  #ifndef _IMXIMAGE_H_
  #define _IMXIMAGE_H_
  
 -#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 
 */
 +#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 
 */
  #define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 
 */
  #define APP_CODE_BARKER  0xB1
  #define DCD_BARKER   0xB17219E9
 

Acked-by: Nitin Garg nitin.g...@freescale.com

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Re: [U-Boot] [PATCH] tools: imximage: Fix the maximum DCD size for mx53/mx6

[Nitin Garg]

On 09/01/2014 07:56 AM, Fabio Estevam wrote:
 According to mx53 and mx6 reference manuals:
 
 The maximum size of the DCD limited to 1768 bytes.
 
 As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and
 excluding the first entry, which is the header leads to 220 as the maximum
 number for DCD size.
 
 Reported-by: Jonas Karlsson jonas.d.karls...@gmail.com 
 Signed-off-by: Fabio Estevam fabio.este...@freescale.com
 ---
  tools/imximage.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/tools/imximage.h b/tools/imximage.h
 index 01f861e..5b5ad0e 100644
 --- a/tools/imximage.h
 +++ b/tools/imximage.h
 @@ -8,7 +8,7 @@
  #ifndef _IMXIMAGE_H_
  #define _IMXIMAGE_H_
  
 -#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 
 */
 +#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set for v2 
 */
  #define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 
 */
  #define APP_CODE_BARKER  0xB1
  #define DCD_BARKER   0xB17219E9
 

Acked-by: Nitin Garg nitin.g...@freescale.com

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[U-Boot] [PATCH v2] imx: Support i.MX6 High Assurance Boot authentication

[Nitin Garg]

When CONFIG_SECURE_BOOT is enabled, the signed images
like kernel and dtb can be authenticated using iMX6 CAAM.
The added command hab_auth_img can be used for HAB
authentication of images. The command takes the image
DDR location, IVT (Image Vector Table) offset inside
image as parameters. Detailed info about signing images
can be found in Freescale AppNote AN4581.

Signed-off-by: Nitin Garg nitin.g...@freescale.com

---

Changes in v2:
- Cleaned up clock code as per review comments
- Removed dead code as per review comments
- Re-written commit log as per review comments

 arch/arm/cpu/armv7/mx6/clock.c|   32 +-
 arch/arm/cpu/armv7/mx6/hab.c  |  165 -
 arch/arm/cpu/armv7/mx6/soc.c  |   15 +++
 arch/arm/include/asm/arch-mx6/clock.h |4 +
 arch/arm/include/asm/arch-mx6/sys_proto.h |2 +-
 5 files changed, 215 insertions(+), 3 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index 820b8d5..db6a8fc 100644
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -543,6 +543,36 @@ int enable_pcie_clock(void)
   BM_ANADIG_PLL_ENET_ENABLE_PCIE);
 }
 
+#ifdef CONFIG_SECURE_BOOT
+void hab_caam_clock_enable(void)
+{
+   struct mxc_ccm_reg *const imx_ccm =
+   (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   /*CG4 ~ CG6, enable CAAM clocks*/
+   setbits_le32(imx_ccm-CCGR0, MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+
+   /* Enable EMI slow clk */
+   setbits_le32(imx_ccm-CCGR6, MXC_CCM_CCGR6_EMI_SLOW_MASK);
+}
+
+void hab_caam_clock_disable(void)
+{
+   struct mxc_ccm_reg *const imx_ccm =
+   (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+   /*CG4 ~ CG6, disable CAAM clocks*/
+   clrbits_le32(imx_ccm-CCGR0, MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+
+   /* Disable EMI slow clk */
+   clrbits_le32(imx_ccm-CCGR6, MXC_CCM_CCGR6_EMI_SLOW_MASK);
+}
+#endif
+
 unsigned int mxc_get_clock(enum mxc_clock clk)
 {
switch (clk) {
diff --git a/arch/arm/cpu/armv7/mx6/hab.c b/arch/arm/cpu/armv7/mx6/hab.c
index f6810a6..61a94a1 100644
--- a/arch/arm/cpu/armv7/mx6/hab.c
+++ b/arch/arm/cpu/armv7/mx6/hab.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
+ * Copyright (C) 2010-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -7,8 +7,12 @@
 #include common.h
 #include asm/io.h
 #include asm/arch/hab.h
+#include asm/arch/clock.h
 #include asm/arch/sys_proto.h
 
+/* HAB (High Assurance Boot) debug */
+#undef DEBUG_AUTHENTICATE_IMAGE
+
 /*  start of HAB API updates */
 
 #define hab_rvt_report_event_p \
@@ -71,6 +75,41 @@
((hab_rvt_exit_t *)HAB_RVT_EXIT)\
 )
 
+#define IVT_SIZE   0x20
+#define ALIGN_SIZE 0x1000
+#define CSF_PAD_SIZE   0x2000
+
+/*
+ * ++  0x0 (DDR_UIMAGE_START) -
+ * |   Header   |  |
+ * ++  0x40|
+ * ||  |
+ * ||  |
+ * ||  |
+ * ||  |
+ * | Image Data |  |
+ * .|  |
+ * .|Stuff to be authenticated +
+ * .|  ||
+ * ||  ||
+ * ||  ||
+ * ++  ||
+ * ||  ||
+ * | Fill Data  |  ||
+ * ||  ||
+ * ++ Align to ALIGN_SIZE  ||
+ * |IVT |  ||
+ * ++ + IVT_SIZE  - |
+ * ||   |
+ * |  CSF DATA  | -+
+ * ||
+ * ++
+ * ||
+ * | Fill Data  |
+ * ||
+ * ++ + CSF_PAD_SIZE
+ */
+
 bool is_hab_enabled(void

Re: [U-Boot] [PATCH] Support i.MX6 High Assurance Boot (HAB) authentication of images

[Nitin Garg]

On 08/31/2014 08:09 PM, Otavio Salvador wrote:
 Hello Nitin,
 
 On Sun, Aug 31, 2014 at 5:16 PM,  nitin.g...@freescale.com wrote:
 From: Nitin Garg nitin.g...@freescale.com

 Add hab_auth_img u-boot command which can be used for HAB authentication
 of images.

 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 
 As the other patch I commented, this commit log also needs some rework
 to comply to the guidelines. I would also welcome a more detailed
 description about what this adds on top of previous HAB code.

I will improve the commit log and add detailed description.
 
 ...
 diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h 
 b/arch/arm/include/asm/arch-mx6/sys_proto.h
 index 306d699..2bbb86e 100644
 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h
 +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
 ...
 @@ -11,7 +13,7 @@
  #include asm/imx-common/regs-common.h
  #include ../arch-imx/cpu.h

 -#define soc_rev() (get_cpu_rev()  0xFF)
 +#define soc_rev() ((int)(get_cpu_rev()  0xFF))
 
 This seems unrelated change, isn't it?
 
Since get_cpu_rev returns unsigned int, this was causing
a mix of unsigned int and int across binary operators.

e.g:
if(soc_rev() = CHIP_REV_1_5)
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Re: [U-Boot] [PATCH] Support i.MX6 High Assurance Boot (HAB) authentication of images

[Nitin Garg]

On 09/02/2014 08:41 PM, Otavio Salvador wrote:
 Hello Nitin,
 
 On Tue, Sep 2, 2014 at 10:36 PM, Nitin Garg nitin.g...@freescale.com wrote:
 On 08/31/2014 08:09 PM, Otavio Salvador wrote:
 diff --git a/arch/arm/include/asm/arch-mx6/sys_proto.h 
 b/arch/arm/include/asm/arch-mx6/sys_proto.h
 index 306d699..2bbb86e 100644
 --- a/arch/arm/include/asm/arch-mx6/sys_proto.h
 +++ b/arch/arm/include/asm/arch-mx6/sys_proto.h
 ...
 @@ -11,7 +13,7 @@
  #include asm/imx-common/regs-common.h
  #include ../arch-imx/cpu.h

 -#define soc_rev() (get_cpu_rev()  0xFF)
 +#define soc_rev() ((int)(get_cpu_rev()  0xFF))

 This seems unrelated change, isn't it?

 Since get_cpu_rev returns unsigned int, this was causing
 a mix of unsigned int and int across binary operators.

 e.g:
 if(soc_rev() = CHIP_REV_1_5)
 
 In this case, please split this change.
 
 Shouldn't this to be fixed in the get_cpu_rev?
 
 Cheers,
 
But get_cpu_rev is correct, it returns unsigned int.
The problem happens in hab code where there are 
comparisons between int and unsigned int, hence 
I think it should not be split. Pls advice.
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Re: [U-Boot] [PATCH] Support i.MX6 High Assurance Boot (HAB) authentication of images

[Nitin Garg]

On 09/02/2014 08:52 PM, Fabio Estevam wrote:
 On Tue, Sep 2, 2014 at 10:47 PM, Nitin Garg nitin.g...@freescale.com wrote:
 
 But get_cpu_rev is correct, it returns unsigned int.
 The problem happens in hab code where there are
 comparisons between int and unsigned int, hence
 
 Where exactly in the hab code does the problem happen?
 
In the macros of HAB, like:
hab_rvt_report_event_p

The compiler generates bhi instead of bgt.

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Re: [U-Boot] [PATCH] tools: imximage: Fix the maximum DCD size for mx53/mx6

[Nitin Garg]

Acked!

Regards,
Nitin Garg


-Original Message-
From: Fabio Estevam [mailto:fabio.este...@freescale.com] 
Sent: Monday, September 01, 2014 7:56 AM
To: sba...@denx.de
Cc: u-boot@lists.denx.de; jonas.d.karls...@gmail.com; Li Ye-B37916; Garg 
Nitin-B37173; Estevam Fabio-R49496
Subject: [PATCH] tools: imximage: Fix the maximum DCD size for mx53/mx6

According to mx53 and mx6 reference manuals:

The maximum size of the DCD limited to 1768 bytes.

As each DCD entry consists of 8 bytes, we have a total of 1768 / 8 = 221, and 
excluding the first entry, which is the header leads to 220 as the maximum 
number for DCD size.

Reported-by: Jonas Karlsson jonas.d.karls...@gmail.com
Signed-off-by: Fabio Estevam fabio.este...@freescale.com
---
 tools/imximage.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/imximage.h b/tools/imximage.h index 01f861e..5b5ad0e 100644
--- a/tools/imximage.h
+++ b/tools/imximage.h
@@ -8,7 +8,7 @@
 #ifndef _IMXIMAGE_H_
 #define _IMXIMAGE_H_
 
-#define MAX_HW_CFG_SIZE_V2 121 /* Max number of registers imx can set for v2 */
+#define MAX_HW_CFG_SIZE_V2 220 /* Max number of registers imx can set 
+for v2 */
 #define MAX_HW_CFG_SIZE_V1 60  /* Max number of registers imx can set for v1 */
 #define APP_CODE_BARKER0xB1
 #define DCD_BARKER 0xB17219E9
--
1.9.1

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[U-Boot] [PATCH v2] imx: ddr: Move mx6q_4x_mt41j128.cfg to mx6sabresd board dir

[Nitin Garg]

Move board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg to
board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg as this is
was designed for the mx6sabresd board. This also updates the
cgtqmx6qeval which makes use of this configuration.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

 .../{imx/ddr = mx6sabresd}/mx6q_4x_mt41j128.cfg   |0
 configs/cgtqmx6qeval_defconfig |2 +-
 configs/mx6qsabresd_defconfig  |2 +-
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename board/freescale/{imx/ddr = mx6sabresd}/mx6q_4x_mt41j128.cfg (100%)

diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg 
b/board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
similarity index 100%
rename from board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
rename to board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg
diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig
index 6699381..2f83808 100644
--- a/configs/cgtqmx6qeval_defconfig
+++ b/configs/cgtqmx6qeval_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
+CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q
 CONFIG_ARM=y
 CONFIG_TARGET_CGTQMX6EVAL=y
diff --git a/configs/mx6qsabresd_defconfig b/configs/mx6qsabresd_defconfig
index dc8e254..67c1b77 100644
--- a/configs/mx6qsabresd_defconfig
+++ b/configs/mx6qsabresd_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg,MX6Q
+CONFIG_SYS_EXTRA_OPTIONS=IMX_CONFIG=board/freescale/mx6sabresd/mx6q_4x_mt41j128.cfg,MX6Q
 CONFIG_ARM=y
 CONFIG_TARGET_MX6SABRESD=y
-- 
1.7.9.5

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[U-Boot] [imx PATCH v2] Add i.MX6 CPU temperature sensor support

[Nitin Garg]

i.MX6 SoC has onChip temperature sensor. Add support
for this sensor.

Signed-off-by: Nitin Garg nitin.g...@freescale.com
---

 arch/arm/cpu/armv7/mx6/soc.c |  142 +++-
 arch/arm/imx-common/cpu.c|7 +-
 arch/arm/include/asm/arch-mx6/crm_regs.h |  543 +-
 arch/arm/include/asm/arch-mx6/imx-regs.h |9 +-
 include/configs/mx6sabre_common.h|1 +
 5 files changed, 698 insertions(+), 4 deletions(-)

diff --git a/arch/arm/cpu/armv7/mx6/soc.c b/arch/arm/cpu/armv7/mx6/soc.c
index ac84a1f..20f1261 100644
--- a/arch/arm/cpu/armv7/mx6/soc.c
+++ b/arch/arm/cpu/armv7/mx6/soc.c
@@ -2,7 +2,7 @@
  * (C) Copyright 2007
  * Sascha Hauer, Pengutronix
  *
- * (C) Copyright 2009 Freescale Semiconductor, Inc.
+ * (C) Copyright 2009-2014 Freescale Semiconductor, Inc.
  *
  * SPDX-License-Identifier:GPL-2.0+
  */
@@ -35,6 +35,20 @@ struct scu_regs {
u32 fpga_rev;
 };
 
+#define TEMPERATURE_MIN-40
+#define TEMPERATURE_HOT80
+#define TEMPERATURE_MAX125
+#define FACTOR115976
+#define FACTOR24297157
+#define MEASURE_FREQ   327
+
+#define REG_VALUE_TO_CEL(ratio, raw) \
+   ((raw_n40c - raw) * 100 / ratio - 40)
+
+#ifdef CONFIG_IMX6_TEMP_SENSOR
+static unsigned int fuse = ~0;
+#endif
+
 u32 get_nr_cpus(void)
 {
struct scu_regs *scu = (struct scu_regs *)SCU_BASE_ADDR;
@@ -218,6 +232,132 @@ static void imx_set_wdog_powerdown(bool enable)
writew(enable, wdog2-wmcr);
 }
 
+#ifdef CONFIG_IMX6_TEMP_SENSOR
+static int read_cpu_temperature(void)
+{
+   int temperature;
+   unsigned int ccm_ccgr2;
+   unsigned int reg, tmp;
+   unsigned int raw_25c, raw_n40c, ratio;
+   struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
+   struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+   struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+   struct fuse_bank *bank = ocotp-bank[1];
+   struct fuse_bank1_regs *fuse_bank1 =
+   (struct fuse_bank1_regs *)bank-fuse_regs;
+
+   /* need to make sure pll3 is enabled for thermal sensor */
+   if ((readl(anatop-usb1_pll_480_ctrl) 
+   BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0) {
+   /* enable pll's power */
+   writel(BM_ANADIG_USB1_PLL_480_CTRL_POWER,
+  anatop-usb1_pll_480_ctrl_set);
+   writel(0x80, anatop-ana_misc2_clr);
+   /* wait for pll lock */
+   while ((readl(anatop-usb1_pll_480_ctrl) 
+   BM_ANADIG_USB1_PLL_480_CTRL_LOCK) == 0)
+   ;
+   /* disable bypass */
+   writel(BM_ANADIG_USB1_PLL_480_CTRL_BYPASS,
+  anatop-usb1_pll_480_ctrl_clr);
+   /* enable pll output */
+   writel(BM_ANADIG_USB1_PLL_480_CTRL_ENABLE,
+  anatop-usb1_pll_480_ctrl_set);
+   }
+
+   ccm_ccgr2 = readl(mxc_ccm-CCGR2);
+   /* enable OCOTP_CTRL clock in CCGR2 */
+   writel(ccm_ccgr2 | MXC_CCM_CCGR2_OCOTP_CTRL_MASK, mxc_ccm-CCGR2);
+   fuse = readl(fuse_bank1-ana1);
+
+   /* restore CCGR2 */
+   writel(ccm_ccgr2, mxc_ccm-CCGR2);
+
+   if (fuse == 0 || fuse == 0x || (fuse  0xfff0) == 0)
+   return TEMPERATURE_MIN;
+
+   /*
+* fuse data layout:
+* [31:20] sensor value @ 25C
+* [19:8] sensor value of hot
+* [7:0] hot temperature value
+*/
+   raw_25c = fuse  20;
+
+   /*
+* The universal equation for thermal sensor
+* is slope = 0.4297157 - (0.0015976 * 25C fuse),
+* here we convert them to integer to make them
+* easy for counting, FACTOR1 is 15976,
+* FACTOR2 is 4297157. Our ratio = -100 * slope
+*/
+   ratio = ((FACTOR1 * raw_25c - FACTOR2) + 5) / 10;
+
+   debug(Thermal sensor with ratio = %d\n, ratio);
+
+   raw_n40c = raw_25c + (13 * ratio) / 20;
+
+   /*
+* now we only use single measure, every time we read
+* the temperature, we will power on/down anadig thermal
+* module
+*/
+   writel(BM_ANADIG_TEMPSENSE0_POWER_DOWN, anatop-tempsense0_clr);
+   writel(BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF, anatop-ana_misc0_set);
+
+   /* write measure freq */
+   reg = readl(anatop-tempsense1);
+   reg = ~BM_ANADIG_TEMPSENSE1_MEASURE_FREQ;
+   reg |= MEASURE_FREQ;
+   writel(reg, anatop-tempsense1);
+
+   writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, anatop-tempsense0_clr);
+   writel(BM_ANADIG_TEMPSENSE0_FINISHED, anatop-tempsense0_clr);
+   writel(BM_ANADIG_TEMPSENSE0_MEASURE_TEMP, anatop-tempsense0_set);
+
+   while ((readl(anatop-tempsense0) 
+   BM_ANADIG_TEMPSENSE0_FINISHED) == 0)
+   udelay(1);
+
+   reg

Re: [U-Boot] [PATCH] mx6: drop ARM errata 742230

[Nitin Garg]

Acked-by: Nitin Garg nitin.g...@freescale.com

Regards,
Nitin Garg

-Original Message-
From: Shawn Guo [mailto:shawn@freescale.com] 
Sent: Wednesday, June 11, 2014 3:53 AM
To: u-boot@lists.denx.de
Cc: Garg Nitin-B37173; Stefano Babic; Guo Shawn-R65073
Subject: [PATCH] mx6: drop ARM errata 742230

Commit e9fd66defd7e (ARM: mx6: define CONFIG_ARM_ERRATA_742230) enables errata 
742230 for imx6, because it helps remove one reboot issue.
However, this errata does not really apply on imx6, because Cortex-A9 on imx6 
is r2p10 while the errata only applies to revisions r1p0..r2p2.

At a later time, commit f71cbfe3ca5d (ARM: Add workaround for Cortex-A9 errata 
794072) adds support of errata 794072, which applies to all
Cortex-A9 revisions.  As the workaround for both errata are exactly same, it 
makes a lot more sense to select 794072 instead of 742230 for imx6.  Since we 
already enable 794072 for imx6, it's time to drop errata 742230 to avoid 
confusion.

Signed-off-by: Shawn Guo shawn@freescale.com
---
 include/configs/mx6_common.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/configs/mx6_common.h b/include/configs/mx6_common.h index 
8a8920f6cc8a..e4a5cc5be1a6 100644
--- a/include/configs/mx6_common.h
+++ b/include/configs/mx6_common.h
@@ -17,7 +17,6 @@
 #ifndef __MX6_COMMON_H
 #define __MX6_COMMON_H
 
-#define CONFIG_ARM_ERRATA_742230
 #define CONFIG_ARM_ERRATA_743622
 #define CONFIG_ARM_ERRATA_751472
 #define CONFIG_ARM_ERRATA_794072
--
1.8.3.2

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Re: [U-Boot] [PATCH 1/2] ARM: Add workaround for Cortex-A9 errata 794072

[Nitin Garg]

Good point! I will do that.

Regards,
Nitin Garg


-Original Message-
From: Dirk Behme [mailto:dirk.be...@de.bosch.com] 
Sent: Wednesday, April 02, 2014 1:42 AM
To: Garg Nitin-B37173
Cc: tr...@ti.com; Estevam Fabio-R49496; u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH 1/2] ARM: Add workaround for Cortex-A9 errata 
794072

On 02.04.2014 05:33, nitin.g...@freescale.com wrote:
 From: Nitin Garg nitin.g...@freescale.com

 A short loop including a DMB instruction might cause a denial of 
 service on another processor which executes a CP15 broadcast operation.
 Exists on r1, r2, r3, r4 revisions.

 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 ---
   README |1 +
   arch/arm/cpu/armv7/start.S |5 +
   2 files changed, 6 insertions(+), 0 deletions(-)

 diff --git a/README b/README
 index 7cb7c4f..a496c65 100644
 --- a/README
 +++ b/README
 @@ -566,6 +566,7 @@ The following options need to be configured:
   CONFIG_ARM_ERRATA_742230
   CONFIG_ARM_ERRATA_743622
   CONFIG_ARM_ERRATA_751472
 + CONFIG_ARM_ERRATA_794072

   If set, the workarounds for these ARM errata are applied early
   during U-Boot startup. Note that these options force the diff 
 --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 
 ac1e55a..b87a378 100644
 --- a/arch/arm/cpu/armv7/start.S
 +++ b/arch/arm/cpu/armv7/start.S
 @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
   orr r0, r0, #1  11@ set bit #11
   mcr p15, 0, r0, c15, c0, 1  @ write diagnostic register
   #endif
 +#ifdef CONFIG_ARM_ERRATA_794072
 + mrc p15, 0, r0, c15, c0, 1  @ read diagnostic register
 + orr r0, r0, #1  4 @ set bit #4
 + mcr p15, 0, r0, c15, c0, 1  @ write diagnostic register
 +#endif

Where is the difference between the errata code for above new
CONFIG_ARM_ERRATA_794072 and the existing

#ifdef CONFIG_ARM_ERRATA_742230
mrc p15, 0, r0, c15, c0, 1  @ read diagnostic register
orr r0, r0, #1  4 @ set bit #4
mcr p15, 0, r0, c15, c0, 1  @ write diagnostic register
#endif

?

Maybe we should just do a

#if (defined(CONFIG_ARM_ERRATA_794072) || defined(CONFIG_ARM_ERRATA_742230))

?

Best regards

Dirk










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Re: [U-Boot] [PATCH 2/2] ARM: Add workaround for Cortex-A9 errata 761320

[Nitin Garg]

Hi Dirk,

There is no revision and variant in this cpu_init_cp15 function. I think this 
function is common unlike kernel code which was cortex specific.

Regards,
Nitin Garg


-Original Message-
From: Dirk Behme [mailto:dirk.be...@de.bosch.com] 
Sent: Wednesday, April 02, 2014 1:46 AM
To: Garg Nitin-B37173
Cc: tr...@ti.com; Estevam Fabio-R49496; u-boot@lists.denx.de
Subject: Re: [U-Boot] [PATCH 2/2] ARM: Add workaround for Cortex-A9 errata 
761320

On 02.04.2014 05:33, nitin.g...@freescale.com wrote:
 From: Nitin Garg nitin.g...@freescale.com

 Full cache line writes to the same memory region from at least two 
 processors might deadlock the processor. Exists on r1, r2, r3 
 revisions.

 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 ---
   README |1 +
   arch/arm/cpu/armv7/start.S |5 +
   2 files changed, 6 insertions(+), 0 deletions(-)

 diff --git a/README b/README
 index a496c65..b7c0f68 100644
 --- a/README
 +++ b/README
 @@ -567,6 +567,7 @@ The following options need to be configured:
   CONFIG_ARM_ERRATA_743622
   CONFIG_ARM_ERRATA_751472
   CONFIG_ARM_ERRATA_794072
 + CONFIG_ARM_ERRATA_761320

   If set, the workarounds for these ARM errata are applied early
   during U-Boot startup. Note that these options force the diff 
 --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 
 b87a378..1229476 100644
 --- a/arch/arm/cpu/armv7/start.S
 +++ b/arch/arm/cpu/armv7/start.S
 @@ -227,6 +227,11 @@ ENTRY(cpu_init_cp15)
   orr r0, r0, #1  4 @ set bit #4
   mcr p15, 0, r0, c15, c0, 1  @ write diagnostic register
   #endif
 +#ifdef CONFIG_ARM_ERRATA_761320
 + mrc p15, 0, r0, c15, c0, 1  @ read diagnostic register
 + orr r0, r0, #1  21@ set bit #21
 + mcr p15, 0, r0, c15, c0, 1  @ write diagnostic register
 +#endif

Is there any reason why you dropped the check for r4p0

cmp r6, #0x40   @ present prior to r4p0

which you still had in

http://www.spinics.net/lists/arm-kernel/msg319223.html

?

Best regards

Dirk



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Re: [U-Boot] [PATCH v3 1/3] ARM: Add workaround for Cortex-A9 errata 794072

[Nitin Garg]

Hi Stefano,

Errata 742230 applies to r1p0, r1p1, r1p2, r1p3, r2p0, r2p1,
r2p2 revision of Cortex-A9. Errata 794072 applies to r1, 2, 
r3, r4 revisions. Software workaround is same for both.

Since diff products use diff revisions of core, I would 
suggest to have it this way. Otherwise it might lead to 
confusion if one has to enable 742230 (for 794072 workaround)
even though the core revision does not need it.

Regards,
Nitin Garg


-Original Message-
From: Stefano Babic [mailto:sba...@denx.de] 
Sent: Wednesday, April 02, 2014 10:26 AM
To: Garg Nitin-B37173; tr...@ti.com; Estevam Fabio-R49496; sba...@denx.de
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH v3 1/3] ARM: Add workaround for Cortex-A9 errata 794072

Hi Nitin,

On 02/04/2014 15:55, nitin.g...@freescale.com wrote:
 From: Nitin Garg nitin.g...@freescale.com
 
 A short loop including a DMB instruction might cause a denial of 
 service on another processor which executes a CP15 broadcast operation.
 Exists on r1, r2, r3, r4 revisions.
 
 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 Acked-by: Dirk Behme dirk.be...@de.bosch.com
 ---
  README |1 +
  arch/arm/cpu/armv7/start.S |2 +-
  2 files changed, 2 insertions(+), 1 deletions(-)
 
 diff --git a/README b/README
 index 7cb7c4f..a496c65 100644
 --- a/README
 +++ b/README
 @@ -566,6 +566,7 @@ The following options need to be configured:
   CONFIG_ARM_ERRATA_742230
   CONFIG_ARM_ERRATA_743622
   CONFIG_ARM_ERRATA_751472
 + CONFIG_ARM_ERRATA_794072
  
   If set, the workarounds for these ARM errata are applied early
   during U-Boot startup. Note that these options force the diff 
 --git 
 a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 
 ac1e55a..f3830c8 100644
 --- a/arch/arm/cpu/armv7/start.S
 +++ b/arch/arm/cpu/armv7/start.S
 @@ -205,7 +205,7 @@ ENTRY(cpu_init_cp15)
   mcr p15, 0, r0, c1, c0, 0   @ write system control register
  #endif
  
 -#ifdef CONFIG_ARM_ERRATA_742230
 +#if (defined(CONFIG_ARM_ERRATA_742230) || 
 +defined(CONFIG_ARM_ERRATA_794072))
   mrc p15, 0, r0, c15, c0, 1  @ read diagnostic register
   orr r0, r0, #1  4 @ set bit #4
   mcr p15, 0, r0, c15, c0, 1  @ write diagnostic register
 

Apart having an additional errata number, which is the contribute of
CONFIG_ARM_ERRATA_794072 ? We are already covered with
CONFIG_ARM_ERRATA_742230 and the work-around for dmb is already implemented.

Best regards,
Stefano Babic

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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de 
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Re: [U-Boot] [PATCH v3 2/3] ARM: Add workaround for Cortex-A9 errata 761320

[Nitin Garg]

Sorry, I don't have a link. We are in the process of updating
the i.MX6 Chip errata document to include this.

Regards,
Nitin Garg


-Original Message-
From: Stefano Babic [mailto:sba...@denx.de] 
Sent: Wednesday, April 02, 2014 10:29 AM
To: Garg Nitin-B37173; tr...@ti.com; Estevam Fabio-R49496; sba...@denx.de
Cc: u-boot@lists.denx.de
Subject: Re: [PATCH v3 2/3] ARM: Add workaround for Cortex-A9 errata 761320

Hi Nitin,

On 02/04/2014 15:55, nitin.g...@freescale.com wrote:
 From: Nitin Garg nitin.g...@freescale.com
 
 Full cache line writes to the same memory region from at least two 
 processors might deadlock the processor. Exists on r1, r2, r3 
 revisions.
 
 Signed-off-by: Nitin Garg nitin.g...@freescale.com
 ---
  README |1 +
  arch/arm/cpu/armv7/start.S |5 +
  2 files changed, 6 insertions(+), 0 deletions(-)
 
 diff --git a/README b/README
 index a496c65..b7c0f68 100644
 --- a/README
 +++ b/README
 @@ -567,6 +567,7 @@ The following options need to be configured:
   CONFIG_ARM_ERRATA_743622
   CONFIG_ARM_ERRATA_751472
   CONFIG_ARM_ERRATA_794072
 + CONFIG_ARM_ERRATA_761320
  
   If set, the workarounds for these ARM errata are applied early
   during U-Boot startup. Note that these options force the diff 
 --git 
 a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 
 f3830c8..27be451 100644
 --- a/arch/arm/cpu/armv7/start.S
 +++ b/arch/arm/cpu/armv7/start.S
 @@ -222,6 +222,11 @@ ENTRY(cpu_init_cp15)
   orr r0, r0, #1  11@ set bit #11
   mcr p15, 0, r0, c15, c0, 1  @ write diagnostic register
  #endif
 +#ifdef CONFIG_ARM_ERRATA_761320
 + mrc p15, 0, r0, c15, c0, 1  @ read diagnostic register
 + orr r0, r0, #1  21@ set bit #21
 + mcr p15, 0, r0, c15, c0, 1  @ write diagnostic register
 +#endif
  
   mov pc, lr  @ back to my caller
  ENDPROC(cpu_init_cp15)
 

I admit I am not able to find the documentation for this errata neither the ARM 
center nor in the i.MX6 errata. Do you have a link to get some more infos about 
it ?

Best regards,
Stefano Babic

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DENX Software Engineering GmbH, MD: Wolfgang Denk  Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: +49-8142-66989-53 Fax: +49-8142-66989-80 Email: sba...@denx.de 
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