[PATCH 1/1] ARM: dts: chameleonv3: Update handoffs

[Paweł Anikiel]

Update the chameleonv3 handoffs with the ones generated from the final
FPGA design.

Signed-off-by: Paweł Anikiel 
---
 ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 22 +--
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h 
b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
index caaff604eb..37cd5d653d 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
@@ -13,9 +13,9 @@
 #define EMAC2_CLK_HZ 25000
 #define EOSC1_CLK_HZ 
 #define F2H_FREE_CLK_HZ 2
-#define H2F_USER0_CLK_HZ 2
+#define H2F_USER0_CLK_HZ 25000
 #define H2F_USER1_CLK_HZ 1
-#define L3_MAIN_FREE_CLK_HZ 2
+#define L3_MAIN_FREE_CLK_HZ 25000
 #define SDMMC_CLK_HZ 2
 #define TPIU_CLK_HZ 1
 #define MAINPLLGRP_CNTR15CLK_CNT 900
@@ -24,7 +24,7 @@
 #define MAINPLLGRP_CNTR4CLK_CNT 900
 #define MAINPLLGRP_CNTR5CLK_CNT 900
 #define MAINPLLGRP_CNTR6CLK_CNT 9
-#define MAINPLLGRP_CNTR7CLK_CNT 9
+#define MAINPLLGRP_CNTR7CLK_CNT 7
 #define MAINPLLGRP_CNTR7CLK_SRC 0
 #define MAINPLLGRP_CNTR8CLK_CNT 19
 #define MAINPLLGRP_CNTR9CLK_CNT 900
@@ -68,7 +68,7 @@
 #define CLKMGR_TESTIOCTRL_PERICLKSEL 8
 #define ALTERAGRP_MPUCLK_MAINCNT 1
 #define ALTERAGRP_MPUCLK_PERICNT 900
-#define ALTERAGRP_NOCCLK_MAINCNT 9
+#define ALTERAGRP_NOCCLK_MAINCNT 7
 #define ALTERAGRP_NOCCLK_PERICNT 900
 #define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
(ALTERAGRP_MPUCLK_MAINCNT))
@@ -120,9 +120,9 @@
 #define CONFIG_IO_15_WK_PU_EN 1
 #define CONFIG_IO_16_INPUT_BUF_EN 0
 #define CONFIG_IO_16_PD_DRV_STRG 10
-#define CONFIG_IO_16_PD_SLW_RT 1
+#define CONFIG_IO_16_PD_SLW_RT 0
 #define CONFIG_IO_16_PU_DRV_STRG 8
-#define CONFIG_IO_16_PU_SLW_RT 1
+#define CONFIG_IO_16_PU_SLW_RT 0
 #define CONFIG_IO_16_RTRIM 1
 #define CONFIG_IO_16_WK_PU_EN 0
 #define CONFIG_IO_17_INPUT_BUF_EN 1
@@ -169,9 +169,9 @@
 #define CONFIG_IO_5_WK_PU_EN 0
 #define CONFIG_IO_6_INPUT_BUF_EN 0
 #define CONFIG_IO_6_PD_DRV_STRG 10
-#define CONFIG_IO_6_PD_SLW_RT 1
+#define CONFIG_IO_6_PD_SLW_RT 0
 #define CONFIG_IO_6_PU_DRV_STRG 8
-#define CONFIG_IO_6_PU_SLW_RT 1
+#define CONFIG_IO_6_PU_SLW_RT 0
 #define CONFIG_IO_6_RTRIM 1
 #define CONFIG_IO_6_WK_PU_EN 0
 #define CONFIG_IO_7_INPUT_BUF_EN 1
@@ -213,7 +213,7 @@
 #define PINMUX_DEDICATED_IO_9_SEL 8
 #define PINMUX_I2C0_USEFPGA_SEL 1
 #define PINMUX_I2C1_USEFPGA_SEL 0
-#define PINMUX_I2CEMAC0_USEFPGA_SEL 0
+#define PINMUX_I2CEMAC0_USEFPGA_SEL 1
 #define PINMUX_I2CEMAC1_USEFPGA_SEL 0
 #define PINMUX_I2CEMAC2_USEFPGA_SEL 0
 #define PINMUX_NAND_USEFPGA_SEL 0
@@ -283,10 +283,10 @@
 /* Bridge Configuration */
 #define F2H_AXI_SLAVE 1
 #define F2SDRAM0_AXI_SLAVE 1
-#define F2SDRAM1_AXI_SLAVE 1
+#define F2SDRAM1_AXI_SLAVE 0
 #define F2SDRAM2_AXI_SLAVE 1
 #define H2F_AXI_MASTER 1
-#define LWH2F_AXI_MASTER 1
+#define LWH2F_AXI_MASTER 0
 
 /* Voltage Select for Config IO */
 #define CONFIG_IO_BANK_VSEL \
-- 
2.43.0.472.g3155946c3a-goog

[PATCH v2 RESEND 4/6] arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi

[Paweł Anikiel]

This file is included by the different chameleonv3 variants. Change the
name to .dtsi.

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 ...arria10_chameleonv3.dts => socfpga_arria10_chameleonv3.dtsi} | 0
 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts  | 2 +-
 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts  | 2 +-
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename arch/arm/dts/{socfpga_arria10_chameleonv3.dts => 
socfpga_arria10_chameleonv3.dtsi} (100%)

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi
similarity index 100%
rename from arch/arm/dts/socfpga_arria10_chameleonv3.dts
rename to arch/arm/dts/socfpga_arria10_chameleonv3.dtsi
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
index 5f40af6eb9..bef0280212 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
@@ -2,4 +2,4 @@
 /*
  * Copyright 2022 Google LLC
  */
-#include "socfpga_arria10_chameleonv3.dts"
+#include "socfpga_arria10_chameleonv3.dtsi"
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
index 5f40af6eb9..bef0280212 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
@@ -2,4 +2,4 @@
 /*
  * Copyright 2022 Google LLC
  */
-#include "socfpga_arria10_chameleonv3.dts"
+#include "socfpga_arria10_chameleonv3.dtsi"
-- 
2.39.2.637.g21b0678d19-goog

[PATCH v2 RESEND 6/6] chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig

[Paweł Anikiel]

This file was missed during the conversion process. Add the symbol to
defconfig.

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 configs/socfpga_chameleonv3_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_chameleonv3_defconfig 
b/configs/socfpga_chameleonv3_defconfig
index 5d08fd282b..41231e2382 100644
--- a/configs/socfpga_chameleonv3_defconfig
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x1
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
 CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
 CONFIG_SPL_FS_EXT4=y
-- 
2.39.2.637.g21b0678d19-goog

[PATCH v2 RESEND 5/6] arm: dts: chameleonv3: Add 270-2 variant

[Paweł Anikiel]

Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 arch/arm/dts/Makefile|  1 +
 .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi| 12 
 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts   |  5 +
 3 files changed, 18 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9d647b9639..7a577deb50 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -442,6 +442,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_agilex_socdk.dtb\
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
+   socfpga_arria10_chameleonv3_270_2.dtb   \
socfpga_arria10_chameleonv3_270_3.dtb   \
socfpga_arria10_chameleonv3_480_2.dtb   \
socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
new file mode 100644
index 00..05b4485cf3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+   altr,bitstream = "fpga-270-2.itb";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
new file mode 100644
index 00..bef0280212
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.dtsi"
-- 
2.39.2.637.g21b0678d19-goog

[PATCH v2 RESEND 1/6] socfpga: chameleonv3: Enable ext4 in SPL

[Paweł Anikiel]

Allow SPL to boot from an ext4 filesystem.

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 configs/socfpga_chameleonv3_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_chameleonv3_defconfig 
b/configs/socfpga_chameleonv3_defconfig
index 4bbce3591d..5d08fd282b 100644
--- a/configs/socfpga_chameleonv3_defconfig
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
 CONFIG_SPL_TEXT_BASE=0xFFE0
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
+CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
-- 
2.39.2.637.g21b0678d19-goog

[PATCH v2 RESEND 3/6] arm: dts: chameleonv3: Override chameleonv3 bitstream names

[Paweł Anikiel]

Set the bitstream name per Chameleon variant. This allows the same
boot filesystem with all bitstream variants to be used on different
boards.

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi | 4 
 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi | 4 
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
index e789d49657..a7aa17b220 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
@@ -6,3 +6,7 @@
 #include "socfpga_arria10-handoff.dtsi"
 #include "socfpga_arria10_handoff_u-boot.dtsi"
 #include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+   altr,bitstream = "fpga-270-3.itb";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
index 7bbcc471c5..82a94894ea 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
@@ -6,3 +6,7 @@
 #include "socfpga_arria10-handoff.dtsi"
 #include "socfpga_arria10_handoff_u-boot.dtsi"
 #include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+   altr,bitstream = "fpga-480-2.itb";
+};
-- 
2.39.2.637.g21b0678d19-goog

[PATCH v2 RESEND 2/6] socfpga: chameleonv3: Move environment to a text file

[Paweł Anikiel]

Move the environment to an easily editable text file in the boot
partition

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 board/google/chameleonv3/environment.txt | 13 +
 include/configs/socfpga_chameleonv3.h|  9 -
 2 files changed, 17 insertions(+), 5 deletions(-)
 create mode 100644 board/google/chameleonv3/environment.txt

diff --git a/board/google/chameleonv3/environment.txt 
b/board/google/chameleonv3/environment.txt
new file mode 100644
index 00..52aedbb90a
--- /dev/null
+++ b/board/google/chameleonv3/environment.txt
@@ -0,0 +1,13 @@
+# MMC boot command
+bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm
+
+# Network boot command and vars
+bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm
+autoload=no
+serverip=192.168.0.1
+
+# U-Boot will run this after loading this file
+bootcmd_txt=run bootcmd_mmc
+
+# Kernel cmdline
+bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 
rootflags=subvol=root rw rootwait
diff --git a/include/configs/socfpga_chameleonv3.h 
b/include/configs/socfpga_chameleonv3.h
index 2ce7011529..fc08e74dba 100644
--- a/include/configs/socfpga_chameleonv3.h
+++ b/include/configs/socfpga_chameleonv3.h
@@ -20,11 +20,10 @@
 #define CFG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
 
 #define CFG_EXTRA_ENV_SETTINGS \
-   "autoload=no\0" \
-   "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw 
rootwait\0" \
-   "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
-   "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
-   "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
+   "distro_bootcmd=bridge enable; " \
+   "load mmc 0:1 ${loadaddr} u-boot.txt; " \
+   "env import -t ${loadaddr}; " \
+   "run bootcmd_txt\0"
 
 /*
  * L4 OSC1 Timer 0
-- 
2.39.2.637.g21b0678d19-goog

[PATCH v2 RESEND 0/6] Update Chameleon v3 configuration

[Paweł Anikiel]

These changes add the third chameleon variation and make it easier to
deploy images to different boards.

v2 changes:
 - rename chameleonv3.dts to .dtsi
 - add missing CONFIG_SPL_MAX_SIZE symbol

Paweł Anikiel (6):
  socfpga: chameleonv3: Enable ext4 in SPL
  socfpga: chameleonv3: Move environment to a text file
  arm: dts: chameleonv3: Override chameleonv3 bitstream names
  arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi
  arm: dts: chameleonv3: Add 270-2 variant
  chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig

 arch/arm/dts/Makefile   |  1 +
 ...eleonv3.dts => socfpga_arria10_chameleonv3.dtsi} |  0
 .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi   | 12 
 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts  |  5 +
 .../socfpga_arria10_chameleonv3_270_3-u-boot.dtsi   |  4 
 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts  |  2 +-
 .../socfpga_arria10_chameleonv3_480_2-u-boot.dtsi   |  4 
 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts  |  2 +-
 board/google/chameleonv3/environment.txt| 13 +
 configs/socfpga_chameleonv3_defconfig   |  2 ++
 include/configs/socfpga_chameleonv3.h   |  9 -
 11 files changed, 47 insertions(+), 7 deletions(-)
 rename arch/arm/dts/{socfpga_arria10_chameleonv3.dts => 
socfpga_arria10_chameleonv3.dtsi} (100%)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
 create mode 100644 board/google/chameleonv3/environment.txt

-- 
2.39.2.637.g21b0678d19-goog

Re: [PATCH v2 0/6] Update Chameleon v3 configuration

[Paweł Anikiel]

On Fri, Oct 14, 2022 at 11:49 AM Paweł Anikiel  wrote:
>
> These changes add the third chameleon variation and make it easier to
> deploy images to different boards.
>
> v2 changes:
>  - rename chameleonv3.dts to .dtsi
>  - add missing CONFIG_SPL_MAX_SIZE symbol
>
> Paweł Anikiel (6):
>   socfpga: chameleonv3: Enable ext4 in SPL
>   socfpga: chameleonv3: Move environment to a text file
>   arm: dts: chameleonv3: Override chameleonv3 bitstream names
>   arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi
>   arm: dts: chameleonv3: Add 270-2 variant
>   chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig
>
>  arch/arm/dts/Makefile   |  1 +
>  ...eleonv3.dts => socfpga_arria10_chameleonv3.dtsi} |  0
>  .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi   | 12 
>  arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts  |  5 +
>  .../socfpga_arria10_chameleonv3_270_3-u-boot.dtsi   |  4 
>  arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts  |  2 +-
>  .../socfpga_arria10_chameleonv3_480_2-u-boot.dtsi   |  4 
>  arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts  |  2 +-
>  board/google/chameleonv3/environment.txt| 13 +
>  configs/socfpga_chameleonv3_defconfig   |  2 ++
>  include/configs/socfpga_chameleonv3.h   |  9 -
>  11 files changed, 47 insertions(+), 7 deletions(-)
>  rename arch/arm/dts/{socfpga_arria10_chameleonv3.dts => 
> socfpga_arria10_chameleonv3.dtsi} (100%)
>  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
>  create mode 100644 board/google/chameleonv3/environment.txt
>
> --
> 2.38.0.413.g74048e4d9e-goog
>

Hi Tien,

Could you please take a look? Do you have any remarks about the patchset?

Regards,
Paweł

[PATCH v2 6/6] chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig

[Paweł Anikiel]

This file was missed during the conversion process. Add the symbol to
defconfig.

Signed-off-by: Paweł Anikiel 
---
 configs/socfpga_chameleonv3_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_chameleonv3_defconfig 
b/configs/socfpga_chameleonv3_defconfig
index e628ee8ad5..6980fafd3c 100644
--- a/configs/socfpga_chameleonv3_defconfig
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x1
 CONFIG_ENV_OFFSET=0x4400
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
 CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_SPL_MAX_SIZE=0x4
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
 CONFIG_SPL_FS_EXT4=y
-- 
2.38.0.413.g74048e4d9e-goog

[PATCH v2 5/6] arm: dts: chameleonv3: Add 270-2 variant

[Paweł Anikiel]

Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module

Signed-off-by: Paweł Anikiel 
---
 arch/arm/dts/Makefile|  1 +
 .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi| 12 
 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts   |  5 +
 3 files changed, 18 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9b00b64509..fc6f6be567 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -429,6 +429,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_agilex_socdk.dtb\
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
+   socfpga_arria10_chameleonv3_270_2.dtb   \
socfpga_arria10_chameleonv3_270_3.dtb   \
socfpga_arria10_chameleonv3_480_2.dtb   \
socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
new file mode 100644
index 00..05b4485cf3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+   altr,bitstream = "fpga-270-2.itb";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
new file mode 100644
index 00..bef0280212
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.dtsi"
-- 
2.38.0.413.g74048e4d9e-goog

[PATCH v2 4/6] arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi

[Paweł Anikiel]

This file is included by the different chameleonv3 variants. Change the
name to .dtsi.

Signed-off-by: Paweł Anikiel 
---
 ...arria10_chameleonv3.dts => socfpga_arria10_chameleonv3.dtsi} | 0
 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts  | 2 +-
 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts  | 2 +-
 3 files changed, 2 insertions(+), 2 deletions(-)
 rename arch/arm/dts/{socfpga_arria10_chameleonv3.dts => 
socfpga_arria10_chameleonv3.dtsi} (100%)

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3.dtsi
similarity index 100%
rename from arch/arm/dts/socfpga_arria10_chameleonv3.dts
rename to arch/arm/dts/socfpga_arria10_chameleonv3.dtsi
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
index 5f40af6eb9..bef0280212 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
@@ -2,4 +2,4 @@
 /*
  * Copyright 2022 Google LLC
  */
-#include "socfpga_arria10_chameleonv3.dts"
+#include "socfpga_arria10_chameleonv3.dtsi"
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
index 5f40af6eb9..bef0280212 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
@@ -2,4 +2,4 @@
 /*
  * Copyright 2022 Google LLC
  */
-#include "socfpga_arria10_chameleonv3.dts"
+#include "socfpga_arria10_chameleonv3.dtsi"
-- 
2.38.0.413.g74048e4d9e-goog

[PATCH v2 3/6] arm: dts: chameleonv3: Override chameleonv3 bitstream names

[Paweł Anikiel]

Set the bitstream name per Chameleon variant. This allows the same
boot filesystem with all bitstream variants to be used on different
boards.

Signed-off-by: Paweł Anikiel 
---
 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi | 4 
 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi | 4 
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
index e789d49657..a7aa17b220 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
@@ -6,3 +6,7 @@
 #include "socfpga_arria10-handoff.dtsi"
 #include "socfpga_arria10_handoff_u-boot.dtsi"
 #include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+   altr,bitstream = "fpga-270-3.itb";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
index 7bbcc471c5..82a94894ea 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
@@ -6,3 +6,7 @@
 #include "socfpga_arria10-handoff.dtsi"
 #include "socfpga_arria10_handoff_u-boot.dtsi"
 #include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+   altr,bitstream = "fpga-480-2.itb";
+};
-- 
2.38.0.413.g74048e4d9e-goog

[PATCH v2 1/6] socfpga: chameleonv3: Enable ext4 in SPL

[Paweł Anikiel]

Allow SPL to boot from an ext4 filesystem.

Signed-off-by: Paweł Anikiel 
---
 configs/socfpga_chameleonv3_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_chameleonv3_defconfig 
b/configs/socfpga_chameleonv3_defconfig
index 478efc59ea..e628ee8ad5 100644
--- a/configs/socfpga_chameleonv3_defconfig
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
 CONFIG_SPL_TEXT_BASE=0xFFE0
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
+CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
-- 
2.38.0.413.g74048e4d9e-goog

[PATCH v2 2/6] socfpga: chameleonv3: Move environment to a text file

[Paweł Anikiel]

Move the environment to an easily editable text file in the boot
partition

Signed-off-by: Paweł Anikiel 
---
 board/google/chameleonv3/environment.txt | 13 +
 include/configs/socfpga_chameleonv3.h|  9 -
 2 files changed, 17 insertions(+), 5 deletions(-)
 create mode 100644 board/google/chameleonv3/environment.txt

diff --git a/board/google/chameleonv3/environment.txt 
b/board/google/chameleonv3/environment.txt
new file mode 100644
index 00..52aedbb90a
--- /dev/null
+++ b/board/google/chameleonv3/environment.txt
@@ -0,0 +1,13 @@
+# MMC boot command
+bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm
+
+# Network boot command and vars
+bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm
+autoload=no
+serverip=192.168.0.1
+
+# U-Boot will run this after loading this file
+bootcmd_txt=run bootcmd_mmc
+
+# Kernel cmdline
+bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 
rootflags=subvol=root rw rootwait
diff --git a/include/configs/socfpga_chameleonv3.h 
b/include/configs/socfpga_chameleonv3.h
index 75d2081fac..4c43d89a20 100644
--- a/include/configs/socfpga_chameleonv3.h
+++ b/include/configs/socfpga_chameleonv3.h
@@ -21,11 +21,10 @@
 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-   "autoload=no\0" \
-   "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw 
rootwait\0" \
-   "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
-   "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
-   "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
+   "distro_bootcmd=bridge enable; " \
+   "load mmc 0:1 ${loadaddr} u-boot.txt; " \
+   "env import -t ${loadaddr}; " \
+   "run bootcmd_txt\0"
 
 /*
  * L4 OSC1 Timer 0
-- 
2.38.0.413.g74048e4d9e-goog

[PATCH v2 0/6] Update Chameleon v3 configuration

[Paweł Anikiel]

These changes add the third chameleon variation and make it easier to
deploy images to different boards.

v2 changes:
 - rename chameleonv3.dts to .dtsi
 - add missing CONFIG_SPL_MAX_SIZE symbol

Paweł Anikiel (6):
  socfpga: chameleonv3: Enable ext4 in SPL
  socfpga: chameleonv3: Move environment to a text file
  arm: dts: chameleonv3: Override chameleonv3 bitstream names
  arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi
  arm: dts: chameleonv3: Add 270-2 variant
  chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig

 arch/arm/dts/Makefile   |  1 +
 ...eleonv3.dts => socfpga_arria10_chameleonv3.dtsi} |  0
 .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi   | 12 
 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts  |  5 +
 .../socfpga_arria10_chameleonv3_270_3-u-boot.dtsi   |  4 
 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts  |  2 +-
 .../socfpga_arria10_chameleonv3_480_2-u-boot.dtsi   |  4 
 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts  |  2 +-
 board/google/chameleonv3/environment.txt| 13 +
 configs/socfpga_chameleonv3_defconfig   |  2 ++
 include/configs/socfpga_chameleonv3.h   |  9 -
 11 files changed, 47 insertions(+), 7 deletions(-)
 rename arch/arm/dts/{socfpga_arria10_chameleonv3.dts => 
socfpga_arria10_chameleonv3.dtsi} (100%)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
 create mode 100644 board/google/chameleonv3/environment.txt

-- 
2.38.0.413.g74048e4d9e-goog

Re: [PATCH 4/4] arm: dts: chameleonv3: Add 270-2 variant

[Paweł Anikiel]

On Fri, Sep 2, 2022 at 9:59 PM Simon Glass  wrote:
>
> Hi Paweł,
>
> On Fri, 2 Sept 2022 at 07:16, Paweł Anikiel  wrote:
> >
> > On Tue, Aug 30, 2022 at 5:57 PM Simon Glass  wrote:
> > >
> > > Hi Paweł,
> > >
> > > On Tue, 30 Aug 2022 at 05:51, Paweł Anikiel  wrote:
> > > >
> > > > On Tue, Aug 30, 2022 at 5:13 AM Alexandru M Stan  
> > > > wrote:
> > > > >
> > > > > Hey Simon,
> > > > >
> > > > > On Mon, Aug 29, 2022 at 7:29 PM Simon Glass  wrote:
> > > > > >
> > > > > > Hi Paweł,
> > > > > >
> > > > > > On Mon, 29 Aug 2022 at 02:23, Paweł Anikiel  
> > > > > > wrote:
> > > > > > >
> > > > > > > On Sat, Aug 27, 2022 at 2:22 AM Simon Glass  
> > > > > > > wrote:
> > > > > > > >
> > > > > > > > Hi Paweł,
> > > > > > > >
> > > > > > > > On Fri, 26 Aug 2022 at 01:54, Paweł Anikiel  
> > > > > > > > wrote:
> > > > > > > > >
> > > > > > > > > Add devicetree for chameleonv3 with the 270-2I2-D11E variant 
> > > > > > > > > of the
> > > > > > > > > Mercury+ AA1 module
> > > > > > > > >
> > > > > > > > > Signed-off-by: Paweł Anikiel 
> > > > > > > > > ---
> > > > > > > > >  arch/arm/dts/Makefile|  1 +
> > > > > > > > >  .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi| 12 
> > > > > > > > > 
> > > > > > > > >  arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts   |  5 
> > > > > > > > > +
> > > > > > > > >  3 files changed, 18 insertions(+)
> > > > > > > > >  create mode 100644 
> > > > > > > > > arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > > > > > > > >  create mode 100644 
> > > > > > > > > arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> > > > > > > > >
> > > > > >
> > > > > >
> > > > > > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > > > > > > > > index 7330121dba..36d5d65595 100644
> > > > > > > > > --- a/arch/arm/dts/Makefile
> > > > > > > > > +++ b/arch/arm/dts/Makefile
> > > > > > > > > @@ -425,6 +425,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += 
> > > > > > > > >   \
> > > > > > > > > socfpga_agilex_socdk.dtb\
> > > > > > > > > socfpga_arria5_secu1.dtb\
> > > > > > > > > socfpga_arria5_socdk.dtb\
> > > > > > > > > +   socfpga_arria10_chameleonv3_270_2.dtb   \
> > > > > > > > > socfpga_arria10_chameleonv3_270_3.dtb   \
> > > > > > > > > socfpga_arria10_chameleonv3_480_2.dtb   \
> > > > > > > > > socfpga_arria10_socdk_sdmmc.dtb \
> > > > > > > > > diff --git 
> > > > > > > > > a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi 
> > > > > > > > > b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > > > > > > > > new file mode 100644
> > > > > > > > > index 00..05b4485cf3
> > > > > > > > > --- /dev/null
> > > > > > > > > +++ 
> > > > > > > > > b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > > > > > > > > @@ -0,0 +1,12 @@
> > > > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > > > +/*
> > > > > > > > > + * Copyright 2022 Google LLC
> > > > > > > > > + */
> > > > > > > > > +#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
> > > > > > > > > +#include "socfpga_arria10-handoff.dtsi"

Re: [PATCH 4/4] arm: dts: chameleonv3: Add 270-2 variant

[Paweł Anikiel]

On Tue, Aug 30, 2022 at 5:57 PM Simon Glass  wrote:
>
> Hi Paweł,
>
> On Tue, 30 Aug 2022 at 05:51, Paweł Anikiel  wrote:
> >
> > On Tue, Aug 30, 2022 at 5:13 AM Alexandru M Stan  
> > wrote:
> > >
> > > Hey Simon,
> > >
> > > On Mon, Aug 29, 2022 at 7:29 PM Simon Glass  wrote:
> > > >
> > > > Hi Paweł,
> > > >
> > > > On Mon, 29 Aug 2022 at 02:23, Paweł Anikiel  wrote:
> > > > >
> > > > > On Sat, Aug 27, 2022 at 2:22 AM Simon Glass  wrote:
> > > > > >
> > > > > > Hi Paweł,
> > > > > >
> > > > > > On Fri, 26 Aug 2022 at 01:54, Paweł Anikiel  
> > > > > > wrote:
> > > > > > >
> > > > > > > Add devicetree for chameleonv3 with the 270-2I2-D11E variant of 
> > > > > > > the
> > > > > > > Mercury+ AA1 module
> > > > > > >
> > > > > > > Signed-off-by: Paweł Anikiel 
> > > > > > > ---
> > > > > > >  arch/arm/dts/Makefile|  1 +
> > > > > > >  .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi| 12 
> > > > > > > 
> > > > > > >  arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts   |  5 +
> > > > > > >  3 files changed, 18 insertions(+)
> > > > > > >  create mode 100644 
> > > > > > > arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > > > > > >  create mode 100644 
> > > > > > > arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> > > > > > >
> > > >
> > > >
> > > > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > > > > > > index 7330121dba..36d5d65595 100644
> > > > > > > --- a/arch/arm/dts/Makefile
> > > > > > > +++ b/arch/arm/dts/Makefile
> > > > > > > @@ -425,6 +425,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += 
> > > > > > >   \
> > > > > > > socfpga_agilex_socdk.dtb\
> > > > > > > socfpga_arria5_secu1.dtb\
> > > > > > > socfpga_arria5_socdk.dtb\
> > > > > > > +   socfpga_arria10_chameleonv3_270_2.dtb   \
> > > > > > > socfpga_arria10_chameleonv3_270_3.dtb   \
> > > > > > > socfpga_arria10_chameleonv3_480_2.dtb   \
> > > > > > > socfpga_arria10_socdk_sdmmc.dtb \
> > > > > > > diff --git 
> > > > > > > a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi 
> > > > > > > b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > > > > > > new file mode 100644
> > > > > > > index 00..05b4485cf3
> > > > > > > --- /dev/null
> > > > > > > +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > > > > > > @@ -0,0 +1,12 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > > > +/*
> > > > > > > + * Copyright 2022 Google LLC
> > > > > > > + */
> > > > > > > +#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
> > > > > > > +#include "socfpga_arria10-handoff.dtsi"
> > > > > > > +#include "socfpga_arria10_handoff_u-boot.dtsi"
> > > > > > > +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
> > > > > > > +
> > > > > > > +&fpga_mgr {
> > > > > > > +   altr,bitstream = "fpga-270-2.itb";
> > > > > > > +};
> > > > > > > diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts 
> > > > > > > b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> > > > > > > new file mode 100644
> > > > > > > index 00..5f40af6eb9
> > > > > > > --- /dev/null
> > > > > > > +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> > > > > > > @@ -0,0 +1,5 @@
> > > > > > > +// SPDX-License-Identifier: GPL-2.0
> > &g

Re: [PATCH 4/4] arm: dts: chameleonv3: Add 270-2 variant

[Paweł Anikiel]

On Tue, Aug 30, 2022 at 5:13 AM Alexandru M Stan  wrote:
>
> Hey Simon,
>
> On Mon, Aug 29, 2022 at 7:29 PM Simon Glass  wrote:
> >
> > Hi Paweł,
> >
> > On Mon, 29 Aug 2022 at 02:23, Paweł Anikiel  wrote:
> > >
> > > On Sat, Aug 27, 2022 at 2:22 AM Simon Glass  wrote:
> > > >
> > > > Hi Paweł,
> > > >
> > > > On Fri, 26 Aug 2022 at 01:54, Paweł Anikiel  wrote:
> > > > >
> > > > > Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
> > > > > Mercury+ AA1 module
> > > > >
> > > > > Signed-off-by: Paweł Anikiel 
> > > > > ---
> > > > >  arch/arm/dts/Makefile|  1 +
> > > > >  .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi| 12 
> > > > > 
> > > > >  arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts   |  5 +
> > > > >  3 files changed, 18 insertions(+)
> > > > >  create mode 100644 
> > > > > arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > > > >  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> > > > >
> >
> >
> > > > > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > > > > index 7330121dba..36d5d65595 100644
> > > > > --- a/arch/arm/dts/Makefile
> > > > > +++ b/arch/arm/dts/Makefile
> > > > > @@ -425,6 +425,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += 
> > > > >   \
> > > > > socfpga_agilex_socdk.dtb\
> > > > > socfpga_arria5_secu1.dtb\
> > > > > socfpga_arria5_socdk.dtb\
> > > > > +   socfpga_arria10_chameleonv3_270_2.dtb   \
> > > > > socfpga_arria10_chameleonv3_270_3.dtb   \
> > > > > socfpga_arria10_chameleonv3_480_2.dtb   \
> > > > > socfpga_arria10_socdk_sdmmc.dtb \
> > > > > diff --git 
> > > > > a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi 
> > > > > b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > > > > new file mode 100644
> > > > > index 00..05b4485cf3
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > > > > @@ -0,0 +1,12 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > +/*
> > > > > + * Copyright 2022 Google LLC
> > > > > + */
> > > > > +#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
> > > > > +#include "socfpga_arria10-handoff.dtsi"
> > > > > +#include "socfpga_arria10_handoff_u-boot.dtsi"
> > > > > +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
> > > > > +
> > > > > +&fpga_mgr {
> > > > > +   altr,bitstream = "fpga-270-2.itb";
> > > > > +};
> > > > > diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts 
> > > > > b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> > > > > new file mode 100644
> > > > > index 00..5f40af6eb9
> > > > > --- /dev/null
> > > > > +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> > > > > @@ -0,0 +1,5 @@
> > > > > +// SPDX-License-Identifier: GPL-2.0
> > > > > +/*
> > > > > + * Copyright 2022 Google LLC
> > > > > + */
> > > > > +#include "socfpga_arria10_chameleonv3.dts"
> > > >
> > > > Can you create a common .dtsi file instead? We should not be including
> > > > a .dts file into another file.
> > > >
> > > Do you mean renaming chameleonv3.dts to .dtsi? In Linux it's a .dts,
> > > because nothing includes it (no handoff headers are needed). Is it
> > > fine to have the names differ across U-Boot and Linux?
> >
> > Ideally not, but we should not include a .dts file in another one and
> > it is probably more important to follow that rule. But why is Linux
> > not getting this variant?
> >
> > Regards,
> > Simon
>
> Linux (at least for the near future) does not care about which variant
> it is. The big differences between 270, 480, -2, -3 are mostly about
> the number of FPGA logic gates and speed grades. Such things affect
> the FPGA bitstream greatly, and might even affect clock presets that
> u-boot cares about, but by the time linux loads it doesn't matter
> anymore.

Perhaps a more detailed explanation:

The Main and Peripheral PLLs (as well as some other clocks) are
configured by U-Boot. On the other hand, Linux expects them to be
configured when it boots, and does not touch them.

The clock configuration depends mainly on the speed grade of the Arria
10 SoC (marked by us as -2 and -3), but also on the fpga hardware
design (e.g. user-defined clocks for the fpga), and is included in the
u-boot devicetree:
> +#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
> +#include "socfpga_arria10-handoff.dtsi"
> +#include "socfpga_arria10_handoff_u-boot.dtsi"

Linux, on the other hand, doesn't need such information, and there is
no distinction between the different chameleon variants.

Regards,
Paweł

Re: [PATCH 4/4] arm: dts: chameleonv3: Add 270-2 variant

[Paweł Anikiel]

On Sat, Aug 27, 2022 at 2:22 AM Simon Glass  wrote:
>
> Hi Paweł,
>
> On Fri, 26 Aug 2022 at 01:54, Paweł Anikiel  wrote:
> >
> > Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
> > Mercury+ AA1 module
> >
> > Signed-off-by: Paweł Anikiel 
> > ---
> >  arch/arm/dts/Makefile|  1 +
> >  .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi| 12 
> >  arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts   |  5 +
> >  3 files changed, 18 insertions(+)
> >  create mode 100644 
> > arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> >  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> >
> > diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> > index 7330121dba..36d5d65595 100644
> > --- a/arch/arm/dts/Makefile
> > +++ b/arch/arm/dts/Makefile
> > @@ -425,6 +425,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
> > \
> > socfpga_agilex_socdk.dtb\
> > socfpga_arria5_secu1.dtb\
> > socfpga_arria5_socdk.dtb\
> > +   socfpga_arria10_chameleonv3_270_2.dtb   \
> > socfpga_arria10_chameleonv3_270_3.dtb   \
> > socfpga_arria10_chameleonv3_480_2.dtb   \
> > socfpga_arria10_socdk_sdmmc.dtb \
> > diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi 
> > b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > new file mode 100644
> > index 00..05b4485cf3
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
> > @@ -0,0 +1,12 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2022 Google LLC
> > + */
> > +#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
> > +#include "socfpga_arria10-handoff.dtsi"
> > +#include "socfpga_arria10_handoff_u-boot.dtsi"
> > +#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
> > +
> > +&fpga_mgr {
> > +   altr,bitstream = "fpga-270-2.itb";
> > +};
> > diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts 
> > b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> > new file mode 100644
> > index 00..5f40af6eb9
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
> > @@ -0,0 +1,5 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2022 Google LLC
> > + */
> > +#include "socfpga_arria10_chameleonv3.dts"
>
> Can you create a common .dtsi file instead? We should not be including
> a .dts file into another file.
>
Do you mean renaming chameleonv3.dts to .dtsi? In Linux it's a .dts,
because nothing includes it (no handoff headers are needed). Is it
fine to have the names differ across U-Boot and Linux?

Regards,
Paweł

[PATCH 4/4] arm: dts: chameleonv3: Add 270-2 variant

[Paweł Anikiel]

Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module

Signed-off-by: Paweł Anikiel 
---
 arch/arm/dts/Makefile|  1 +
 .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi| 12 
 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts   |  5 +
 3 files changed, 18 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7330121dba..36d5d65595 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -425,6 +425,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_agilex_socdk.dtb\
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
+   socfpga_arria10_chameleonv3_270_2.dtb   \
socfpga_arria10_chameleonv3_270_3.dtb   \
socfpga_arria10_chameleonv3_480_2.dtb   \
socfpga_arria10_socdk_sdmmc.dtb \
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
new file mode 100644
index 00..05b4485cf3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
@@ -0,0 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_480_2_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+   altr,bitstream = "fpga-270-2.itb";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
new file mode 100644
index 00..5f40af6eb9
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.dts"
-- 
2.37.2.672.g94769d06f0-goog

[PATCH 3/4] arm: dts: chameleonv3: Override chameleonv3 bitstream names

[Paweł Anikiel]

Set the bitstream name per Chameleon variant. This allows the same
boot filesystem with all bitstream variants to be used on different
boards.

Signed-off-by: Paweł Anikiel 
---
 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi | 4 
 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi | 4 
 2 files changed, 8 insertions(+)

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
index e789d49657..a7aa17b220 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
@@ -6,3 +6,7 @@
 #include "socfpga_arria10-handoff.dtsi"
 #include "socfpga_arria10_handoff_u-boot.dtsi"
 #include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+   altr,bitstream = "fpga-270-3.itb";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
index 7bbcc471c5..82a94894ea 100644
--- a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
@@ -6,3 +6,7 @@
 #include "socfpga_arria10-handoff.dtsi"
 #include "socfpga_arria10_handoff_u-boot.dtsi"
 #include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
+
+&fpga_mgr {
+   altr,bitstream = "fpga-480-2.itb";
+};
-- 
2.37.2.672.g94769d06f0-goog

[PATCH 2/4] socfpga: chameleonv3: Move environment to a text file

[Paweł Anikiel]

Move the environment to an easily editable text file in the boot
partition

Signed-off-by: Paweł Anikiel 
---
 board/google/chameleonv3/environment.txt | 13 +
 include/configs/socfpga_chameleonv3.h|  9 -
 2 files changed, 17 insertions(+), 5 deletions(-)
 create mode 100644 board/google/chameleonv3/environment.txt

diff --git a/board/google/chameleonv3/environment.txt 
b/board/google/chameleonv3/environment.txt
new file mode 100644
index 00..52aedbb90a
--- /dev/null
+++ b/board/google/chameleonv3/environment.txt
@@ -0,0 +1,13 @@
+# MMC boot command
+bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm
+
+# Network boot command and vars
+bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm
+autoload=no
+serverip=192.168.0.1
+
+# U-Boot will run this after loading this file
+bootcmd_txt=run bootcmd_mmc
+
+# Kernel cmdline
+bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 
rootflags=subvol=root rw rootwait
diff --git a/include/configs/socfpga_chameleonv3.h 
b/include/configs/socfpga_chameleonv3.h
index 75d2081fac..4c43d89a20 100644
--- a/include/configs/socfpga_chameleonv3.h
+++ b/include/configs/socfpga_chameleonv3.h
@@ -21,11 +21,10 @@
 #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
 
 #define CONFIG_EXTRA_ENV_SETTINGS \
-   "autoload=no\0" \
-   "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw 
rootwait\0" \
-   "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
-   "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
-   "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
+   "distro_bootcmd=bridge enable; " \
+   "load mmc 0:1 ${loadaddr} u-boot.txt; " \
+   "env import -t ${loadaddr}; " \
+   "run bootcmd_txt\0"
 
 /*
  * L4 OSC1 Timer 0
-- 
2.37.2.672.g94769d06f0-goog

[PATCH 1/4] socfpga: chameleonv3: Enable ext4 in SPL

[Paweł Anikiel]

Allow SPL to boot from an ext4 filesystem.

Signed-off-by: Paweł Anikiel 
---
 configs/socfpga_chameleonv3_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/socfpga_chameleonv3_defconfig 
b/configs/socfpga_chameleonv3_defconfig
index e78d3b51de..a6901980b5 100644
--- a/configs/socfpga_chameleonv3_defconfig
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -6,6 +6,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
 CONFIG_SPL_TEXT_BASE=0xFFE0
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
+CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_FS_FAT=y
 CONFIG_DISTRO_DEFAULTS=y
 CONFIG_FIT=y
-- 
2.37.2.672.g94769d06f0-goog

[PATCH 0/4] Update Chameleon v3 configuration

[Paweł Anikiel]

These changes add the third chameleon variation and make it easier to
deploy images to different boards.

Paweł Anikiel (4):
  socfpga: chameleonv3: Enable ext4 in SPL
  socfpga: chameleonv3: Move environment to a text file
  arm: dts: chameleonv3: Override chameleonv3 bitstream names
  arm: dts: chameleonv3: Add 270-2 variant

 arch/arm/dts/Makefile   |  1 +
 .../socfpga_arria10_chameleonv3_270_2-u-boot.dtsi   | 12 
 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts  |  5 +
 .../socfpga_arria10_chameleonv3_270_3-u-boot.dtsi   |  4 
 .../socfpga_arria10_chameleonv3_480_2-u-boot.dtsi   |  4 
 board/google/chameleonv3/environment.txt| 13 +
 configs/socfpga_chameleonv3_defconfig   |  1 +
 include/configs/socfpga_chameleonv3.h   |  9 -
 8 files changed, 44 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_2.dts
 create mode 100644 board/google/chameleonv3/environment.txt

-- 
2.37.2.672.g94769d06f0-goog

Re: [PATCH] misc: atsha204a: Don't check for error when waking up the device

[Paweł Anikiel]

Hi Pali,

I applied the patch and it works fine on my board. Log from atsha204a_wakeup():
  Waking up ATSHA204A
  Try 1... success

Tested-by: Paweł Anikiel 

Regards,
Paweł

On Sun, Aug 7, 2022 at 9:30 PM Pali Rohár  wrote:
>
> Paweł, could you please test this change if it works on your board? I
> was that you were fixing another wakeup issue in patch "misc: atsha204a:
> Increase wake delay by tWHI".
>
> On Thursday 04 August 2022 13:03:44 Pali Rohár wrote:
> > The device ignores any levels or transitions on the SCL pin when the device
> > is idle, asleep or during waking up.
> >
> > Linux kernel driver for atsha204a (atmel-sha204a.ko) also ignores return
> > value from i2c wakeup send command, see:
> > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/crypto/atmel-i2c.c?h=v5.19#n174
> >
> > And also userspace Turris libatsha204 library ignores return value from
> > wakeup send command, see:
> > https://gitlab.nic.cz/turris/libatsha204/-/blob/v29.2/src/libatsha204/layer_ni2c.c#L75-76
> >
> > U-Boot driver should do same thing.
> >
> > Fixes waking up ATSHA204 on Turris 1.x boards.
> >
> > Signed-off-by: Pali Rohár 
> > ---
> >  drivers/misc/atsha204a-i2c.c | 11 ++-
> >  1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
> > index 81ecb5b6177b..fa2d5948f128 100644
> > --- a/drivers/misc/atsha204a-i2c.c
> > +++ b/drivers/misc/atsha204a-i2c.c
> > @@ -103,12 +103,13 @@ int atsha204a_wakeup(struct udevice *dev)
> >   for (try = 1; try <= 10; ++try) {
> >   debug("Try %i... ", try);
> >
> > + /*
> > +  * The device ignores any levels or transitions on the SCL pin
> > +  * when the device is idle, asleep or during waking up.
> > +  * Don't check for error when waking up the device.
> > +  */
> >   memset(req, 0, 4);
> > - res = atsha204a_send(dev, req, 4);
> > - if (res) {
> > - debug("failed on I2C send, trying again\n");
> > - continue;
> > - }
> > + atsha204a_send(dev, req, 4);
> >
> >   udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
> >
> > --
> > 2.20.1
> >

Re: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg

[Paweł Anikiel]

On Mon, Jun 20, 2022 at 2:29 PM Chee, Tien Fong
 wrote:
>
>
>
> > -Original Message-
> > From: Paweł Anikiel 
> > Sent: Monday, 20 June, 2022 8:14 PM
> > To: Chee, Tien Fong 
> > Cc: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> > michal.si...@xilinx.com; u-boot@lists.denx.de; s...@chromium.org;
> > feste...@denx.de; ja...@amarulasolutions.com;
> > andre.przyw...@arm.com; Armstrong, Neil ;
> > pbrobin...@gmail.com; thar...@gateworks.com; paul@linaro.org;
> > christianshew...@gmail.com; adrian.fiergol...@fastree3d.com;
> > marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew Chin
> > ; upstr...@semihalf.com;
> > ams...@chromium.org
> > Subject: Re: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy
> > waiting in cm_full_cfg
> >
> > On Mon, Jun 20, 2022 at 10:40 AM Chee, Tien Fong
> >  wrote:
> > >
> > > Hi,
> > >
> > > > -Original Message-
> > > > From: Paweł Anikiel 
> > > > Sent: Friday, 17 June, 2022 6:47 PM
> > > > To: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> > > > Chee, Tien Fong ; michal.si...@xilinx.com
> > > > Cc: u-boot@lists.denx.de; s...@chromium.org; feste...@denx.de;
> > > > ja...@amarulasolutions.com; andre.przyw...@arm.com; Armstrong,
> > Neil
> > > > ; pbrobin...@gmail.com;
> > > > thar...@gateworks.com; paul@linaro.org;
> > > > christianshew...@gmail.com; adrian.fiergol...@fastree3d.com;
> > > > marek.be...@nic.cz; Denk, Wolfgang ; Lim, Elly Siew
> > Chin
> > > > ; upstr...@semihalf.com;
> > > > ams...@chromium.org; Paweł Anikiel 
> > > > Subject: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy
> > > > waiting in cm_full_cfg
> > > >
> > > > Using udelay while the clocks aren't fully configured causes the
> > > > timer system to save the wrong clock rate. Use sdelay and
> > > > wait_on_value instead (the values used in these functions were found
> > experimentally).
> > > >
> > > > Signed-off-by: Paweł Anikiel 
> > > > ---
> > > >  arch/arm/mach-socfpga/clock_manager_arria10.c | 31
> > > > +-
> > > > -
> > > >  1 file changed, 22 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > index 58d5d3fd8a..b48a2b47bc 100644
> > > > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > > > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > >
> > > Did you try to call timer_init() after cm_basic_init() in board_init_f? 
> > > If that's
> > working, then no change is required to fix this clock issue.
> >
> > Seems like timer_init() isn't implemented on Arria 10 (it defaults to the
> > return 0 stub). I also tried dm_timer_init(), no luck.
> >
> > I did some code digging, the clock rate is read by clk_get_rate(), and the
> > timer rate is set by dw_apb_timer_probe() (drivers/timer/dw-apb-
> > timer.c:77), and there doesn't seem to be a good way of updating that value
> > later.
> >
> > The only other function I could find that sets the timer rate is
> > timer_pre_probe() from drivers/timer/timer-uclass.c, which very much looks
> > like what we need, but it's static and the name suggests it shouldn't be 
> > called
> > manually anyway.
> >
>
> Thanks for the details finding.
>
> I found that both Cyclone 5 and S10 (including all AARCH64 devices) having 
> own timer_init() as solution for this issue.
> Cyclone 5 : 
> https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-socfpga/timer.c
> S10: 
> https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-socfpga/timer_s10.c
>
> Do you think this is good idea having the same for A10 device?

I don't think overriding timer_init() alone is going to help.
(Re)initializing the timer after cm_basic_init() won't help the fact
that xdelay() divides the clock ticks (which are correct) by
gd->timer->uclass_priv_->clock_rate
(https://source.denx.de/u-boot/u-boot/-/blob/master/lib/time.c#L81)
(which was incorrectly set by a call to udelay() from cm_full_cfg()).

I honestly don't see how Cyclone/Arria 5 solve this problem, as they
don't implement a __udelay(), and their cm_basic_init() also uses
timer-based delays
(https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/mach-socfpga/clock_manager_gen5.c#L98,
eventually calls udelay(1) in include/wait_bit.h). I don't have any
board on which I could test this on, but I suspect they may also save
the wrong clock rate value (causing xdelay() to delay for wrong
amounts of time).

Stratix 10 looks okay to me, as it implements its own __udelay() and
__usec_to_tick() in SPL.

So a solution would be to implement a __udelay() and a
__usec_to_tick(). I don't really know how to do that though, S10 uses
the built-in armv8 timer for that.

Regards,
Paweł

Re: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg

[Paweł Anikiel]

On Mon, Jun 20, 2022 at 10:40 AM Chee, Tien Fong
 wrote:
>
> Hi,
>
> > -Original Message-
> > From: Paweł Anikiel 
> > Sent: Friday, 17 June, 2022 6:47 PM
> > To: Vasut, Marek ; simon.k.r.goldschm...@gmail.com;
> > Chee, Tien Fong ; michal.si...@xilinx.com
> > Cc: u-boot@lists.denx.de; s...@chromium.org; feste...@denx.de;
> > ja...@amarulasolutions.com; andre.przyw...@arm.com; Armstrong, Neil
> > ; pbrobin...@gmail.com;
> > thar...@gateworks.com; paul@linaro.org; christianshew...@gmail.com;
> > adrian.fiergol...@fastree3d.com; marek.be...@nic.cz; Denk, Wolfgang
> > ; Lim, Elly Siew Chin ;
> > upstr...@semihalf.com; ams...@chromium.org; Paweł Anikiel
> > 
> > Subject: [PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting
> > in cm_full_cfg
> >
> > Using udelay while the clocks aren't fully configured causes the timer 
> > system
> > to save the wrong clock rate. Use sdelay and wait_on_value instead (the
> > values used in these functions were found experimentally).
> >
> > Signed-off-by: Paweł Anikiel 
> > ---
> >  arch/arm/mach-socfpga/clock_manager_arria10.c | 31 +-
> > -
> >  1 file changed, 22 insertions(+), 9 deletions(-)
> >
> > diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > b/arch/arm/mach-socfpga/clock_manager_arria10.c
> > index 58d5d3fd8a..b48a2b47bc 100644
> > --- a/arch/arm/mach-socfpga/clock_manager_arria10.c
> > +++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
>
> Did you try to call timer_init() after cm_basic_init() in board_init_f? If 
> that's working, then no change is required to fix this clock issue.

Seems like timer_init() isn't implemented on Arria 10 (it defaults to
the return 0 stub). I also tried dm_timer_init(), no luck.

I did some code digging, the clock rate is read by clk_get_rate(), and
the timer rate is set by dw_apb_timer_probe()
(drivers/timer/dw-apb-timer.c:77), and there doesn't seem to be a good
way of updating that value later.

The only other function I could find that sets the timer rate is
timer_pre_probe() from drivers/timer/timer-uclass.c, which very much
looks like what we need, but it's static and the name suggests it
shouldn't be called manually anyway.

Regards,
Paweł

[PATCH v3 11/11] socfpga: arria10: Allow dcache_enable before relocation

[Paweł Anikiel]

Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 arch/arm/mach-socfpga/misc_arria10.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
index 0ed2adfd84..7ce888d197 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)
return 0;
 }
 #endif
+
+void dram_bank_mmu_setup(int bank)
+{
+   struct bd_info *bd = gd->bd;
+   u32 start, size;
+   int i;
+
+   /* If we're still in OCRAM, don't set the XN bit on it */
+   if (!(gd->flags & GD_FLG_RELOC)) {
+   set_section_dcache(
+   CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+   DCACHE_WRITETHROUGH);
+   }
+
+   /*
+* The default implementation of this function allows the DRAM dcache
+* to be enabled only after relocation. However, to speed up ECC
+* initialization, we want to be able to enable DRAM dcache before
+* relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+* is set first).
+*/
+   start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+   size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+   for (i = start; i < start + size; i++)
+   set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
-- 
2.36.1.476.g0c4daa206d-goog

[PATCH v3 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream

[Paweł Anikiel]

For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 drivers/fpga/socfpga_arria10.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 07bfe3060e..d8089122af 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -80,6 +80,13 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
 }
 
+static int wait_for_fifo_empty(void)
+{
+   return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
+   1, FPGA_TIMEOUT_MSEC, false);
+}
+
 int is_fpgamgr_early_user_mode(void)
 {
return (readl(&fpga_manager_base->imgcfg_stat) &
@@ -874,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void 
*buf, size_t bsize,
 
WATCHDOG_RESET();
}
+   wait_for_fifo_empty();
 
if (fpga_loadfs.rbfinfo.section == periph_section) {
if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
-- 
2.36.1.476.g0c4daa206d-goog

[PATCH v3 09/11] socfpga: arria10: Improve bitstream loading speed

[Paweł Anikiel]

Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):

 * Change the size of the first fs read, so that all the subsequent
   reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
   This value was chosen so that in subsequent reads the fat fs driver
   doesn't have to allocate a temporary buffer in get_contents
   (assuming 8KiB clusters).

 * Change the buffer size to a larger value when reading to ddr
   (but not too large, because large transfers cause a stack overflow
   in the dwmmc driver).

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 drivers/fpga/socfpga_arria10.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 798e3a3f90..07bfe3060e 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,6 +30,14 @@
 #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT   0x100
 #define DEFAULT_DDR_LOAD_ADDRESS   0x400
+#define DDR_BUFFER_SIZE0x10
+
+/* When reading bitstream from a filesystem, the size of the first read is
+ * changed so that the subsequent reads are aligned to this value. This value
+ * was chosen so that in subsequent reads the fat fs driver doesn't have to
+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
+ */
+#define MAX_FIRST_LOAD_SIZE0x2000
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -526,7 +534,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16 
*buffer)
 #ifdef CONFIG_FS_LOADER
 static int first_loading_rbf_to_buffer(struct udevice *dev,
struct fpga_loadfs_info *fpga_loadfs,
-   u32 *buffer, size_t *buffer_bsize)
+   u32 *buffer, size_t *buffer_bsize,
+   size_t *buffer_bsize_ori)
 {
u32 *buffer_p = (u32 *)*buffer;
u32 *loadable = buffer_p;
@@ -674,6 +683,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
}
 
buffer_size = rbf_size;
+   *buffer_bsize_ori = DDR_BUFFER_SIZE;
}
 
debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
@@ -686,11 +696,16 @@ static int first_loading_rbf_to_buffer(struct udevice 
*dev,
 * chunk by chunk transfer is required due to smaller buffer size
 * compare to bitstream
 */
+
+   if (buffer_size > MAX_FIRST_LOAD_SIZE)
+   buffer_size = MAX_FIRST_LOAD_SIZE;
+
if (rbf_size <= buffer_size) {
/* Loading whole bitstream into buffer */
buffer_size = rbf_size;
fpga_loadfs->remaining = 0;
} else {
+   buffer_size -= rbf_offset % buffer_size;
fpga_loadfs->remaining -= buffer_size;
}
 
@@ -806,7 +821,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void 
*buf, size_t bsize,
 * function below.
 */
ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
-  &buffer_sizebytes);
+  &buffer_sizebytes,
+  &buffer_sizebytes_ori);
if (ret == 1) {
printf("FPGA: Skipping configuration ...\n");
return 0;
-- 
2.36.1.476.g0c4daa206d-goog

[PATCH v3 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg

[Paweł Anikiel]

Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).

Signed-off-by: Paweł Anikiel 
---
 arch/arm/mach-socfpga/clock_manager_arria10.c | 31 +--
 1 file changed, 22 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 58d5d3fd8a..b48a2b47bc 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -15,6 +15,10 @@
 
 #ifdef CONFIG_SPL_BUILD
 
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound);
+
 static u32 eosc1_hz;
 static u32 cb_intosc_hz;
 static u32 f2s_free_hz;
@@ -551,13 +555,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
main_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
 }
 
@@ -585,16 +589,25 @@ static void cm_pll_ramp_periph(struct mainpll_cfg 
*main_cfg,
 clk_hz),
  socfpga_get_clkmgr_addr() +
  CLKMGR_A10_PERPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
  per_cfg->vco1_numer,
  socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
 }
 
+/* function to poll in the fsm busy bit */
+static int cm_busy_wait_for_fsm(void)
+{
+   void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);
+
+   /* 20s timeout */
+   return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 1);
+}
+
 /*
  * Setup clocks while making no assumptions of the
  * previous state of the clocks.
@@ -727,7 +740,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct 
perpll_cfg *per_cfg)
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 
/* Wait for at least 5 us */
-   udelay(5);
+   sdelay(5000);
 
/* Now deassert BGPWRDN and PWRDN */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
@@ -738,7 +751,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct 
perpll_cfg *per_cfg)
 CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 
/* Wait for at least 7 us */
-   udelay(7);
+   sdelay(7000);
 
/* enable the VCO and disable the external regulator to PLL */
writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
@@ -878,19 +891,19 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, 
struct perpll_cfg *per_cfg)
writel(CLKMGR_MAINPLL_BYPASS_RESET,
   socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);
/* wait till Clock Manager is not busy */
-   cm_wait_for_fsm();
+   cm_busy_wait_for_fsm();
 
/* release perpll from bypass */
writel(CLKMGR_PERPLL_BYPASS_RESET,
   socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);
/* wait till Clock Manager is not busy */
-   cm_wait_for_fsm();
+   cm_busy_wait_for_fsm();
 
/* clear boot mode */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,
 CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);
/* wait till Clock Manager is not busy */
-   cm_wait_for_fsm();
+   cm_busy_wait_for_fsm();
 
/* At here, we need to ramp to final value if needed */
if (pll_ramp_main_hz != 0)
-- 
2.36.1.476.g0c4daa206d-goog

[PATCH v3 07/11] sysreset: socfpga: Use parent device for reading base address

[Paweł Anikiel]

This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 drivers/sysreset/sysreset_socfpga.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/sysreset/sysreset_socfpga.c 
b/drivers/sysreset/sysreset_socfpga.c
index e38296ac3f..9b62dd5eab 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
 {
struct socfpga_sysreset_data *data = dev_get_priv(dev);
 
-   data->rstmgr_base = dev_read_addr_ptr(dev);
+   data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
return 0;
 }
 
-- 
2.36.1.476.g0c4daa206d-goog

[PATCH v3 06/11] misc: atsha204a: Increase wake delay by tWHI

[Paweł Anikiel]

>From the ATSHA204A datasheet (document DS40002025A):

Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.

tWHI value can be found in table 7-2.

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 drivers/misc/atsha204a-i2c.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index aa6acf0f9a..81ecb5b617 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -21,7 +21,8 @@
 #include 
 #include 
 
-#define ATSHA204A_TWLO 60
+#define ATSHA204A_TWLO_US  60
+#define ATSHA204A_TWHI_US  2500
 #define ATSHA204A_TRANSACTION_TIMEOUT  10
 #define ATSHA204A_TRANSACTION_RETRY5
 #define ATSHA204A_EXECTIME 5000
@@ -109,7 +110,7 @@ int atsha204a_wakeup(struct udevice *dev)
continue;
}
 
-   udelay(ATSHA204A_TWLO);
+   udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
 
res = atsha204a_recv_resp(dev, &resp);
if (res) {
-- 
2.36.1.476.g0c4daa206d-goog

[PATCH v3 05/11] config: Add Chameleonv3 config

[Paweł Anikiel]

Add defconfig and Kconfig files for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 arch/arm/mach-socfpga/Kconfig |  7 +
 configs/socfpga_chameleonv3_defconfig | 29 ++
 include/configs/socfpga_chameleonv3.h | 44 +++
 3 files changed, 80 insertions(+)
 create mode 100644 configs/socfpga_chameleonv3_defconfig
 create mode 100644 include/configs/socfpga_chameleonv3.h

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 78a7549a41..fe851f575e 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -143,6 +143,10 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
 
+config TARGET_SOCFPGA_CHAMELEONV3
+   bool "Google Chameleon v3 (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -194,6 +198,7 @@ config SYS_BOARD
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+   default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -219,6 +224,7 @@ config SYS_VENDOR
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+   default "google" if TARGET_SOCFPGA_CHAMELEONV3
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -234,6 +240,7 @@ config SYS_CONFIG_NAME
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+   default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
diff --git a/configs/socfpga_chameleonv3_defconfig 
b/configs/socfpga_chameleonv3_defconfig
new file mode 100644
index 00..7870d31b09
--- /dev/null
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x1
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_MMC_DW=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_MISC_INIT_R=y
+CONFIG_ATSHA204A=y
diff --git a/include/configs/socfpga_chameleonv3.h 
b/include/configs/socfpga_chameleonv3.h
new file mode 100644
index 00..891b762946
--- /dev/null
+++ b/include/configs/socfpga_chameleonv3.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 Google LLC
+ */
+#ifndef __SOCFGPA_CHAMELEONV3_H__
+#define __SOCFGPA_CHAMELEONV3_H__
+
+#include 
+
+#define CONFIG_SYS_BOOTM_LEN   (32 * 1024 * 1024)
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x4000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "autoload=no\0" \
+   "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw 
rootwait\0" \
+   "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
+   "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
+   "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/* SPL memory allocation configuration, this is for FAT implementation */
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
+
+/* The rest of the configuration is shared */
+#include 
+
+#endif /* __SOCFGPA_CHAMELEONV3_H__ */
-- 
2.36.1.476.g0c4daa206d-goog

[PATCH v3 04/11] board: Add Chameleonv3 board dir

[Paweł Anikiel]

Add board directory for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 board/google/chameleonv3/Makefile  |  5 +++
 board/google/chameleonv3/board.c   | 27 ++
 board/google/chameleonv3/fpga.its  | 28 ++
 board/google/chameleonv3/fpga_early_io.its | 35 ++
 board/google/chameleonv3/mercury_aa1.c | 43 ++
 board/google/chameleonv3/mercury_aa1.h | 12 ++
 6 files changed, 150 insertions(+)
 create mode 100644 board/google/chameleonv3/Makefile
 create mode 100644 board/google/chameleonv3/board.c
 create mode 100644 board/google/chameleonv3/fpga.its
 create mode 100644 board/google/chameleonv3/fpga_early_io.its
 create mode 100644 board/google/chameleonv3/mercury_aa1.c
 create mode 100644 board/google/chameleonv3/mercury_aa1.h

diff --git a/board/google/chameleonv3/Makefile 
b/board/google/chameleonv3/Makefile
new file mode 100644
index 00..bb413fde83
--- /dev/null
+++ b/board/google/chameleonv3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright 2022 Google LLC
+
+obj-y  := board.o mercury_aa1.o
diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c
new file mode 100644
index 00..4d3049689d
--- /dev/null
+++ b/board/google/chameleonv3/board.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include 
+#include 
+#include "mercury_aa1.h"
+
+int misc_init_r(void)
+{
+   u8 mac[ARP_HLEN];
+   int res;
+
+   if (env_get("ethaddr"))
+   return 0;
+
+   res = mercury_aa1_read_mac(mac);
+   if (res) {
+   printf("couldn't read mac address: %s\n", errno_str(res));
+   return 0;
+   }
+
+   if (is_valid_ethaddr(mac))
+   eth_env_set_enetaddr("ethaddr", mac);
+
+   return 0;
+}
diff --git a/board/google/chameleonv3/fpga.its 
b/board/google/chameleonv3/fpga.its
new file mode 100644
index 00..85a830002f
--- /dev/null
+++ b/board/google/chameleonv3/fpga.its
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+   description = "FIT image with FPGA bistream";
+   #address-cells = <1>;
+
+   images {
+   fpga-periph-1 {
+   description = "FPGA full bitstream";
+   data = /incbin/("../../../fpga.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   };
+
+   configurations {
+   default = "config-1";
+   config-1 {
+   description = "Boot with FPGA config";
+   fpga = "fpga-periph-1";
+   };
+   };
+};
diff --git a/board/google/chameleonv3/fpga_early_io.its 
b/board/google/chameleonv3/fpga_early_io.its
new file mode 100644
index 00..ebc7bcbaae
--- /dev/null
+++ b/board/google/chameleonv3/fpga_early_io.its
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+   description = "FIT image with FPGA bistream";
+   #address-cells = <1>;
+
+   images {
+   fpga-periph-1 {
+   description = "FPGA peripheral bitstream";
+   data = /incbin/("../../../periph.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   fpga-core-1 {
+   description = "FPGA core bitstream";
+   data = /incbin/("../../../core.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   };
+
+   configurations {
+   default = "config-1";
+   config-1 {
+   description = "Boot with FPGA config";
+   fpga = "fpga-periph-1", "fpga-core-1";
+   };
+   };
+};
diff --git a/board/google/chameleonv3/mercury_aa1.c 
b/board/google/chameleonv3/mercury_aa1.c
new file mode 100644
index 00..ed447ec37c
--- /dev/null
+++ b/board/google/chameleonv3/mercury_aa1.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include 
+#include 
+#include 
+#include 
+#include "mercury_aa1.h"
+
+#define MERCURY_AA1_ATSHA204A_OTP_MAC0 4
+#define MERCURY_AA1_ATSHA204A_OTP_MAC1 5
+
+int mercury_aa1_read_mac(u8 *mac)
+{
+   struct udevice *de

[PATCH v3 03/11] arm: dts: Add Chameleonv3 devicetrees

[Paweł Anikiel]

Add devicetrees for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel 
Signed-off-by: Alexandru M Stan 
Reviewed-by: Simon Glass 
---
 arch/arm/dts/Makefile |  2 +
 arch/arm/dts/socfpga_arria10_chameleonv3.dts  | 90 +++
 ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi |  8 ++
 .../dts/socfpga_arria10_chameleonv3_270_3.dts |  5 ++
 ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi |  8 ++
 .../dts/socfpga_arria10_chameleonv3_480_2.dts |  5 ++
 6 files changed, 118 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83630af4f6..910b6c3acd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -418,6 +418,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_agilex_socdk.dtb\
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
+   socfpga_arria10_chameleonv3_270_3.dtb   \
+   socfpga_arria10_chameleonv3_480_2.dtb   \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb\
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3.dts
new file mode 100644
index 00..988cc44543
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+   model = "Google Chameleon V3";
+   compatible = "google,chameleon-v3",
+"altr,socfpga-arria10", "altr,socfpga";
+
+   aliases {
+   serial0 = &uart0;
+   i2c0 = &i2c0;
+   i2c1 = &i2c1;
+   };
+};
+
+&gmac0 {
+   status = "okay";
+};
+
+&gpio0 {
+   status = "okay";
+};
+
+&gpio1 {
+   status = "okay";
+};
+
+&gpio2 {
+   status = "okay";
+};
+
+&i2c0 {
+   status = "okay";
+
+   ssm2603: ssm2603@1a {
+   compatible = "adi,ssm2603";
+   reg = <0x1a>;
+   };
+};
+
+&i2c1 {
+   status = "okay";
+
+   u80: u80@21 {
+   compatible = "nxp,pca9535";
+   reg = <0x21>;
+   gpio-controller;
+   #gpio-cells = <2>;
+
+   gpio-line-names =
+   "SOM_AUD_MUTE",
+   "DP1_OUT_CEC_EN",
+   "DP2_OUT_CEC_EN",
+   "DP1_SOM_PS8469_CAD",
+   "DPD_SOM_PS8469_CAD",
+   "DP_OUT_PWR_EN",
+   "STM32_RST_L",
+   "STM32_BOOT0",
+
+   "FPGA_PROT",
+   "STM32_FPGA_COMM0",
+   "TP119",
+   "TP120",
+   "TP121",
+   "TP122",
+   "TP123",
+   "TP124";
+   };
+};
+
+&mmc {
+   status = "okay";
+};
+
+&uart0 {
+   status = "okay";
+};
+
+&uart1 {
+   status = "okay";
+};
+
+&usb0 {
+   status = "okay";
+   dr_mode = "host";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
new file mode 100644
index 00..e789d49657
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_270_3_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
new file mode 100644
index 00..5f40af6eb9
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.

[PATCH v3 02/11] arm: dts: Add Chameleonv3 handoff headers

[Paweł Anikiel]

Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++
 ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++
 2 files changed, 610 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
new file mode 100644
index 00..9d8f4a0dd3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Intel Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 6000
+#define EMAC0_CLK_HZ 25000
+#define EMAC1_CLK_HZ 25000
+#define EMAC2_CLK_HZ 25000
+#define EOSC1_CLK_HZ 
+#define F2H_FREE_CLK_HZ 2
+#define H2F_USER0_CLK_HZ 2
+#define H2F_USER1_CLK_HZ 1
+#define L3_MAIN_FREE_CLK_HZ 2
+#define SDMMC_CLK_HZ 2
+#define TPIU_CLK_HZ 1
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 7
+#define MAINPLLGRP_CNTR7CLK_CNT 7
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 15
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 1
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 32
+#define MAINPLLGRP_VCO1_NUMER 1584
+#define PERPLLGRP_CNTR2CLK_CNT 5
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 14
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 374
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 0
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 32
+#define PERPLLGRP_VCO1_NUMER 1485
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 7
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+   (ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+   (ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CONFIG_IO_10_INPUT_BUF_EN 1
+#define CONFIG_IO_10_PD_DRV_STRG 10
+#define CONFIG_IO_10_PD_SLW_RT 1
+#define CONFIG_IO_10_PU_DRV_STRG 8
+#define CONFIG_IO_10_PU_SLW_RT 1
+#define CONFIG_IO_10_RTRIM 1
+#define CONFIG_IO_10_WK_PU_EN 0
+#define CONFIG_IO_11_INPUT_BUF_EN 1
+#define CONFIG_IO_11_PD_DRV_STRG 10
+#define CONFIG_IO_11_PD_SLW_RT 1
+#define CONFIG_IO_11_PU_DRV_STRG 8
+#define CONFIG_IO_11_PU_SLW_RT 1
+#define CONFIG_IO_11_RTRIM 1
+#define CONFIG_IO_11_WK_PU_EN 0
+#define CONFIG_IO_12_INPUT_BUF_EN 0
+#define CONFIG_IO_12_PD_DRV_STRG 0
+#define CONFIG_IO_12_PD_SLW_RT 0
+#define CONFIG_IO_12_PU_DRV_STRG 0
+#define CONFIG_IO_12_PU_SLW_RT 0
+#define CONFIG_IO_12_RTRIM 1
+#define CONFIG_IO_12_WK_PU_EN 1
+#define CONFIG_IO_13_INPUT_BUF_EN 0
+#define CONFIG_IO_13_PD_DRV_STRG 0
+#define CONFIG_IO_13_PD_SLW_RT 0
+#define CONFIG_IO_13_PU_DRV_STRG 0
+#define CONFIG_IO_13_PU_SLW_RT 0
+#define CONFIG_IO_13_RTRIM 1
+#define CONFIG_IO_13_WK_PU_EN 1
+#define CONFIG_IO_14_INPUT_BUF_EN 0
+#define CONFIG_IO_14_PD_DRV_STRG 0
+#define CONFIG_IO_14_PD_SLW_RT 0
+#define CONFIG_IO_14_PU_DRV_STRG 0
+#define CONFIG_IO_14_PU_SLW_RT 0
+#define CONFIG_IO_14_RTRIM 1
+#define CONFIG_IO_14_WK_PU_EN 1
+#define CONFIG_IO_15_INPUT_BUF_EN 0
+#define CONFIG_IO_15_PD_DRV_STRG 0
+#define CONFIG_IO_15_PD_SLW_RT 0
+#define CONFIG_IO_15_PU_DRV_STRG 0
+#define CONFIG_IO_15_PU_SLW_RT 0
+#define CONFIG_IO_15_RTRIM 1
+#define CONFIG_IO_15_WK_PU_EN 1
+#define CONFIG_IO_16_INPUT_BUF_EN 0
+#define CONFIG_IO_16_PD_DRV_STRG

[PATCH v3 01/11] arm: dts: Add Mercury+ AA1 devicetrees

[Paweł Anikiel]

Devicetree headers for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel 
Reviewed-by: Simon Glass 
---
 .../socfpga_arria10_mercury_aa1-u-boot.dtsi   | 54 ++
 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++
 2 files changed, 126 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi

diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
new file mode 100644
index 00..365e05100a
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+   chosen {
+   firmware-loader = <&fs_loader0>;
+   };
+
+   fs_loader0: fs-loader {
+   u-boot,dm-pre-reloc;
+   compatible = "u-boot,fs-loader";
+   phandlepart = <&mmc 1>;
+   };
+};
+
+&atsha204a {
+   u-boot,dm-pre-reloc;
+};
+
+&fpga_mgr {
+   u-boot,dm-pre-reloc;
+   altr,bitstream = "fpga.itb";
+};
+
+&i2c1 {
+   u-boot,dm-pre-reloc;
+};
+
+&main_sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&mmc {
+   u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi 
b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
new file mode 100644
index 00..fee1fc39bb
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10.dtsi"
+
+/ {
+   aliases {
+   ethernet0 = &gmac0;
+   serial1 = &uart1;
+   };
+
+   chosen {
+   stdout-path = "serial1:115200n8";
+   };
+
+   memory@0 {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x8000>; /* 2GB */
+   };
+};
+
+&gmac0 {
+   phy-mode = "rgmii";
+   phy-handle = <&phy3>;
+
+   max-frame-size = <3800>;
+
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   phy3: ethernet-phy@3 {
+   reg = <3>;
+   txd0-skew-ps = <0>; /* -420ps */
+   txd1-skew-ps = <0>; /* -420ps */
+   txd2-skew-ps = <0>; /* -420ps */
+   txd3-skew-ps = <0>; /* -420ps */
+   rxd0-skew-ps = <420>; /* 0ps */
+   rxd1-skew-ps = <420>; /* 0ps */
+   rxd2-skew-ps = <420>; /* 0ps */
+   rxd3-skew-ps = <420>; /* 0ps */
+   txen-skew-ps = <0>; /* -420ps */
+   txc-skew-ps = <1860>; /* 960ps */
+   rxdv-skew-ps = <420>; /* 0ps */
+   rxc-skew-ps = <1680>; /* 780ps */
+   };
+   };
+};
+
+&i2c1 {
+   atsha204a: atsha204a@64 {
+   compatible = "atmel,atsha204a";
+   reg = <0x64>;
+   };
+
+   isl12022: isl12022@6f {
+   compatible = "isil,isl12022";
+   reg = <0x6f>;
+   };
+};
+
+&mmc {
+   cap-sd-highspeed;
+   broken-cd;
+   bus-width = <4>;
+};
+
+&osc1 {
+   clock-frequency = <>;
+};
-- 
2.36.1.476.g0c4daa206d-goog

[PATCH v3 00/11] Add Chameleon v3 support

[Paweł Anikiel]

The Google Chameleon v3 is a board made for testing both video and audio
interfaces of external devices. It has a connector compatible with the
Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The AA1
module comes in a few different configurations, the Chameleon V3 supports
ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E.

This patchset adds support for the Chameleon v3 (both versions), as well
as some bugfixes and optimizations, mostly in Arria 10 code.

V3:
  Move clock manager changes out of socfpga-generic code (aarch64 compilation 
issue)

V2:
  Adjust devicetrees so that they work both in u-boot and linux
  Put u-boot-specific parts of devicetrees into *-u-boot.dtsi files
  Minor changes in Kconfig, defconfig, and config.h

Paweł Anikiel (11):
  arm: dts: Add Mercury+ AA1 devicetrees
  arm: dts: Add Chameleonv3 handoff headers
  arm: dts: Add Chameleonv3 devicetrees
  board: Add Chameleonv3 board dir
  config: Add Chameleonv3 config
  misc: atsha204a: Increase wake delay by tWHI
  sysreset: socfpga: Use parent device for reading base address
  socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
  socfpga: arria10: Improve bitstream loading speed
  socfpga: arria10: Wait for fifo empty after writing bitstream
  socfpga: arria10: Allow dcache_enable before relocation

 arch/arm/dts/Makefile |   2 +
 arch/arm/dts/socfpga_arria10_chameleonv3.dts  |  90 ++
 ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi |   8 +
 .../dts/socfpga_arria10_chameleonv3_270_3.dts |   5 +
 ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++
 ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi |   8 +
 .../dts/socfpga_arria10_chameleonv3_480_2.dts |   5 +
 ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++
 .../socfpga_arria10_mercury_aa1-u-boot.dtsi   |  54 
 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi |  72 +
 arch/arm/mach-socfpga/Kconfig |   7 +
 arch/arm/mach-socfpga/clock_manager_arria10.c |  31 +-
 arch/arm/mach-socfpga/misc_arria10.c  |  26 ++
 board/google/chameleonv3/Makefile |   5 +
 board/google/chameleonv3/board.c  |  27 ++
 board/google/chameleonv3/fpga.its |  28 ++
 board/google/chameleonv3/fpga_early_io.its|  35 ++
 board/google/chameleonv3/mercury_aa1.c|  43 +++
 board/google/chameleonv3/mercury_aa1.h|  12 +
 configs/socfpga_chameleonv3_defconfig |  29 ++
 drivers/fpga/socfpga_arria10.c|  28 +-
 drivers/misc/atsha204a-i2c.c  |   5 +-
 drivers/sysreset/sysreset_socfpga.c   |   2 +-
 include/configs/socfpga_chameleonv3.h |  44 +++
 24 files changed, 1162 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
 create mode 100644 board/google/chameleonv3/Makefile
 create mode 100644 board/google/chameleonv3/board.c
 create mode 100644 board/google/chameleonv3/fpga.its
 create mode 100644 board/google/chameleonv3/fpga_early_io.its
 create mode 100644 board/google/chameleonv3/mercury_aa1.c
 create mode 100644 board/google/chameleonv3/mercury_aa1.h
 create mode 100644 configs/socfpga_chameleonv3_defconfig
 create mode 100644 include/configs/socfpga_chameleonv3.h

-- 
2.36.1.476.g0c4daa206d-goog

Re: [PATCH v2 00/11] Add Chameleon v3 support

[Paweł Anikiel]

On Thu, May 26, 2022 at 4:37 PM Paweł Anikiel  wrote:
>
> The Google Chameleon v3 is a board made for testing both video and audio
> interfaces of external devices. It has a connector compatible with the
> Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The AA1
> module comes in a few different configurations, the Chameleon V3 supports
> ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E.
>
> This patchset adds support for the Chameleon v3 (both versions), as well
> as some bugfixes and optimizations, mostly in Arria 10 code.
>
> V2:
>   Adjust devicetrees so that they work both in u-boot and linux
>   Put u-boot-specific parts of devicetrees into *-u-boot.dtsi files
>   Minor changes in Kconfig, defconfig, and config.h
>
> Paweł Anikiel (11):
>   arm: dts: Add Mercury+ AA1 devicetrees
>   arm: dts: Add Chameleonv3 handoff headers
>   arm: dts: Add Chameleonv3 devicetrees
>   board: Add Chameleonv3 board dir
>   config: Add Chameleonv3 config
>   misc: atsha204a: Increase wake delay by tWHI
>   sysreset: socfpga: Use parent device for reading base address
>   socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
>   socfpga: arria10: Improve bitstream loading speed
>   socfpga: arria10: Wait for fifo empty after writing bitstream
>   socfpga: arria10: Allow dcache_enable before relocation
>
>  arch/arm/dts/Makefile |   2 +
>  arch/arm/dts/socfpga_arria10_chameleonv3.dts  |  90 ++
>  ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi |   8 +
>  .../dts/socfpga_arria10_chameleonv3_270_3.dts |   5 +
>  ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++
>  ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi |   8 +
>  .../dts/socfpga_arria10_chameleonv3_480_2.dts |   5 +
>  ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++
>  .../socfpga_arria10_mercury_aa1-u-boot.dtsi   |  54 
>  arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi |  72 +
>  arch/arm/mach-socfpga/Kconfig |   7 +
>  arch/arm/mach-socfpga/clock_manager.c |   7 +-
>  arch/arm/mach-socfpga/clock_manager_arria10.c |  12 +-
>  .../mach-socfpga/include/mach/clock_manager.h |   4 +
>  arch/arm/mach-socfpga/misc_arria10.c  |  26 ++
>  board/google/chameleonv3/Makefile |   5 +
>  board/google/chameleonv3/board.c  |  27 ++
>  board/google/chameleonv3/fpga.its |  28 ++
>  board/google/chameleonv3/fpga_early_io.its|  35 ++
>  board/google/chameleonv3/mercury_aa1.c|  43 +++
>  board/google/chameleonv3/mercury_aa1.h|  12 +
>  configs/socfpga_chameleonv3_defconfig |  29 ++
>  drivers/fpga/socfpga_arria10.c|  28 +-
>  drivers/misc/atsha204a-i2c.c  |   5 +-
>  drivers/sysreset/sysreset_socfpga.c   |   2 +-
>  include/configs/socfpga_chameleonv3.h |  44 +++
>  26 files changed, 1154 insertions(+), 14 deletions(-)
>  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts
>  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
>  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
>  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
>  create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
>  create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
>  create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
>  create mode 100644 board/google/chameleonv3/Makefile
>  create mode 100644 board/google/chameleonv3/board.c
>  create mode 100644 board/google/chameleonv3/fpga.its
>  create mode 100644 board/google/chameleonv3/fpga_early_io.its
>  create mode 100644 board/google/chameleonv3/mercury_aa1.c
>  create mode 100644 board/google/chameleonv3/mercury_aa1.h
>  create mode 100644 configs/socfpga_chameleonv3_defconfig
>  create mode 100644 include/configs/socfpga_chameleonv3.h
>
> --
> 2.36.1.124.g0e6072fb45-goog
>

Hi,

Could you please take a look? Do you have any comments or remarks to
the patchset?

Regards,
Paweł

Re: [PATCH v2 09/11] socfpga: arria10: Improve bitstream loading speed

[Paweł Anikiel]

On Fri, May 27, 2022 at 5:55 PM Simon Glass  wrote:
>
> On Thu, 26 May 2022 at 07:38, Paweł Anikiel  wrote:
> >
> > Apply some optimizations to speed up bitstream loading
> > (both for full and split periph/core bitstreams):
> >
> >  * Change the size of the first fs read, so that all the subsequent
> >reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
> >This value was chosen so that in subsequent reads the fat fs driver
> >doesn't have to allocate a temporary buffer in get_contents
> >(assuming 8KiB clusters).
> >
> >  * Change the buffer size to a larger value when reading to ddr
> >(but not too large, because large transfers cause a stack overflow
> >in the dwmmc driver).
>
> When the size is too large, where exactly does that stack overflow happen?

In dwmci_send_cmd (at drivers/mmc/dw_mmc.c:243). It stack-allocates a
buffer of size sizeof(struct dwmci_idmac) * (data->blocks / 8). Since
loading the bitstream is done from SPL (which is still in sram), we
only have about 100K of stack, which is not enough to load an 11MB
file in one go.

[PATCH v2 09/11] socfpga: arria10: Improve bitstream loading speed

[Paweł Anikiel]

Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):

 * Change the size of the first fs read, so that all the subsequent
   reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
   This value was chosen so that in subsequent reads the fat fs driver
   doesn't have to allocate a temporary buffer in get_contents
   (assuming 8KiB clusters).

 * Change the buffer size to a larger value when reading to ddr
   (but not too large, because large transfers cause a stack overflow
   in the dwmmc driver).

Signed-off-by: Paweł Anikiel 
---
 drivers/fpga/socfpga_arria10.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 798e3a3f90..07bfe3060e 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,6 +30,14 @@
 #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT   0x100
 #define DEFAULT_DDR_LOAD_ADDRESS   0x400
+#define DDR_BUFFER_SIZE0x10
+
+/* When reading bitstream from a filesystem, the size of the first read is
+ * changed so that the subsequent reads are aligned to this value. This value
+ * was chosen so that in subsequent reads the fat fs driver doesn't have to
+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
+ */
+#define MAX_FIRST_LOAD_SIZE0x2000
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -526,7 +534,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16 
*buffer)
 #ifdef CONFIG_FS_LOADER
 static int first_loading_rbf_to_buffer(struct udevice *dev,
struct fpga_loadfs_info *fpga_loadfs,
-   u32 *buffer, size_t *buffer_bsize)
+   u32 *buffer, size_t *buffer_bsize,
+   size_t *buffer_bsize_ori)
 {
u32 *buffer_p = (u32 *)*buffer;
u32 *loadable = buffer_p;
@@ -674,6 +683,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
}
 
buffer_size = rbf_size;
+   *buffer_bsize_ori = DDR_BUFFER_SIZE;
}
 
debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
@@ -686,11 +696,16 @@ static int first_loading_rbf_to_buffer(struct udevice 
*dev,
 * chunk by chunk transfer is required due to smaller buffer size
 * compare to bitstream
 */
+
+   if (buffer_size > MAX_FIRST_LOAD_SIZE)
+   buffer_size = MAX_FIRST_LOAD_SIZE;
+
if (rbf_size <= buffer_size) {
/* Loading whole bitstream into buffer */
buffer_size = rbf_size;
fpga_loadfs->remaining = 0;
} else {
+   buffer_size -= rbf_offset % buffer_size;
fpga_loadfs->remaining -= buffer_size;
}
 
@@ -806,7 +821,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void 
*buf, size_t bsize,
 * function below.
 */
ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
-  &buffer_sizebytes);
+  &buffer_sizebytes,
+  &buffer_sizebytes_ori);
if (ret == 1) {
printf("FPGA: Skipping configuration ...\n");
return 0;
-- 
2.36.1.124.g0e6072fb45-goog

[PATCH v2 11/11] socfpga: arria10: Allow dcache_enable before relocation

[Paweł Anikiel]

Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel 
---
 arch/arm/mach-socfpga/misc_arria10.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
index 0ed2adfd84..7ce888d197 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)
return 0;
 }
 #endif
+
+void dram_bank_mmu_setup(int bank)
+{
+   struct bd_info *bd = gd->bd;
+   u32 start, size;
+   int i;
+
+   /* If we're still in OCRAM, don't set the XN bit on it */
+   if (!(gd->flags & GD_FLG_RELOC)) {
+   set_section_dcache(
+   CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+   DCACHE_WRITETHROUGH);
+   }
+
+   /*
+* The default implementation of this function allows the DRAM dcache
+* to be enabled only after relocation. However, to speed up ECC
+* initialization, we want to be able to enable DRAM dcache before
+* relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+* is set first).
+*/
+   start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+   size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+   for (i = start; i < start + size; i++)
+   set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
-- 
2.36.1.124.g0e6072fb45-goog

[PATCH v2 06/11] misc: atsha204a: Increase wake delay by tWHI

[Paweł Anikiel]

>From the ATSHA204A datasheet (document DS40002025A):

Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.

tWHI value can be found in table 7-2.

Signed-off-by: Paweł Anikiel 
---
 drivers/misc/atsha204a-i2c.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index aa6acf0f9a..81ecb5b617 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -21,7 +21,8 @@
 #include 
 #include 
 
-#define ATSHA204A_TWLO 60
+#define ATSHA204A_TWLO_US  60
+#define ATSHA204A_TWHI_US  2500
 #define ATSHA204A_TRANSACTION_TIMEOUT  10
 #define ATSHA204A_TRANSACTION_RETRY5
 #define ATSHA204A_EXECTIME 5000
@@ -109,7 +110,7 @@ int atsha204a_wakeup(struct udevice *dev)
continue;
}
 
-   udelay(ATSHA204A_TWLO);
+   udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
 
res = atsha204a_recv_resp(dev, &resp);
if (res) {
-- 
2.36.1.124.g0e6072fb45-goog

[PATCH v2 05/11] config: Add Chameleonv3 config

[Paweł Anikiel]

Add defconfig and Kconfig files for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel 
---
 arch/arm/mach-socfpga/Kconfig |  7 +
 configs/socfpga_chameleonv3_defconfig | 29 ++
 include/configs/socfpga_chameleonv3.h | 44 +++
 3 files changed, 80 insertions(+)
 create mode 100644 configs/socfpga_chameleonv3_defconfig
 create mode 100644 include/configs/socfpga_chameleonv3.h

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 78a7549a41..fe851f575e 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -143,6 +143,10 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
 
+config TARGET_SOCFPGA_CHAMELEONV3
+   bool "Google Chameleon v3 (Arria 10)"
+   select TARGET_SOCFPGA_ARRIA10
+
 config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -194,6 +198,7 @@ config SYS_BOARD
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+   default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -219,6 +224,7 @@ config SYS_VENDOR
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+   default "google" if TARGET_SOCFPGA_CHAMELEONV3
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -234,6 +240,7 @@ config SYS_CONFIG_NAME
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+   default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
diff --git a/configs/socfpga_chameleonv3_defconfig 
b/configs/socfpga_chameleonv3_defconfig
new file mode 100644
index 00..7870d31b09
--- /dev/null
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_chameleonv3_480_2"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x1
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_MMC_DW=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_MISC_INIT_R=y
+CONFIG_ATSHA204A=y
diff --git a/include/configs/socfpga_chameleonv3.h 
b/include/configs/socfpga_chameleonv3.h
new file mode 100644
index 00..891b762946
--- /dev/null
+++ b/include/configs/socfpga_chameleonv3.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 Google LLC
+ */
+#ifndef __SOCFGPA_CHAMELEONV3_H__
+#define __SOCFGPA_CHAMELEONV3_H__
+
+#include 
+
+#define CONFIG_SYS_BOOTM_LEN   (32 * 1024 * 1024)
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x4000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "autoload=no\0" \
+   "bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw 
rootwait\0" \
+   "distro_bootcmd=bridge enable; run bootcmd_mmc\0" \
+   "bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\0" \
+   "bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\0"
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL 0x
+
+/* SPL memory allocation configuration, this is for FAT implementation */
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00015000
+
+/* The rest of the configuration is shared */
+#include 
+
+#endif /* __SOCFGPA_CHAMELEONV3_H__ */
-- 
2.36.1.124.g0e6072fb45-goog

[PATCH v2 04/11] board: Add Chameleonv3 board dir

[Paweł Anikiel]

Add board directory for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel 
---
 board/google/chameleonv3/Makefile  |  5 +++
 board/google/chameleonv3/board.c   | 27 ++
 board/google/chameleonv3/fpga.its  | 28 ++
 board/google/chameleonv3/fpga_early_io.its | 35 ++
 board/google/chameleonv3/mercury_aa1.c | 43 ++
 board/google/chameleonv3/mercury_aa1.h | 12 ++
 6 files changed, 150 insertions(+)
 create mode 100644 board/google/chameleonv3/Makefile
 create mode 100644 board/google/chameleonv3/board.c
 create mode 100644 board/google/chameleonv3/fpga.its
 create mode 100644 board/google/chameleonv3/fpga_early_io.its
 create mode 100644 board/google/chameleonv3/mercury_aa1.c
 create mode 100644 board/google/chameleonv3/mercury_aa1.h

diff --git a/board/google/chameleonv3/Makefile 
b/board/google/chameleonv3/Makefile
new file mode 100644
index 00..bb413fde83
--- /dev/null
+++ b/board/google/chameleonv3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright 2022 Google LLC
+
+obj-y  := board.o mercury_aa1.o
diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c
new file mode 100644
index 00..4d3049689d
--- /dev/null
+++ b/board/google/chameleonv3/board.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include 
+#include 
+#include "mercury_aa1.h"
+
+int misc_init_r(void)
+{
+   u8 mac[ARP_HLEN];
+   int res;
+
+   if (env_get("ethaddr"))
+   return 0;
+
+   res = mercury_aa1_read_mac(mac);
+   if (res) {
+   printf("couldn't read mac address: %s\n", errno_str(res));
+   return 0;
+   }
+
+   if (is_valid_ethaddr(mac))
+   eth_env_set_enetaddr("ethaddr", mac);
+
+   return 0;
+}
diff --git a/board/google/chameleonv3/fpga.its 
b/board/google/chameleonv3/fpga.its
new file mode 100644
index 00..85a830002f
--- /dev/null
+++ b/board/google/chameleonv3/fpga.its
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+   description = "FIT image with FPGA bistream";
+   #address-cells = <1>;
+
+   images {
+   fpga-periph-1 {
+   description = "FPGA full bitstream";
+   data = /incbin/("../../../fpga.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   };
+
+   configurations {
+   default = "config-1";
+   config-1 {
+   description = "Boot with FPGA config";
+   fpga = "fpga-periph-1";
+   };
+   };
+};
diff --git a/board/google/chameleonv3/fpga_early_io.its 
b/board/google/chameleonv3/fpga_early_io.its
new file mode 100644
index 00..ebc7bcbaae
--- /dev/null
+++ b/board/google/chameleonv3/fpga_early_io.its
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+   description = "FIT image with FPGA bistream";
+   #address-cells = <1>;
+
+   images {
+   fpga-periph-1 {
+   description = "FPGA peripheral bitstream";
+   data = /incbin/("../../../periph.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   fpga-core-1 {
+   description = "FPGA core bitstream";
+   data = /incbin/("../../../core.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   };
+
+   configurations {
+   default = "config-1";
+   config-1 {
+   description = "Boot with FPGA config";
+   fpga = "fpga-periph-1", "fpga-core-1";
+   };
+   };
+};
diff --git a/board/google/chameleonv3/mercury_aa1.c 
b/board/google/chameleonv3/mercury_aa1.c
new file mode 100644
index 00..ed447ec37c
--- /dev/null
+++ b/board/google/chameleonv3/mercury_aa1.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include 
+#include 
+#include 
+#include 
+#include "mercury_aa1.h"
+
+#define MERCURY_AA1_ATSHA204A_OTP_MAC0 4
+#define MERCURY_AA1_ATSHA204A_OTP_MAC1 5
+
+int mercury_aa1_read_mac(u8 *mac)
+{
+   struct udevice *de

[PATCH v2 03/11] arm: dts: Add Chameleonv3 devicetrees

[Paweł Anikiel]

Add devicetrees for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel 
Signed-off-by: Alexandru M Stan 
---
 arch/arm/dts/Makefile |  2 +
 arch/arm/dts/socfpga_arria10_chameleonv3.dts  | 90 +++
 ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi |  8 ++
 .../dts/socfpga_arria10_chameleonv3_270_3.dts |  5 ++
 ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi |  8 ++
 .../dts/socfpga_arria10_chameleonv3_480_2.dts |  5 ++
 6 files changed, 118 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 83630af4f6..910b6c3acd 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -418,6 +418,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_agilex_socdk.dtb\
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
+   socfpga_arria10_chameleonv3_270_3.dtb   \
+   socfpga_arria10_chameleonv3_480_2.dtb   \
socfpga_arria10_socdk_sdmmc.dtb \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb\
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3.dts
new file mode 100644
index 00..988cc44543
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3.dts
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+#include "socfpga_arria10_mercury_aa1.dtsi"
+
+/ {
+   model = "Google Chameleon V3";
+   compatible = "google,chameleon-v3",
+"altr,socfpga-arria10", "altr,socfpga";
+
+   aliases {
+   serial0 = &uart0;
+   i2c0 = &i2c0;
+   i2c1 = &i2c1;
+   };
+};
+
+&gmac0 {
+   status = "okay";
+};
+
+&gpio0 {
+   status = "okay";
+};
+
+&gpio1 {
+   status = "okay";
+};
+
+&gpio2 {
+   status = "okay";
+};
+
+&i2c0 {
+   status = "okay";
+
+   ssm2603: ssm2603@1a {
+   compatible = "adi,ssm2603";
+   reg = <0x1a>;
+   };
+};
+
+&i2c1 {
+   status = "okay";
+
+   u80: u80@21 {
+   compatible = "nxp,pca9535";
+   reg = <0x21>;
+   gpio-controller;
+   #gpio-cells = <2>;
+
+   gpio-line-names =
+   "SOM_AUD_MUTE",
+   "DP1_OUT_CEC_EN",
+   "DP2_OUT_CEC_EN",
+   "DP1_SOM_PS8469_CAD",
+   "DPD_SOM_PS8469_CAD",
+   "DP_OUT_PWR_EN",
+   "STM32_RST_L",
+   "STM32_BOOT0",
+
+   "FPGA_PROT",
+   "STM32_FPGA_COMM0",
+   "TP119",
+   "TP120",
+   "TP121",
+   "TP122",
+   "TP123",
+   "TP124";
+   };
+};
+
+&mmc {
+   status = "okay";
+};
+
+&uart0 {
+   status = "okay";
+};
+
+&uart1 {
+   status = "okay";
+};
+
+&usb0 {
+   status = "okay";
+   dr_mode = "host";
+};
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
new file mode 100644
index 00..e789d49657
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3_270_3_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_arria10_handoff_u-boot.dtsi"
+#include "socfpga_arria10_mercury_aa1-u-boot.dtsi"
diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
new file mode 100644
index 00..5f40af6eb9
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
@@ -0,0 +1,5 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10_chameleonv3.dts"
d

[PATCH v2 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream

[Paweł Anikiel]

For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel 
---
 drivers/fpga/socfpga_arria10.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 07bfe3060e..d8089122af 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -80,6 +80,13 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
 }
 
+static int wait_for_fifo_empty(void)
+{
+   return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
+   1, FPGA_TIMEOUT_MSEC, false);
+}
+
 int is_fpgamgr_early_user_mode(void)
 {
return (readl(&fpga_manager_base->imgcfg_stat) &
@@ -874,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void 
*buf, size_t bsize,
 
WATCHDOG_RESET();
}
+   wait_for_fifo_empty();
 
if (fpga_loadfs.rbfinfo.section == periph_section) {
if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
-- 
2.36.1.124.g0e6072fb45-goog

[PATCH v2 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg

[Paweł Anikiel]

Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).

Signed-off-by: Paweł Anikiel 
---
 arch/arm/mach-socfpga/clock_manager.c  |  7 ---
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 12 ++--
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  4 
 3 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index 9e645a4253..c9bd4859f7 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -39,9 +39,10 @@ void cm_wait_for_lock(u32 mask)
 /* function to poll in the fsm busy bit */
 int cm_wait_for_fsm(void)
 {
-   return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
-CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 2,
-false);
+   void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);
+
+   /* 20s timeout */
+   return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 1);
 }
 
 int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 58d5d3fd8a..daa06b9d03 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -551,13 +551,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
main_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
 }
 
@@ -585,13 +585,13 @@ static void cm_pll_ramp_periph(struct mainpll_cfg 
*main_cfg,
 clk_hz),
  socfpga_get_clkmgr_addr() +
  CLKMGR_A10_PERPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
  per_cfg->vco1_numer,
  socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
 }
 
@@ -727,7 +727,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct 
perpll_cfg *per_cfg)
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 
/* Wait for at least 5 us */
-   udelay(5);
+   sdelay(5000);
 
/* Now deassert BGPWRDN and PWRDN */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
@@ -738,7 +738,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct 
perpll_cfg *per_cfg)
 CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 
/* Wait for at least 7 us */
-   udelay(7);
+   sdelay(7000);
 
/* enable the VCO and disable the external regulator to PLL */
writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index a8cb07a1c4..78013f0527 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -20,6 +20,10 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
 #endif
 #endif
 
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound);
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-- 
2.36.1.124.g0e6072fb45-goog

[PATCH v2 07/11] sysreset: socfpga: Use parent device for reading base address

[Paweł Anikiel]

This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.

Signed-off-by: Paweł Anikiel 
---
 drivers/sysreset/sysreset_socfpga.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/sysreset/sysreset_socfpga.c 
b/drivers/sysreset/sysreset_socfpga.c
index e38296ac3f..9b62dd5eab 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
 {
struct socfpga_sysreset_data *data = dev_get_priv(dev);
 
-   data->rstmgr_base = dev_read_addr_ptr(dev);
+   data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
return 0;
 }
 
-- 
2.36.1.124.g0e6072fb45-goog

[PATCH v2 01/11] arm: dts: Add Mercury+ AA1 devicetrees

[Paweł Anikiel]

Devicetree headers for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel 
---
 .../socfpga_arria10_mercury_aa1-u-boot.dtsi   | 54 ++
 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi | 72 +++
 2 files changed, 126 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi

diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi 
b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
new file mode 100644
index 00..365e05100a
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+   chosen {
+   firmware-loader = <&fs_loader0>;
+   };
+
+   fs_loader0: fs-loader {
+   u-boot,dm-pre-reloc;
+   compatible = "u-boot,fs-loader";
+   phandlepart = <&mmc 1>;
+   };
+};
+
+&atsha204a {
+   u-boot,dm-pre-reloc;
+};
+
+&fpga_mgr {
+   u-boot,dm-pre-reloc;
+   altr,bitstream = "fpga.itb";
+};
+
+&i2c1 {
+   u-boot,dm-pre-reloc;
+};
+
+&main_sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&mmc {
+   u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+   u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi 
b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
new file mode 100644
index 00..fee1fc39bb
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10.dtsi"
+
+/ {
+   aliases {
+   ethernet0 = &gmac0;
+   serial1 = &uart1;
+   };
+
+   chosen {
+   stdout-path = "serial1:115200n8";
+   };
+
+   memory@0 {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x8000>; /* 2GB */
+   };
+};
+
+&gmac0 {
+   phy-mode = "rgmii";
+   phy-handle = <&phy3>;
+
+   max-frame-size = <3800>;
+
+   mdio {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   compatible = "snps,dwmac-mdio";
+   phy3: ethernet-phy@3 {
+   reg = <3>;
+   txd0-skew-ps = <0>; /* -420ps */
+   txd1-skew-ps = <0>; /* -420ps */
+   txd2-skew-ps = <0>; /* -420ps */
+   txd3-skew-ps = <0>; /* -420ps */
+   rxd0-skew-ps = <420>; /* 0ps */
+   rxd1-skew-ps = <420>; /* 0ps */
+   rxd2-skew-ps = <420>; /* 0ps */
+   rxd3-skew-ps = <420>; /* 0ps */
+   txen-skew-ps = <0>; /* -420ps */
+   txc-skew-ps = <1860>; /* 960ps */
+   rxdv-skew-ps = <420>; /* 0ps */
+   rxc-skew-ps = <1680>; /* 780ps */
+   };
+   };
+};
+
+&i2c1 {
+   atsha204a: atsha204a@64 {
+   compatible = "atmel,atsha204a";
+   reg = <0x64>;
+   };
+
+   isl12022: isl12022@6f {
+   compatible = "isil,isl12022";
+   reg = <0x6f>;
+   };
+};
+
+&mmc {
+   cap-sd-highspeed;
+   broken-cd;
+   bus-width = <4>;
+};
+
+&osc1 {
+   clock-frequency = <>;
+};
-- 
2.36.1.124.g0e6072fb45-goog

[PATCH v2 02/11] arm: dts: Add Chameleonv3 handoff headers

[Paweł Anikiel]

Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.

Signed-off-by: Paweł Anikiel 
---
 ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++
 ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++
 2 files changed, 610 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h

diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h 
b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
new file mode 100644
index 00..9d8f4a0dd3
--- /dev/null
+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Intel Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 6000
+#define EMAC0_CLK_HZ 25000
+#define EMAC1_CLK_HZ 25000
+#define EMAC2_CLK_HZ 25000
+#define EOSC1_CLK_HZ 
+#define F2H_FREE_CLK_HZ 2
+#define H2F_USER0_CLK_HZ 2
+#define H2F_USER1_CLK_HZ 1
+#define L3_MAIN_FREE_CLK_HZ 2
+#define SDMMC_CLK_HZ 2
+#define TPIU_CLK_HZ 1
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 7
+#define MAINPLLGRP_CNTR7CLK_CNT 7
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 15
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 1
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 32
+#define MAINPLLGRP_VCO1_NUMER 1584
+#define PERPLLGRP_CNTR2CLK_CNT 5
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 14
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 374
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 0
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 32
+#define PERPLLGRP_VCO1_NUMER 1485
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 7
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+   (ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+   (ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CONFIG_IO_10_INPUT_BUF_EN 1
+#define CONFIG_IO_10_PD_DRV_STRG 10
+#define CONFIG_IO_10_PD_SLW_RT 1
+#define CONFIG_IO_10_PU_DRV_STRG 8
+#define CONFIG_IO_10_PU_SLW_RT 1
+#define CONFIG_IO_10_RTRIM 1
+#define CONFIG_IO_10_WK_PU_EN 0
+#define CONFIG_IO_11_INPUT_BUF_EN 1
+#define CONFIG_IO_11_PD_DRV_STRG 10
+#define CONFIG_IO_11_PD_SLW_RT 1
+#define CONFIG_IO_11_PU_DRV_STRG 8
+#define CONFIG_IO_11_PU_SLW_RT 1
+#define CONFIG_IO_11_RTRIM 1
+#define CONFIG_IO_11_WK_PU_EN 0
+#define CONFIG_IO_12_INPUT_BUF_EN 0
+#define CONFIG_IO_12_PD_DRV_STRG 0
+#define CONFIG_IO_12_PD_SLW_RT 0
+#define CONFIG_IO_12_PU_DRV_STRG 0
+#define CONFIG_IO_12_PU_SLW_RT 0
+#define CONFIG_IO_12_RTRIM 1
+#define CONFIG_IO_12_WK_PU_EN 1
+#define CONFIG_IO_13_INPUT_BUF_EN 0
+#define CONFIG_IO_13_PD_DRV_STRG 0
+#define CONFIG_IO_13_PD_SLW_RT 0
+#define CONFIG_IO_13_PU_DRV_STRG 0
+#define CONFIG_IO_13_PU_SLW_RT 0
+#define CONFIG_IO_13_RTRIM 1
+#define CONFIG_IO_13_WK_PU_EN 1
+#define CONFIG_IO_14_INPUT_BUF_EN 0
+#define CONFIG_IO_14_PD_DRV_STRG 0
+#define CONFIG_IO_14_PD_SLW_RT 0
+#define CONFIG_IO_14_PU_DRV_STRG 0
+#define CONFIG_IO_14_PU_SLW_RT 0
+#define CONFIG_IO_14_RTRIM 1
+#define CONFIG_IO_14_WK_PU_EN 1
+#define CONFIG_IO_15_INPUT_BUF_EN 0
+#define CONFIG_IO_15_PD_DRV_STRG 0
+#define CONFIG_IO_15_PD_SLW_RT 0
+#define CONFIG_IO_15_PU_DRV_STRG 0
+#define CONFIG_IO_15_PU_SLW_RT 0
+#define CONFIG_IO_15_RTRIM 1
+#define CONFIG_IO_15_WK_PU_EN 1
+#define CONFIG_IO_16_INPUT_BUF_EN 0
+#define CONFIG_IO_16_PD_DRV_STRG 10
+#define CONFIG_IO_16_PD_SLW_R

[PATCH v2 00/11] Add Chameleon v3 support

[Paweł Anikiel]

The Google Chameleon v3 is a board made for testing both video and audio
interfaces of external devices. It has a connector compatible with the
Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The AA1
module comes in a few different configurations, the Chameleon V3 supports
ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E.

This patchset adds support for the Chameleon v3 (both versions), as well
as some bugfixes and optimizations, mostly in Arria 10 code.

V2:
  Adjust devicetrees so that they work both in u-boot and linux
  Put u-boot-specific parts of devicetrees into *-u-boot.dtsi files
  Minor changes in Kconfig, defconfig, and config.h

Paweł Anikiel (11):
  arm: dts: Add Mercury+ AA1 devicetrees
  arm: dts: Add Chameleonv3 handoff headers
  arm: dts: Add Chameleonv3 devicetrees
  board: Add Chameleonv3 board dir
  config: Add Chameleonv3 config
  misc: atsha204a: Increase wake delay by tWHI
  sysreset: socfpga: Use parent device for reading base address
  socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
  socfpga: arria10: Improve bitstream loading speed
  socfpga: arria10: Wait for fifo empty after writing bitstream
  socfpga: arria10: Allow dcache_enable before relocation

 arch/arm/dts/Makefile |   2 +
 arch/arm/dts/socfpga_arria10_chameleonv3.dts  |  90 ++
 ...fpga_arria10_chameleonv3_270_3-u-boot.dtsi |   8 +
 .../dts/socfpga_arria10_chameleonv3_270_3.dts |   5 +
 ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++
 ...fpga_arria10_chameleonv3_480_2-u-boot.dtsi |   8 +
 .../dts/socfpga_arria10_chameleonv3_480_2.dts |   5 +
 ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++
 .../socfpga_arria10_mercury_aa1-u-boot.dtsi   |  54 
 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi |  72 +
 arch/arm/mach-socfpga/Kconfig |   7 +
 arch/arm/mach-socfpga/clock_manager.c |   7 +-
 arch/arm/mach-socfpga/clock_manager_arria10.c |  12 +-
 .../mach-socfpga/include/mach/clock_manager.h |   4 +
 arch/arm/mach-socfpga/misc_arria10.c  |  26 ++
 board/google/chameleonv3/Makefile |   5 +
 board/google/chameleonv3/board.c  |  27 ++
 board/google/chameleonv3/fpga.its |  28 ++
 board/google/chameleonv3/fpga_early_io.its|  35 ++
 board/google/chameleonv3/mercury_aa1.c|  43 +++
 board/google/chameleonv3/mercury_aa1.h|  12 +
 configs/socfpga_chameleonv3_defconfig |  29 ++
 drivers/fpga/socfpga_arria10.c|  28 +-
 drivers/misc/atsha204a-i2c.c  |   5 +-
 drivers/sysreset/sysreset_socfpga.c   |   2 +-
 include/configs/socfpga_chameleonv3.h |  44 +++
 26 files changed, 1154 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2.dts
 create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1-u-boot.dtsi
 create mode 100644 arch/arm/dts/socfpga_arria10_mercury_aa1.dtsi
 create mode 100644 board/google/chameleonv3/Makefile
 create mode 100644 board/google/chameleonv3/board.c
 create mode 100644 board/google/chameleonv3/fpga.its
 create mode 100644 board/google/chameleonv3/fpga_early_io.its
 create mode 100644 board/google/chameleonv3/mercury_aa1.c
 create mode 100644 board/google/chameleonv3/mercury_aa1.h
 create mode 100644 configs/socfpga_chameleonv3_defconfig
 create mode 100644 include/configs/socfpga_chameleonv3.h

-- 
2.36.1.124.g0e6072fb45-goog

Re: [PATCH 03/11] arm: dts: Add Chameleonv3 devicetree

[Paweł Anikiel]

On Mon, Apr 11, 2022 at 8:35 PM Simon Glass  wrote:
>
> On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel  wrote:
> >
> > Add devicetree for Google Chameleon V3 board
> >
> > Signed-off-by: Paweł Anikiel 
> > ---
> >  arch/arm/dts/Makefile  |  2 ++
> >  arch/arm/dts/socfpga_chameleonv3.dtsi  | 21 +
> >  arch/arm/dts/socfpga_chameleonv3_270_3.dts |  9 +
> >  arch/arm/dts/socfpga_chameleonv3_480_2.dts |  9 +
> >  4 files changed, 41 insertions(+)
> >  create mode 100644 arch/arm/dts/socfpga_chameleonv3.dtsi
> >  create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3.dts
> >  create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2.dts
>
> Reviewed-by: Simon Glass 
>
> (has this been sent to Linux?)

It has not been sent to Linux.

Regards,
Paweł

Re: [PATCH 01/11] arm: dts: Add Mercury+ AA1 devicetree

[Paweł Anikiel]

On Mon, Apr 11, 2022 at 8:35 PM Simon Glass  wrote:
>
> Hi Paweł,
>
> On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel  wrote:
> >
> > Device tree header for Mercury+ AA1 module
> >
> > Signed-off-by: Paweł Anikiel 
> > ---
> >  arch/arm/dts/socfpga_mercury_aa1.dtsi | 95 +++
> >  1 file changed, 95 insertions(+)
> >  create mode 100644 arch/arm/dts/socfpga_mercury_aa1.dtsi
> >
>
> Has this been sent to Linux?

Yes, a while ago. It's under
arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dts

>
> > diff --git a/arch/arm/dts/socfpga_mercury_aa1.dtsi 
> > b/arch/arm/dts/socfpga_mercury_aa1.dtsi
> > new file mode 100644
> > index 00..7d0bf884a3
> > --- /dev/null
> > +++ b/arch/arm/dts/socfpga_mercury_aa1.dtsi
> > @@ -0,0 +1,95 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright 2022 Google LLC
> > + */
> > +#include "socfpga_arria10.dtsi"
> > +#include "socfpga_arria10-u-boot.dtsi"
> > +
> > +/ {
> > +   model = "Altera SOCFPGA Arria 10";
> > +   compatible = "altr,socfpga-arria10", "altr,socfpga";
> > +
> > +   aliases {
> > +   ethernet0 = &gmac0;
> > +   serial0 = &uart1;
> > +   };
> > +
> > +   chosen {
> > +   stdout-path = "serial0:115200n8";
> > +   firmware-loader = <&fs_loader0>;
> > +   };
> > +
> > +   memory@0 {
> > +   name = "memory";
> > +   device_type = "memory";
> > +   reg = <0x0 0x8000>; /* 2GB */
> > +   };
> > +
> > +   fs_loader0: fs-loader {
> > +   u-boot,dm-pre-reloc;
> > +   compatible = "u-boot,fs-loader";
> > +   phandlepart = <&mmc 1>;
> > +   };
> > +};
> > +
> > +&fpga_mgr {
> > +   u-boot,dm-pre-reloc;
> > +   altr,bitstream = "fpga.itb";
> > +};
> > +
> > +&gmac0 {
> > +   phy-mode = "rgmii";
> > +   phy-addr = <0x>; /* probe for phy addr */
> > +
> > +   txd0-skew-ps = <0>; /* -420ps */
> > +   txd1-skew-ps = <0>; /* -420ps */
> > +   txd2-skew-ps = <0>; /* -420ps */
> > +   txd3-skew-ps = <0>; /* -420ps */
> > +   rxd0-skew-ps = <420>; /* 0ps */
> > +   rxd1-skew-ps = <420>; /* 0ps */
> > +   rxd2-skew-ps = <420>; /* 0ps */
> > +   rxd3-skew-ps = <420>; /* 0ps */
> > +   txen-skew-ps = <0>; /* -420ps */
> > +   txc-skew-ps = <1860>; /* 960ps */
> > +   rxdv-skew-ps = <420>; /* 0ps */
> > +   rxc-skew-ps = <1680>; /* 780ps */
> > +   max-frame-size = <3800>;
> > +};
> > +
> > +&i2c1 {
> > +   u-boot,dm-pre-reloc;
> > +
> > +   atsha204a@64 {
> > +   u-boot,dm-pre-reloc;
> > +   compatible = "atmel,atsha204a";
> > +   reg = <0x64>;
> > +   };
> > +};
> > +
> > +&main_sdmmc_clk {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > +&mmc {
> > +   cap-sd-highspeed;
> > +   cap-mmc-highspeed;
> > +   broken-cd;
> > +   bus-width = <4>;
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > +&peri_sdmmc_clk {
> > +   u-boot,dm-pre-reloc;
> > +};
> > +
> > +&sdmmc_clk {
> > +   u-boot,dm-pre-reloc;
>
> These U-Boot tags should be in the u-boot.dtsi file that you include above.

I believe these are board-specific, so they shouldn't go into
socfpga_arria10-u-boot.dtsi.
I will make a seperate file socfpga_arria10_chameleonv3-u-boot.dtsi
and put them there.

Regards,
Paweł

Re: [PATCH 02/11] arm: dts: Add Chameleonv3 handoff headers

[Paweł Anikiel]

On Mon, Apr 11, 2022 at 8:35 PM Simon Glass  wrote:
>
> On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel  wrote:
> >
> > Add handoff headers for the Google Chameleonv3 variants: 480-2 and
> > 270-3. Both files were generated using qts-filter-a10.sh.
> >
> > Signed-off-by: Paweł Anikiel 
> > ---
> >  .../dts/socfpga_chameleonv3_270_3_handoff.h   | 305 ++
> >  .../dts/socfpga_chameleonv3_480_2_handoff.h   | 305 ++
> >  2 files changed, 610 insertions(+)
> >  create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h
> >  create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2_handoff.h
>
> If these are binding files needed for the dts, should they not go into
> include/dt-bindings ?
>
> If not, can they go into arch/arm/include/asm/arch-... ?

These files are generated by Quartus, they include things like pinmux
configurations and clock settings.
I put them in the same place as the existing arria10_socdk handoff:
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.h

I don't mind putting them in include/dt-bindings, but then we should
probably also move the arria10_socdk one.
What do you think?

Regards,
Paweł

Re: [PATCH 07/11] sysreset: socfpga: Use parent device for reading base address

[Paweł Anikiel]

On Mon, Apr 11, 2022 at 8:36 PM Simon Glass  wrote:
>
> On Fri, 1 Apr 2022 at 06:44, Paweł Anikiel  wrote:
> >
> > This driver is a child of the rstmgr driver, both of which share the
> > same devicetree node. As a result, passing the child's udevice pointer
> > to dev_read_addr_ptr results in a failure of reading the #address-cells
> > property. Use the parent udevice pointer instead.
> >
> > Signed-off-by: Paweł Anikiel 
> > ---
> >  drivers/sysreset/sysreset_socfpga.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
>
> Reviewed-by: Simon Glass 
>
> >
> > diff --git a/drivers/sysreset/sysreset_socfpga.c 
> > b/drivers/sysreset/sysreset_socfpga.c
> > index e38296ac3f..9b62dd5eab 100644
> > --- a/drivers/sysreset/sysreset_socfpga.c
> > +++ b/drivers/sysreset/sysreset_socfpga.c
> > @@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
>
> Perhaps this function
> >  {
> > struct socfpga_sysreset_data *data = dev_get_priv(dev);
> >
> > -   data->rstmgr_base = dev_read_addr_ptr(dev);
> > +   data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
> > return 0;
> >  }
> >
> > --
> > 2.35.1.1094.g7c7d902a7c-goog
> >
>
> This is pretty odd and I think it could use a comment, particularly as
> this driver doesn't seem to be in the device tree.

It does get bound to a devicetree node by a different driver:
reset-socfpga (drivers/reset/reset-socfpga.c:141):
/*
 * The sysreset driver does not have a device node, so bind it here.
 * Bind it to the node, too, so that it can get its base address.
 */
ret = device_bind_driver_to_node(dev, "socfpga_sysreset", "sysreset",
 dev_ofnode(dev), &sys_child);
However, this makes it so that dev_read_addr_ptr doesn't behave the way
one would think, hence this patch.

It is pretty odd, it seems to be caused by the fact that Arria 10's
peripheral reset manager
is also responsible for system reset (see "ctrl" register in rst_mgr's
register map):
https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#topic/sfo1429890591861.html
Because of this, the two drivers have to share the same devicetree node.

Do you see a different way this could be fixed? If not, I will add
a comment with an explanation similar to the commit message.

Regards,
Paweł

[PATCH 11/11] socfpga: arria10: Allow dcache_enable before relocation

[Paweł Anikiel]

Before relocating to SDRAM, the ECC is initialized by clearing the
whole SDRAM. In order to speed this up, dcache_enable is used (see
sdram_init_ecc_bits).

Since commit 503eea451903 ("arm: cp15: update DACR value to activate
access control"), this no longer works, because running code in OCRAM
with the XN bit set causes a page fault. Override dram_bank_mmu_setup
to disable XN in the OCRAM and setup DRAM dcache before relocation.

Signed-off-by: Paweł Anikiel 
---
 arch/arm/mach-socfpga/misc_arria10.c | 26 ++
 1 file changed, 26 insertions(+)

diff --git a/arch/arm/mach-socfpga/misc_arria10.c 
b/arch/arm/mach-socfpga/misc_arria10.c
index 0ed2adfd84..7ce888d197 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)
return 0;
 }
 #endif
+
+void dram_bank_mmu_setup(int bank)
+{
+   struct bd_info *bd = gd->bd;
+   u32 start, size;
+   int i;
+
+   /* If we're still in OCRAM, don't set the XN bit on it */
+   if (!(gd->flags & GD_FLG_RELOC)) {
+   set_section_dcache(
+   CONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,
+   DCACHE_WRITETHROUGH);
+   }
+
+   /*
+* The default implementation of this function allows the DRAM dcache
+* to be enabled only after relocation. However, to speed up ECC
+* initialization, we want to be able to enable DRAM dcache before
+* relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram
+* is set first).
+*/
+   start = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;
+   size = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;
+   for (i = start; i < start + size; i++)
+   set_section_dcache(i, DCACHE_DEFAULT_OPTION);
+}
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 04/11] board: Add Chameleonv3 board dir

[Paweł Anikiel]

Add board directory for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel 
---
 board/google/chameleonv3/Makefile  |  5 +++
 board/google/chameleonv3/board.c   | 27 ++
 board/google/chameleonv3/fpga.its  | 28 ++
 board/google/chameleonv3/fpga_early_io.its | 35 ++
 board/google/chameleonv3/mercury_aa1.c | 43 ++
 board/google/chameleonv3/mercury_aa1.h | 12 ++
 6 files changed, 150 insertions(+)
 create mode 100644 board/google/chameleonv3/Makefile
 create mode 100644 board/google/chameleonv3/board.c
 create mode 100644 board/google/chameleonv3/fpga.its
 create mode 100644 board/google/chameleonv3/fpga_early_io.its
 create mode 100644 board/google/chameleonv3/mercury_aa1.c
 create mode 100644 board/google/chameleonv3/mercury_aa1.h

diff --git a/board/google/chameleonv3/Makefile 
b/board/google/chameleonv3/Makefile
new file mode 100644
index 00..bb413fde83
--- /dev/null
+++ b/board/google/chameleonv3/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Copyright 2022 Google LLC
+
+obj-y  := board.o mercury_aa1.o
diff --git a/board/google/chameleonv3/board.c b/board/google/chameleonv3/board.c
new file mode 100644
index 00..4d3049689d
--- /dev/null
+++ b/board/google/chameleonv3/board.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include 
+#include 
+#include "mercury_aa1.h"
+
+int misc_init_r(void)
+{
+   u8 mac[ARP_HLEN];
+   int res;
+
+   if (env_get("ethaddr"))
+   return 0;
+
+   res = mercury_aa1_read_mac(mac);
+   if (res) {
+   printf("couldn't read mac address: %s\n", errno_str(res));
+   return 0;
+   }
+
+   if (is_valid_ethaddr(mac))
+   eth_env_set_enetaddr("ethaddr", mac);
+
+   return 0;
+}
diff --git a/board/google/chameleonv3/fpga.its 
b/board/google/chameleonv3/fpga.its
new file mode 100644
index 00..85a830002f
--- /dev/null
+++ b/board/google/chameleonv3/fpga.its
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+   description = "FIT image with FPGA bistream";
+   #address-cells = <1>;
+
+   images {
+   fpga-periph-1 {
+   description = "FPGA full bitstream";
+   data = /incbin/("../../../fpga.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   };
+
+   configurations {
+   default = "config-1";
+   config-1 {
+   description = "Boot with FPGA config";
+   fpga = "fpga-periph-1";
+   };
+   };
+};
diff --git a/board/google/chameleonv3/fpga_early_io.its 
b/board/google/chameleonv3/fpga_early_io.its
new file mode 100644
index 00..ebc7bcbaae
--- /dev/null
+++ b/board/google/chameleonv3/fpga_early_io.its
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+/ {
+   description = "FIT image with FPGA bistream";
+   #address-cells = <1>;
+
+   images {
+   fpga-periph-1 {
+   description = "FPGA peripheral bitstream";
+   data = /incbin/("../../../periph.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   fpga-core-1 {
+   description = "FPGA core bitstream";
+   data = /incbin/("../../../core.rbf");
+   type = "fpga";
+   arch = "arm";
+   compression = "none";
+   };
+   };
+
+   configurations {
+   default = "config-1";
+   config-1 {
+   description = "Boot with FPGA config";
+   fpga = "fpga-periph-1", "fpga-core-1";
+   };
+   };
+};
diff --git a/board/google/chameleonv3/mercury_aa1.c 
b/board/google/chameleonv3/mercury_aa1.c
new file mode 100644
index 00..ed447ec37c
--- /dev/null
+++ b/board/google/chameleonv3/mercury_aa1.c
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include 
+#include 
+#include 
+#include 
+#include "mercury_aa1.h"
+
+#define MERCURY_AA1_ATSHA204A_OTP_MAC0 4
+#define MERCURY_AA1_ATSHA204A_OTP_MAC1 5
+
+int mercury_aa1_read_mac(u8 *mac)
+{
+   struct udevice *de

[PATCH 10/11] socfpga: arria10: Wait for fifo empty after writing bitstream

[Paweł Anikiel]

For some reason, on the Mercury+ AA1 module, calling
fpgamgr_wait_early_user_mode immediately after writing the peripheral
bitstream leaves the fpga in a broken state (ddr calibration hangs).
Adding a delay before the first sync word is written seems to fix this.
Inspecting the fpgamgr registers before and after the delay,
imgcfg_FifoEmpty is the only bit that changes. Waiting for this bit
(instead of a hardcoded delay) also fixes the issue.

Signed-off-by: Paweł Anikiel 
---
 drivers/fpga/socfpga_arria10.c | 8 
 1 file changed, 8 insertions(+)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 07bfe3060e..d8089122af 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -80,6 +80,13 @@ static int wait_for_user_mode(void)
1, FPGA_TIMEOUT_MSEC, false);
 }
 
+static int wait_for_fifo_empty(void)
+{
+   return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
+   ALT_FPGAMGR_IMGCFG_STAT_F2S_IMGCFG_FIFOEMPTY_SET_MSK,
+   1, FPGA_TIMEOUT_MSEC, false);
+}
+
 int is_fpgamgr_early_user_mode(void)
 {
return (readl(&fpga_manager_base->imgcfg_stat) &
@@ -874,6 +881,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void 
*buf, size_t bsize,
 
WATCHDOG_RESET();
}
+   wait_for_fifo_empty();
 
if (fpga_loadfs.rbfinfo.section == periph_section) {
if (fpgamgr_wait_early_user_mode() != -ETIMEDOUT) {
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg

[Paweł Anikiel]

Using udelay while the clocks aren't fully configured causes the timer
system to save the wrong clock rate. Use sdelay and wait_on_value
instead (the values used in these functions were found experimentally).

Signed-off-by: Paweł Anikiel 
---
 arch/arm/mach-socfpga/clock_manager.c  |  7 ---
 arch/arm/mach-socfpga/clock_manager_arria10.c  | 12 ++--
 arch/arm/mach-socfpga/include/mach/clock_manager.h |  4 
 3 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/arch/arm/mach-socfpga/clock_manager.c 
b/arch/arm/mach-socfpga/clock_manager.c
index 9e645a4253..c9bd4859f7 100644
--- a/arch/arm/mach-socfpga/clock_manager.c
+++ b/arch/arm/mach-socfpga/clock_manager.c
@@ -39,9 +39,10 @@ void cm_wait_for_lock(u32 mask)
 /* function to poll in the fsm busy bit */
 int cm_wait_for_fsm(void)
 {
-   return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() +
-CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 2,
-false);
+   void *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);
+
+   /* 20s timeout */
+   return wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 1);
 }
 
 int set_cpu_clk_info(void)
diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c 
b/arch/arm/mach-socfpga/clock_manager_arria10.c
index 58d5d3fd8a..daa06b9d03 100644
--- a/arch/arm/mach-socfpga/clock_manager_arria10.c
+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c
@@ -551,13 +551,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,
CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
cm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |
main_cfg->vco1_numer,
socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
 }
 
@@ -585,13 +585,13 @@ static void cm_pll_ramp_periph(struct mainpll_cfg 
*main_cfg,
 clk_hz),
  socfpga_get_clkmgr_addr() +
  CLKMGR_A10_PERPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
}
writel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |
  per_cfg->vco1_numer,
  socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
-   mdelay(1);
+   sdelay(100); /* 1ms */
cm_wait_for_lock(LOCKED_MASK);
 }
 
@@ -727,7 +727,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct 
perpll_cfg *per_cfg)
socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);
 
/* Wait for at least 5 us */
-   udelay(5);
+   sdelay(5000);
 
/* Now deassert BGPWRDN and PWRDN */
clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,
@@ -738,7 +738,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct 
perpll_cfg *per_cfg)
 CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);
 
/* Wait for at least 7 us */
-   udelay(7);
+   sdelay(7000);
 
/* enable the VCO and disable the external regulator to PLL */
writel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h 
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index a8cb07a1c4..78013f0527 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -20,6 +20,10 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
 #endif
 #endif
 
+void sdelay(unsigned long loops);
+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,
+ u32 bound);
+
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include 
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 09/11] socfpga: arria10: Improve bitstream loading speed

[Paweł Anikiel]

Apply some optimizations to speed up bitstream loading
(both for full and split periph/core bitstreams):

 * Change the size of the first fs read, so that all the subsequent
   reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).
   This value was chosen so that in subsequent reads the fat fs driver
   doesn't have to allocate a temporary buffer in get_contents
   (assuming 8KiB clusters).

 * Change the buffer size to a larger value when reading to ddr
   (but not too large, because large transfers cause a stack overflow
   in the dwmmc driver).

Signed-off-by: Paweł Anikiel 
---
 drivers/fpga/socfpga_arria10.c | 20 ++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c
index 798e3a3f90..07bfe3060e 100644
--- a/drivers/fpga/socfpga_arria10.c
+++ b/drivers/fpga/socfpga_arria10.c
@@ -30,6 +30,14 @@
 #define FPGA_TIMEOUT_MSEC  1000  /* timeout in ms */
 #define FPGA_TIMEOUT_CNT   0x100
 #define DEFAULT_DDR_LOAD_ADDRESS   0x400
+#define DDR_BUFFER_SIZE0x10
+
+/* When reading bitstream from a filesystem, the size of the first read is
+ * changed so that the subsequent reads are aligned to this value. This value
+ * was chosen so that in subsequent reads the fat fs driver doesn't have to
+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).
+ */
+#define MAX_FIRST_LOAD_SIZE0x2000
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -526,7 +534,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16 
*buffer)
 #ifdef CONFIG_FS_LOADER
 static int first_loading_rbf_to_buffer(struct udevice *dev,
struct fpga_loadfs_info *fpga_loadfs,
-   u32 *buffer, size_t *buffer_bsize)
+   u32 *buffer, size_t *buffer_bsize,
+   size_t *buffer_bsize_ori)
 {
u32 *buffer_p = (u32 *)*buffer;
u32 *loadable = buffer_p;
@@ -674,6 +683,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,
}
 
buffer_size = rbf_size;
+   *buffer_bsize_ori = DDR_BUFFER_SIZE;
}
 
debug("FPGA: External data: offset = 0x%x, size = 0x%x.\n",
@@ -686,11 +696,16 @@ static int first_loading_rbf_to_buffer(struct udevice 
*dev,
 * chunk by chunk transfer is required due to smaller buffer size
 * compare to bitstream
 */
+
+   if (buffer_size > MAX_FIRST_LOAD_SIZE)
+   buffer_size = MAX_FIRST_LOAD_SIZE;
+
if (rbf_size <= buffer_size) {
/* Loading whole bitstream into buffer */
buffer_size = rbf_size;
fpga_loadfs->remaining = 0;
} else {
+   buffer_size -= rbf_offset % buffer_size;
fpga_loadfs->remaining -= buffer_size;
}
 
@@ -806,7 +821,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void 
*buf, size_t bsize,
 * function below.
 */
ret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,
-  &buffer_sizebytes);
+  &buffer_sizebytes,
+  &buffer_sizebytes_ori);
if (ret == 1) {
printf("FPGA: Skipping configuration ...\n");
return 0;
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 05/11] config: Add Chameleonv3 config

[Paweł Anikiel]

Add defconfig and Kconfig files for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel 
---
 arch/arm/mach-socfpga/Kconfig | 15 
 configs/socfpga_chameleonv3_defconfig | 29 
 include/configs/socfpga_chameleonv3.h | 49 +++
 3 files changed, 93 insertions(+)
 create mode 100644 configs/socfpga_chameleonv3_defconfig
 create mode 100644 include/configs/socfpga_chameleonv3.h

diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index bddfd44427..926d535e54 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -118,6 +118,10 @@ config TARGET_SOCFPGA_STRATIX10
select FPGA_INTEL_SDM_MAILBOX
select TARGET_SOCFPGA_SOC64
 
+config TARGET_SOCFPGA_CHAMELEONV3
+   bool
+   select TARGET_SOCFPGA_ARRIA10
+
 choice
prompt "Altera SOCFPGA board select"
optional
@@ -143,6 +147,14 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK
bool "Altera SOCFPGA SoCDK (Arria V)"
select TARGET_SOCFPGA_ARRIA5
 
+config TARGET_SOCFPGA_CHAMELEONV3_480_2
+   bool "Google Chameleon V3 480-2 (Arria 10)"
+   select TARGET_SOCFPGA_CHAMELEONV3
+
+config TARGET_SOCFPGA_CHAMELEONV3_270_3
+   bool "Google Chameleon V3 270-3 (Arria 10)"
+   select TARGET_SOCFPGA_CHAMELEONV3
+
 config TARGET_SOCFPGA_CYCLONE5_SOCDK
bool "Altera SOCFPGA SoCDK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -194,6 +206,7 @@ config SYS_BOARD
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+   default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -219,6 +232,7 @@ config SYS_VENDOR
default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
+   default "google" if TARGET_SOCFPGA_CHAMELEONV3
default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
@@ -234,6 +248,7 @@ config SYS_CONFIG_NAME
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
+   default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
diff --git a/configs/socfpga_chameleonv3_defconfig 
b/configs/socfpga_chameleonv3_defconfig
new file mode 100644
index 00..815250e589
--- /dev/null
+++ b/configs/socfpga_chameleonv3_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_ARCH_SOCFPGA=y
+CONFIG_TARGET_SOCFPGA_CHAMELEONV3_480_2=y
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_chameleonv3_480_2"
+CONFIG_DISTRO_DEFAULTS=y
+# CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_FIT=y
+CONFIG_SPL_FIT=y
+CONFIG_FS_LOADER=y
+CONFIG_SPL_FS_LOADER=y
+CONFIG_SPL_FS_FAT=y
+CONFIG_SPL_FPGA=y
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_SIZE=0x1
+CONFIG_ENV_OFFSET=0x4400
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_TIMER=y
+CONFIG_SPL_TIMER=y
+CONFIG_DESIGNWARE_APB_TIMER=y
+CONFIG_MMC_DW=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_DW=y
+CONFIG_MISC=y
+CONFIG_MISC_INIT_R=y
+CONFIG_ATSHA204A=y
diff --git a/include/configs/socfpga_chameleonv3.h 
b/include/configs/socfpga_chameleonv3.h
new file mode 100644
index 00..2f224dfa4c
--- /dev/null
+++ b/include/configs/socfpga_chameleonv3.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2022 Google LLC
+ */
+#ifndef __SOCFGPA_CHAMELEONV3_H__
+#define __SOCFGPA_CHAMELEONV3_H__
+
+#include 
+
+#define CONFIG_SYS_BOOTM_LEN   (32 * 1024 * 1024)
+
+/*
+ * U-Boot general configurations
+ */
+
+/* Memory configurations  */
+#define PHYS_SDRAM_1_SIZE  0x4000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+   "kernel_addr_r=0x0100\0" \
+   "fdt_addr_r=0x0200\0" \
+   "bootargs=cma=

[PATCH 07/11] sysreset: socfpga: Use parent device for reading base address

[Paweł Anikiel]

This driver is a child of the rstmgr driver, both of which share the
same devicetree node. As a result, passing the child's udevice pointer
to dev_read_addr_ptr results in a failure of reading the #address-cells
property. Use the parent udevice pointer instead.

Signed-off-by: Paweł Anikiel 
---
 drivers/sysreset/sysreset_socfpga.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/sysreset/sysreset_socfpga.c 
b/drivers/sysreset/sysreset_socfpga.c
index e38296ac3f..9b62dd5eab 100644
--- a/drivers/sysreset/sysreset_socfpga.c
+++ b/drivers/sysreset/sysreset_socfpga.c
@@ -40,7 +40,7 @@ static int socfpga_sysreset_probe(struct udevice *dev)
 {
struct socfpga_sysreset_data *data = dev_get_priv(dev);
 
-   data->rstmgr_base = dev_read_addr_ptr(dev);
+   data->rstmgr_base = dev_read_addr_ptr(dev_get_parent(dev));
return 0;
 }
 
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 06/11] misc: atsha204a: Increase wake delay by tWHI

[Paweł Anikiel]

>From the ATSHA204A datasheet (document DS40002025A):

Wake: If SDA is held low for a period greater than tWLO, the device
exits low-power mode and, after a delay of tWHI, is ready to receive
I2C commands.

tWHI value can be found in table 7-2.

Signed-off-by: Paweł Anikiel 
---
 drivers/misc/atsha204a-i2c.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/atsha204a-i2c.c b/drivers/misc/atsha204a-i2c.c
index b89463babb..ba2ae3d85a 100644
--- a/drivers/misc/atsha204a-i2c.c
+++ b/drivers/misc/atsha204a-i2c.c
@@ -20,7 +20,8 @@
 #include 
 #include 
 
-#define ATSHA204A_TWLO 60
+#define ATSHA204A_TWLO_US  60
+#define ATSHA204A_TWHI_US  2500
 #define ATSHA204A_TRANSACTION_TIMEOUT  10
 #define ATSHA204A_TRANSACTION_RETRY5
 #define ATSHA204A_EXECTIME 5000
@@ -225,7 +226,7 @@ int atsha204a_wakeup(struct udevice *dev)
continue;
}
 
-   udelay(ATSHA204A_TWLO);
+   udelay(ATSHA204A_TWLO_US + ATSHA204A_TWHI_US);
 
res = atsha204a_recv_resp(dev, &resp);
if (res) {
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 03/11] arm: dts: Add Chameleonv3 devicetree

[Paweł Anikiel]

Add devicetree for Google Chameleon V3 board

Signed-off-by: Paweł Anikiel 
---
 arch/arm/dts/Makefile  |  2 ++
 arch/arm/dts/socfpga_chameleonv3.dtsi  | 21 +
 arch/arm/dts/socfpga_chameleonv3_270_3.dts |  9 +
 arch/arm/dts/socfpga_chameleonv3_480_2.dts |  9 +
 4 files changed, 41 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_chameleonv3.dtsi
 create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3.dts
 create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2.dts

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index beaaf15131..0ec4a4cab6 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -411,6 +411,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=   
\
socfpga_arria5_secu1.dtb\
socfpga_arria5_socdk.dtb\
socfpga_arria10_socdk_sdmmc.dtb \
+   socfpga_chameleonv3_270_3.dtb   \
+   socfpga_chameleonv3_480_2.dtb   \
socfpga_cyclone5_mcvevk.dtb \
socfpga_cyclone5_is1.dtb\
socfpga_cyclone5_socdk.dtb  \
diff --git a/arch/arm/dts/socfpga_chameleonv3.dtsi 
b/arch/arm/dts/socfpga_chameleonv3.dtsi
new file mode 100644
index 00..8b6a6cd8e4
--- /dev/null
+++ b/arch/arm/dts/socfpga_chameleonv3.dtsi
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_mercury_aa1.dtsi"
+
+&gmac0 {
+   status = "okay";
+};
+
+&i2c1 {
+   status = "okay";
+};
+
+&mmc {
+   status = "okay";
+};
+
+&uart1 {
+   status = "okay";
+};
diff --git a/arch/arm/dts/socfpga_chameleonv3_270_3.dts 
b/arch/arm/dts/socfpga_chameleonv3_270_3.dts
new file mode 100644
index 00..2e29d052e3
--- /dev/null
+++ b/arch/arm/dts/socfpga_chameleonv3_270_3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+#include "socfpga_chameleonv3_270_3_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_chameleonv3.dtsi"
diff --git a/arch/arm/dts/socfpga_chameleonv3_480_2.dts 
b/arch/arm/dts/socfpga_chameleonv3_480_2.dts
new file mode 100644
index 00..3273f216f2
--- /dev/null
+++ b/arch/arm/dts/socfpga_chameleonv3_480_2.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+/dts-v1/;
+
+#include "socfpga_chameleonv3_480_2_handoff.h"
+#include "socfpga_arria10-handoff.dtsi"
+#include "socfpga_chameleonv3.dtsi"
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 02/11] arm: dts: Add Chameleonv3 handoff headers

[Paweł Anikiel]

Add handoff headers for the Google Chameleonv3 variants: 480-2 and
270-3. Both files were generated using qts-filter-a10.sh.

Signed-off-by: Paweł Anikiel 
---
 .../dts/socfpga_chameleonv3_270_3_handoff.h   | 305 ++
 .../dts/socfpga_chameleonv3_480_2_handoff.h   | 305 ++
 2 files changed, 610 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h
 create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2_handoff.h

diff --git a/arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h 
b/arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h
new file mode 100644
index 00..9d8f4a0dd3
--- /dev/null
+++ b/arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h
@@ -0,0 +1,305 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Intel Arria 10 SoCFPGA configuration
+ */
+
+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__
+#define __SOCFPGA_ARRIA10_CONFIG_H__
+
+/* Clocks */
+#define CB_INTOSC_LS_CLK_HZ 6000
+#define EMAC0_CLK_HZ 25000
+#define EMAC1_CLK_HZ 25000
+#define EMAC2_CLK_HZ 25000
+#define EOSC1_CLK_HZ 
+#define F2H_FREE_CLK_HZ 2
+#define H2F_USER0_CLK_HZ 2
+#define H2F_USER1_CLK_HZ 1
+#define L3_MAIN_FREE_CLK_HZ 2
+#define SDMMC_CLK_HZ 2
+#define TPIU_CLK_HZ 1
+#define MAINPLLGRP_CNTR15CLK_CNT 900
+#define MAINPLLGRP_CNTR2CLK_CNT 900
+#define MAINPLLGRP_CNTR3CLK_CNT 900
+#define MAINPLLGRP_CNTR4CLK_CNT 900
+#define MAINPLLGRP_CNTR5CLK_CNT 900
+#define MAINPLLGRP_CNTR6CLK_CNT 7
+#define MAINPLLGRP_CNTR7CLK_CNT 7
+#define MAINPLLGRP_CNTR7CLK_SRC 0
+#define MAINPLLGRP_CNTR8CLK_CNT 15
+#define MAINPLLGRP_CNTR9CLK_CNT 900
+#define MAINPLLGRP_CNTR9CLK_SRC 0
+#define MAINPLLGRP_MPUCLK_CNT 0
+#define MAINPLLGRP_MPUCLK_SRC 0
+#define MAINPLLGRP_NOCCLK_CNT 0
+#define MAINPLLGRP_NOCCLK_SRC 0
+#define MAINPLLGRP_NOCDIV_CSATCLK 0
+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1
+#define MAINPLLGRP_NOCDIV_CSTRACECLK 0
+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0
+#define MAINPLLGRP_NOCDIV_L4MPCLK 1
+#define MAINPLLGRP_NOCDIV_L4SPCLK 2
+#define MAINPLLGRP_VCO0_PSRC 0
+#define MAINPLLGRP_VCO1_DENOM 32
+#define MAINPLLGRP_VCO1_NUMER 1584
+#define PERPLLGRP_CNTR2CLK_CNT 5
+#define PERPLLGRP_CNTR2CLK_SRC 1
+#define PERPLLGRP_CNTR3CLK_CNT 900
+#define PERPLLGRP_CNTR3CLK_SRC 1
+#define PERPLLGRP_CNTR4CLK_CNT 14
+#define PERPLLGRP_CNTR4CLK_SRC 1
+#define PERPLLGRP_CNTR5CLK_CNT 374
+#define PERPLLGRP_CNTR5CLK_SRC 1
+#define PERPLLGRP_CNTR6CLK_CNT 900
+#define PERPLLGRP_CNTR6CLK_SRC 0
+#define PERPLLGRP_CNTR7CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_CNT 900
+#define PERPLLGRP_CNTR8CLK_SRC 0
+#define PERPLLGRP_CNTR9CLK_CNT 900
+#define PERPLLGRP_EMACCTL_EMAC0SEL 0
+#define PERPLLGRP_EMACCTL_EMAC1SEL 0
+#define PERPLLGRP_EMACCTL_EMAC2SEL 0
+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000
+#define PERPLLGRP_VCO0_PSRC 0
+#define PERPLLGRP_VCO1_DENOM 32
+#define PERPLLGRP_VCO1_NUMER 1485
+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16
+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8
+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8
+#define ALTERAGRP_MPUCLK_MAINCNT 1
+#define ALTERAGRP_MPUCLK_PERICNT 900
+#define ALTERAGRP_NOCCLK_MAINCNT 7
+#define ALTERAGRP_NOCCLK_PERICNT 900
+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \
+   (ALTERAGRP_MPUCLK_MAINCNT))
+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \
+   (ALTERAGRP_NOCCLK_MAINCNT))
+
+/* Pin Mux Configuration */
+#define CONFIG_IO_10_INPUT_BUF_EN 1
+#define CONFIG_IO_10_PD_DRV_STRG 10
+#define CONFIG_IO_10_PD_SLW_RT 1
+#define CONFIG_IO_10_PU_DRV_STRG 8
+#define CONFIG_IO_10_PU_SLW_RT 1
+#define CONFIG_IO_10_RTRIM 1
+#define CONFIG_IO_10_WK_PU_EN 0
+#define CONFIG_IO_11_INPUT_BUF_EN 1
+#define CONFIG_IO_11_PD_DRV_STRG 10
+#define CONFIG_IO_11_PD_SLW_RT 1
+#define CONFIG_IO_11_PU_DRV_STRG 8
+#define CONFIG_IO_11_PU_SLW_RT 1
+#define CONFIG_IO_11_RTRIM 1
+#define CONFIG_IO_11_WK_PU_EN 0
+#define CONFIG_IO_12_INPUT_BUF_EN 0
+#define CONFIG_IO_12_PD_DRV_STRG 0
+#define CONFIG_IO_12_PD_SLW_RT 0
+#define CONFIG_IO_12_PU_DRV_STRG 0
+#define CONFIG_IO_12_PU_SLW_RT 0
+#define CONFIG_IO_12_RTRIM 1
+#define CONFIG_IO_12_WK_PU_EN 1
+#define CONFIG_IO_13_INPUT_BUF_EN 0
+#define CONFIG_IO_13_PD_DRV_STRG 0
+#define CONFIG_IO_13_PD_SLW_RT 0
+#define CONFIG_IO_13_PU_DRV_STRG 0
+#define CONFIG_IO_13_PU_SLW_RT 0
+#define CONFIG_IO_13_RTRIM 1
+#define CONFIG_IO_13_WK_PU_EN 1
+#define CONFIG_IO_14_INPUT_BUF_EN 0
+#define CONFIG_IO_14_PD_DRV_STRG 0
+#define CONFIG_IO_14_PD_SLW_RT 0
+#define CONFIG_IO_14_PU_DRV_STRG 0
+#define CONFIG_IO_14_PU_SLW_RT 0
+#define CONFIG_IO_14_RTRIM 1
+#define CONFIG_IO_14_WK_PU_EN 1
+#define CONFIG_IO_15_INPUT_BUF_EN 0
+#define CONFIG_IO_15_PD_DRV_STRG 0
+#define CONFIG_IO_15_PD_SLW_RT 0
+#define CONFIG_IO_15_PU_DRV_STRG 0
+#define CONFIG_IO_15_PU_SLW_RT 0
+#define CONFIG_IO_15_RTRIM 1
+#define CONFIG_IO_15_WK_PU_EN 1
+#define CONFIG_IO_16_INPUT_BUF_EN 0
+#define CONFIG_IO_16_PD_DRV_STRG 10
+#define CONFIG_IO_16_PD_SLW_RT 1
+#define CONFIG_IO_16_PU_DRV_STR

[PATCH 01/11] arm: dts: Add Mercury+ AA1 devicetree

[Paweł Anikiel]

Device tree header for Mercury+ AA1 module

Signed-off-by: Paweł Anikiel 
---
 arch/arm/dts/socfpga_mercury_aa1.dtsi | 95 +++
 1 file changed, 95 insertions(+)
 create mode 100644 arch/arm/dts/socfpga_mercury_aa1.dtsi

diff --git a/arch/arm/dts/socfpga_mercury_aa1.dtsi 
b/arch/arm/dts/socfpga_mercury_aa1.dtsi
new file mode 100644
index 00..7d0bf884a3
--- /dev/null
+++ b/arch/arm/dts/socfpga_mercury_aa1.dtsi
@@ -0,0 +1,95 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2022 Google LLC
+ */
+#include "socfpga_arria10.dtsi"
+#include "socfpga_arria10-u-boot.dtsi"
+
+/ {
+   model = "Altera SOCFPGA Arria 10";
+   compatible = "altr,socfpga-arria10", "altr,socfpga";
+
+   aliases {
+   ethernet0 = &gmac0;
+   serial0 = &uart1;
+   };
+
+   chosen {
+   stdout-path = "serial0:115200n8";
+   firmware-loader = <&fs_loader0>;
+   };
+
+   memory@0 {
+   name = "memory";
+   device_type = "memory";
+   reg = <0x0 0x8000>; /* 2GB */
+   };
+
+   fs_loader0: fs-loader {
+   u-boot,dm-pre-reloc;
+   compatible = "u-boot,fs-loader";
+   phandlepart = <&mmc 1>;
+   };
+};
+
+&fpga_mgr {
+   u-boot,dm-pre-reloc;
+   altr,bitstream = "fpga.itb";
+};
+
+&gmac0 {
+   phy-mode = "rgmii";
+   phy-addr = <0x>; /* probe for phy addr */
+
+   txd0-skew-ps = <0>; /* -420ps */
+   txd1-skew-ps = <0>; /* -420ps */
+   txd2-skew-ps = <0>; /* -420ps */
+   txd3-skew-ps = <0>; /* -420ps */
+   rxd0-skew-ps = <420>; /* 0ps */
+   rxd1-skew-ps = <420>; /* 0ps */
+   rxd2-skew-ps = <420>; /* 0ps */
+   rxd3-skew-ps = <420>; /* 0ps */
+   txen-skew-ps = <0>; /* -420ps */
+   txc-skew-ps = <1860>; /* 960ps */
+   rxdv-skew-ps = <420>; /* 0ps */
+   rxc-skew-ps = <1680>; /* 780ps */
+   max-frame-size = <3800>;
+};
+
+&i2c1 {
+   u-boot,dm-pre-reloc;
+
+   atsha204a@64 {
+   u-boot,dm-pre-reloc;
+   compatible = "atmel,atsha204a";
+   reg = <0x64>;
+   };
+};
+
+&main_sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&mmc {
+   cap-sd-highspeed;
+   cap-mmc-highspeed;
+   broken-cd;
+   bus-width = <4>;
+   u-boot,dm-pre-reloc;
+};
+
+&peri_sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&sdmmc_free_clk {
+   u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+   u-boot,dm-pre-reloc;
+};
-- 
2.35.1.1094.g7c7d902a7c-goog

[PATCH 00/11] Add Chameleon V3 support

[Paweł Anikiel]

The Google Chameleon V3 is a board made for testing both video and audio
interfaces of external devices. It has a connector compatible with the
Mercury+ AA1 module, which itself contains an Arria 10 SoCFPGA. The AA1
module comes in a few different configurations, the Chameleon V3 supports
ME-AA1-270-3E4-D11 and ME-AA1-480-2I3-D12E.

This patchset adds support for the Chameleon V3 (both versions), as well
as some bugfixes and optimizations, mostly in Arria 10 code.

Paweł Anikiel (11):
  arm: dts: Add Mercury+ AA1 devicetree
  arm: dts: Add Chameleonv3 handoff headers
  arm: dts: Add Chameleonv3 devicetree
  board: Add Chameleonv3 board dir
  config: Add Chameleonv3 config
  misc: atsha204a: Increase wake delay by tWHI
  sysreset: socfpga: Use parent device for reading base address
  socfpga: arria10: Replace delays with busy waiting in cm_full_cfg
  socfpga: arria10: Improve bitstream loading speed
  socfpga: arria10: Wait for fifo empty after writing bitstream
  socfpga: arria10: Allow dcache_enable before relocation

 arch/arm/dts/Makefile |   2 +
 arch/arm/dts/socfpga_chameleonv3.dtsi |  21 ++
 arch/arm/dts/socfpga_chameleonv3_270_3.dts|   9 +
 .../dts/socfpga_chameleonv3_270_3_handoff.h   | 305 ++
 arch/arm/dts/socfpga_chameleonv3_480_2.dts|   9 +
 .../dts/socfpga_chameleonv3_480_2_handoff.h   | 305 ++
 arch/arm/dts/socfpga_mercury_aa1.dtsi | 103 ++
 arch/arm/mach-socfpga/Kconfig |  15 +
 arch/arm/mach-socfpga/clock_manager.c |   7 +-
 arch/arm/mach-socfpga/clock_manager_arria10.c |  12 +-
 .../mach-socfpga/include/mach/clock_manager.h |   4 +
 arch/arm/mach-socfpga/misc_arria10.c  |  26 ++
 board/google/chameleonv3/Makefile |   5 +
 board/google/chameleonv3/board.c  |  27 ++
 board/google/chameleonv3/fpga.its |  28 ++
 board/google/chameleonv3/fpga_early_io.its|  35 ++
 board/google/chameleonv3/mercury_aa1.c|  43 +++
 board/google/chameleonv3/mercury_aa1.h|  12 +
 configs/socfpga_chameleonv3_defconfig |  29 ++
 drivers/fpga/socfpga_arria10.c|  28 +-
 drivers/misc/atsha204a-i2c.c  |   5 +-
 drivers/sysreset/sysreset_socfpga.c   |   2 +-
 include/configs/socfpga_chameleonv3.h |  49 +++
 23 files changed, 1067 insertions(+), 14 deletions(-)
 create mode 100644 arch/arm/dts/socfpga_chameleonv3.dtsi
 create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3.dts
 create mode 100644 arch/arm/dts/socfpga_chameleonv3_270_3_handoff.h
 create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2.dts
 create mode 100644 arch/arm/dts/socfpga_chameleonv3_480_2_handoff.h
 create mode 100644 arch/arm/dts/socfpga_mercury_aa1.dtsi
 create mode 100644 board/google/chameleonv3/Makefile
 create mode 100644 board/google/chameleonv3/board.c
 create mode 100644 board/google/chameleonv3/fpga.its
 create mode 100644 board/google/chameleonv3/fpga_early_io.its
 create mode 100644 board/google/chameleonv3/mercury_aa1.c
 create mode 100644 board/google/chameleonv3/mercury_aa1.h
 create mode 100644 configs/socfpga_chameleonv3_defconfig
 create mode 100644 include/configs/socfpga_chameleonv3.h

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2.35.1.1094.g7c7d902a7c-goog