[U-Boot] Dove / Cubox support patch series (was: Re: [PATCH v4 05/10] SPI: Add Dove SPI driver)
Hello Jagan, Jagan Teki jagannadh.t...@gmail.com writes: Any update on this. The Wandboard Quad is working well for my purposes and much easier to work with (schematics and very extensive data sheets available, mainline support in both U-Boot and Linux). As a result, I'm focusing my limited resources on the Wandboard rather than the Cubox. Sascha pgpKZOKuaHMtk.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 02/28] sf: probe: Add new spi_flash_probe support
Hi Jagannadha, Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com writes: Added new spi_flash_probe support, currently added N25Q* flash part attributes support. [...] I've given your series another try on Cubox. It looks better this time (e.g. the probe issue is gone), but there are still a couple of issues. I'm going to reply to each of the affected patches (2, 7, 14) individually so it shows up properly in Patchwork. This patch causes a major regression and thus breaks bisectability. It rips out support for all SPI flash chips except for STMICRO ones, unless CONFIG_SPI_FLASH_LEGACY is defined. However, CONFIG_SPI_FLASH_LEGACY doesn't get defined anywhere. A better approach would be to make the new code opt-in rather than opt-out, and selecting it automatically for CONFIG_SPI_FLASH_vendor as support for each vendor is added. PS: What's the etiquette for the CC list of replies to patches? Keep all original recipients CC'ed? Or should I have dropped the chip vendor contacts for this reply? Sascha pgpc63HuOMARK.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 07/28] sf: probe: Add support for W25* flash parts
Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com
writes:
Added W25* parts are which are avilable in spi_flash_probe_legacy.c.
Updated the sector_size attributes as per the flash parts.
Looks fine for with this sector_size for computing the size
of flash.
This breaks sector-sized (i.e. 4KiB) erases on W25Q32BV (and many other
Winbond chips). The sizes are set differently by the old code and yours:
old yours
page_size 256 256
sector_size 4K 64K
size 4M 4M
The data sheet defines three different granularities: pages (256B, used
for writing), sectors (4KiB, used for erasing), blocks (64KiB, used for
write protection in some configurations). You seem to have mixed sectors
and blocks. The total size is the same, but sector-sized erases stop
working.
With the following change, my (rather simple) test cases work again:
diff --git i/drivers/mtd/spi/spi_flash_probe.c
w/drivers/mtd/spi/spi_flash_probe.c
index 1ff3b60..6f13484 100644
--- i/drivers/mtd/spi/spi_flash_probe.c
+++ w/drivers/mtd/spi/spi_flash_probe.c
@@ -85,7 +85,7 @@ static const struct spi_flash_params spi_flash_params_table[]
= {
{W25X64, 0xef3017, 0x0, 64 * 1024,128},
{W25Q80BL,0xef4014, 0x0, 64 * 1024, 16},
{W25Q16CL,0xef4015, 0x0, 64 * 1024, 32},
- {W25Q32BV,0xef4016, 0x0, 64 * 1024, 64},
+ {W25Q32BV,0xef4016, 0x0, 4 * 1024, 1024},
{W25Q64CV,0xef4017, 0x0, 64 * 1024,128},
{W25Q128BV, 0xef4018, 0x0, 64 * 1024,256},
{W25Q256, 0xef4019, 0x0, 64 * 1024,512},
The other chips will need similar changes.
Sascha
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Re: [U-Boot] [PATCH v3 14/28] sf: probe: Add support for erase sector selection flag
Hi Jagannadha,
Jagannadha Sutradharudu Teki jagannadha.sutradharudu-t...@xilinx.com
writes:
SECT_4K, SECT_32K and SECT_64K opeartions are performed to
to specific flash by adding a SECT* flag on respective
spi_flash_params.flag param.
[...]
[drivers/mtd/spi/spi_flash_ops.c]
@@ -153,17 +153,13 @@ int spi_flash_cmd_erase(struct spi_flash *flash, u32
offset, size_t len)
u8 cmd[4];
int ret = -1;
- erase_size = flash-sector_size;
+ erase_size = flash-erase_size;
if (offset % erase_size || len % erase_size) {
debug(SF: Erase offset/length not multiple of erase size\n);
return -1;
}
- if (erase_size == 4096)
- cmd[0] = CMD_ERASE_4K;
- else
- cmd[0] = CMD_ERASE_64K;
-
+ cmd[0] = flash-erase_cmd;
[...]
[drivers/mtd/spi/spi_flash_probe.c]
[...]
+ {W25Q32BV, 0xef4016, 0x0, 64 * 1024,64,
SEC_4K},
[...]
I don't quite see the point of this patch. AFAICT, at least the Winbond
chips support _both_ sector-sized and block-sized (32KiB, 64KiB)
erases. The latter are just a more efficient way of erasing larger
regions. So selecting the command to use should be based on the size and
alignment of the region that's going to be erased, not based on the size
of the chip.
In addition, a couple of typos (SEC_* instead of SECT_*) break the
build.
Sascha
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[U-Boot] [PATCH 0/3] openrd: Check U-Boot size at build time
Tom Rini tr...@ti.com writes: Yes, you can try using CONFIG_BOARD_SIZE_LIMIT, which is missing from the README, but does have a few examples (git grep around). A patch to document it, and then a patch to enable for openrd would be much appreciated. Thanks! Thanks for the pointer. Here we go. Sascha Silbe (3): README: document CONFIG_BOARD_SIZE_LIMIT Makefile: check native boot image sizes against CONFIG_BOARD_SIZE_LIMIT openrd: fail build if U-Boot would overlap with environment in flash Makefile | 3 +++ README | 5 + include/configs/openrd.h | 5 + 3 files changed, 13 insertions(+) -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] openrd: fail build if U-Boot would overlap with environment in flash
Set CONFIG_BOARD_SIZE_LIMIT so we'll notice at build time if U-Boot has grown so large that it would overlap with the environment area in flash, rather than bricking the device at run-time on first saveenv. Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de --- include/configs/openrd.h | 5 + 1 file changed, 5 insertions(+) diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 8fab6e6..b7526f8 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -76,6 +76,11 @@ #define CONFIG_ENV_SIZE0x2 /* 128k */ #define CONFIG_ENV_ADDR0x6 #define CONFIG_ENV_OFFSET 0x6 /* env starts here */ +/* + * Environment is right behind U-Boot in flash. Make sure U-Boot + * doesn't grow into the environment area. + */ +#define CONFIG_BOARD_SIZE_LIMITCONFIG_ENV_OFFSET /* * Default environment variables -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] README: document CONFIG_BOARD_SIZE_LIMIT
CONFIG_BOARD_SIZE_LIMIT was introduced by f3a14d37 [Makefile: allow boards to check file size limits] and is in use by several boards, but never got documented. Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de --- README | 5 + 1 file changed, 5 insertions(+) diff --git a/README b/README index a5c3e8d..760c417 100644 --- a/README +++ b/README @@ -3843,6 +3843,11 @@ use the saveenv command to store a valid environment. later, once stdio is running and output goes to the LCD, if present. +- CONFIG_BOARD_SIZE_LIMIT: + Maximum size of the U-Boot image. When defined, the + build system checks that the actual size does not + exceed it. + Low Level (hardware related) configuration options: --- -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] Makefile: check native boot image sizes against CONFIG_BOARD_SIZE_LIMIT
The purpose of CONFIG_BOARD_SIZE_LIMIT is to make sure that U-Boot fits into the space reserved for it in some permanent storage. This includes any overhead incurred by native boot image formats, so check the final image against the size limit, too. Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de --- Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile b/Makefile index d545d30..3e05f9a 100644 --- a/Makefile +++ b/Makefile @@ -459,15 +459,18 @@ $(obj)u-boot.img: $(obj)u-boot.bin $(obj)u-boot.imx: $(obj)u-boot.bin depend $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx + $(BOARD_SIZE_CHECK) $(obj)u-boot.kwb: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_SYS_KWD_CONFIG) -T kwbimage \ -a $(CONFIG_SYS_TEXT_BASE) -e $(CONFIG_SYS_TEXT_BASE) -d $ $@ + $(BOARD_SIZE_CHECK) $(obj)u-boot.pbl: $(obj)u-boot.bin $(obj)tools/mkimage -n $(CONFIG_PBLRCW_CONFIG) \ -R $(CONFIG_PBLPBI_CONFIG) -T pblimage \ -d $ $@ + $(BOARD_SIZE_CHECK) $(obj)u-boot.sha1: $(obj)u-boot.bin $(obj)tools/ubsha1 $(obj)u-boot.bin -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RESEND PATCH v2 00/20] sf: Add common probe support
Hello Jagan,
Jagan Teki jagannadh.t...@gmail.com writes:
Please find the test branch for this patch series, here.
http://git.denx.de/?p=u-boot/u-boot-spi.git;a=shortlog;h=refs/heads/master-test
Request to test these changes on your boards.
Let me know for any issues.
Thanks for setting up a branch for easier testing. I've rebased the
CuBox support patch series [1] on top of your branch and tested the
result. SPI flash support worked before on CuBox, but fails with your
branch.
At build time, the following warnings are issued (found using
DBGFLAGS=-g -Werror):
make[1]: Entering directory `/lhome/sascha.silbe/src/u-boot/common'
arm-linux-gnueabi-gcc -g -Werror -Os -ffunction-sections -fdata-sections
-fno-common -ffixed-r8 -msoft-float -D__KERNEL__
-DCONFIG_SYS_TEXT_BASE=0x0060 -I/lhome/sascha.silbe/src/u-boot/include
-fno-builtin -ffreestanding -nostdinc -isystem
/usr/lib/gcc/arm-linux-gnueabi/4.7/include -pipe -DCONFIG_ARM -D__ARM__ -marm
-mno-thumb-interwork -mabi=aapcs-linux -march=armv7-a -Wall -Wstrict-prototypes
-fno-stack-protector -Wno-format-nonliteral -Wno-format-security -fstack-usage
-o cmd_sf.o cmd_sf.c -c
In file included from cmd_sf.c:11:0:
/lhome/sascha.silbe/src/u-boot/include/spi_flash.h:37:12: error:
‘spi_write_cmds_array’ defined but not used [-Werror=unused-variable]
/lhome/sascha.silbe/src/u-boot/include/spi_flash.h:56:12: error:
‘spi_read_cmds_array’ defined but not used [-Werror=unused-variable]
cc1: all warnings being treated as errors
make[1]: *** [cmd_sf.o] Error 1
At run time, automatically reading the environment from SPI flash
fails. sf probe and sf read both appear to work, but sf probe
reports 64KiB page size and sf read only yields 0xff rather than the
U-Boot binary that's at the start of SPI flash:
=== Begin ===
U-Boot 2013.07-00163-g753bc19 (Aug 11 2013 - 12:13:01)SolidRun CuBox
SoC: Dove 88AP510 (A1)
CPU: Marvell Sheeva (rev 5)
DRAM: 2 GiB
MMC: Dove SDHCI0: 0
*** Warning - spi_flash_probe() failed, using default environment
In:serial
Out: serial
Err: serial
Net: egiga0 Waiting for PHY auto negotiation to complete done
egiga0
Warning: failed to set MAC address
Hit any key to stop autoboot: 0
CuBox sf probe
SF: Detected W25Q32BV with page size 64 KiB, total 4 MiB
CuBox sf read ${loadaddr} 0 0x2
SF: 131072 bytes @ 0x0 Read: OK
CuBox md.b ${loadaddr}
0200: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
0210: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
0220: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
0230: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
=== End ===
For comparison, this is what it looks like on top of current master:
=== Begin ===
U-Boot 2013.07-00123-gde877d3 (Aug 11 2013 - 13:39:44)SolidRun CuBox
SoC: Dove 88AP510 (A1)
CPU: Marvell Sheeva (rev 5)
DRAM: 2 GiB
MMC: Dove SDHCI0: 0
SF: Detected W25Q32BV/W25Q32FV_SPI with page size 4 KiB, total 4 MiB
In:serial
Out: serial
Err: serial
Net: egiga0 Waiting for PHY auto negotiation to complete... done
egiga0
Hit any key to stop autoboot: 0
CuBox sf probe
SF: Detected W25Q32BV/W25Q32FV_SPI with page size 4 KiB, total 4 MiB
CuBox sf read ${loadaddr} 0 0x2
SF: 131072 bytes @ 0x0 Read: OK
CuBox md.b ${loadaddr}
0200: 5a 00 00 00 54 67 04 00 00 00 00 00 00 02 00 00Z...Tg..
0210: 00 00 60 00 00 00 60 00 00 00 00 00 00 00 01 dc..`...`.
0220: 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00@...
0230: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
CuBox
=== End ===
Is there something that needs to be done differently now? Some
additional function to call in board setup code or defines to set in the
board configuration?
Sascha
[1] mid:1372195668-25496-1-git-send-email-t-ub...@infra-silbe.de
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/148412/focus=164287
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Re: [U-Boot] [PATCH] OpenRD: relocate environment to 640kB
Hi Albert, Albert ARIBAUD albert.u.b...@aribaud.net writes: On Mon, 15 Jul 2013 08:19:57 -0400, Tom Rini tr...@ti.com wrote: On Mon, Jul 15, 2013 at 11:23:54AM +0200, Sascha Silbe wrote: With v2013.07-rc3, we are now at 376344B (~ 96% of 384KiB) for openrd_ultimate when built on Debian Wheezy using gcc-4.7-arm-linux-gnueabi from Emdebian. [...] Yes, you can try using CONFIG_BOARD_SIZE_LIMIT, which is missing from the README, but does have a few examples (git grep around). A patch to document it, and then a patch to enable for openrd would be much appreciated. Thanks! Sascha, does this mean the env relocate patch here is dropped in favor of a CONFIG_BOARD_SIZE_LIMIT check at build time? Given that we're already very close to the limit, we'll likely need the environment relocation patch sooner or later anyway. I'd prefer it to go in now as part of the regular release cycle, rather than as a hot-fix whenever it finally spills over. That also reduces the risk of builds failing only with particular toolchain versions. Sascha pgpn1UoGIiKjZ.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] kirkwood: use 64bit integer for IDE LBA sector numbers
Many recent hard disks are larger than 2TiB. They still use a logical sector size of 512, so 32-bit sector numbers are insufficient (and even with 4K logical sector size we'd exceed the limit once there are 16TiB drives). Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de --- arch/arm/include/asm/arch-kirkwood/config.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h index 197703b..d7129e2 100644 --- a/arch/arm/include/asm/arch-kirkwood/config.h +++ b/arch/arm/include/asm/arch-kirkwood/config.h @@ -117,6 +117,7 @@ #define CONFIG_SYS_ATA_STRIDE 4 /* Controller supports 48-bits LBA addressing */ #define CONFIG_LBA48 +#define CONFIG_SYS_64BIT_LBA /* CONFIG_CMD_IDE requires some #defines for ATA registers */ #define CONFIG_SYS_IDE_MAXBUS 2 #define CONFIG_SYS_IDE_MAXDEVICE 2 -- 1.8.3.2 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v6] NET: mvgbe: avoid unused variable warning when used without phylib support
Avoid a recently introduced unused variable warning for boards that
use mvgbe but not phylib.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v5-v6: Split out from CuBox support patch series.
drivers/net/mvgbe.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 6c901d1..0cd06b6 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -420,8 +420,9 @@ static int mvgbe_init(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe-regs;
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
- defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
+ !defined(CONFIG_PHYLIB)\
+ defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
--
1.8.3.2
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Re: [U-Boot] Ethernet support broken for Wandboard Quad on master
Hello Charles, [CC += a few people that were CC'ed on the revert of Charles' patch] Charles Coldwell coldw...@gmail.com writes: I've never heard of the Wandboard Quad, so I suppose the short answer is no. However, the philosophy of the patch I submitted was: [...] Thanks for the description and the pointer to the Xilinx register description. I think I got to the bottom of it. The Xilinx PHY supports the GMII basic register set (registers 0, 1 and 15), but not the full extended register set (registers 2-14). Especially the MASTER-SLAVE Control and Status registers (IEEE 802.3 terminology) are missing. Bit 0 (Extended Capability) of the (non-Extended) Status register is correctly set to 0 to indicate this lack of support. Without the MASTER-SLAVE Status register, we can't tell whether the _peer_ also supports 1Gbps operation. Your patch ends up enabling it anyway, even for 10/100Mbps peers. Can you try the patch below, please? It restricts Extended Status processing to the PHYs that don't support the MASTER-SLAVE Control and Status registers, like the Xilinx one you use. The other PHYs should continue to work as before your patch. Tested successfully on Wandboard Quad. Sascha -- 8 -- From: Sascha Silbe t-ub...@infra-silbe.de Date: Fri, 19 Jul 2013 11:37:54 +0200 Subject: [PATCH] phy: fix 10/100Mbps operation on 1Gbps-capable links de1d786 [add support for Xilinx 1000BASE-X phy (GTX)] introduced a check for the extended status register in order to support 1Gbps-capable PHYs that don't have the 1000BASE-T registers. Since Extended Status only indicates what the PHY (i.e. the local side) is capable of, this broke communication with non-1Gbps peers. Only check the extended status if the 1000BASE-T registers are actually missing so we don't end up setting speed to 1Gbps even though the previous test (for the combination of local and peer support for 1Gbps) already indicated we can't do 1Gbps with the current peer. Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de --- drivers/net/phy/phy.c | 9 - 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c index 7c0eaec..f803834 100644 --- a/drivers/net/phy/phy.c +++ b/drivers/net/phy/phy.c @@ -333,7 +333,14 @@ int genphy_parse_link(struct phy_device *phydev) } else if (lpa LPA_10FULL) phydev-duplex = DUPLEX_FULL; - if (mii_reg BMSR_ESTATEN) + /* Extended status may indicate that the PHY supports +* 1000BASE-T/X even though the 1000BASE-T registers +* are missing. In this case we can't tell whether the +* peer also supports it, so we only check extended +* status if the 1000BASE-T registers are actually +* missing. + */ + if ((mii_reg BMSR_ESTATEN) !(mii_reg BMSR_ERCAP)) estatus = phy_read(phydev, MDIO_DEVAD_NONE, MII_ESTATUS); -- 1.8.3.2 pgpPbtL_rTpG9.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [RFC] Multiple binaries per U-Boot target
Albert ARIBAUD albert.u.b...@aribaud.net writes: Although, with recent proposals like the TPL one: http://permalink.gmane.org/gmane.comp.boot-loaders.u-boot/164432 ... I am toying with the idea of a more generic build mechanism which would allow a target to specify as many binaries as it needs, each with its own configuration. FWIW, I like the idea. Apart from streamlining the current code, it would allow building custom chains of bootloaders. One thing I could use for development would be a minimal stage that can load one of two normal / full-blown U-Boot versions, similar to dual BIOS support on modern x86 PCs. All devices I work with can be un-bricked reasonably easily, but for most of them it either requires manual interaction (e.g. the push-button for UART boot on CuBox) or prevents normal boots (e.g. removing the SD card on Wandboard so that it boots via USB _instead_ of from SD card). In addition, it would allow customising SPL features without having to introduce more special code. Sascha pgpzj8c2lbVgp.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] net: phy: Set SUPPORTED_1000baseX_Half flag in ESTATUS_1000_XHALF case
Fabio Estevam feste...@gmail.com writes: Commit de1d786e (add support for Xilinx 1000BASE-X phy (GTX)) introduced the checking for ESTATUS_1000_XHALF, but it incorrectly sets the SUPPORTED_1000baseX_Full flag in this case. Set the SUPPORTED_1000baseX_Half flag instead. Nice catch. Reviewed-By: Sascha Silbe t-ub...@infra-silbe.de No test done as my current test set-up is 100Base-T only. Sascha pgpK771OQifMU.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Ethernet support broken for Wandboard Quad on master
Hello,
ethernet support for Wandboard Quad seems to be broken on current master
(576aacdb):
U-Boot 2013.07-rc3-00021-g576aacd (Jul 18 2013 - 08:34:32)
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: POR
Board: Wandboard
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment
In:serial
Out: serial
Err: serial
Net: FEC [PRIME]
Warning: FEC using MAC address from net device
Hit any key to stop autoboot: 0
= setenv autoload no dhcp tftp ${fdt_addr}
/wandboard/imx6q-wandboard.dtb fdt addr ${fdt_addr} tftpboot ${loadaddr}
/wandboard/zImage setenv bootargs console=${console},
${baudrate} rootwait bootz ${loadaddr} - ${fdt_addr}
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
Retry count exceeded; starting again
[...]
It used to work as of e6c7f86f:
U-Boot 2013.04-00603-ge6c7f86 (Jul 18 2013 - 08:42:04)
Re: [U-Boot] Ethernet support broken for Wandboard Quad on master
Sascha Silbe t-ub...@infra-silbe.de writes:
I've started a git bisect run (booting via USB OTG), but it's going to
take a while as git bisect is throwing lots of commits without Wandboard
Quad support at me and seems to be only narrowing down the commits one
by one rather than on a log-2 basis.
A slightly more refined approach (cherry-picking the Wandboard Quad
support patch each time the build fails) enabled git bisect to track the
breakage down to:
commit de1d786edf01035f60a87e1e0f917a4169dc6964
Author: Charles Coldwell coldw...@gmail.com
Date: Thu Feb 21 08:25:52 2013 -0500
add support for Xilinx 1000BASE-X phy (GTX)
commit 39695029bc15041c809df3db4ba19bd729c447fa
Author: Charles Coldwell coldw...@ll.mit.edu
Date: Tue Feb 19 08:27:33 2013 -0500
Changes to support the Xilinx 1000BASE-X phy (GTX/MGT)
Signed-off-by: Charles Coldwell coldw...@ll.mit.edu
:04 04 459dbd37eb25461cc71d6e59b91a4b4994dca297
ee62742c09ab981c458ee61a1c827ee6baefb08b M drivers
:04 04 f8ebebe7282a5a69ed50b1f4ed687f8e8fc6a9ce
ffd40f9c2a640f9aa74bbef92fc4a3e2925b04e0 M include
Reverting the commit fixes ethernet support on Wandboard Quad.
Charles, do you have any idea why your commit breaks ethernet support on
Wandboard Quad? This is what I'm seeing:
U-Boot 2013.07-rc3-00021-g576aacd (Jul 18 2013 - 08:34:32)
CPU: Freescale i.MX6Q rev1.2 at 792 MHz
Reset cause: POR
Board: Wandboard
DRAM: 2 GiB
MMC: FSL_SDHC: 0, FSL_SDHC: 1
*** Warning - bad CRC, using default environment
In:serial
Out: serial
Err: serial
Net: FEC [PRIME]
Warning: FEC using MAC address from net device
Hit any key to stop autoboot: 0
= setenv autoload no dhcp tftp ${fdt_addr}
/wandboard/imx6q-wandboard.dtb fdt addr ${fdt_addr} tftpboot ${loadaddr}
/wandboard/zImage setenv bootargs console=${console},
${baudrate} rootwait bootz ${loadaddr} - ${fdt_addr}
BOOTP broadcast 1
BOOTP broadcast 2
BOOTP broadcast 3
BOOTP broadcast 4
BOOTP broadcast 5
Re: [U-Boot] [PATCH] OpenRD: relocate environment to 640kB
Albert ARIBAUD albert.u.b...@aribaud.net writes: The situation has gotten better recently and U-Boot fits into the previous partition size of 384KiB again. So it isn't broken on OpenRD anymore and the above would seem like a good approach. How well does it fit again, and do you have any idea what caused the increase in size, and what caused the decrease? I had the same questions and tried a few buildman runs, but didn't get a clear picture. The size was going up and down for various slices of commits. With v2013.07-rc3, we are now at 376344B (≈ 96% of 384KiB) for openrd_ultimate when built on Debian Wheezy using gcc-4.7-arm-linux-gnueabi from Emdebian. Is there an equivalent to CONFIG_SPL_MAX_SIZE for the regular U-Boot? Detecting the overlap at build time would prevent bricking the device using saveenv at run time. As an additional benefit, commits that push the size beyond the limit would also show up in buildman reports as build failures. Sascha pgpBUpjog_PVY.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] usb: ehci-marvell: use structs for registers
Use structs instead of computing offsets for accessing individual
registers. The base address of the USB controller is still an offset
defined in SoC headers as it can differ between SoCs.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
Tested on CuBox Pro only.
drivers/usb/host/ehci-marvell.c | 48 +
1 file changed, 34 insertions(+), 14 deletions(-)
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 2b73e4a..e4d6881 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -36,17 +36,35 @@
DECLARE_GLOBAL_DATA_PTR;
-#define rdl(off) readl(MVUSB0_BASE + (off))
-#define wrl(off, val) writel((val), MVUSB0_BASE + (off))
-
-#define USB_WINDOW_CTRL(i) (0x320 + ((i) 4))
-#define USB_WINDOW_BASE(i) (0x324 + ((i) 4))
#define USB_TARGET_DRAM0x0
+/* USB 2.0 Bridge Address Decoding registers */
+struct mvusb_bad_window_regs {
+ u32 control;
+ u32 base;
+ u32 reserved[2];
+};
+
+struct mvusb_bridge_regs {
+ u32 bridge_control;
+ u32 reserved1[3];
+ u32 int_cause; /* Bridge Interrupt Cause Register */
+ u32 int_mask; /* Bridge Interrupt Mask Register */
+ u32 reserved2;
+ u32 error_addr; /* Bridge Error Address Register */
+ struct mvusb_bad_window_regs window[4];
+};
+
+struct mvusb_regs {
+ u32 unused1[0x40];
+ u32 ehci_regs[0x80];
+ struct mvusb_bridge_regs bridge;
+};
+
/*
* USB 2.0 Bridge Address Decoding registers setup
*/
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(struct mvusb_regs *usb_base)
{
int i;
u32 size, base, attrib;
@@ -75,14 +93,15 @@ static void usb_brg_adrdec_setup(void)
size = gd-bd-bi_dram[i].size;
base = gd-bd-bi_dram[i].start;
- if ((size) (attrib))
- wrl(USB_WINDOW_CTRL(i),
- MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
- attrib, MVCPU_WIN_ENABLE));
+ if (size attrib)
+ writel(MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+ attrib, MVCPU_WIN_ENABLE),
+ usb_base-bridge.window[i].control);
else
- wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+ writel(MVCPU_WIN_DISABLE,
+ usb_base-bridge.window[i].control);
- wrl(USB_WINDOW_BASE(i), base);
+ writel(base, usb_base-bridge.window[i].base);
}
}
@@ -92,9 +111,10 @@ static void usb_brg_adrdec_setup(void)
*/
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- usb_brg_adrdec_setup();
+ struct mvusb_regs *usb_base = (struct mvusb_regs *)MVUSB0_BASE;
- *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+ usb_brg_adrdec_setup(usb_base);
+ *hccr = (struct ehci_hccr *)(usb_base-ehci_regs);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
--
1.8.2.1
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Re: [U-Boot] [PATCH v5 2/8] usb: ehci-marvell: add support for second USB controller
Dear Wolfgang Denk, Wolfgang Denk w...@denx.de writes: -#define rdl(off)readl(MVUSB0_BASE + (off)) -#define wrl(off, val) writel((val), MVUSB0_BASE + (off)) +#define rdl(base, off) readl((base) + (off)) +#define wrl(base, off, val) writel((val), (base) + (off)) Instead of extending this, can we eventually clean this up and use C structs instead? U-Boot does not allow device accesses through a based plus offset notation. Thanks for the review. I've given the clean-up a stab today, as a separate patch that the CuBox support series can build on. u32 size, base, attrib; +#ifdef MVUSB1_BASE +u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE; +#else +u32 usb_base = MVUSB0_BASE; +#endif Can we please also avoid this #ifdef's ? Eventually you can use something like base_0 + index * sizeof(struct usb_something) ? The two USB host controllers on Dove are separate entities at different base offsets (0x5 vs. 0x51000). We could fill up the register struct to have a size of 0x1000, but then the next SoC to be supported could come up with a different offset. Sascha ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] OpenRD: relocate environment to 640kB
Hello Albert, hello Tom, Albert ARIBAUD albert.u.b...@aribaud.net writes: [Move environment to account for increase in U-Boot size] This patch is for 2013.10, not 2013.07, but I prefer raising the issue as early as possible. If there is no way to make things smoother, then I think the 2013.10 release notes should contain a red, blinking, paragraph about this. I would *hate* it if people were not warned and given a method to port their current environment setting over. Possibly even, the 2013.07 could have a warning about the change to come, so that people have a better chance yet to prepare for the change. The situation has gotten better recently and U-Boot fits into the previous partition size of 384KiB again. So it isn't broken on OpenRD anymore and the above would seem like a good approach. Where are the U-Boot Release Notes located? Who is responsible for editing them? Sascha pgp7TqeKwcqSm.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver
Sebastian Hesselbarth sebastian.hesselba...@gmail.com writes: Either orion_spi as it was named originally, or mv_spi as Prafulla suggested. Then move mpp (pinctrl) from kirkwood_spi to corresponding boards, switch to orion_/mv_spi, and remove kirkwood_spi. I suggest orion_spi, but Prafulla had his word so it should be mv_spi I guess. I've given it a try and modified the Kirkwood GPIO and SPI drivers rather than duplicating their code. As I neither know the Dove SoCs nor have any hardware using them, I don't feel comfortable merging this with any existing orion code. For similar reasons and also for a lack of time I've left the MPP support code in place, just protected with CONFIG_KIRKWOOD. As for the naming: there's already a GPIO driver called mvgpio that looks quite different from the Kirkwood / Dove one. Naming the latter one mv_gpio would work for the build tools, but needlessly cause confusion to developers. Therefore I chose to keep the current names of the Kirkwood drivers (kw_gpio, kirkwood_spi). If anyone has a better suggestion, I'm happy to change the names. Sebastian, does the resulting code still match your intentions or would you like me to remove your Signed-off-by from those two patches when posting the updated patch series? Sascha pgpc0RNEsvCFC.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver
Hello Jagan, Jagan Teki jagannadh.t...@gmail.com writes: Looks ok to me as per coding style after a quick look. Thanks for the review. [...] Done use the below tag code instead go for spi_alloc_slave() see the sample code on drivers/spi/exynos_spi.c --- TAG+ + slave = malloc(sizeof(struct spi_slave)); + if (!slave) + return NULL; + + slave-bus = bus; + slave-cs = cs; + - TAG- That's going to be fixed in the next version which builds directly on kirkwood_spi (rather than duplicating it), which already uses spi_alloc_slave(). +__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave) Why your using __attribute__((weak)) here, may be use to pre-load the symbol library but what is the use case here? That's coming from kirkwood_spi. The Keymile boards apparently use it to select between NAND and SPI flash (see board/keymile/km_arm/km_arm.c). Sascha pgpRDasJW0Jm_.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver
Sebastian Hesselbarth sebastian.hesselba...@gmail.com writes: [...] I was under the impression that you resent the patches because you have a CuBox you want to get supported. Exactly. I'd like to see support for CuBox enter mainline U-Boot. However, there's also a limit to the amount of time I can afford to spend on it (both per week and in total). TBH, I would have hoped the _vendor_ (SolidRun) would take a more active role in this. For that reason I'm now going to evaluate a Wandboard Quad, where more effort seems to get spent on upstreaming (not to mention that the schematics are available, which makes working on board support a lot easier). When I ordered the CuBox Pro, the then-existing Wandboard variants (Solo and DualLite) lacked SATA support, but the Quad meets my requirements. Naming was the main discussion of this patch set back then, there have been some ??? on the mpp stuff. I suggested several times not to use mv as I knew that Marvell PXA also uses mv as prefix all over. The PXA SPI controller is based on different IP. Unfortunately PXA naming is not consitent over SoCs, Dove is also nick-named PXA510 sometimes. Actually, we are merging Orion SoCs and Armada 370/XP to mach-mvebu - so the best name would be mvebu_spi as the spi controller is also in Armada 370/XP. You're confusing me even more than I already was. :) It's probably best to leave this reorganisation to someone else who better knows the relationships between the several SoC families from Marvell. [...] Uhm, did you forget to send code? No, I was holding back until I knew whether you still feel comfortable being associated with the patches. I'll send them out now. I will not likely get back to Dove support on u-boot. I cannot really re-test on Kirkwood and it just takes to long to get feedback. I suggest to remove my Signed-off-by and especially the MAINTAINERS entry. OK, will do. Sorry you feel that way. Sascha pgpVKHVR2sElb.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Fix ext2/ext4 filesystem accesses beyond 2TiB
Frederic Leroy fr...@starox.org writes:
[...]
disk/part_efi.c| 4 ++--
While testing the CuBox patches using buildman, I noticed a warning in
disk/part_iso.c. The following patch should fix it:
diff --git a/disk/part_iso.c b/disk/part_iso.c
index cc323b0..e15e1b9 100644
--- a/disk/part_iso.c
+++ b/disk/part_iso.c
@@ -249,7 +249,7 @@ void print_part_iso(block_dev_desc_t * dev_desc)
printf(Part Start Sect x Size Type\n);
i=0;
do {
- printf ( %2d %8ld %8ld %6ld %.32s\n,
+ printf ( %2d LBAFu LBAFu %6ld %.32s\n,
i, info.start, info.size, info.blksz, info.type);
i++;
} while (get_partition_info_iso_verb(dev_desc,i,info,0)!=-1);
Sascha
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[U-Boot] [PATCH v5 0/8] Add Marvell Dove and SolidRun CuBox support
Changes from v4: - some patches got included in master, so they've been dropped from the series - removed Sebastian Hesselbarth's Signed-off-by and MAINTAINERS entry on his request - modified Kirkwood GPIO and SPI drivers rather than duplicating them This version has only been tested (lightly) on CuBox Pro, not on OpenRD (Kirkwood). The latter box is in production use, so I'd like to know whether the current approach is acceptable before I spend considerable time on testing. Sascha Silbe (8): ARM: dove: add support for Marvell Dove SoC usb: ehci-marvell: add support for second USB controller GPIO: add Dove support to Kirkwood GPIO driver MMC: sdhci: Add support for dove sdhci SPI: add Dove support to Kirkwood SPI driver block: mvsata: add dove include NET: mvgbe: avoid unused variable warning when used without phylib support Boards: Add support for SolidRun CuBox arch/arm/cpu/armv7/dove/Makefile | 49 arch/arm/cpu/armv7/dove/cpu.c | 274 ++ arch/arm/cpu/armv7/dove/dram.c | 117 arch/arm/cpu/armv7/dove/lowlevel_init.S| 83 ++ arch/arm/cpu/armv7/dove/mpp.c | 318 + arch/arm/cpu/armv7/dove/timer.c| 176 arch/arm/cpu/armv7/dove/usb.c | 101 +++ arch/arm/include/asm/arch-dove/config.h| 153 ++ arch/arm/include/asm/arch-dove/cpu.h | 204 + arch/arm/include/asm/arch-dove/dove.h | 98 +++ arch/arm/include/asm/arch-dove/gpio.h | 35 +++ arch/arm/include/asm/arch-dove/mmc.h | 27 ++ arch/arm/include/asm/arch-dove/mpp.h | 283 ++ arch/arm/include/asm/arch-dove/usb.h | 27 ++ arch/arm/include/asm/arch-kirkwood/gpio.h | 42 +-- arch/arm/include/asm/arch-kirkwood/spi.h | 27 -- board/solidrun/cubox/Makefile | 45 +++ board/solidrun/cubox/cubox.c | 142 + board/solidrun/cubox/kwbimage-spi-1gb.cfg | 76 + board/solidrun/cubox/kwbimage-spi-2gb.cfg | 76 + board/solidrun/cubox/kwbimage-uart.cfg | 76 + boards.cfg | 3 + drivers/block/mvsata_ide.c | 2 + drivers/gpio/kw_gpio.c | 43 +-- drivers/mmc/Makefile | 1 + drivers/mmc/dove_sdhci.c | 101 +++ drivers/net/mvgbe.c| 5 +- drivers/spi/kirkwood_spi.c | 47 ++- drivers/usb/host/ehci-marvell.c| 35 ++- include/configs/cubox.h| 185 .../asm/arch-kirkwood/gpio.h = include/kw_gpio.h | 43 ++- 31 files changed, 2769 insertions(+), 125 deletions(-) create mode 100644 arch/arm/cpu/armv7/dove/Makefile create mode 100644 arch/arm/cpu/armv7/dove/cpu.c create mode 100644 arch/arm/cpu/armv7/dove/dram.c create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/dove/mpp.c create mode 100644 arch/arm/cpu/armv7/dove/timer.c create mode 100644 arch/arm/cpu/armv7/dove/usb.c create mode 100644 arch/arm/include/asm/arch-dove/config.h create mode 100644 arch/arm/include/asm/arch-dove/cpu.h create mode 100644 arch/arm/include/asm/arch-dove/dove.h create mode 100644 arch/arm/include/asm/arch-dove/gpio.h create mode 100644 arch/arm/include/asm/arch-dove/mmc.h create mode 100644 arch/arm/include/asm/arch-dove/mpp.h create mode 100644 arch/arm/include/asm/arch-dove/usb.h create mode 100644 board/solidrun/cubox/Makefile create mode 100644 board/solidrun/cubox/cubox.c create mode 100644 board/solidrun/cubox/kwbimage-spi-1gb.cfg create mode 100644 board/solidrun/cubox/kwbimage-spi-2gb.cfg create mode 100644 board/solidrun/cubox/kwbimage-uart.cfg create mode 100644 drivers/mmc/dove_sdhci.c create mode 100644 include/configs/cubox.h copy arch/arm/include/asm/arch-kirkwood/gpio.h = include/kw_gpio.h (60%) -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 5/8] SPI: add Dove support to Kirkwood SPI driver
The SPI support on Dove is very similar to that on Kirkwood (and
possibly orion5x as well). Instead of duplicating the code, we tweak
the Kirkwood driver so it works for Dove, too.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v4-v5: Modify Kirkwood driver rather than duplicating it.
The patch description might do with slightly more detail, but I'd
like some feedback on the approach first. The patch itself should be
pretty self-explanatory.
arch/arm/include/asm/arch-kirkwood/spi.h | 27 --
drivers/spi/kirkwood_spi.c | 47 +---
2 files changed, 43 insertions(+), 31 deletions(-)
diff --git a/arch/arm/include/asm/arch-kirkwood/spi.h
b/arch/arm/include/asm/arch-kirkwood/spi.h
index 113f258..4145f62 100644
--- a/arch/arm/include/asm/arch-kirkwood/spi.h
+++ b/arch/arm/include/asm/arch-kirkwood/spi.h
@@ -27,16 +27,6 @@
#ifndef __KW_SPI_H__
#define __KW_SPI_H__
-/* SPI Registers on kirkwood SOC */
-struct kwspi_registers {
- u32 ctrl; /* 0x10600 */
- u32 cfg;/* 0x10604 */
- u32 dout; /* 0x10608 */
- u32 din;/* 0x1060c */
- u32 irq_cause; /* 0x10610 */
- u32 irq_mask; /* 0x10614 */
-};
-
/* They are used to define CONFIG_SYS_KW_SPI_MPP
* each of the below #defines selects which mpp is
* configured for each SPI signal in spi_claim_bus
@@ -48,21 +38,4 @@ struct kwspi_registers {
#define SCK_MPP10 (1 1)
#define MISO_MPP11 (1 2)
-#define KWSPI_CLKPRESCL_MASK 0x1f
-#define KWSPI_CLKPRESCL_MIN0x12
-#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */
-#define KWSPI_SMEMRDY (1 1) /* SerMem Data xfer ready */
-#define KWSPI_IRQUNMASK1 /* unmask SPI interrupt */
-#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
-#define KWSPI_SMEMRDIRQ1 /* SerMem data xfer ready irq */
-#define KWSPI_XFERLEN_1BYTE0
-#define KWSPI_XFERLEN_2BYTE(1 5)
-#define KWSPI_XFERLEN_MASK (1 5)
-#define KWSPI_ADRLEN_1BYTE 0
-#define KWSPI_ADRLEN_2BYTE 1 8
-#define KWSPI_ADRLEN_3BYTE 2 8
-#define KWSPI_ADRLEN_4BYTE 3 8
-#define KWSPI_ADRLEN_MASK 3 8
-#define KWSPI_TIMEOUT 1
-
#endif /* __KW_SPI_H__ */
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index caa91e3..4e4c814 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -28,23 +28,58 @@
#include malloc.h
#include spi.h
#include asm/io.h
-#include asm/arch/kirkwood.h
-#include asm/arch/spi.h
-#include asm/arch/mpp.h
+#include asm/arch/config.h
-static struct kwspi_registers *spireg = (struct kwspi_registers *)KW_SPI_BASE;
+/* SPI Registers on Dove/Kirkwood SOC */
+struct kwspi_registers {
+ u32 ctrl; /* 0x00 */
+ u32 cfg;/* 0x04 */
+ u32 dout; /* 0x08 */
+ u32 din;/* 0x0c */
+ u32 irq_cause; /* 0x10 */
+ u32 irq_mask; /* 0x14 */
+};
+#if defined(CONFIG_KIRKWOOD)
+static struct kwspi_registers *spireg =
+(struct kwspi_registers *)KW_SPI_BASE;
+#elif defined(CONFIG_DOVE)
+static struct kwspi_registers *spireg =
+(struct kwspi_registers *)DOVE_SPI_BASE;
+#endif
+
+#define KWSPI_CLKPRESCL_MASK 0x1f
+#define KWSPI_CLKPRESCL_MIN0x12
+#define KWSPI_CSN_ACT 1 /* Activates serial memory interface */
+#define KWSPI_SMEMRDY (1 1) /* SerMem Data xfer ready */
+#define KWSPI_IRQUNMASK1 /* unmask SPI interrupt */
+#define KWSPI_IRQMASK 0 /* mask SPI interrupt */
+#define KWSPI_SMEMRDIRQ1 /* SerMem data xfer ready irq */
+#define KWSPI_XFERLEN_1BYTE0
+#define KWSPI_XFERLEN_2BYTE(1 5)
+#define KWSPI_XFERLEN_MASK (1 5)
+#define KWSPI_ADRLEN_1BYTE 0
+#define KWSPI_ADRLEN_2BYTE (1 8)
+#define KWSPI_ADRLEN_3BYTE (2 8)
+#define KWSPI_ADRLEN_4BYTE (3 8)
+#define KWSPI_ADRLEN_MASK (3 8)
+#define KWSPI_TIMEOUT 1
+
+#if defined(CONFIG_KIRKWOOD)
u32 cs_spi_mpp_back[2];
+#endif
struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
unsigned int max_hz, unsigned int mode)
{
struct spi_slave *slave;
u32 data;
+#if defined(CONFIG_KIRKWOOD)
static const u32 kwspi_mpp_config[2][2] = {
{ MPP0_SPI_SCn, 0 }, /* if cs == 0 */
{ MPP7_SPI_SCn, 0 } /* if cs != 0 */
};
+#endif
if (!spi_cs_is_valid(bus, cs))
return NULL;
@@ -67,15 +102,19 @@ struct spi_slave *spi_setup_slave(unsigned int bus,
unsigned int cs,
writel(KWSPI_SMEMRDIRQ, spireg-irq_cause);
writel(KWSPI_IRQMASK, spireg-irq_mask);
+#if defined(CONFIG_KIRKWOOD)
/* program mpp registers to select SPI_CSn */
kirkwood_mpp_conf(kwspi_mpp_config[cs ? 1 : 0], cs_spi_mpp_back);
+#endif
return slave;
}
void spi_free_slave(struct spi_slave *slave)
{
+#if defined
[U-Boot] [PATCH v5 3/8] GPIO: add Dove support to Kirkwood GPIO driver
The GPIO support of Dove is very similar to that on Kirkwood (and
possibly orion5x as well). Instead of duplicating the code, we tweak
the Kirkwood driver so it works for Dove, too.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v4-v5: Modify Kirkwood driver rather than duplicating it.
The patch description might do with slightly more detail, but I'd
like some feedback on the approach first. The patch itself should be
pretty self-explanatory.
arch/arm/include/asm/arch-kirkwood/gpio.h | 42 ++---
drivers/gpio/kw_gpio.c | 43 +++---
.../asm/arch-kirkwood/gpio.h = include/kw_gpio.h | 43 +++---
3 files changed, 47 insertions(+), 81 deletions(-)
diff --git a/arch/arm/include/asm/arch-kirkwood/gpio.h
b/arch/arm/include/asm/arch-kirkwood/gpio.h
index cd1bc00..8c8f239 100644
--- a/arch/arm/include/asm/arch-kirkwood/gpio.h
+++ b/arch/arm/include/asm/arch-kirkwood/gpio.h
@@ -20,46 +20,12 @@
* MA 02110-1301 USA
*/
-/*
- * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
- * Removed kernel level irq handling. Took some macros from kernel to
- * allow build.
- *
- * Dieter Kiermaier dk-arm-li...@gmx.de
- */
+#ifndef __ARCH_KIRKWOOD_GPIO_H
+#define __ARCH_KIRKWOOD_GPIO_H
-#ifndef __KIRKWOOD_GPIO_H
-#define __KIRKWOOD_GPIO_H
-
-/* got from kernel include/linux/bitops.h */
-#define BITS_PER_BYTE 8
-#define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
+#include kw_gpio.h
#define GPIO_MAX 50
-#define GPIO_OFF(pin) (((pin) 5) ? 0x0040 : 0x)
-#define GPIO_OUT(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x00)
-#define GPIO_IO_CONF(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x04)
-#define GPIO_BLINK_EN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x08)
-#define GPIO_IN_POL(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x0c)
-#define GPIO_DATA_IN(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x10)
-#define GPIO_EDGE_CAUSE(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x14)
-#define GPIO_EDGE_MASK(pin)(KW_GPIO0_BASE + GPIO_OFF(pin) + 0x18)
-#define GPIO_LEVEL_MASK(pin) (KW_GPIO0_BASE + GPIO_OFF(pin) + 0x1c)
-
-/*
- * Kirkwood-specific GPIO API
- */
-
-void kw_gpio_set_valid(unsigned pin, int mode);
-int kw_gpio_is_valid(unsigned pin, int mode);
-int kw_gpio_direction_input(unsigned pin);
-int kw_gpio_direction_output(unsigned pin, int value);
-int kw_gpio_get_value(unsigned pin);
-void kw_gpio_set_value(unsigned pin, int value);
-void kw_gpio_set_blink(unsigned pin, int blink);
-void kw_gpio_set_unused(unsigned pin);
-
-#define GPIO_INPUT_OK (1 0)
-#define GPIO_OUTPUT_OK (1 1)
+#define GPIO_BASE(pin) (((pin) 5) ? (KW_GPIO0_BASE + 0x0040) :
KW_GPIO0_BASE)
#endif
diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c
index 51a826d..d6fdb69 100644
--- a/drivers/gpio/kw_gpio.c
+++ b/drivers/gpio/kw_gpio.c
@@ -1,7 +1,11 @@
/*
- * arch/arm/plat-orion/gpio.c
+ * Marvell Dove and Kirkwood SoC GPIO handling
*
- * Marvell Orion SoC GPIO handling.
+ * Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ *
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed orion_gpiochip struct and kernel level irq handling.
+ * Dieter Kiermaier dk-arm-li...@gmx.de
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,58 +26,54 @@
* MA 02110-1301 USA
*/
-/*
- * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
- * Removed orion_gpiochip struct and kernel level irq handling.
- *
- * Dieter Kiermaier dk-arm-li...@gmx.de
- */
-
#include common.h
#include asm/bitops.h
#include asm/io.h
-#include asm/arch/kirkwood.h
#include asm/arch/gpio.h
+#include kw_gpio.h
static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
void __set_direction(unsigned pin, int input)
{
+ u32 base = GPIO_BASE(pin);
u32 u;
- u = readl(GPIO_IO_CONF(pin));
+ u = readl(GPIO_IO_CONF(base));
if (input)
u |= 1 (pin 31);
else
u = ~(1 (pin 31));
- writel(u, GPIO_IO_CONF(pin));
+ writel(u, GPIO_IO_CONF(base));
- u = readl(GPIO_IO_CONF(pin));
+ u = readl(GPIO_IO_CONF(base));
}
void __set_level(unsigned pin, int high)
{
+ u32 base = GPIO_BASE(pin);
u32 u;
- u = readl(GPIO_OUT(pin));
+ u = readl(GPIO_OUT(base));
if (high)
u |= 1 (pin 31);
else
u = ~(1 (pin 31));
- writel(u, GPIO_OUT(pin));
+ writel(u, GPIO_OUT(base));
}
void __set_blinking(unsigned pin, int blink)
{
+ u32 base = GPIO_BASE(pin);
u32 u;
- u = readl(GPIO_BLINK_EN(pin));
+ u = readl(GPIO_BLINK_EN(base));
if (blink)
u |= 1 (pin 31);
else
u = ~(1
[U-Boot] [PATCH v5 4/8] MMC: sdhci: Add support for dove sdhci
This adds a driver for the sdhci controller found on Dove SoCs.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v4-v5: no changes
arch/arm/include/asm/arch-dove/mmc.h | 27 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/dove_sdhci.c | 101 +++
3 files changed, 129 insertions(+)
diff --git a/arch/arm/include/asm/arch-dove/mmc.h
b/arch/arm/include/asm/arch-dove/mmc.h
new file mode 100644
index 000..579396c
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/mmc.h
@@ -0,0 +1,27 @@
+/*
+ * Marvell Dove SoC SDHCI
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVEMMC_H
+#define _DOVEMMC_H
+
+int dove_sdhci_init(int num);
+#endif /* _DOVEMMC_H */
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index 24648a2..074af75 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -28,6 +28,7 @@ LIB := $(obj)libmmc.o
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+COBJS-$(CONFIG_DOVE_SDHCI) += dove_sdhci.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
COBJS-$(CONFIG_FTSDC010) += ftsdc010_mci.o
COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
diff --git a/drivers/mmc/dove_sdhci.c b/drivers/mmc/dove_sdhci.c
new file mode 100644
index 000..ac15fd7
--- /dev/null
+++ b/drivers/mmc/dove_sdhci.c
@@ -0,0 +1,101 @@
+/*
+ *
+ * Marvell Dove SDHCI driver
+ *
+ * Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ *
+ * Based on linux drivers/mmc/host/sdhci-dove.c
+ * by: Saeed Bishara sa...@marvell.com
+ * Mike Rapoport m...@compulab.co.il
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include sdhci.h
+#include asm/arch/dove.h
+
+static u16 dove_sdhci_readw(struct sdhci_host *host, int reg)
+{
+ u16 ret;
+
+ switch (reg) {
+ case SDHCI_HOST_VERSION:
+ case SDHCI_SLOT_INT_STATUS:
+ /* those registers don't exist */
+ return 0;
+ default:
+ ret = readw(host-ioaddr + reg);
+ }
+
+ return ret;
+}
+
+static u32 dove_sdhci_readl(struct sdhci_host *host, int reg)
+{
+ u32 ret;
+
+ switch (reg) {
+ case SDHCI_CAPABILITIES:
+ ret = readl(host-ioaddr + reg);
+ /* Mask the support for 3.0V */
+ ret = ~SDHCI_CAN_VDD_300;
+ break;
+ default:
+ ret = readl(host-ioaddr + reg);
+ }
+
+ return ret;
+}
+
+static struct sdhci_ops dove_sdhci_ops = {
+ .read_w = dove_sdhci_readw,
+ .read_l = dove_sdhci_readl,
+};
+
+static struct sdhci_host hosts[2] = {
+ {
+ .name = Dove SDHCI0,
+ .ioaddr = (void *)DOVE_SDIO0_BASE,
+ },
+ {
+ .name = Dove SDHCI1,
+ .ioaddr = (void *)DOVE_SDIO1_BASE,
+ },
+};
+
+int dove_sdhci_init(int num)
+{
+ struct sdhci_host *host;
+
+ if (num 0 || num 1)
+ return 1;
+
+ host = hosts[num];
+
+ if (host-version)
+ return 1;
+
+ host-quirks =
+ SDHCI_QUIRK_NO_HISPD_BIT |
+ SDHCI_QUIRK_BROKEN_R1B |
+ SDHCI_QUIRK_32BIT_DMA_ADDR;
+ host-version = SDHCI_SPEC_200;
+ host-ops = dove_sdhci_ops;
+
+ add_sdhci(host, 5000, 400);
+ return 0;
+}
--
1.8.2.1
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[U-Boot] [PATCH v5 2/8] usb: ehci-marvell: add support for second USB controller
From: Sascha Silbe sascha-...@silbe.org
Marvell 88AP510 (Armada 510, dove) has two separate USB
controllers. Use the index parameter that already gets passed in to
calculate the base address of the controller.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v4-v5: no changes
drivers/usb/host/ehci-marvell.c | 35 ---
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 2b73e4a..d2cf026 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -28,7 +28,9 @@
#include ehci.h
#include asm/arch/cpu.h
-#if defined(CONFIG_KIRKWOOD)
+#if defined(CONFIG_DOVE)
+#include asm/arch/dove.h
+#elif defined(CONFIG_KIRKWOOD)
#include asm/arch/kirkwood.h
#elif defined(CONFIG_ORION5X)
#include asm/arch/orion5x.h
@@ -36,8 +38,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define rdl(off) readl(MVUSB0_BASE + (off))
-#define wrl(off, val) writel((val), MVUSB0_BASE + (off))
+#define rdl(base, off) readl((base) + (off))
+#define wrl(base, off, val)writel((val), (base) + (off))
#define USB_WINDOW_CTRL(i) (0x320 + ((i) 4))
#define USB_WINDOW_BASE(i) (0x324 + ((i) 4))
@@ -46,10 +48,15 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* USB 2.0 Bridge Address Decoding registers setup
*/
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(int index)
{
int i;
u32 size, base, attrib;
+#ifdef MVUSB1_BASE
+ u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
+#else
+ u32 usb_base = MVUSB0_BASE;
+#endif
for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
@@ -76,13 +83,13 @@ static void usb_brg_adrdec_setup(void)
size = gd-bd-bi_dram[i].size;
base = gd-bd-bi_dram[i].start;
if ((size) (attrib))
- wrl(USB_WINDOW_CTRL(i),
- MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
- attrib, MVCPU_WIN_ENABLE));
+ wrl(usb_base, USB_WINDOW_CTRL(i),
+ MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+ attrib, MVCPU_WIN_ENABLE));
else
- wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+ wrl(usb_base, USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
- wrl(USB_WINDOW_BASE(i), base);
+ wrl(usb_base, USB_WINDOW_BASE(i), base);
}
}
@@ -92,9 +99,15 @@ static void usb_brg_adrdec_setup(void)
*/
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- usb_brg_adrdec_setup();
+#ifdef MVUSB1_BASE
+ u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
+#else
+ u32 usb_base = MVUSB0_BASE;
+#endif
- *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+ usb_brg_adrdec_setup(index);
+
+ *hccr = (struct ehci_hccr *)(usb_base + 0x100);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
--
1.8.2.1
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[U-Boot] [PATCH v5 8/8] Boards: Add support for SolidRun CuBox
With latest support for Marvell Dove SoC, add the SolidRun CuBox as
the very first board with that SoC.
Three variants are provided:
1. A regular SPI boot image for CuBox (1GiB)
The CuBox (without Pro) has 1GiB of memory.
2. A regular SPI boot image for CuBox Pro (2GiB)
The CuBox Pro has 2GiB of memory. Because larger SDRAM chips are
used, tRFC needs to be longer than on the 1GiB variant.
3. A UART boot image for both CuBox and CuBox Pro
This is just for recovery purposes, so the smaller memory map (on
CuBox Pro) and slower SDRAM access (on CuBox) doesn't
matter. Having a single image that works on both hardware variants
is quite convenient during recovery.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v4-v5:
- dropped MAINTAINERS entry on Sebastian Hesselbarth's request
- some adjustments to account for GPIO and SPI driver changes
board/solidrun/cubox/Makefile | 45
board/solidrun/cubox/cubox.c | 142 +++
board/solidrun/cubox/kwbimage-spi-1gb.cfg | 76
board/solidrun/cubox/kwbimage-spi-2gb.cfg | 76
board/solidrun/cubox/kwbimage-uart.cfg| 76
boards.cfg| 3 +
include/configs/cubox.h | 185 ++
7 files changed, 603 insertions(+)
diff --git a/board/solidrun/cubox/Makefile b/board/solidrun/cubox/Makefile
new file mode 100644
index 000..c771d72
--- /dev/null
+++ b/board/solidrun/cubox/Makefile
@@ -0,0 +1,45 @@
+#
+# SolidRun CuBox Makefile
+#
+# Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := cubox.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB):$(obj).depend $(OBJS) $(SOBJS)
+ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/solidrun/cubox/cubox.c b/board/solidrun/cubox/cubox.c
new file mode 100644
index 000..7d265e4
--- /dev/null
+++ b/board/solidrun/cubox/cubox.c
@@ -0,0 +1,142 @@
+/*
+ * SolidRun CuBox board support
+ *
+ * Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include miiphy.h
+#include asm/arch/cpu.h
+#include asm/arch/dove.h
+#include asm/arch/mpp.h
+#include asm/arch/mmc.h
+#include kw_gpio.h
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static u16 mpp_config[] = {
+ MPP0_GPIO,
+ MPP1_GPIO, /* USB power enable */
+ MPP2_GPIO, /* USB over-current indication */
+ MPP3_GPIO, /* micro button beneath eSATA port */
+ MPP4_GPIO,
+ MPP5_GPIO,
+ MPP6_GPIO,
+ MPP7_GPIO,
+
+ MPP8_GPIO,
+ MPP9_GPIO,
+ MPP10_GPIO,
+ MPP11_GPIO,
+ MPP12_GPIO, /* SDIO0 card detect */
+ MPP13_AUDIO1_EXTCLK, /* Si5351a audio clock output */
+ MPP14_GPIO,
+ MPP15_GPIO,
+
+ MPP16_GPIO,
+ MPP17_GPIO,
+ MPP18_GPIO, /* Red front LED */
+ MPP19_UART3_RXD, /* IR sensor */
+ MPP20_GPIO,
+ MPP21_GPIO,
+ MPP22_GPIO
[U-Boot] [PATCH v5 6/8] block: mvsata: add dove include
Dove SoC also uses mvsata, therefore add a SoC specific include to allow to reuse the mvsata ide driver. Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de Acked-by: Prafulla Wadaskar prafu...@marvell.com --- v4-v5: no changes drivers/block/mvsata_ide.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 42c177f..500f13c 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -29,6 +29,8 @@ #include asm/arch/orion5x.h #elif defined(CONFIG_KIRKWOOD) #include asm/arch/kirkwood.h +#elif defined(CONFIG_DOVE) +#include asm/arch/dove.h #endif /* SATA port registers */ -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v5 7/8] NET: mvgbe: avoid unused variable warning when used without phylib support
Avoid a recently introduced unused variable warning for boards that
use mvgbe but not phylib.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v4-v5: Most of the original patch (NET: mvgbe: add phylib support)
was merged to master, only this clean-up remains.
drivers/net/mvgbe.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 319fe8a..e19696a 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -436,8 +436,9 @@ static int mvgbe_init(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe-regs;
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
- defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
+ !defined(CONFIG_PHYLIB)\
+ defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
--
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Re: [U-Boot] [PATCH] Fix block device accesses beyond 2TiB
Frédéric Leroy fr...@starox.org writes: Le 22/06/2013 17:31, Albert ARIBAUD a écrit : However, the patch issues no warning at compile time and fixes the ide block layer. OK -- anyone has any idea why Sasha's patch fixes reading from far blocks but does not fix ex2ls? Frankly, I'd prefer it if the patch fixed it all. :) Thanks to Frédéric for testing and to Marek for the quick review. [...] Ext2 code use unsigned long for the partition offset and int for sector computation. I will try to fix it, and try to test the other fs ( ext4, xfs, fat). I would see one patch for the ide code, and one or more patch for the fs code. IMHO, Sascha patch can be applied as. While the IDE layer fix isn't enough for most use cases (storage devices in the TiB range are usually used with file systems rather than raw partitions), I agree that the file system level fixes should happen in separate patches. Tom, do you consider this a bug fix worth landing in v2013.07 or an intrusive change (possibly even a feature as it never worked before) that would go into v2013.10 instead? If it's considered a bug fix, it would probably be a good idea to land my patch ASAP rather than waiting for the FS level fixes. In the feature case we can wait and include both IDE and FS fixes in a single patch set once someone gets around to do the FS fixes. Sascha pgphRl9hgGvO0.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] Fix ext2/ext4 filesystem accesses beyond 2TiB
Frederic Leroy fr...@starox.org writes: From: Frédéric Leroy fr...@starox.org With CONFIG_SYS_64BIT_LBA, lbaint_t gets defined as a 64-bit type, which is required to represent block numbers for storage devices that exceed 2TiB (the block size usually is 512B), e.g. recent hard drives We now use lbaint_t for partition offset to reflect the lbaint_t change, and access partitions beyond or crossing the 2.1TiB limit. This required changes to signature of ext4fs_devread(), and type of all variables relatives to block sector. ext2/ext4 fs uses logical block represented by a 32 bit value. Logical block is a multiple of device block sector. To avoid overflow problem when calling ext4fs_devread(), we need to cast the sector parameter. Thanks for the patch! Reading a file on an ext4 file system located on a partition starting beyond the 2TiB limit on a SATA hard disk attached to a CuBox Pro works fine now. Tested-by: Sascha Silbe t-ub...@infra-silbe.de You'll probably have to add your Signed-off-by before your patch can be merged. A minor nitpick: The limit is at 2TiB (2^41 Bytes), which is roughly 2.2TB (2.2 * 10^12 Bytes). Sascha pgpQm5lQFRpec.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] Fix block device accesses beyond 2TiB
With CONFIG_SYS_64BIT_LBA, lbaint_t gets defined as a 64-bit type,
which is required to represent block numbers for storage devices that
exceed 2TiB (the block size usually is 512B), e.g. recent hard drives.
For some obscure reason, the current U-Boot code uses lbaint_t for the
number of blocks to read (a rather optimistic estimation of how RAM
sizes will evolve), but not for the starting address. Trying to access
blocks beyond the 2TiB boundary will simply wrap around and read a
block within the 0..2TiB range.
We now use lbaint_t for block start addresses, too. This required
changes to all block drivers as the signature of block_read(),
block_write() and block_erase() in block_dev_desc_t changed.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
Functionality tested on CuBox Pro with a Western Digital WD30EFRX hard
disk (3TB). Build tested for all arm boards and sandbox.
Testing on other boards and architectures would be appreciated.
Fixes for typos, style errors etc. are explicitly out of scope for
this patch, even those checkpatch complains about because they appear
on or near lines touched by the patch. They are unrelated to the issue
at hand and can be fixed up later. Mixing in unrelated changes would
just make harder to revert any problematic change.
common/cmd_ide.c | 14 +++---
common/usb_storage.c | 8
drivers/mmc/mmc.c| 17 +
include/ide.h| 5 +++--
include/part.h | 6 +++---
5 files changed, 26 insertions(+), 24 deletions(-)
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index 78b4aa7..59e95df 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -830,7 +830,7 @@ static void ide_ident(block_dev_desc_t *dev_desc)
/* - */
-ulong ide_read(int device, ulong blknr, lbaint_t blkcnt, void *buffer)
+ulong ide_read(int device, lbaint_t blknr, lbaint_t blkcnt, void *buffer)
{
ulong n = 0;
unsigned char c;
@@ -844,7 +844,7 @@ ulong ide_read(int device, ulong blknr, lbaint_t blkcnt,
void *buffer)
lba48 = 1;
}
#endif
- debug(ide_read dev %d start %lX, blocks LBAF buffer at %lX\n,
+ debug(ide_read dev %d start LBAF , blocks LBAF buffer at %lX\n,
device, blknr, blkcnt, (ulong) buffer);
ide_led(DEVICE_LED(device), 1); /* LED on */
@@ -934,8 +934,8 @@ ulong ide_read(int device, ulong blknr, lbaint_t blkcnt,
void *buffer)
if ((c (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
ATA_STAT_DRQ) {
- printf(Error (no IRQ) dev %d blk %ld: status %#02x\n,
- device, blknr, c);
+ printf(Error (no IRQ) dev %d blk LBAF : status
+ %#02x\n, device, blknr, c);
break;
}
@@ -954,7 +954,7 @@ IDE_READ_E:
/* - */
-ulong ide_write(int device, ulong blknr, lbaint_t blkcnt, const void *buffer)
+ulong ide_write(int device, lbaint_t blknr, lbaint_t blkcnt, const void
*buffer)
{
ulong n = 0;
unsigned char c;
@@ -1022,8 +1022,8 @@ ulong ide_write(int device, ulong blknr, lbaint_t blkcnt,
const void *buffer)
if ((c (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR)) !=
ATA_STAT_DRQ) {
- printf(Error (no IRQ) dev %d blk %ld: status %#02x\n,
- device, blknr, c);
+ printf(Error (no IRQ) dev %d blk LBAF : status
+ %#02x\n, device, blknr, c);
goto WR_OUT;
}
diff --git a/common/usb_storage.c b/common/usb_storage.c
index 457970f..4599d03 100644
--- a/common/usb_storage.c
+++ b/common/usb_storage.c
@@ -170,9 +170,9 @@ int usb_stor_get_info(struct usb_device *dev, struct
us_data *us,
block_dev_desc_t *dev_desc);
int usb_storage_probe(struct usb_device *dev, unsigned int ifnum,
struct us_data *ss);
-unsigned long usb_stor_read(int device, unsigned long blknr,
+unsigned long usb_stor_read(int device, lbaint_t blknr,
lbaint_t blkcnt, void *buffer);
-unsigned long usb_stor_write(int device, unsigned long blknr,
+unsigned long usb_stor_write(int device, lbaint_t blknr,
lbaint_t blkcnt, const void *buffer);
struct usb_device * usb_get_dev_index(int index);
void uhci_show_temp_int_td(void);
@@ -1054,7 +1054,7 @@ static void usb_bin_fixup(struct usb_device_descriptor
descriptor,
}
#endif /* CONFIG_USB_BIN_FIXUP */
-unsigned long usb_stor_read(int device, unsigned long blknr,
+unsigned long usb_stor_read(int device, lbaint_t blknr,
lbaint_t blkcnt, void *buffer)
{
lbaint_t start, blks;
@@ -1127,7 +1127,7 @@ retry_it
Re: [U-Boot] [PATCH] LaCie kirkwood boards: allow disk 2TB
Frédéric Leroy fr...@starox.org writes: I will convert every ide block number to 64 bit for disk and partitions. I guess CONFIG_LBA48 is also broken in common/cmd_ide.c : FWIW, I have a patch pending for this already. But it's necessarily pretty invasive and I'm not even sure yet that I've found all places that need to be adapted. It works fine on CuBox Pro and builds without warnings for all ARM boards and sandbox (or at least MAKEALL succeeds with -Werror added to a few places). Not sure whether I'll get around to working on it this weekend, but I'll try to at least post the patch tomorrow so others can test it. Sascha pgpfiODmqWheM.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 04/10] SPI: Add Orion SPI driver
Dear Jagan, Jagan Teki jagannadh.t...@gmail.com writes: Does this tested on hw, please re-base the tree and send the next version patch. Let me know if it ok to review under current tree. I'd appreciate a review of the latest patch [1,2]. There have been no changes in master to the files touched by the patch since I sent it. After rebasing the entire series on today's master (d6639d1) I've successfully verified SPI flash functionality on CuBox Pro. Sascha [1] mid:1369593423-19763-6-git-send-email-t-ub...@infra-silbe.de [2] http://patchwork.ozlabs.org/patch/246468/ pgpWOycwgx9zs.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 04/10] SPI: Add Orion SPI driver
Dear Jagan, Jagan Teki jagannadh.t...@gmail.com writes: I'd appreciate a review of the latest patch [1,2]. [...] [1] mid:1369593423-19763-6-git-send-email-t-ub...@infra-silbe.de [2] http://patchwork.ozlabs.org/patch/246468/ Thank you, means this v4 is the latest one? http://patchwork.ozlabs.org/patch/246468/ Yes, it is. Sascha pgpgMrapTfTCb.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] OpenRD: relocate environment to 640kB
U-Boot has become slightly larger than where the environment sector was previously located. Saving the environment would brick the device. Relocate the environment to where it is with the stock (i.e. Marvell USP) U-Boot version. That should give plenty of room for U-Boot to grow, including local customisations. This obviously breaks compatibility with previous mainline versions of U-Boot. Users will need to back up the environment before an update and restore it afterwards, or manually copy it to the new address before the update. Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de --- include/configs/openrd.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/openrd.h b/include/configs/openrd.h index 53bafe1..ea7f9aa 100644 --- a/include/configs/openrd.h +++ b/include/configs/openrd.h @@ -90,8 +90,8 @@ * it has to be rounded to sector size */ #define CONFIG_ENV_SIZE0x2 /* 128k */ -#define CONFIG_ENV_ADDR0x6 -#define CONFIG_ENV_OFFSET 0x6 /* env starts here */ +#define CONFIG_ENV_ADDR0xa +#define CONFIG_ENV_OFFSET 0xa /* env starts here */ /* * Default environment variables -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 00/10] Add Marvell Dove and SolidRun CuBox support
Got this to work. The problem was that I didn't know about make u-boot.kwb, so I tried invoking mkimage using the load address and entry point used in Rabeeh's tree. For some reason, the entry point is different in mainline U-Boot. Changes compared to v3 from Sebastian: - rebased on master (using generic global_data) - added support for CuBox Pro and UART boot - second USB port works now - drives 2TiB work now - using dove_* naming convention rather than orion_* (mv is already taken, at least for GPIO) - removed EBAR_DRAM_CS* for dove (dove doesn't encode SDRAM bank in attributes) - removed hard-coded ethaddr - general clean-ups (checkpatch clean except for one spot now) I'm assuming Sebastian (CC'ed) is still willing to be the maintainer. Sascha Silbe (1): usb: ehci-marvell: add support for second USB controller Sebastian Hesselbarth (9): ARM: dove: add support for Marvell Dove SoC GPIO: add gpio driver for Dove SoCs MMC: sdhci: Add support for dove sdhci SPI: Add Dove SPI driver block: mvsata: add dove include NET: phy: add 88E1310 PHY initialization NET: mvgbe: add phylib support NET: mvgbe: add support for Dove Boards: Add support for SolidRun CuBox MAINTAINERS | 4 + arch/arm/cpu/armv7/dove/Makefile | 49 + arch/arm/cpu/armv7/dove/cpu.c | 274 + arch/arm/cpu/armv7/dove/dram.c| 117 +++ arch/arm/cpu/armv7/dove/lowlevel_init.S | 83 arch/arm/cpu/armv7/dove/mpp.c | 318 ++ arch/arm/cpu/armv7/dove/timer.c | 176 + arch/arm/cpu/armv7/dove/usb.c | 101 ++ arch/arm/include/asm/arch-dove/config.h | 153 ++ arch/arm/include/asm/arch-dove/cpu.h | 204 +++ arch/arm/include/asm/arch-dove/dove.h | 98 + arch/arm/include/asm/arch-dove/gpio.h | 35 arch/arm/include/asm/arch-dove/mmc.h | 27 +++ arch/arm/include/asm/arch-dove/mpp.h | 283 ++ arch/arm/include/asm/arch-dove/usb.h | 27 +++ board/solidrun/cubox/Makefile | 45 + board/solidrun/cubox/cubox.c | 142 + board/solidrun/cubox/kwbimage-spi-1gb.cfg | 76 +++ board/solidrun/cubox/kwbimage-spi-2gb.cfg | 76 +++ board/solidrun/cubox/kwbimage-uart.cfg| 76 +++ boards.cfg| 3 + drivers/block/mvsata_ide.c| 2 + drivers/gpio/Makefile | 1 + drivers/gpio/dove_gpio.c | 167 drivers/mmc/Makefile | 1 + drivers/mmc/dove_sdhci.c | 101 ++ drivers/net/mvgbe.c | 83 +++- drivers/net/mvgbe.h | 2 + drivers/net/phy/marvell.c | 48 + drivers/spi/Makefile | 1 + drivers/spi/dove_spi.c| 212 drivers/usb/host/ehci-marvell.c | 35 ++-- include/configs/cubox.h | 185 + include/dove_gpio.h | 64 ++ 34 files changed, 3251 insertions(+), 18 deletions(-) create mode 100644 arch/arm/cpu/armv7/dove/Makefile create mode 100644 arch/arm/cpu/armv7/dove/cpu.c create mode 100644 arch/arm/cpu/armv7/dove/dram.c create mode 100644 arch/arm/cpu/armv7/dove/lowlevel_init.S create mode 100644 arch/arm/cpu/armv7/dove/mpp.c create mode 100644 arch/arm/cpu/armv7/dove/timer.c create mode 100644 arch/arm/cpu/armv7/dove/usb.c create mode 100644 arch/arm/include/asm/arch-dove/config.h create mode 100644 arch/arm/include/asm/arch-dove/cpu.h create mode 100644 arch/arm/include/asm/arch-dove/dove.h create mode 100644 arch/arm/include/asm/arch-dove/gpio.h create mode 100644 arch/arm/include/asm/arch-dove/mmc.h create mode 100644 arch/arm/include/asm/arch-dove/mpp.h create mode 100644 arch/arm/include/asm/arch-dove/usb.h create mode 100644 board/solidrun/cubox/Makefile create mode 100644 board/solidrun/cubox/cubox.c create mode 100644 board/solidrun/cubox/kwbimage-spi-1gb.cfg create mode 100644 board/solidrun/cubox/kwbimage-spi-2gb.cfg create mode 100644 board/solidrun/cubox/kwbimage-uart.cfg create mode 100644 drivers/gpio/dove_gpio.c create mode 100644 drivers/mmc/dove_sdhci.c create mode 100644 drivers/spi/dove_spi.c create mode 100644 include/configs/cubox.h create mode 100644 include/dove_gpio.h -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 10/10] Boards: Add support for SolidRun CuBox
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com With latest support for Marvell Dove SoC, add the SolidRun CuBox as the very first board with that SoC. Three variants are provided: 1. A regular SPI boot image for CuBox (1GiB) The CuBox (without Pro) has 1GiB of memory. 2. A regular SPI boot image for CuBox Pro (2GiB) The CuBox Pro has 2GiB of memory. Because larger SDRAM chips are used, tRFC needs to be longer than on the 1GiB variant. 3. A UART boot image for both CuBox and CuBox Pro This is just for recovery purposes, so the smaller memory map (on CuBox Pro) and slower SDRAM access (on CuBox) doesn't matter. Having a single image that works on both hardware variants is quite convenient during recovery. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de --- v3-v4: added second USB port; added 2GiB and UART variants; removed hardcoded MAC address; fixed some typos; made checkpatch clean Tested on CuBox Pro (SPI and UART boot). MAINTAINERS | 4 + board/solidrun/cubox/Makefile | 45 board/solidrun/cubox/cubox.c | 142 +++ board/solidrun/cubox/kwbimage-spi-1gb.cfg | 76 board/solidrun/cubox/kwbimage-spi-2gb.cfg | 76 board/solidrun/cubox/kwbimage-uart.cfg| 76 boards.cfg| 3 + include/configs/cubox.h | 185 ++ 8 files changed, 607 insertions(+) create mode 100644 board/solidrun/cubox/Makefile create mode 100644 board/solidrun/cubox/cubox.c create mode 100644 board/solidrun/cubox/kwbimage-spi-1gb.cfg create mode 100644 board/solidrun/cubox/kwbimage-spi-2gb.cfg create mode 100644 board/solidrun/cubox/kwbimage-uart.cfg create mode 100644 include/configs/cubox.h diff --git a/MAINTAINERS b/MAINTAINERS index 643a5ac..07faf39 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -693,6 +693,10 @@ Lauri Hintsala lauri.hints...@bluegiga.com apx4devkit i.MX28 +Sebastian Hesselbarth sebastian.hesselba...@gmail.com + + cubox ARM ARMV7 (Dove SoC) + Vaibhav Hiremath hvaib...@ti.com am3517_evm ARM ARMV7 (AM35x SoC) diff --git a/board/solidrun/cubox/Makefile b/board/solidrun/cubox/Makefile new file mode 100644 index 000..c771d72 --- /dev/null +++ b/board/solidrun/cubox/Makefile @@ -0,0 +1,45 @@ +# +# SolidRun CuBox Makefile +# +# Sebastian Hesselbarth sebastian.hesselba...@gmail.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(BOARD).o + +COBJS := cubox.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB):$(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS) $(SOBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/board/solidrun/cubox/cubox.c b/board/solidrun/cubox/cubox.c new file mode 100644 index 000..3d8140d --- /dev/null +++ b/board/solidrun/cubox/cubox.c @@ -0,0 +1,142 @@ +/* + * SolidRun CuBox board support + * + * Sebastian Hesselbarth sebastian.hesselba...@gmail.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51
[U-Boot] [PATCH v4 08/10] NET: mvgbe: add phylib support
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
This add phylib support to the Marvell GBE driver.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Acked-by: Prafulla Wadaskar prafu...@marvell.com
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v3-v4: avoided unused variable warning; made checkpatch clean
drivers/net/mvgbe.c | 74 -
1 file changed, 68 insertions(+), 6 deletions(-)
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 47bf27c..7f0ddf5 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -52,7 +52,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define MV_PHY_ADR_REQUEST 0xee
#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)-smi)
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
/*
* smi_reg_read - miiphy_read callback function.
*
@@ -184,6 +184,25 @@ static int smi_reg_write(const char *devname, u8 phy_adr,
u8 reg_ofs, u16 data)
}
#endif
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phy_read(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr)
+{
+ u16 data;
+ int ret;
+ ret = smi_reg_read(bus-name, phy_addr, reg_addr, data);
+ if (ret)
+ return ret;
+ return data;
+}
+
+int mvgbe_phy_write(struct mii_dev *bus, int phy_addr, int dev_addr,
+ int reg_addr, u16 data)
+{
+ return smi_reg_write(bus-name, phy_addr, reg_addr, data);
+}
+#endif
+
/* Stop and checks all queues */
static void stop_queue(u32 * qreg)
{
@@ -415,8 +434,9 @@ static int mvgbe_init(struct eth_device *dev)
{
struct mvgbe_device *dmvgbe = to_mvgbe(dev);
struct mvgbe_registers *regs = dmvgbe-regs;
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
- defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
+ !defined(CONFIG_PHYLIB)\
+ defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
int i;
#endif
/* setup RX rings */
@@ -467,8 +487,9 @@ static int mvgbe_init(struct eth_device *dev)
/* Enable port Rx. */
MVGBE_REG_WR(regs-rqc, (1 RXUQ));
-#if (defined (CONFIG_MII) || defined (CONFIG_CMD_MII)) \
- defined (CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) \
+ !defined(CONFIG_PHYLIB)\
+ defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
/* Wait up to 5s for the link status */
for (i = 0; i 5; i++) {
u16 phyadr;
@@ -647,6 +668,45 @@ static int mvgbe_recv(struct eth_device *dev)
return 0;
}
+#if defined(CONFIG_PHYLIB)
+int mvgbe_phylib_init(struct eth_device *dev, int phyid)
+{
+ struct mii_dev *bus;
+ struct phy_device *phydev;
+ int ret;
+
+ bus = mdio_alloc();
+ if (!bus) {
+ printf(mdio_alloc failed\n);
+ return -ENOMEM;
+ }
+ bus-read = mvgbe_phy_read;
+ bus-write = mvgbe_phy_write;
+ sprintf(bus-name, dev-name);
+
+ ret = mdio_register(bus);
+ if (ret) {
+ printf(mdio_register failed\n);
+ free(bus);
+ return -ENOMEM;
+ }
+
+ /* Set phy address of the port */
+ mvgbe_phy_write(bus, MV_PHY_ADR_REQUEST, 0, MV_PHY_ADR_REQUEST, phyid);
+
+ phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RGMII);
+ if (!phydev) {
+ printf(phy_connect failed\n);
+ return -ENODEV;
+ }
+
+ phy_config(phydev);
+ phy_startup(phydev);
+
+ return 0;
+}
+#endif
+
int mvgbe_initialize(bd_t *bis)
{
struct mvgbe_device *dmvgbe;
@@ -729,7 +789,9 @@ error1:
eth_register(dev);
-#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_PHYLIB)
+ mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
+#elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
miiphy_register(dev-name, smi_reg_read, smi_reg_write);
/* Set phy address of the port */
miiphy_write(dev-name, MV_PHY_ADR_REQUEST,
--
1.8.2.1
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[U-Boot] [PATCH v4 02/10] usb: ehci-marvell: add support for second USB controller
From: Sascha Silbe sascha-...@silbe.org
Marvell 88AP510 (Armada 510, dove) has two separate USB
controllers. Use the index parameter that already gets passed in to
calculate the base address of the controller.
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v3-v4: new patch
drivers/usb/host/ehci-marvell.c | 35 ---
1 file changed, 24 insertions(+), 11 deletions(-)
diff --git a/drivers/usb/host/ehci-marvell.c b/drivers/usb/host/ehci-marvell.c
index 2b73e4a..d2cf026 100644
--- a/drivers/usb/host/ehci-marvell.c
+++ b/drivers/usb/host/ehci-marvell.c
@@ -28,7 +28,9 @@
#include ehci.h
#include asm/arch/cpu.h
-#if defined(CONFIG_KIRKWOOD)
+#if defined(CONFIG_DOVE)
+#include asm/arch/dove.h
+#elif defined(CONFIG_KIRKWOOD)
#include asm/arch/kirkwood.h
#elif defined(CONFIG_ORION5X)
#include asm/arch/orion5x.h
@@ -36,8 +38,8 @@
DECLARE_GLOBAL_DATA_PTR;
-#define rdl(off) readl(MVUSB0_BASE + (off))
-#define wrl(off, val) writel((val), MVUSB0_BASE + (off))
+#define rdl(base, off) readl((base) + (off))
+#define wrl(base, off, val)writel((val), (base) + (off))
#define USB_WINDOW_CTRL(i) (0x320 + ((i) 4))
#define USB_WINDOW_BASE(i) (0x324 + ((i) 4))
@@ -46,10 +48,15 @@ DECLARE_GLOBAL_DATA_PTR;
/*
* USB 2.0 Bridge Address Decoding registers setup
*/
-static void usb_brg_adrdec_setup(void)
+static void usb_brg_adrdec_setup(int index)
{
int i;
u32 size, base, attrib;
+#ifdef MVUSB1_BASE
+ u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
+#else
+ u32 usb_base = MVUSB0_BASE;
+#endif
for (i = 0; i CONFIG_NR_DRAM_BANKS; i++) {
@@ -76,13 +83,13 @@ static void usb_brg_adrdec_setup(void)
size = gd-bd-bi_dram[i].size;
base = gd-bd-bi_dram[i].start;
if ((size) (attrib))
- wrl(USB_WINDOW_CTRL(i),
- MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
- attrib, MVCPU_WIN_ENABLE));
+ wrl(usb_base, USB_WINDOW_CTRL(i),
+ MVCPU_WIN_CTRL_DATA(size, USB_TARGET_DRAM,
+ attrib, MVCPU_WIN_ENABLE));
else
- wrl(USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
+ wrl(usb_base, USB_WINDOW_CTRL(i), MVCPU_WIN_DISABLE);
- wrl(USB_WINDOW_BASE(i), base);
+ wrl(usb_base, USB_WINDOW_BASE(i), base);
}
}
@@ -92,9 +99,15 @@ static void usb_brg_adrdec_setup(void)
*/
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
- usb_brg_adrdec_setup();
+#ifdef MVUSB1_BASE
+ u32 usb_base = (index == 0) ? MVUSB0_BASE : MVUSB1_BASE;
+#else
+ u32 usb_base = MVUSB0_BASE;
+#endif
- *hccr = (struct ehci_hccr *)(MVUSB0_BASE + 0x100);
+ usb_brg_adrdec_setup(index);
+
+ *hccr = (struct ehci_hccr *)(usb_base + 0x100);
*hcor = (struct ehci_hcor *)((uint32_t) *hccr
+ HC_LENGTH(ehci_readl((*hccr)-cr_capbase)));
--
1.8.2.1
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[U-Boot] [PATCH v4 07/10] NET: phy: add 88E1310 PHY initialization
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
This adds PHY initialization for Marvell Alaska 88E1310 PHY.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
---
drivers/net/phy/marvell.c | 48 +++
1 file changed, 48 insertions(+)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index 4b27198..1205166 100644
--- a/drivers/net/phy/marvell.c
+++ b/drivers/net/phy/marvell.c
@@ -89,6 +89,12 @@
#define MIIM_88E1149_PHY_PAGE 29
+/* 88E1310 PHY defines */
+#define MIIM_88E1310_PHY_LED_CTRL 16
+#define MIIM_88E1310_PHY_IRQ_EN18
+#define MIIM_88E1310_PHY_RGMII_CTRL21
+#define MIIM_88E1310_PHY_PAGE 22
+
/* Marvell 88E1011S */
static int m88e1011s_config(struct phy_device *phydev)
{
@@ -394,6 +400,37 @@ static int m88e1149_config(struct phy_device *phydev)
return 0;
}
+/* Marvell 88E1310 */
+static int m88e1310_config(struct phy_device *phydev)
+{
+ u16 reg;
+
+ /* LED link and activity */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL);
+ reg = (reg ~0xf) | 0x1;
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_LED_CTRL, reg);
+
+ /* Set LED2/INT to INT mode, low active */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0003);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN);
+ reg = (reg 0x77ff) | 0x0880;
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_IRQ_EN, reg);
+
+ /* Set RGMII delay */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x0002);
+ reg = phy_read(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL);
+ reg |= 0x0030;
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_RGMII_CTRL, reg);
+
+ /* Ensure to return to page 0 */
+ phy_write(phydev, MDIO_DEVAD_NONE, MIIM_88E1310_PHY_PAGE, 0x);
+
+ genphy_config_aneg(phydev);
+ phy_reset(phydev);
+
+ return 0;
+}
static struct phy_driver M88E1011S_driver = {
.name = Marvell 88E1011S,
@@ -465,8 +502,19 @@ static struct phy_driver M88E1149S_driver = {
.shutdown = genphy_shutdown,
};
+static struct phy_driver M88E1310_driver = {
+ .name = Marvell 88E1310,
+ .uid = 0x01410e90,
+ .mask = 0xff0,
+ .features = PHY_GBIT_FEATURES,
+ .config = m88e1310_config,
+ .startup = m88e1011s_startup,
+ .shutdown = genphy_shutdown,
+};
+
int phy_marvell_init(void)
{
+ phy_register(M88E1310_driver);
phy_register(M88E1149S_driver);
phy_register(M88E1145_driver);
phy_register(M88E1121R_driver);
--
1.8.2.1
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[U-Boot] [PATCH v4 06/10] block: mvsata: add dove include
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com Dove SoC also uses mvsata, therefore add a SoC specific include to allow to reuse the mvsata ide driver. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com Acked-by: Prafulla Wadaskar prafu...@marvell.com --- drivers/block/mvsata_ide.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/block/mvsata_ide.c b/drivers/block/mvsata_ide.c index 42c177f..500f13c 100644 --- a/drivers/block/mvsata_ide.c +++ b/drivers/block/mvsata_ide.c @@ -29,6 +29,8 @@ #include asm/arch/orion5x.h #elif defined(CONFIG_KIRKWOOD) #include asm/arch/kirkwood.h +#elif defined(CONFIG_DOVE) +#include asm/arch/dove.h #endif /* SATA port registers */ -- 1.8.2.1 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v4 09/10] NET: mvgbe: add support for Dove
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Marvell Dove also uses mvgbe as ethernet driver, therefore add support
for Dove to reuse the current driver.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v3-v4: removed EBAR_DRAM_CS* for Dove
drivers/net/mvgbe.c | 9 -
drivers/net/mvgbe.h | 2 ++
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index 7f0ddf5..57692e3 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -43,6 +43,8 @@
#include asm/arch/kirkwood.h
#elif defined(CONFIG_ORION5X)
#include asm/arch/orion5x.h
+#elif defined(CONFIG_DOVE)
+#include asm/arch/dove.h
#endif
#include mvgbe.h
@@ -286,7 +288,11 @@ static void set_dram_access(struct mvgbe_registers *regs)
else
win_param.enable = 1; /* Enable the access */
- /* Enable DRAM bank */
+#ifdef CONFIG_DOVE
+ /* Choose DRAM as target */
+ win_param.attrib = 0;
+#else
+ /* Choose one DRAM bank (chip select line) as target */
switch (i) {
case 0:
win_param.attrib = EBAR_DRAM_CS0;
@@ -306,6 +312,7 @@ static void set_dram_access(struct mvgbe_registers *regs)
win_param.attrib = 0;
break;
}
+#endif
/* Set the access control for address window(EPAPR) RD/WR */
set_access_control(regs, win_param);
}
diff --git a/drivers/net/mvgbe.h b/drivers/net/mvgbe.h
index d8a5429..22b571e 100644
--- a/drivers/net/mvgbe.h
+++ b/drivers/net/mvgbe.h
@@ -308,10 +308,12 @@
#define EBAR_TARGET_GUNIT 0x0007
/* Window attrib */
+#if !defined(CONFIG_DOVE)
#define EBAR_DRAM_CS0 0x0E00
#define EBAR_DRAM_CS1 0x0D00
#define EBAR_DRAM_CS2 0x0B00
#define EBAR_DRAM_CS3 0x0700
+#endif
/* DRAM Target interface */
#define EBAR_DRAM_NO_CACHE_COHERENCY 0x
--
1.8.2.1
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[U-Boot] [PATCH v4 03/10] GPIO: add gpio driver for Dove SoCs
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
This adds a gpio driver for Marvell Dove SoCs. It is based on kw_gpio;
but as gpio capabilities depend heavily on the mpp configuration for
dove, it allows to set gpi/gpo capabilities from mpp.
While it's currently targeted at Dove SoCs only, the driver should in
large parts be compatible with orion5x and kirkwood. As a future
clean-up step, the MPP and GPIO code for the three platforms could be
merged.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v3-v4: renamed to dove_gpio, adjusted description
drivers/gpio/Makefile| 1 +
drivers/gpio/dove_gpio.c | 167 +++
include/dove_gpio.h | 64 ++
3 files changed, 232 insertions(+)
create mode 100644 drivers/gpio/dove_gpio.c
create mode 100644 include/dove_gpio.h
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 830e8e6..6d44bfd 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk
LIB:= $(obj)libgpio.o
COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
+COBJS-$(CONFIG_DOVE_GPIO) += dove_gpio.o
COBJS-$(CONFIG_INTEL_ICH6_GPIO)+= intel_ich6_gpio.o
COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
diff --git a/drivers/gpio/dove_gpio.c b/drivers/gpio/dove_gpio.c
new file mode 100644
index 000..d16e641
--- /dev/null
+++ b/drivers/gpio/dove_gpio.c
@@ -0,0 +1,167 @@
+/*
+ * Marvell Dove SoC GPIO handling.
+ *
+ * Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ *
+ * Based on (mostly copied from) plat-orion based Linux 2.6 kernel driver.
+ * Removed orion_gpiochip struct and kernel level irq handling.
+ * Dieter Kiermaier dk-arm-li...@gmx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include asm/bitops.h
+#include asm/io.h
+#include asm/arch/gpio.h
+#include dove_gpio.h
+
+static unsigned long gpio_valid_input[BITS_TO_LONGS(GPIO_MAX)];
+static unsigned long gpio_valid_output[BITS_TO_LONGS(GPIO_MAX)];
+
+void __set_direction(unsigned pin, int input)
+{
+ u32 base = GPIO_BASE(pin);
+ u32 u;
+
+ u = readl(GPIO_IO_CONF(base));
+ if (input)
+ u |= 1 (pin 31);
+ else
+ u = ~(1 (pin 31));
+ writel(u, GPIO_IO_CONF(base));
+
+ u = readl(GPIO_IO_CONF(base));
+}
+
+void __set_level(unsigned pin, int high)
+{
+ u32 base = GPIO_BASE(pin);
+ u32 u;
+
+ u = readl(GPIO_OUT(base));
+ if (high)
+ u |= 1 (pin 31);
+ else
+ u = ~(1 (pin 31));
+ writel(u, GPIO_OUT(base));
+}
+
+void __set_blinking(unsigned pin, int blink)
+{
+ u32 base = GPIO_BASE(pin);
+ u32 u;
+
+ u = readl(GPIO_BLINK_EN(base));
+ if (blink)
+ u |= 1 (pin 31);
+ else
+ u = ~(1 (pin 31));
+ writel(u, GPIO_BLINK_EN(base));
+}
+
+int dove_gpio_is_valid(unsigned pin, int mode)
+{
+ if (pin GPIO_MAX) {
+ if ((mode GPIO_INPUT_OK)
+ !test_bit(pin, gpio_valid_input))
+ goto err_out;
+
+ if ((mode GPIO_OUTPUT_OK)
+ !test_bit(pin, gpio_valid_output))
+ goto err_out;
+ return 0;
+ }
+
+err_out:
+ printf(%s: invalid GPIO %d/%d\n, __func__, pin, GPIO_MAX);
+ return 1;
+}
+
+void dove_gpio_set_valid(unsigned pin, int mode)
+{
+ if (mode GPIO_INPUT_OK)
+ __set_bit(pin, gpio_valid_input);
+ else
+ __clear_bit(pin, gpio_valid_input);
+ if (mode GPIO_OUTPUT_OK)
+ __set_bit(pin, gpio_valid_output);
+ else
+ __clear_bit(pin, gpio_valid_output);
+}
+
+/*
+ * GENERIC_GPIO primitives.
+ */
+int dove_gpio_direction_input(unsigned pin)
+{
+ if (dove_gpio_is_valid(pin, GPIO_INPUT_OK) != 0)
+ return 1;
+
+ /* Configure GPIO direction. */
+ __set_direction(pin, 1);
+
+ return 0;
+}
+
+int dove_gpio_direction_output(unsigned pin, int value
[U-Boot] [PATCH v4 05/10] SPI: Add Dove SPI driver
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
This adds an SPI driver for Marvell Dove SoCs. This driver is taken
from kirkwood_spi but removes mpp configuration as dove has dedicated
spi pins.
As a future clean-up step, the code for orion5x, kirkwood and dove
could be merged, with MPP configuration being be handled as part of
cpu/board-specific setup.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v3-v4: renamed to dove, adjusted description, removed unused
variable, made checkpatch clean
drivers/spi/Makefile | 1 +
drivers/spi/dove_spi.c | 212 +
2 files changed, 213 insertions(+)
create mode 100644 drivers/spi/dove_spi.c
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index d08609e..62ad970 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -38,6 +38,7 @@ COBJS-$(CONFIG_BFIN_SPI6XX) += bfin_spi6xx.o
COBJS-$(CONFIG_CF_SPI) += cf_spi.o
COBJS-$(CONFIG_CF_QSPI) += cf_qspi.o
COBJS-$(CONFIG_DAVINCI_SPI) += davinci_spi.o
+COBJS-$(CONFIG_DOVE_SPI) += dove_spi.o
COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
COBJS-$(CONFIG_ICH_SPI) += ich.o
COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
diff --git a/drivers/spi/dove_spi.c b/drivers/spi/dove_spi.c
new file mode 100644
index 000..c61ba89
--- /dev/null
+++ b/drivers/spi/dove_spi.c
@@ -0,0 +1,212 @@
+/*
+ * Marvell Dove SoCs common spi driver
+ *
+ * Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ * based on kirkwood_spi.c written by
+ * Prafulla Wadaskar prafu...@marvell.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include common.h
+#include malloc.h
+#include spi.h
+#include asm/io.h
+#include asm/arch/config.h
+
+/* SPI Registers on dove SOC */
+struct dovespi_registers {
+ u32 ctrl; /* 0x00 */
+ u32 cfg;/* 0x04 */
+ u32 dout; /* 0x08 */
+ u32 din;/* 0x0c */
+ u32 irq_cause; /* 0x10 */
+ u32 irq_mask; /* 0x14 */
+};
+
+#define DOVESPI_CLKPRESCL_MASK 0x1f
+#define DOVESPI_CLKPRESCL_MIN 0x12
+#define DOVESPI_CSN_ACT1 /* Activates serial memory interface */
+#define DOVESPI_SMEMRDY(1 1) /* SerMem Data xfer ready */
+#define DOVESPI_IRQUNMASK 1 /* unmask SPI interrupt */
+#define DOVESPI_IRQMASK0 /* mask SPI interrupt */
+#define DOVESPI_SMEMRDIRQ 1 /* SerMem data xfer ready irq */
+#define DOVESPI_XFERLEN_1BYTE 0
+#define DOVESPI_XFERLEN_2BYTE (1 5)
+#define DOVESPI_XFERLEN_MASK (1 5)
+#define DOVESPI_ADRLEN_1BYTE 0
+#define DOVESPI_ADRLEN_2BYTE (1 8)
+#define DOVESPI_ADRLEN_3BYTE (2 8)
+#define DOVESPI_ADRLEN_4BYTE (3 8)
+#define DOVESPI_ADRLEN_MASK(3 8)
+#define DOVESPI_TIMEOUT1
+
+static struct dovespi_registers *spireg =
+ (struct dovespi_registers *)DOVE_SPI_BASE;
+
+struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
+ unsigned int max_hz, unsigned int mode)
+{
+ struct spi_slave *slave;
+ u32 data;
+
+ if (!spi_cs_is_valid(bus, cs))
+ return NULL;
+
+ slave = malloc(sizeof(struct spi_slave));
+ if (!slave)
+ return NULL;
+
+ slave-bus = bus;
+ slave-cs = cs;
+
+ writel(~DOVESPI_CSN_ACT | DOVESPI_SMEMRDY, spireg-ctrl);
+
+ /* calculate spi clock prescaller using max_hz */
+ data = ((CONFIG_SYS_TCLK / 2) / max_hz) + 0x10;
+ data = data DOVESPI_CLKPRESCL_MIN ? DOVESPI_CLKPRESCL_MIN : data;
+ data = data DOVESPI_CLKPRESCL_MASK ? DOVESPI_CLKPRESCL_MASK : data;
+
+ /* program spi clock prescaller using max_hz */
+ writel(DOVESPI_ADRLEN_3BYTE | data, spireg-cfg);
+ debug(data = 0x%08x\n, data);
+
+ writel(DOVESPI_SMEMRDIRQ, spireg-irq_cause);
+ writel(DOVESPI_IRQMASK, spireg-irq_mask);
+
+ return slave;
+}
+
+void spi_free_slave(struct spi_slave *slave)
+{
+ free(slave);
+}
+
+__attribute__((weak)) int board_spi_claim_bus(struct spi_slave *slave)
+{
+ return 0;
+}
+
+int spi_claim_bus(struct spi_slave *slave)
+{
+ return board_spi_claim_bus(slave
[U-Boot] [PATCH v4 04/10] MMC: sdhci: Add support for dove sdhci
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
This adds a driver for the sdhci controller found on Dove SoCs.
Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com
Signed-off-by: Sascha Silbe t-ub...@infra-silbe.de
---
v3-v4: added header file with exported function
arch/arm/include/asm/arch-dove/mmc.h | 27 ++
drivers/mmc/Makefile | 1 +
drivers/mmc/dove_sdhci.c | 101 +++
3 files changed, 129 insertions(+)
create mode 100644 arch/arm/include/asm/arch-dove/mmc.h
create mode 100644 drivers/mmc/dove_sdhci.c
diff --git a/arch/arm/include/asm/arch-dove/mmc.h
b/arch/arm/include/asm/arch-dove/mmc.h
new file mode 100644
index 000..579396c
--- /dev/null
+++ b/arch/arm/include/asm/arch-dove/mmc.h
@@ -0,0 +1,27 @@
+/*
+ * Marvell Dove SoC SDHCI
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _DOVEMMC_H
+#define _DOVEMMC_H
+
+int dove_sdhci_init(int num);
+#endif /* _DOVEMMC_H */
diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile
index fb6b502..cdff33d 100644
--- a/drivers/mmc/Makefile
+++ b/drivers/mmc/Makefile
@@ -31,6 +31,7 @@ endif
COBJS-$(CONFIG_BFIN_SDH) += bfin_sdh.o
COBJS-$(CONFIG_DAVINCI_MMC) += davinci_mmc.o
+COBJS-$(CONFIG_DOVE_SDHCI) += dove_sdhci.o
COBJS-$(CONFIG_FSL_ESDHC) += fsl_esdhc.o
COBJS-$(CONFIG_FTSDC010) += ftsdc010_esdhc.o
COBJS-$(CONFIG_GENERIC_MMC) += mmc.o
diff --git a/drivers/mmc/dove_sdhci.c b/drivers/mmc/dove_sdhci.c
new file mode 100644
index 000..ac15fd7
--- /dev/null
+++ b/drivers/mmc/dove_sdhci.c
@@ -0,0 +1,101 @@
+/*
+ *
+ * Marvell Dove SDHCI driver
+ *
+ * Sebastian Hesselbarth sebastian.hesselba...@gmail.com
+ *
+ * Based on linux drivers/mmc/host/sdhci-dove.c
+ * by: Saeed Bishara sa...@marvell.com
+ * Mike Rapoport m...@compulab.co.il
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include common.h
+#include malloc.h
+#include sdhci.h
+#include asm/arch/dove.h
+
+static u16 dove_sdhci_readw(struct sdhci_host *host, int reg)
+{
+ u16 ret;
+
+ switch (reg) {
+ case SDHCI_HOST_VERSION:
+ case SDHCI_SLOT_INT_STATUS:
+ /* those registers don't exist */
+ return 0;
+ default:
+ ret = readw(host-ioaddr + reg);
+ }
+
+ return ret;
+}
+
+static u32 dove_sdhci_readl(struct sdhci_host *host, int reg)
+{
+ u32 ret;
+
+ switch (reg) {
+ case SDHCI_CAPABILITIES:
+ ret = readl(host-ioaddr + reg);
+ /* Mask the support for 3.0V */
+ ret = ~SDHCI_CAN_VDD_300;
+ break;
+ default:
+ ret = readl(host-ioaddr + reg);
+ }
+
+ return ret;
+}
+
+static struct sdhci_ops dove_sdhci_ops = {
+ .read_w = dove_sdhci_readw,
+ .read_l = dove_sdhci_readl,
+};
+
+static struct sdhci_host hosts[2] = {
+ {
+ .name = Dove SDHCI0,
+ .ioaddr = (void *)DOVE_SDIO0_BASE,
+ },
+ {
+ .name = Dove SDHCI1,
+ .ioaddr = (void *)DOVE_SDIO1_BASE,
+ },
+};
+
+int dove_sdhci_init(int num)
+{
+ struct sdhci_host *host;
+
+ if (num 0 || num 1)
+ return 1;
+
+ host = hosts[num];
+
+ if (host-version)
+ return 1;
+
+ host-quirks =
+ SDHCI_QUIRK_NO_HISPD_BIT |
+ SDHCI_QUIRK_BROKEN_R1B |
+ SDHCI_QUIRK_32BIT_DMA_ADDR;
+ host-version = SDHCI_SPEC_200;
+ host-ops
Re: [U-Boot] [PATCH v3 00/10] Add Marvell Dove and SolidRun CuBox
Sebastian Hesselbarth sebastian.hesselba...@gmail.com writes: This patch set add support for the Marvell Dove 88AP510 SoC and the SolidRun CuBox board based on that SoC. The patch set is divided into the four following sections: [...] What's the state of this? I tried applying your patch series on top of current master and getting it to work on a CuBox Pro (2GiB SDRAM instead of 1GiB), but with no success so far. I changed kwbimage.cfg to match dramregs_cubox_2gb.txt in Rabeeh's tree and fixed arch/arm/cpu/armv7/dove/timer.c to work with the generic global_data (introduced by baa1e53 and 50b1fa3). However there seems to be something else missing or broken as there's no output whatsoever on the serial console after booting the new image via UART. The same boot procedure works fine with an image built using Rabeeh's tree. Sascha pgppssB6CIeJy.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] u-boot UBI support
Paul B. Henson hen...@acm.org writes: I'm trying to get u-boot to read from a ubifs volume on an mx28evk board, and failing :(. [...] MX28EVK U-Boot ubifsmount recovery UBIFS error (pid 0): ubifs_get_sb: cannot open recovery, error -22 UBIFS error (pid 0): ubifs_mount: Error reading superblock on volume 'recovery' errno=-22! Try increasing CONFIG_SYS_MALLOC_LEN, e.g. to 4MiB. That fixed it for me on a different board. Sascha -- http://www.infra-silbe.de/ pgp0rxUMOdHsa.pgp Description: PGP signature ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
