[U-Boot] [PATCH][v2] powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200
MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha
---
chnages in v2:
Incorporated review comments
All DSP aware code is enclosed with #ifdef
to not increase the uboot code size for other platforms
Tested it on B4860QDS and on T4240QDS
arch/powerpc/cpu/mpc85xx/cpu.c| 28 ++
arch/powerpc/cpu/mpc85xx/speed.c | 140 +
arch/powerpc/cpu/mpc8xxx/cpu.c| 91 ++-
arch/powerpc/include/asm/config_mpc85xx.h | 14 +++-
arch/powerpc/include/asm/processor.h |5 +
doc/README.Heterogeneous-SoCs | 105 +
include/common.h |2 +
include/e500.h| 11 +++
8 files changed, 393 insertions(+), 3 deletions(-)
create mode 100644 doc/README.Heterogeneous-SoCs
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 3d6ec84..ef08489 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -73,6 +73,11 @@ int checkcpu (void)
unsigned int i, core, nr_cores = cpu_numcores();
u32 mask = cpu_mask();
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
+ u32 dsp_mask = cpu_dsp_mask();
+#endif
+
svr = get_svr();
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
@@ -166,6 +171,16 @@ int checkcpu (void)
printf("CPU%d:%-4s MHz, ", core,
strmhz(buf1, sysinfo.freq_processor[core]));
}
+
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
+ if (!(j & 3))
+ printf("\n ");
+ printf("DSP CPU%d:%-4s MHz, ", j,
+ strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
+ }
+#endif
+
printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
printf("\n");
@@ -224,6 +239,19 @@ int checkcpu (void)
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
#endif
+#if defined(CONFIG_SYS_CPRI)
+ printf(" ");
+ printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
+#endif
+
+#if defined(CONFIG_SYS_MAPLE)
+ printf("\n ");
+ printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
+ printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
+ printf("MAPLE-eTVPE:%-4s MHz\n",
+ strmhz(buf1, sysinfo.freq_maple_etvpe));
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 7e69873..e24b857 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -34,6 +34,10 @@ void get_sys_info(sys_info_t *sys_info)
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned int dsp_cpu;
+ uint rcw_tmp1, rcw_tmp2;
+#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif
@@ -157,6 +161,7 @@ void get_sys_info(sys_info_t *sys_info)
else
freq_c_pll[i] = sys_info->freq_systembu
[U-Boot] [PATCH] powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4860QDS:
U-Boot 2015.01-00232-geef6e36-dirty (Jan 19 2015 - 11:58:45)
CPU0: B4860E, Version: 2.2, (0x86880022)
Core: e6500, Version: 2.0, (0x80400120)
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz, CPU2:1600 MHz, CPU3:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200
MHz,
DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
CCB:666.667 MHz,
DDR:933.333 MHz (1866.667 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha
---
arch/powerpc/cpu/mpc85xx/cpu.c| 28 ++
arch/powerpc/cpu/mpc85xx/speed.c | 140 +
arch/powerpc/cpu/mpc8xxx/cpu.c| 91 ++-
arch/powerpc/include/asm/config_mpc85xx.h | 14 +++-
arch/powerpc/include/asm/processor.h |5 +
doc/README.Heterogeneous-SoCs | 105 +
include/common.h |2 +
include/e500.h| 11 +++
8 files changed, 393 insertions(+), 3 deletions(-)
create mode 100644 doc/README.Heterogeneous-SoCs
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 3d6ec84..ef08489 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -73,6 +73,11 @@ int checkcpu (void)
unsigned int i, core, nr_cores = cpu_numcores();
u32 mask = cpu_mask();
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
+ u32 dsp_mask = cpu_dsp_mask();
+#endif
+
svr = get_svr();
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
@@ -166,6 +171,16 @@ int checkcpu (void)
printf("CPU%d:%-4s MHz, ", core,
strmhz(buf1, sysinfo.freq_processor[core]));
}
+
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
+ if (!(j & 3))
+ printf("\n ");
+ printf("DSP CPU%d:%-4s MHz, ", j,
+ strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
+ }
+#endif
+
printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
printf("\n");
@@ -224,6 +239,19 @@ int checkcpu (void)
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
#endif
+#if defined(CONFIG_SYS_CPRI)
+ printf(" ");
+ printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
+#endif
+
+#if defined(CONFIG_SYS_MAPLE)
+ printf("\n ");
+ printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
+ printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
+ printf("MAPLE-eTVPE:%-4s MHz\n",
+ strmhz(buf1, sysinfo.freq_maple_etvpe));
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 7e69873..e24b857 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -34,6 +34,10 @@ void get_sys_info(sys_info_t *sys_info)
#ifdef CONFIG_FSL_CORENET
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ unsigned int dsp_cpu;
+ uint rcw_tmp1, rcw_tmp2;
+#endif
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif
@@ -157,6 +161,7 @@ void get_sys_info(sys_info_t *sys_info)
else
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
}
+
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
* As per CHASSIS2 architeture total 12 clusters are posible and
@@ -181,6 +186,20 @@ void get_sys_info(sys_info_t *sys_info)
[U-Boot] [PATCH] powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4420:
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz,
CCB:666.667 MHz,
DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structures like "cpu_type" and "MPC85xx_SYS_INFO"
updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha
---
arch/powerpc/cpu/mpc85xx/cpu.c| 25 +
arch/powerpc/cpu/mpc85xx/speed.c | 136 +
arch/powerpc/cpu/mpc8xxx/cpu.c| 89 +++-
arch/powerpc/include/asm/config_mpc85xx.h | 14 +++-
arch/powerpc/include/asm/processor.h |5 +
doc/README.Heterogeneous-SoCs | 105 ++
include/common.h |2 +
include/e500.h| 11 +++
8 files changed, 384 insertions(+), 3 deletions(-)
create mode 100644 doc/README.Heterogeneous-SoCs
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 3d6ec84..69ab14c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -71,7 +71,9 @@ int checkcpu (void)
#endif /* CONFIG_FSL_CORENET */
unsigned int i, core, nr_cores = cpu_numcores();
+ unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
u32 mask = cpu_mask();
+ u32 dsp_mask = cpu_dsp_mask();
svr = get_svr();
major = SVR_MAJ(svr);
@@ -166,6 +168,16 @@ int checkcpu (void)
printf("CPU%d:%-4s MHz, ", core,
strmhz(buf1, sysinfo.freq_processor[core]));
}
+
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
+ if (!(j & 3))
+ printf("\n ");
+ printf("DSP CPU%d:%-4s MHz, ", j,
+ strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
+ }
+#endif
+
printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
printf("\n");
@@ -224,6 +236,19 @@ int checkcpu (void)
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
#endif
+#if defined(CONFIG_SYS_CPRI)
+ printf(" ");
+ printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
+#endif
+
+#if defined(CONFIG_SYS_MAPLE)
+ printf("\n ");
+ printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
+ printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
+ printf("MAPLE-eTVPE:%-4s MHz\n",
+ strmhz(buf1, sysinfo.freq_maple_etvpe));
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 7e69873..43e23a5 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -35,6 +35,7 @@ void get_sys_info(sys_info_t *sys_info)
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ unsigned int dsp_cpu;
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif
__maybe_unused u32 svr;
@@ -69,6 +70,7 @@ void get_sys_info(sys_info_t *sys_info)
[14] = 4, /* CC4 PPL / 4 */
};
uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint rcw_tmp1, rcw_tmp2;
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
uint rcw_tmp;
#endif
@@ -157,6 +159,7 @@ void get_sys_info(sys_info_t *sys_info)
else
freq_c_pll[i] = sys_info->freq_systembus * ratio[i];
}
+
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
/*
* As per CHASSIS2 architeture total 12 clusters are posible and
@@ -181,6 +184,18 @@ void get_sys_info(sys_info_t *sys_info)
sys_info->freq_processor[cpu] =
[U-Boot] [PATCH 2/3] B4860QDS: SGMII related updates
- Enable SGMII support for 0x8d Serdes 2 protocol.
- Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol.
- Updated debug statement
- Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1)
- Rename onboard PHY address defines for more readability
- Add these new Defines in B4860QDS.h file
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
Signed-off-by: Suresh Gupta
Change-Id: I4d9a8c602bdaac8404577ab9642f8c5f37ac7cdc
Reviewed-on: http://git.am.freescale.net:8181/23353
Tested-by: Review Code-CDREVIEW
Reviewed-by: Yusong Sun
---
board/freescale/b4860qds/eth_b4860qds.c | 64 ++
include/configs/B4860QDS.h |4 +-
2 files changed, 40 insertions(+), 28 deletions(-)
diff --git a/board/freescale/b4860qds/eth_b4860qds.c
b/board/freescale/b4860qds/eth_b4860qds.c
index 12df9a8..2726cd2 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -112,7 +112,10 @@ static void initialize_lane_to_slot(void)
* Lanes: A,B,C,D: PCI
* Lanes: E,F,G,H: XAUI2
*/
+ case 0xb1:
case 0xb2:
+ case 0x8c:
+ case 0x8d:
/*
* Configuration:
* SERDES: 2
@@ -195,34 +198,34 @@ int board_eth_init(bd_t *bis)
* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
* 6 to on board SGMII phys
*/
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
switch (serdes1_prtcl) {
case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
- debug("Setting phy addresses for FM1_DTSEC5: %x and"
- "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#ifdef CONFIG_PPC_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
- debug("Setting phy addresses for FM1_DTSEC3: %x and"
- "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
/* Fixing Serdes clock by programming FPGA register */
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#endif
default:
@@ -233,8 +236,8 @@ int board_eth_init(bd_t *bis)
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@@ -246,8 +249,8 @@ int board_eth_init(bd_t *bis)
break;
case 0x48:
case 0x49:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_
[U-Boot] [PATCH 3/3] B4860: Add alternate LC VCO serdes protocols support in board file
Add the support of newly added LC VCO SerDes protocols
for configuration of IDT and VSC crossbar
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
Change-Id: I16ad23e2cbea3b0a232a153984d5126bc79ddd26
Reviewed-on: http://git.am.freescale.net:8181/23354
Tested-by: Yusong Sun
Reviewed-by: Yusong Sun
---
board/freescale/b4860qds/b4860qds.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index 975952f..7f2437e 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -385,15 +385,18 @@ int configure_vsc3316_3308(void)
}
break;
+ case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
+ case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@@ -494,10 +497,14 @@ int configure_vsc3316_3308(void)
case 0x9E:
case 0x9A:
case 0x98:
+ case 0xb1:
case 0xb2:
+ case 0x48:
case 0x49:
case 0x4E:
+ case 0x8C:
case 0x8D:
+ case 0x79:
case 0x7A:
num_vsc08_con = NUM_CON_VSC3308;
/* Configure VSC3308 crossbar switch */
@@ -730,19 +737,23 @@ int config_serdes1_refclks(void)
* to 122.88MHz
*/
switch (serdes1_prtcl) {
+ case 0x29:
case 0x2A:
case 0x2C:
case 0x2D:
case 0x2E:
+ case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
+ case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@@ -860,6 +871,8 @@ int config_serdes2_refclks(void)
#endif
case 0x9E:
case 0x9A:
+ /* fallthrough */
+ case 0xb1:
case 0xb2:
debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
serdes2_prtcl);
--
1.7.6.GIT
___
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[U-Boot] [PATCH 1/3] 85xx/b4860: Add alternate serdes protocols for B4860/B4420
Addded Alternate options with LC VCO for following protocols:
0x02 --> 0x01
0x08 --> 0x07
0x18 --> 0x17
0x1E --> 0x1D
0x49 --> 0x48
0x6F --> 0x6E
0x9A --> 0x99
0x9E --> 0x9D
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal i
Change-Id: Iefe14012ee897095f0198453d50f31096ca020e2
Reviewed-on: http://git.am.freescale.net:8181/23352
Tested-by: Review Code-CDREVIEW
Reviewed-by: Yusong Sun
---
arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index cf18be5..63172de 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -18,6 +18,8 @@ struct serdes_config {
#ifdef CONFIG_PPC_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
+ {0x01, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x02, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x04, {AURORA, AURORA, CPRI6, CPRI5,
@@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x06, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x07, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x08, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x09, {AURORA, AURORA, CPRI6, CPRI5,
@@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, NONE, NONE} },
{0x0F, {NONE, NONE, CPRI6, CPRI5,
CPRI4, CPRI3, NONE, NONE} },
+ {0x17, {NONE, NONE,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
{0x18, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
{0x1B, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
+ {0x1D, {NONE, NONE, AURORA, AURORA,
+ NONE, NONE, NONE, NONE} },
{0x1E, {NONE, NONE, AURORA, AURORA,
NONE, NONE, NONE, NONE} },
{0x21, {NONE, NONE, AURORA, AURORA,
@@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
+ {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ NONE, NONE, NONE, NONE} },
{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
+ {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
+ {0x99, {PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
{0x9A, {PCIE1, PCIE1,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
+ {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
+ NONE, NONE, NONE, NONE} },
{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
NONE, NONE, NONE, NONE} },
{}
--
1.7.6.GIT
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[U-Boot] [PATCH 1/3] 85xx/b4860: Add alternate serdes protocols for B4860/B4420
Addded Alternate options with LC VCO for following protocols:
0x02 --> 0x01
0x08 --> 0x07
0x18 --> 0x17
0x1E --> 0x1D
0x49 --> 0x48
0x6F --> 0x6E
0x9A --> 0x99
0x9E --> 0x9D
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
Change-Id: Iefe14012ee897095f0198453d50f31096ca020e2
Reviewed-on: http://git.am.freescale.net:8181/23352
Tested-by: Review Code-CDREVIEW
Reviewed-by: Yusong Sun
---
arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index cf18be5..63172de 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -18,6 +18,8 @@ struct serdes_config {
#ifdef CONFIG_PPC_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
+ {0x01, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x02, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x04, {AURORA, AURORA, CPRI6, CPRI5,
@@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x06, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x07, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x08, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x09, {AURORA, AURORA, CPRI6, CPRI5,
@@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, NONE, NONE} },
{0x0F, {NONE, NONE, CPRI6, CPRI5,
CPRI4, CPRI3, NONE, NONE} },
+ {0x17, {NONE, NONE,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
{0x18, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
{0x1B, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
+ {0x1D, {NONE, NONE, AURORA, AURORA,
+ NONE, NONE, NONE, NONE} },
{0x1E, {NONE, NONE, AURORA, AURORA,
NONE, NONE, NONE, NONE} },
{0x21, {NONE, NONE, AURORA, AURORA,
@@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
+ {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ NONE, NONE, NONE, NONE} },
{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
+ {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
+ {0x99, {PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
{0x9A, {PCIE1, PCIE1,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
+ {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
+ NONE, NONE, NONE, NONE} },
{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
NONE, NONE, NONE, NONE} },
{}
--
1.7.6.GIT
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[U-Boot] [PATCH 2/3] B4860QDS: SGMII related updates
- Enable SGMII support for 0x8d Serdes 2 protocol.
- Correct Phy address for DTSECx for 0x8d/0xb2 Serdes 2 protocol.
- Updated debug statement
- Add Alternate LC VCO protocols(0x8d-->0x8c, 0xb2-->0xb1)
- Rename onboard PHY address defines for more readability
- Add these new Defines in B4860QDS.h file
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
Signed-off-by: Suresh Gupta
Change-Id: I4d9a8c602bdaac8404577ab9642f8c5f37ac7cdc
Reviewed-on: http://git.am.freescale.net:8181/23353
Tested-by: Review Code-CDREVIEW
Reviewed-by: Yusong Sun
---
board/freescale/b4860qds/eth_b4860qds.c | 64 ++
include/configs/B4860QDS.h |4 +-
2 files changed, 40 insertions(+), 28 deletions(-)
diff --git a/board/freescale/b4860qds/eth_b4860qds.c
b/board/freescale/b4860qds/eth_b4860qds.c
index 12df9a8..2726cd2 100644
--- a/board/freescale/b4860qds/eth_b4860qds.c
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -112,7 +112,10 @@ static void initialize_lane_to_slot(void)
* Lanes: A,B,C,D: PCI
* Lanes: E,F,G,H: XAUI2
*/
+ case 0xb1:
case 0xb2:
+ case 0x8c:
+ case 0x8d:
/*
* Configuration:
* SERDES: 2
@@ -195,34 +198,34 @@ int board_eth_init(bd_t *bis)
* all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
* 6 to on board SGMII phys
*/
- fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
- fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
switch (serdes1_prtcl) {
case 0x29:
case 0x2a:
/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
- debug("Setting phy addresses for FM1_DTSEC5: %x and"
- "FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC5:%x, FM1_DTSEC6:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
fm_info_set_phy_address(FM1_DTSEC5,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC6,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#ifdef CONFIG_PPC_B4420
case 0x17:
case 0x18:
/* Serdes 1: A-D SGMII, Configuring on board dual SGMII Phy */
- debug("Setting phy addresses for FM1_DTSEC3: %x and"
- "FM1_DTSEC4: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ debug("Set phy addresses for FM1_DTSEC3:%x, FM1_DTSEC4:%x\n",
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR,
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
/* Fixing Serdes clock by programming FPGA register */
QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
fm_info_set_phy_address(FM1_DTSEC3,
- CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR);
fm_info_set_phy_address(FM1_DTSEC4,
- CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+ CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR);
break;
#endif
default:
@@ -233,8 +236,8 @@ int board_eth_init(bd_t *bis)
switch (serdes2_prtcl) {
case 0x17:
case 0x18:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC2,
@@ -246,8 +249,8 @@ int board_eth_init(bd_t *bis)
break;
case 0x48:
case 0x49:
- debug("Setting phy addresses on SGMII Riser card for"
- "FM1_DTSEC ports: \n");
+ debug("Set phy address on SGMII Riser for FM1_DTSEC1:%x\n",
+ CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC1,
CONFIG_SYS_FM1_
[U-Boot] [PATCH 1/3] 85xx/b4860: Add alternate serdes protocols for B4860/B4420
Addded Alternate options with LC VCO for following protocols:
0x02 --> 0x01
0x08 --> 0x07
0x18 --> 0x17
0x1E --> 0x1D
0x49 --> 0x48
0x6F --> 0x6E
0x9A --> 0x99
0x9E --> 0x9D
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal i
Change-Id: Iefe14012ee897095f0198453d50f31096ca020e2
Reviewed-on: http://git.am.freescale.net:8181/23352
Tested-by: Review Code-CDREVIEW
Reviewed-by: Yusong Sun
---
arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 19 +++
1 files changed, 19 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index cf18be5..63172de 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -18,6 +18,8 @@ struct serdes_config {
#ifdef CONFIG_PPC_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
+ {0x01, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x02, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x04, {AURORA, AURORA, CPRI6, CPRI5,
@@ -26,6 +28,8 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x06, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x07, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x08, {AURORA, AURORA, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1} },
{0x09, {AURORA, AURORA, CPRI6, CPRI5,
@@ -184,12 +188,17 @@ static struct serdes_config serdes1_cfg_tbl[] = {
CPRI4, CPRI3, NONE, NONE} },
{0x0F, {NONE, NONE, CPRI6, CPRI5,
CPRI4, CPRI3, NONE, NONE} },
+ {0x17, {NONE, NONE,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
{0x18, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
{0x1B, {NONE, NONE,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
+ {0x1D, {NONE, NONE, AURORA, AURORA,
+ NONE, NONE, NONE, NONE} },
{0x1E, {NONE, NONE, AURORA, AURORA,
NONE, NONE, NONE, NONE} },
{0x21, {NONE, NONE, AURORA, AURORA,
@@ -199,19 +208,29 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
+ {0x48, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ SGMII_FM1_DTSEC3, AURORA,
+ NONE, NONE, NONE, NONE} },
{0x49, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
{0x4A, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
SGMII_FM1_DTSEC3, AURORA,
NONE, NONE, NONE, NONE} },
+ {0x6E, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
+ AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x6F, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
{0x70, {SGMII_FM1_DTSEC1, SGMII_FM1_DTSEC2,
AURORA, AURORA, NONE, NONE, NONE, NONE} },
+ {0x99, {PCIE1, PCIE1,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ NONE, NONE, NONE, NONE} },
{0x9A, {PCIE1, PCIE1,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
NONE, NONE, NONE, NONE} },
+ {0x9D, {PCIE1, PCIE1, PCIE1, PCIE1,
+ NONE, NONE, NONE, NONE} },
{0x9E, {PCIE1, PCIE1, PCIE1, PCIE1,
NONE, NONE, NONE, NONE} },
{}
--
1.7.6.GIT
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[U-Boot] [PATCH 3/3] B4860: Add alternate LC VCO serdes protocols support in board file
Add the support of newly added LC VCO SerDes protocols
for configuration of IDT and VSC crossbar
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
Change-Id: I16ad23e2cbea3b0a232a153984d5126bc79ddd26
Reviewed-on: http://git.am.freescale.net:8181/23354
Tested-by: Yusong Sun
Reviewed-by: Yusong Sun
---
board/freescale/b4860qds/b4860qds.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index 975952f..7f2437e 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -385,15 +385,18 @@ int configure_vsc3316_3308(void)
}
break;
+ case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
+ case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@@ -494,10 +497,14 @@ int configure_vsc3316_3308(void)
case 0x9E:
case 0x9A:
case 0x98:
+ case 0xb1:
case 0xb2:
+ case 0x48:
case 0x49:
case 0x4E:
+ case 0x8C:
case 0x8D:
+ case 0x79:
case 0x7A:
num_vsc08_con = NUM_CON_VSC3308;
/* Configure VSC3308 crossbar switch */
@@ -730,19 +737,23 @@ int config_serdes1_refclks(void)
* to 122.88MHz
*/
switch (serdes1_prtcl) {
+ case 0x29:
case 0x2A:
case 0x2C:
case 0x2D:
case 0x2E:
+ case 0x01:
case 0x02:
case 0x04:
case 0x05:
case 0x06:
+ case 0x07:
case 0x08:
case 0x09:
case 0x0A:
case 0x0B:
case 0x0C:
+ case 0x2F:
case 0x30:
case 0x32:
case 0x33:
@@ -860,6 +871,8 @@ int config_serdes2_refclks(void)
#endif
case 0x9E:
case 0x9A:
+ /* fallthrough */
+ case 0xb1:
case 0xb2:
debug("Configuring IDT for PCIe SATA for srds_prctl:%x\n",
serdes2_prtcl);
--
1.7.6.GIT
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[U-Boot] [PATCH] powerpc/b4860: Enable law creation of MAPLE
B4860, B4440, B4420 and B4220 have MAPLE, so enable law creation
for them only
Remove static LAW creation for MAPLE
Signed-off-by: Shaveta Leekha
Signed-off-by: Sandeep Singh
Change-Id: I1d1d6e414617bb45ade5e5ab9134f0464763c034
Reviewed-on: http://git.am.freescale.net:8181/23351
Tested-by: Review Code-CDREVIEW
Reviewed-by: Poonam Aggrwal
Reviewed-by: Yusong Sun
---
board/freescale/b4860qds/b4860qds.c |8
board/freescale/b4860qds/law.c |3 ---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index 34d66d5..975952f 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -915,6 +915,14 @@ int board_early_init_r(void)
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
int flash_esel = find_tlb_idx((void *)flashbase, 1);
int ret;
+ u32 svr = SVR_SOC_VER(get_svr());
+
+ /* Create law for MAPLE only for personalities having MAPLE */
+ if ((svr == SVR_B4860) || (svr == SVR_B4440) ||
+ (svr == SVR_B4420) || (svr == SVR_B4220)) {
+ set_next_law(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M,
+LAW_TRGT_IF_MAPLE);
+ }
/*
* Remap Boot flash + PROMJET region to caching-inhibited
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
index 5b327cc..047c3cb 100644
--- a/board/freescale/b4860qds/law.c
+++ b/board/freescale/b4860qds/law.c
@@ -17,9 +17,6 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
#endif
SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
-#ifdef CONFIG_SYS_MAPLE_MEM_PHYS
- SET_LAW(CONFIG_SYS_MAPLE_MEM_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_MAPLE),
-#endif
#ifdef CONFIG_SYS_DCSRBAR_PHYS
/* Limit DCSR to 32M to access NPC Trace Buffer */
SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_DCSR),
--
1.7.6.GIT
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[U-Boot] [PATCH] drivers/i2c/fsl_i2c: Change CONFIG_I2C_TIMEOUT to 100ms
Some slow I2C devices like Power Monitor(ZM7304) at times do not work well with low timeout value, so I2C bus get stuck during read cycle with this device, changing it to 100ms from 10ms works fine A lot of other i2c drivers like mxc and i2c drivers of BOOTROM also use relax timeouts to give sufficient ticks to work well with slower devices Signed-off-by: Shaveta Leekha Signed-off-by: Poonam Aggrwal --- drivers/i2c/fsl_i2c.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 811033b..7bb1702 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -38,7 +38,7 @@ * generic value. */ #ifndef CONFIG_I2C_TIMEOUT -#define CONFIG_I2C_TIMEOUT 1 +#define CONFIG_I2C_TIMEOUT 10 #endif #define I2C_READ_BIT 1 -- 1.7.6.GIT ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/mpc85xx: Add DSP side awareness for Freescale Heterogeneous SoCs
The code provides framework for heterogeneous multicore chips based on StarCore
and Power Architecture which are chasis-2 compliant, like B4860 and B4420
It will make u-boot recognize all non-ppc cores and peripherals like
SC3900/DSP CPUs, MAPLE, CPRI and print their configuration in u-boot logs.
Example boot logs of B4420:
Clock Configuration:
CPU0:1600 MHz, CPU1:1600 MHz,
DSP CPU0:1200 MHz, DSP CPU1:1200 MHz,
CCB:666.667 MHz,
DDR:800 MHz (1600 MT/s data rate) (Asynchronous), IFC:166.667 MHz
CPRI:600 MHz
MAPLE:600 MHz, MAPLE-ULB:800 MHz, MAPLE-eTVPE:1000 MHz
FMAN1: 666.667 MHz
QMAN: 333.333 MHz
Top level changes include:
(1) Top level CONFIG to identify HETEROGENUOUS clusters
(2) CONFIGS for SC3900/DSP components
(3) Global structure updated for dsp cores and other components
(3) APIs to get DSP num cores and their Mask like:
cpu_dsp_mask, cpu_num_dspcores etc same as that of PowerPC
(5) Code to fetch and print SC cores and other heterogenous
device's frequencies
(6) README added for the same
Signed-off-by: Shaveta Leekha
---
arch/powerpc/cpu/mpc85xx/cpu.c| 25 ++
arch/powerpc/cpu/mpc85xx/speed.c | 133 +
arch/powerpc/cpu/mpc8xxx/cpu.c| 83 ++-
arch/powerpc/include/asm/config_mpc85xx.h | 13 +++-
arch/powerpc/include/asm/processor.h |1 +
doc/README.Heterogeneous-SoCs | 105 +++
include/common.h |2 +
include/e500.h|9 ++
8 files changed, 368 insertions(+), 3 deletions(-)
create mode 100644 doc/README.Heterogeneous-SoCs
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 6274f92..43f5331 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -71,7 +71,9 @@ int checkcpu (void)
#endif /* CONFIG_FSL_CORENET */
unsigned int i, core, nr_cores = cpu_numcores();
+ unsigned int j, dsp_core, dsp_numcores = cpu_num_dspcores();
u32 mask = cpu_mask();
+ u32 dsp_mask = cpu_dsp_mask();
svr = get_svr();
major = SVR_MAJ(svr);
@@ -166,6 +168,16 @@ int checkcpu (void)
printf("CPU%d:%-4s MHz, ", core,
strmhz(buf1, sysinfo.freq_processor[core]));
}
+
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+ for_each_cpu(j, dsp_core, dsp_numcores, dsp_mask) {
+ if (!(j & 3))
+ printf("\n ");
+ printf("DSP CPU%d:%-4s MHz, ", j,
+ strmhz(buf1, sysinfo.freq_processor_dsp[dsp_core]));
+ }
+#endif
+
printf("\n CCB:%-4s MHz,", strmhz(buf1, sysinfo.freq_systembus));
printf("\n");
@@ -224,6 +236,19 @@ int checkcpu (void)
printf(" QE:%-4s MHz\n", strmhz(buf1, sysinfo.freq_qe));
#endif
+#if defined(CONFIG_SYS_CPRI)
+ printf(" ");
+ printf("CPRI:%-4s MHz", strmhz(buf1, sysinfo.freq_cpri));
+#endif
+
+#if defined(CONFIG_SYS_MAPLE)
+ printf("\n ");
+ printf("MAPLE:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple));
+ printf("MAPLE-ULB:%-4s MHz, ", strmhz(buf1, sysinfo.freq_maple_ulb));
+ printf("MAPLE-eTVPE:%-4s MHz\n",
+ strmhz(buf1, sysinfo.freq_maple_etvpe));
+#endif
+
#ifdef CONFIG_SYS_DPAA_FMAN
for (i = 0; i < CONFIG_SYS_NUM_FMAN; i++) {
printf(" FMAN%d: %s MHz\n", i + 1,
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 3236f6a..9a2b487 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -35,6 +35,7 @@ void get_sys_info(sys_info_t *sys_info)
volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR);
unsigned int cpu;
#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+ unsigned int dsp_cpu;
int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS;
#endif
@@ -68,6 +69,7 @@ void get_sys_info(sys_info_t *sys_info)
[14] = 4, /* CC4 PPL / 4 */
};
uint i, freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
+ uint rcw_tmp1, rcw_tmp2;
#if !defined(CONFIG_FM_PLAT_CLK_DIV) || !defined(CONFIG_PME_PLAT_CLK_DIV)
uint rcw_tmp;
#endif
@@ -164,6 +166,16 @@ void get_sys_info(sys_info_t *sys_info)
sys_info->freq_processor[cpu] =
freq_c_pll[cplx_pll] / core_cplx_pll_div[c_pll_sel];
}
+
+ for_each_cpu(i, dsp_cpu, cpu_num_dspcores(), cpu_dsp_mask()) {
+ int cluster = fsl_qoriq_dsp_core_to_cluster(dsp_cpu);
+ u32 c_pll_sel = (in_be32(&clk->clkcsr[cluster].clkcncsr) >> 27)
+ & 0xf;
+ u32 cplx_pll = core_cplx_PLL[c
[U-Boot] [PATCH] B4860QDS: Enable mac command support
One of the I2C EEPROM is used to store/save and edit mac addresses of ports. this patch add required CONFIG to support the same Signed-off-by: Shaveta Leekha --- include/configs/B4860QDS.h |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 6deb784..9063c57 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -227,6 +227,7 @@ unsigned long get_board_ddr_clk(void); #endif /* EEPROM */ +#define CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID #define CONFIG_SYS_EEPROM_BUS_NUM 0 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 -- 1.7.6.GIT ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH][v2] powerpc/b4860: Updated default hwconfig so as to enable only
CPC1 is not being enabled by default as powerpc is supposed to use only CPC2. Though by editing hwconfig en_cpc option, CPC1 can also be enabled Signed-off-by: Shaveta Leekha Signed-off-by: Sandeep Singh --- Tested on B4860QDS Changes in V2: Inserted "en_cpc:cpc2" at right place, not to broke into the settings for DDR include/configs/B4860QDS.h | 11 +-- 1 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 953d06b..6deb784 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -819,9 +819,16 @@ unsigned long get_board_ddr_clk(void); #define __USB_PHY_TYPE ulpi +#ifdef CONFIG_PPC_B4860 +#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ + "bank_intlv=cs0_cs1;" \ + "en_cpc:cpc2;" +#else +#defineHWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" +#endif + #defineCONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=null," \ - "bank_intlv=cs0_cs1;" \ + HWCONFIG\ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -- 1.7.6.GIT ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/b4860: Updated default hwconfig so as to enable only CPC2
CPC1 is not being enabled by default as powerpc is supposed to use only CPC2. Though by editing hwconfig en_cpc option, CPC1 can also be enabled Signed-off-by: Shaveta Leekha Signed-off-by: Sandeep Singh --- include/configs/B4860QDS.h | 11 +-- 1 files changed, 9 insertions(+), 2 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 953d06b..6deb784 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -819,9 +819,16 @@ unsigned long get_board_ddr_clk(void); #define __USB_PHY_TYPE ulpi +#ifdef CONFIG_PPC_B4860 +#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null," \ + "bank_intlv=cs0_cs1;" \ + "en_cpc:cpc2;" +#else +#defineHWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;" +#endif + #defineCONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=null," \ - "bank_intlv=cs0_cs1;" \ + HWCONFIG\ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ -- 1.7.6.GIT ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/chassis2: Configure and enable L2 cache for PPC clusters only
Signed-off-by: Poonam Aggrwal Signed-off-by: Shaveta Leekha --- arch/powerpc/cpu/mpc85xx/cpu_init.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index ecde00b..7970684 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -547,7 +547,8 @@ int enable_cluster_l2(void) u32 idx = (cluster >> (j*8)) & TP_CLUSTER_INIT_MASK; u32 type = in_be32(&gur->tp_ityp[idx]); - if (type & TP_ITYP_AV) + if ((type & TP_ITYP_AV) && + TP_ITYP_TYPE(type) == TP_ITYP_TYPE_PPC) cluster_valid = 1; } -- 1.7.6.GIT ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/b4860: Updated default hwconfig so as to enable only CPC2
CPC1 is not being enabled by default as powerpc is supposed to use only CPC2. Signed-off-by: Shaveta Leekha Signed-off-by: Sandeep Singh --- include/configs/B4860QDS.h |8 +++- 1 files changed, 7 insertions(+), 1 deletions(-) diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h index 1af9ba6..53fdac7 100644 --- a/include/configs/B4860QDS.h +++ b/include/configs/B4860QDS.h @@ -820,8 +820,14 @@ unsigned long get_board_ddr_clk(void); #define __USB_PHY_TYPE ulpi +#ifdef CONFIG_PPC_B4860 +#define HWCONFIG "hwconfig=fsl_ddr:ctlr_intlv=null,en_cpc:cpc2," +#else +#defineHWCONFIG"hwconfig=fsl_ddr:ctlr_intlv=null," +#endif + #defineCONFIG_EXTRA_ENV_SETTINGS \ - "hwconfig=fsl_ddr:ctlr_intlv=null," \ + HWCONFIG\ "bank_intlv=cs0_cs1;" \ "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\ "netdev=eth0\0" \ -- 1.7.6.GIT ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/mpc85xx: Enabling CPC conditionally based on hwconfig options
If hwconfig does not contains "en_cpc" then by default all cpcs are enabled
If this config is defined then only those individual cpcs which are defined
in the subargument of "en_cpc" will be enabled e.g en_cpc:cpc1,cpc2; (this
will enable cpc1 and cpc2) or en_cpc:cpc2; (this enables just cpc2)
Signed-off-by: Shaveta Leekha
Signed-off-by: Sandeep Singh
---
arch/powerpc/cpu/mpc85xx/cpu_init.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 78316a6..ecde00b 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -254,11 +254,38 @@ static void enable_tdm_law(void)
static void enable_cpc(void)
{
int i;
+ int ret;
u32 size = 0;
cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR;
+ char buffer[HWCONFIG_BUFFER_SIZE];
+ char cpc_subarg[16];
+ bool have_hwconfig = false;
+ int cpc_args = 0;
+
+ /*
+* Extract hwconfig from environment since environmen
+* is not setup properly yet
+*/
+ ret = getenv_f("hwconfig", buffer, sizeof(buffer));
+ if (ret > 0) {
+ /*
+* If "en_cpc" is not defined in hwconfig then by default all
+* cpcs are enable. If this config is defined then individual
+* cpcs which have to be enabled should also be defined.
+* e.g en_cpc:cpc1,cpc2;
+*/
+ if (hwconfig_f("en_cpc", buffer))
+ have_hwconfig = true;
+ }
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) {
+ if (have_hwconfig) {
+ sprintf(cpc_subarg, "cpc%u", i + 1);
+ cpc_args = hwconfig_sub_f("en_cpc", cpc_subarg, buffer);
+ if (cpc_args == 0)
+ continue;
+ }
u32 cpccfg0 = in_be32(&cpc->cpccfg0);
size += CPC_CFG0_SZ_K(cpccfg0);
--
1.7.6.GIT
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[U-Boot] [PATCH] powerpc/serdes: Add the workaround for erratum A-007186
SerDes PLL is calibrated at reset. When the junction temperature
delta from the time the PLL is calibrated exceeds +56C/-66C,
jitter may increase and can cause PLL to unlock.
This workaround overwrite the SerDes registers with new values,
to calibrate SerDes registers.
These values are known to work fine for all temperature ranges.
This workaround is valid for B4, T4 and T2 platforms, so
added in their config.
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |3 +
arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 147
arch/powerpc/include/asm/config_mpc85xx.h |6 +
arch/powerpc/include/asm/immap_85xx.h | 33 +-
4 files changed, 187 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 3d37a76..0859151 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -266,6 +266,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
puts("Work-around for Erratum USB14 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ puts("Work-around for Erratum A007186 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A006593
puts("Work-around for Erratum A006593 enabled\n");
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
index 70e09ea..add2cac 100644
--- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c
@@ -147,12 +147,42 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
return -ENODEV;
}
+#define BC3_SHIFT 9
+#define DC3_SHIFT 6
+#define FC3_SHIFT 0
+#define BC2_SHIFT 19
+#define DC2_SHIFT 16
+#define FC2_SHIFT 10
+#define BC1_SHIFT 29
+#define DC1_SHIFT 26
+#define FC1_SHIFT 20
+#define BC_MASK0x1
+#define DC_MASK0x7
+#define FC_MASK0x3F
+
+#define FUSE_VAL_MASK 0x0003
+#define FUSE_VAL_SHIFT 30
+#define CR0_DCBIAS_SHIFT 5
+#define CR1_FCAP_SHIFT 15
+#define CR1_BCAP_SHIFT 29
+#define FCAP_MASK 0x001F8000
+#define BCAP_MASK 0x2000
+#define BCAP_OVD_MASK 0x1000
+#define BYP_CAL_MASK 0x0200
+
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift)
{
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u64 serdes_prtcl_map = 0;
u32 cfg;
int lane;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ ccsr_sfp_regs_t __iomem *sfp_regs = (void *)(CONFIG_SYS_SFP_ADDR);
+ u32 pll_num, pll_status, bc, dc, fc, pll_cr_upd, pll_cr0, pll_cr1;
+ u32 bc_status, fc_status, dc_status, pll_sr2;
+ serdes_corenet_t __iomem *srds_regs = (void *)sd_addr;
+ u32 sfp_spfr0, sel;
+#endif
cfg = in_be32(&gur->rcwsr[4]) & sd_prctl_mask;
/* Is serdes enabled at all? */
@@ -161,6 +191,123 @@ u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask,
u32 sd_prctl_shift)
return 0;
}
+/* Erratum A-007186
+ * Freescale Scratch Pad Fuse Register n (SFP_FSPFR0)
+ * The workaround requires factory pre-set SerDes calibration values to be
+ * read from a fuse block(Freescale Scratch Pad Fuse Register SFP_FSPFR0)
+ * These values have been shown to work across the
+ * entire temperature range for all SerDes. These values are then written into
+ * the SerDes registers to calibrate the SerDes PLL.
+ *
+ * This workaround for the protocols and rates that only have the Ring VCO.
+ */
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007186
+ sfp_spfr0 = in_be32(&sfp_regs->fsl_spfr0);
+ debug("A007186: sfp_spfr0= %x\n", sfp_spfr0);
+
+ sel = (sfp_spfr0 >> FUSE_VAL_SHIFT) & FUSE_VAL_MASK;
+
+ if (sel == 0x01 || sel == 0x02) {
+ for (pll_num = 0; pll_num < SRDS_MAX_BANK; pll_num++) {
+ pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0);
+ debug("A007186: pll_num=%x pllcr0=%x\n",
+ pll_num, pll_status);
+ /* STEP 1 */
+ /* Read factory pre-set SerDes calibration values
+* from fuse block(SFP scratch register-sfp_spfr0)
+*/
+ switch (pll_status & SRDS_PLLCR0_FRATE_SEL_MASK) {
+ case SRDS_PLLCR0_FRATE_SEL_3_0:
+ case SRDS_PLLCR0_FRATE_SEL_3_072:
+ debug("A007186: 3.0/3.072 protocol rate\n");
+ bc = (sfp_spfr0 >> BC1_SHIFT) & BC_MASK;
+
[U-Boot] [PATCH] powerpc/mpc85xx: Added B4460 support
B4460 differs from B4860 only in number of CPU cores,
hence used existing support for B4860.
B4460 has 2 PPC cores whereas B4860 has 4 PPC cores.
Signed-off-by: Shaveta Leekha
Signed-off-by: Sandeep Singh
Signed-off-by: Poonam Aggrwal
---
arch/powerpc/cpu/mpc8xxx/cpu.c |1 +
arch/powerpc/include/asm/processor.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 35795c4..216418b 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -64,6 +64,7 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T4160, T4160, 0),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
+ CPU_TYPE_ENTRY(B4460, B4460, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
diff --git a/arch/powerpc/include/asm/processor.h
b/arch/powerpc/include/asm/processor.h
index 72f30fe..5d7d26e 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1116,6 +1116,7 @@
#define SVR_C293 0x850030
#define SVR_B4860 0X868000
#define SVR_G4860 0x868001
+#define SVR_B4460 0x868003
#define SVR_G4060 0x868003
#define SVR_B4440 0x868100
#define SVR_G4440 0x868101
--
1.7.6.GIT
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[U-Boot] [PATCH v2] drivers/i2c/fsl_i2c: modify i2c_read to handle multi-byte write
Most of the I2C slaves support accesses in the typical style
that is : read/write series of bytes at particular address offset.
These transactions look like:"
(1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"
However there are certain devices which support accesses in
terms of the transactions as follows:
(2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
Here Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.
Type (1) transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.
To handle type (2) along with type (1) transactions,
i2c_read() function has been modified.
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
Changes for v2:
Incorporated review comments of v1
Add driver's path in the subject line to make it more clear
(older patch with different subject line has been discarded
http://patchwork.ozlabs.org/patch/336911/)
drivers/i2c/fsl_i2c.c | 41 ++---
1 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 291ad94..aa159f8 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -423,18 +423,45 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
int alen, u8 *data,
struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i = -1; /* signal error */
u8 *a = (u8*)&addr;
+ int len = alen * -1;
if (i2c_wait4bus(adap) < 0)
return -1;
- if ((!length || alen > 0)
- && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
- && __i2c_write(adap, &a[4 - alen], alen) == alen)
- i = 0; /* No error so far */
+ /* To handle the need of I2C devices that require to write few bytes
+* (more than 4 bytes of address as in the case of else part)
+* of data before reading, Negative equivalent of length(bytes to write)
+* is passed, but used the +ve part of len for writing data
+*/
+ if (alen < 0) {
+ /* Generate a START and send the Address and
+* the Tx Bytes to the slave.
+* "START: Address: Write bytes data[len]"
+* IF part supports writing any number of bytes in contrast
+* to the else part, which supports writing address offset
+* of upto 4 bytes only.
+* bytes that need to be written are passed in
+* "data", which will eventually keep the data READ,
+* after writing the len bytes out of it
+*/
+ if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
+ i = __i2c_write(adap, data, len);
+
+ if (i != len)
+ return -1;
- if (length &&
- i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
- i = __i2c_read(adap, data, length);
+ if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
+ i = __i2c_read(adap, data, length);
+ } else {
+ if ((!length || alen > 0) &&
+ i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
+ __i2c_write(adap, &a[4 - alen], alen) == alen)
+ i = 0; /* No error so far */
+
+ if (length &&
+ i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
+ i = __i2c_read(adap, data, length);
+ }
writeb(I2C_CR_MEN, &device->cr);
--
1.7.6.GIT
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[U-Boot] [PATCH 2/2] board/b4qds: VID support
The fuse status register provides the values from on-chip
voltage ID efuses programmed at the factory.
These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values
into the appropriate commands to set the voltage output
value of an external voltage regulator.
B4860QDS has a PowerOne ZM7300 programmable digital Power
Manager which is programmed as per the value read from
the fuses.
Reference for this code is taken from t4qds VID implementation.
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
board/freescale/b4860qds/b4860qds.c | 240 +++
include/configs/B4860QDS.h | 11 ++
2 files changed, 251 insertions(+), 0 deletions(-)
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index d9c88a0..b2d5378 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -23,6 +23,7 @@
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
#include "../common/idt8t49n222a_serdes_clk.h"
+#include "../common/zm7300.h"
#include "b4860qds.h"
#include "b4860qds_qixis.h"
#include "b4860qds_crossbar_con.h"
@@ -94,6 +95,238 @@ int select_i2c_ch_pca(u8 ch)
return 0;
}
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+
+static inline int read_voltage(void)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+
+static int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid;
+ int vdd_target, vdd_last;
+ int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
+ int ret;
+ unsigned int orig_i2c_speed;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 1, /* 1.V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ }
+ vdd_target = vdd[vid];
+ debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
+ vid, vdd_target/10);
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv("b4qds_vdd_mv");
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= 819 &
[U-Boot] [PATCH 1/2] board/freescale/common: ZM7300 driver
Adds Support for PowerOne ZM7300 voltage regulator.
This device is available on some Freescale Boards like B4860QDS
and has to be programmed to adjust the voltage on the board.
The device is accessible via I2C interface.
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
board/freescale/common/Makefile |1 +
board/freescale/common/zm7300.c | 235 +++
board/freescale/common/zm7300.h | 22
3 files changed, 258 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/common/zm7300.c
create mode 100644 board/freescale/common/zm7300.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index f6a0879..22b57cc 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_P5020DS) += ics307_clk.o
obj-$(CONFIG_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR)+= vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
+obj-$(CONFIG_ZM7300) += zm7300.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c
new file mode 100644
index 000..be5953a
--- /dev/null
+++ b/board/freescale/common/zm7300.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power-One ZM7300 DPM */
+#include "zm7300.h"
+
+#define DPM_WP 0x96
+#define WRP_OPCODE 0x01
+#define WRM_OPCODE 0x02
+#define RRP_OPCODE 0x11
+
+#define DPM_SUCCESS 0x01
+#define DPM_EXEC_FAIL 0x00
+
+static const uint16_t hex_to_1_10mv[] = {
+ 5000,
+ 5125,
+ 5250,
+ 5375,
+ 5500,
+ 5625,
+ 5750,
+ 5875,
+ 6000,
+ 6125,
+ 6250,
+ 6375,
+ 6500,
+ 6625,
+ 6750,
+ 6875,
+ 7000,
+ 7125,
+ 7250,
+ 7375,
+ 7500,
+ 7625,
+ 7750,
+ 7875,
+ 8000,
+ 8125,
+ 8250,
+ 8375,
+ 8500,
+ 8625,
+ 8750,
+ 8875,
+ 9000,
+ 9125,
+ 9250,
+ 9375,
+ 9500, /* 0.95mV */
+ 9625,
+ 9750,
+ 9875,
+ 1, /* 1.0V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 11125,
+ 11250,
+ 11375,
+ 11500,
+ 11625,
+ 11750,
+ 11875,
+ 12000,
+ 12125,
+ 12250,
+ 12375,
+ 0, /* reserved */
+};
+
+
+/* Read Data d from Register r of POL p */
+u8 dpm_rrp(uchar r)
+{
+ u8 ret[5];
+
+ ret[0] = RRP_OPCODE;
+ /* POL is 0 */
+ ret[1] = 0;
+ ret[2] = r;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
+ if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("RRP_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into DPM register r (RAM) */
+int dpm_wrm(u8 r, u8 d)
+{
+ u8 ret[5];
+
+ ret[0] = WRM_OPCODE;
+ ret[1] = r;
+ ret[2] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRM_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into Register r of POL(s) a */
+int dpm_wrp(u8 r, u8 d)
+{
+ u8 ret[7];
+
+ ret[0] = WRP_OPCODE;
+ /* only POL0 is present */
+ ret[1] = 0x01;
+ ret[2] = 0x00;
+ ret[3] = 0x00;
+ ret[4] = 0x00;
+ ret[5] = r;
+ ret[6] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRP_OPCODE returned success data is %x\n", ret[0]);
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+/* Uses the DPM command RRP */
+u8 zm_read(uchar reg)
+{
+ u8 d;
+ d = dpm_rrp(reg);
+ return d;
+}
+
+/* ZM_write --
+ Steps:
+ a. Write data to the register
+ b. Read data from register and compare to written value
+ c. Return return_code & voltage_read
+*/
+u8 zm_write(u8 reg, u8 data)
+{
+ u8 d;
+
+ /* write data to register */
+ dpm_wrp(reg, data);
+
+ /* read register and compare to written value */
+ d = dpm_rrp(reg);
+ if (d != data) {
+ printf("zm_write : Comparison register data failed\n");
+ return -1;
+ }
+
+ return d;
+}
+
+/* zm_write_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_write_voltage(int voltage)
+{
+ u8 reg = 0x7, vid;
+ uint16_t voltage_
[U-Boot] [PATCH] drivers/i2c/fsl_i2c: modify i2c_read to handle multi-byte write
Most of the I2C slaves support accesses in the typical style
that is : read/write series of bytes at particular address offset.
These transactions look like:"
(1) START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"
However there are certain devices which support accesses in
terms of the transactions as follows:
(2) "START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
Here Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.
Type (1) transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.
To handle type (2) along with type (1) transactions,
i2c_read() function has been modified.
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
drivers/i2c/fsl_i2c.c | 41 ++---
1 files changed, 34 insertions(+), 7 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 291ad94..aa159f8 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -423,18 +423,45 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
int alen, u8 *data,
struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
int i = -1; /* signal error */
u8 *a = (u8*)&addr;
+ int len = alen * -1;
if (i2c_wait4bus(adap) < 0)
return -1;
- if ((!length || alen > 0)
- && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
- && __i2c_write(adap, &a[4 - alen], alen) == alen)
- i = 0; /* No error so far */
+ /* To handle the need of I2C devices that require to write few bytes
+* (more than 4 bytes of address as in the case of else part)
+* of data before reading, Negative equivalent of length(bytes to write)
+* is passed, but used the +ve part of len for writing data
+*/
+ if (alen < 0) {
+ /* Generate a START and send the Address and
+* the Tx Bytes to the slave.
+* "START: Address: Write bytes data[len]"
+* IF part supports writing any number of bytes in contrast
+* to the else part, which supports writing address offset
+* of upto 4 bytes only.
+* bytes that need to be written are passed in
+* "data", which will eventually keep the data READ,
+* after writing the len bytes out of it
+*/
+ if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
+ i = __i2c_write(adap, data, len);
+
+ if (i != len)
+ return -1;
- if (length &&
- i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
- i = __i2c_read(adap, data, length);
+ if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
+ i = __i2c_read(adap, data, length);
+ } else {
+ if ((!length || alen > 0) &&
+ i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
+ __i2c_write(adap, &a[4 - alen], alen) == alen)
+ i = 0; /* No error so far */
+
+ if (length &&
+ i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
+ i = __i2c_read(adap, data, length);
+ }
writeb(I2C_CR_MEN, &device->cr);
--
1.7.6.GIT
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[U-Boot] [PATCH 2/2] b4qds: VID support
The fuse status register provides the values from on-chip voltage ID efuses
programmed at the factory. These values define the voltage requirements for
the chip. u-boot reads FUSESR and translates the values into the
appropriate commands to set the voltage output value of an external
voltage regulator.
B4860QDS has a PowerOne ZM7300 programmable digital Power Manager which
is programmed as per the value read from the fuses.
Reference for this code is taken from t4qds VID implementation.
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
board/freescale/b4860qds/b4860qds.c | 240 +++
include/configs/B4860QDS.h | 11 ++
2 files changed, 251 insertions(+), 0 deletions(-)
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index d9c88a0..b2d5378 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -23,6 +23,7 @@
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
#include "../common/idt8t49n222a_serdes_clk.h"
+#include "../common/zm7300.h"
#include "b4860qds.h"
#include "b4860qds_qixis.h"
#include "b4860qds_crossbar_con.h"
@@ -94,6 +95,238 @@ int select_i2c_ch_pca(u8 ch)
return 0;
}
+/*
+ * read_voltage from sensor on I2C bus
+ * We use average of 4 readings, waiting for 532us befor another reading
+ */
+#define WAIT_FOR_ADC 532 /* wait for 532 microseconds for ADC */
+#define NUM_READINGS 4 /* prefer to be power of 2 for efficiency */
+
+static inline int read_voltage(void)
+{
+ int i, ret, voltage_read = 0;
+ u16 vol_mon;
+
+ for (i = 0; i < NUM_READINGS; i++) {
+ ret = i2c_read(I2C_VOL_MONITOR_ADDR,
+ I2C_VOL_MONITOR_BUS_V_OFFSET, 1, (void *)&vol_mon, 2);
+ if (ret) {
+ printf("VID: failed to read core voltage\n");
+ return ret;
+ }
+ if (vol_mon & I2C_VOL_MONITOR_BUS_V_OVF) {
+ printf("VID: Core voltage sensor error\n");
+ return -1;
+ }
+ debug("VID: bus voltage reads 0x%04x\n", vol_mon);
+ /* LSB = 4mv */
+ voltage_read += (vol_mon >> I2C_VOL_MONITOR_BUS_V_SHIFT) * 4;
+ udelay(WAIT_FOR_ADC);
+ }
+ /* calculate the average */
+ voltage_read /= NUM_READINGS;
+
+ return voltage_read;
+}
+
+static int adjust_vdd(ulong vdd_override)
+{
+ int re_enable = disable_interrupts();
+ ccsr_gur_t __iomem *gur =
+ (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ u32 fusesr;
+ u8 vid;
+ int vdd_target, vdd_last;
+ int existing_voltage, temp_voltage, voltage; /* all in 1/10 mV */
+ int ret;
+ unsigned int orig_i2c_speed;
+ unsigned long vdd_string_override;
+ char *vdd_string;
+ static const uint16_t vdd[32] = {
+ 0, /* unused */
+ 9875, /* 0.9875V */
+ 9750,
+ 9625,
+ 9500,
+ 9375,
+ 9250,
+ 9125,
+ 9000,
+ 8875,
+ 8750,
+ 8625,
+ 8500,
+ 8375,
+ 8250,
+ 8125,
+ 1, /* 1.V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 0, /* reserved */
+ };
+ struct vdd_drive {
+ u8 vid;
+ unsigned voltage;
+ };
+
+ ret = select_i2c_ch_pca(I2C_MUX_CH_VOL_MONITOR);
+ if (ret) {
+ printf("VID: I2c failed to switch channel\n");
+ ret = -1;
+ goto exit;
+ }
+
+ /* get the voltage ID from fuse status register */
+ fusesr = in_be32(&gur->dcfg_fusesr);
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_VID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_VID_MASK;
+ if (vid == FSL_CORENET_DCFG_FUSESR_VID_MASK) {
+ vid = (fusesr >> FSL_CORENET_DCFG_FUSESR_ALTVID_SHIFT) &
+ FSL_CORENET_DCFG_FUSESR_ALTVID_MASK;
+ }
+ vdd_target = vdd[vid];
+ debug("VID:Reading from from fuse,vid=%x vdd is %dmV\n",
+ vid, vdd_target/10);
+
+ /* check override variable for overriding VDD */
+ vdd_string = getenv("b4qds_vdd_mv");
+ if (vdd_override == 0 && vdd_string &&
+ !strict_strtoul(vdd_string, 10, &vdd_string_override))
+ vdd_override = vdd_string_override;
+ if (vdd_override >= 819 &
[U-Boot] [PATCH] 2c: modify i2c_read API to handle multi-bytes writes
Most of the I2C slaves support accesses in the typical style
viz.read/write series of bytes at particular address offset.
These transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.
The transactions look like:"
START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"
However there are certain devices which support accesses in
terms of the transactions as follows:
"START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
The Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.
i2c_read() function has been modified to handle
both types of transactions:
the one that writes only offset/address before read and other that
writes some bytes(more than 4 bytes) before read
To handle the case:
Negative equivalent of length has been passed and
interpreted accordinglt and txdata is being passed in
rxdata buffer
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
drivers/i2c/fsl_i2c.c | 40 +++-
1 files changed, 31 insertions(+), 9 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 291ad94..14c66d0 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -424,17 +424,39 @@ fsl_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
int alen, u8 *data,
int i = -1; /* signal error */
u8 *a = (u8*)&addr;
- if (i2c_wait4bus(adap) < 0)
- return -1;
+ if (alen < 0) {
+ int len = alen * -1;
+ if (i2c_wait4bus(adap) < 0)
+ return -1;
+
+ /* Generate a START and send the Address and
+* the Tx Bytes to the slave.
+* "START: Address: Write bytes wdata[wlength]"
+* It supports writing any number of bytes in contrast
+* to the else part, which supports writing address offset
+* of upto 4 bytes only.
+*/
+ if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
+ i = __i2c_write(adap, data, len);
+
+ if (i != len)
+ return -1;
+
+ if (length && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
+ i = __i2c_read(adap, data, length);
+ } else {
+ if (i2c_wait4bus(adap) < 0)
+ return -1;
- if ((!length || alen > 0)
- && i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0
- && __i2c_write(adap, &a[4 - alen], alen) == alen)
- i = 0; /* No error so far */
+ if ((!length || alen > 0) &&
+ i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0 &&
+ __i2c_write(adap, &a[4 - alen], alen) == alen)
+ i = 0; /* No error so far */
- if (length &&
- i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
- i = __i2c_read(adap, data, length);
+ if (length &&
+ i2c_write_addr(adap, dev, I2C_READ_BIT, alen ? 1 : 0) != 0)
+ i = __i2c_read(adap, data, length);
+ }
writeb(I2C_CR_MEN, &device->cr);
--
1.7.6.GIT
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] ZM7300 driver
Adds Support for PowerOne ZM7300 voltage regulator.
This device is available on some Freescale Boards like B4860QDS
and has to be programmed to adjust the voltage on the board.
The device is accessible via I2C interface.
Signed-off-by: Shaveta Leekha
Signed-off-by: Poonam Aggrwal
---
board/freescale/common/Makefile |1 +
board/freescale/common/zm7300.c | 235 +++
board/freescale/common/zm7300.h | 22
3 files changed, 258 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/common/zm7300.c
create mode 100644 board/freescale/common/zm7300.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index f6a0879..22b57cc 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -48,6 +48,7 @@ obj-$(CONFIG_P5020DS) += ics307_clk.o
obj-$(CONFIG_P5040DS) += ics307_clk.o
obj-$(CONFIG_VSC_CROSSBAR)+= vsc3316_3308.o
obj-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
+obj-$(CONFIG_ZM7300) += zm7300.o
# deal with common files for P-series corenet based devices
obj-$(CONFIG_P2041RDB) += p_corenet/
diff --git a/board/freescale/common/zm7300.c b/board/freescale/common/zm7300.c
new file mode 100644
index 000..ed79b43
--- /dev/null
+++ b/board/freescale/common/zm7300.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/* Power-One ZM7300 DPM */
+#include "zm7300.h"
+
+#define DPM_WP 0x96
+#define WRP_OPCODE 0x01
+#define WRM_OPCODE 0x02
+#define RRP_OPCODE 0x11
+
+#define DPM_SUCCESS 0x01
+#define DPM_EXEC_FAIL 0x00
+
+static const uint16_t hex_to_1_10mv[] = {
+ 5000,
+ 5125,
+ 5250,
+ 5375,
+ 5500,
+ 5625,
+ 5750,
+ 5875,
+ 6000,
+ 6125,
+ 6250,
+ 6375,
+ 6500,
+ 6625,
+ 6750,
+ 6875,
+ 7000,
+ 7125,
+ 7250,
+ 7375,
+ 7500,
+ 7625,
+ 7750,
+ 7875,
+ 8000,
+ 8125,
+ 8250,
+ 8375,
+ 8500,
+ 8625,
+ 8750,
+ 8875,
+ 9000,
+ 9125,
+ 9250,
+ 9375,
+ 9500, /* 0.95mV */
+ 9625,
+ 9750,
+ 9875,
+ 1, /* 1.0V */
+ 10125,
+ 10250,
+ 10375,
+ 10500,
+ 10625,
+ 10750,
+ 10875,
+ 11000,
+ 11125,
+ 11250,
+ 11375,
+ 11500,
+ 11625,
+ 11750,
+ 11875,
+ 12000,
+ 12125,
+ 12250,
+ 12375,
+ 0, /* reserved */
+};
+
+
+/* Read Data d from Register r of POL p */
+u8 dpm_rrp(uchar r)
+{
+ u8 dpm_rrp[5], ret[5];
+
+ ret[0] = RRP_OPCODE;
+ /* POL is 0 */
+ ret[1] = 0;
+ ret[2] = r;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 2);
+ if (ret[1] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("RRP_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into DPM register r (RAM) */
+int dpm_wrm(u8 r, u8 d)
+{
+ u8 dpm_wrm[5], ret[5];
+
+ ret[0] = WRM_OPCODE;
+ ret[1] = r;
+ ret[2] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -3, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRM_OPCODE returned success data is %x\n", ret[0]);
+ return ret[0];
+ } else {
+ return -1;
+ }
+}
+
+/* Write Data d into Register r of POL(s) a */
+int dpm_wrp(u8 r, u8 d)
+{
+ u8 dpm_wrp[7], ret[7];
+
+ ret[0] = WRP_OPCODE;
+ /* only POL0 is present */
+ ret[1] = 0x01;
+ ret[2] = 0x00;
+ ret[3] = 0x00;
+ ret[4] = 0x00;
+ ret[5] = r;
+ ret[6] = d;
+ i2c_read(I2C_DPM_ADDR, 0, -7, ret, 1);
+ if (ret[0] == DPM_SUCCESS) { /* the DPM returned success as status */
+ debug("WRP_OPCODE returned success data is %x\n", ret[0]);
+ return 0;
+ } else {
+ return -1;
+ }
+}
+
+/* Uses the DPM command RRP */
+u8 zm_read(uchar reg)
+{
+ u8 d;
+ d = dpm_rrp(reg);
+ return d;
+}
+
+/* ZM_write --
+ Steps:
+ a. Write data to the register
+ b. Read data from register and compare to written value
+ c. Return return_code & voltage_read
+*/
+u8 zm_write(u8 reg, u8 data)
+{
+ u8 d;
+
+ /* write data to register */
+ dpm_wrp(reg, data);
+
+ /* read register and compare to written value */
+ d = dpm_rrp(reg);
+ if (d != data) {
+ printf("zm_write : Comparison register data failed\n");
+ return -1;
+ }
+
+ return d;
+}
+
+/* zm_write_out_voltage
+ * voltage in 1/10 mV
+ */
+int zm_write_voltage(int voltage)
+{
+ u8 reg
[U-Boot] [PATCH] fsl_i2c: Add write-then-read transaction interface for I2C slave
Most of the I2C slaves support accesses in the typical style
viz.read/write series of bytes at particular address offset.
These transactions are currently supportd in the
i2c driver using i2c_read and i2c_write APIs. I2C EEPROMs,
RTC, etc fall in this category.
The transactions look like:"
START:Address:Tx:Offset:RESTART:Address[0..4]:Tx/Rx:data[0..n]:STOP"
However there are certain devices which support accesses in
terms of the transactions as follows:
"START:Address:Tx:Txdata[0..n1]:Clock_stretching:
RESTART:Address:Rx:data[0..n2]"
The Txdata is typically a command and some associated data,
similarly Rxdata could be command status plus some data received
as a response to the command sent.
i2c_write_read() function provides support for such transactions
(multiple bytes write followed by read)
Signed-off-by: Poonam Aggrwal
Signed-off-by: Shaveta Leekha
---
drivers/i2c/fsl_i2c.c | 64 ++-
drivers/i2c/i2c_core.c |7 +
include/i2c.h | 19 ++---
3 files changed, 78 insertions(+), 12 deletions(-)
diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c
index 291ad94..838c1b1 100644
--- a/drivers/i2c/fsl_i2c.c
+++ b/drivers/i2c/fsl_i2c.c
@@ -472,6 +472,56 @@ fsl_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
int alen,
return -1;
}
+/* To perform any generic transaction on a I2C slave which involves
+
+ START: Address: Write bytes(cmd + data): clock extension:
+ RESTART: Address: Read bytes (data + status): STOP
+
+ This is different from standard I2C devices which are supported
+ in existing i2c_read and i2c_write functions.
+ */
+int
+fsl_i2c_write_read(struct i2c_adapter *adap, u8 dev, u8 *wdata, int wlength,
+ u8 *rdata, int rlength)
+{
+ struct fsl_i2c *device = (struct fsl_i2c *)i2c_dev[adap->hwadapnr];
+
+ int i = -1; /* signal error */
+
+ if (i2c_wait4bus(adap))
+ return -1;
+
+/* Generate a START and send the Address and the Tx Bytes to the slave.
+ * "START: Address: Write bytes wdata[wlength]"
+ */
+ if (i2c_write_addr(adap, dev, I2C_WRITE_BIT, 0) != 0)
+ i = __i2c_write(adap, wdata, wlength);
+
+ if (i != wlength)
+ return -1;
+
+/* Now issue a READ by generating a RESTART condition
+ * "RESTART: Address: Read bytes rdata[rlength]"
+ * Some slaves may also do clock stretching and keep the SCL low until
+ * they finish some command processing at their end. The I2C controller
+ * will wait for the clock stretching period to get over before generating
+ * the RESTART condition on the bus.
+ */
+ if (rlength
+ && i2c_write_addr(adap, dev, I2C_READ_BIT, 1) != 0)
+ i = __i2c_read(adap, rdata, rlength);
+
+/* Generate STOP */
+ writeb(I2C_CR_MEN, &device->cr);
+
+ if (i2c_wait4bus(adap)) /* Wait until STOP */
+ debug("i2c_write_read: wait4bus timed out\n");
+
+ if (i != rlength)
+ return -1;
+
+ return 0;
+}
static int
fsl_i2c_probe(struct i2c_adapter *adap, uchar chip)
@@ -503,12 +553,12 @@ static unsigned int fsl_i2c_set_bus_speed(struct
i2c_adapter *adap,
* Register fsl i2c adapters
*/
U_BOOT_I2C_ADAP_COMPLETE(fsl_0, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
-fsl_i2c_write, fsl_i2c_set_bus_speed,
-CONFIG_SYS_FSL_I2C_SPEED, CONFIG_SYS_FSL_I2C_SLAVE,
-0)
-#ifdef CONFIG_SYS_FSL_I2C2_OFFSET
+fsl_i2c_write, fsl_i2c_write_read,
+fsl_i2c_set_bus_speed, CONFIG_SYS_FSL_I2C_SPEED,
+CONFIG_SYS_FSL_I2C_SLAVE, 0);
+#ifdef CONFIG_SYS_I2C2_OFFSET
U_BOOT_I2C_ADAP_COMPLETE(fsl_1, fsl_i2c_init, fsl_i2c_probe, fsl_i2c_read,
-fsl_i2c_write, fsl_i2c_set_bus_speed,
-CONFIG_SYS_FSL_I2C2_SPEED, CONFIG_SYS_FSL_I2C2_SLAVE,
-1)
+fsl_i2c_write, fsl_i2c_write_read,
+fsl_i2c_set_bus_speed, CONFIG_SYS_FSL_I2C2_SPEED,
+CONFIG_SYS_FSL_I2C2_SLAVE, 1);
#endif
diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c
index 18d6736..6647856 100644
--- a/drivers/i2c/i2c_core.c
+++ b/drivers/i2c/i2c_core.c
@@ -341,6 +341,13 @@ int i2c_write(uint8_t chip, unsigned int addr, int alen,
return I2C_ADAP->write(I2C_ADAP, chip, addr, alen, buffer, len);
}
+int i2c_write_read(uchar chip, uint8_t *wbuffer, int wlen, uint8_t *rbuffer,
+ int rlen)
+{
+ return I2C_ADAP->write_read(I2C_ADAP, chip, wbuffer, wlen,
+ rbuffer, rlen);
+}
+
unsigned int i2c_set_bus_speed(unsigned int speed)
{
unsigned int ret;
diff --git a/include/i2c.h b/include/i2c.h
index 1b4078e..7bac2
[U-Boot] [PATCH] board/b4860qds: Add support to make PCIe SATA work on B4860QDS
1) SerDes2 Refclks have been set properly to make
PCIe SATA to work as it work on SerDes refclk of 100MHz
2) Mask the SerDes's device reset request before changing
the Refclks for SerDes1 and SerDes2 for PLL locks to
happen properly, device reset request bit unmasked
after SerDes refclks configuration
Signed-off-by: Shaveta Leekha
---
arch/powerpc/include/asm/immap_85xx.h |3 +
board/freescale/b4860qds/b4860qds.c | 119 ++---
2 files changed, 113 insertions(+), 9 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index 9d08321..e0efc7e 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1722,6 +1722,9 @@ typedef struct ccsr_gur {
u32 rstrqpblsr; /* Reset request preboot loader status */
u8 res11[8];
u32 rstrqmr1; /* Reset request mask */
+#ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
+#define FSL_CORENET_RSTRQMR1_SRDS_RST_MSK 0x0800
+#endif
u8 res12[4];
u32 rstrqsr1; /* Reset request status */
u8 res13[4];
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index f6faa24..9d51864 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -293,7 +294,8 @@ int config_serdes1_refclks(void)
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
u32 serdes1_prtcl, lane;
unsigned int flag_sgmii_aurora_prtcl = 0;
- int ret, i;
+ int i;
+ int ret = 0;
serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -304,10 +306,12 @@ int config_serdes1_refclks(void)
serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
- /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
+ /* To prevent generation of reset request from SerDes
+* while changing the refclks, By setting SRDS_RST_MSK bit,
+* SerDes reset event cannot cause a reset request
*/
- for (i = 0; i < PLL_NUM; i++)
- clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
+ setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
/* Reconfigure IDT idt8t49n222a device for CPRI to work
* For this SerDes1's Refclk1 and refclk2 need to be set
* to 122.88MHz
@@ -345,11 +349,11 @@ int config_serdes1_refclks(void)
SERDES_REFCLK_122_88, 0);
if (ret) {
printf("IDT8T49N222A configuration failed.\n");
- return ret;
+ goto out;
} else
- printf("IDT8T49N222A configured.\n");
+ debug("IDT8T49N222A configured.\n");
} else {
- return ret;
+ goto out;
}
select_i2c_ch_pca(I2C_CH_DEFAULT);
@@ -400,16 +404,99 @@ int config_serdes1_refclks(void)
printf("WARNING:IDT8T49N222A configuration not"
" supported for:%x SerDes1 Protocol.\n",
serdes1_prtcl);
- return -1;
}
- return 0;
+out:
+ /* Clearing SRDS_RST_MSK bit as now
+* SerDes reset event can cause a reset request
+*/
+ clrbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+ return ret;
+}
+
+int config_serdes2_refclks(void)
+{
+ ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_corenet_t *srds2_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR;
+ u32 serdes2_prtcl;
+ int ret = 0;
+ int i;
+
+ serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+ if (!serdes2_prtcl) {
+ debug("SERDES2 is not enabled\n");
+ return -ENODEV;
+ }
+ serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+ debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+ /* To prevent generation of reset request from SerDes
+* while changing the refclks, By setting SRDS_RST_MSK bit,
+* SerDes reset event cannot cause a reset request
+*/
+ setbits_be32(&gur->rstrqmr1, FSL_CORENET_RSTRQMR1_SRDS_RST_MSK);
+
+ /* Reconfigure IDT idt8t49n222a device for PCIe SATA to work
+* For this SerDes2's Refclk1 need to be set to 100MH
[U-Boot] [PATCH] powerpc/b4860: Add workaround for errata A006384 and A006475
SerDes PLLs may not lock reliably at 5 G VCO configuration(A006384)
and at cold temperatures(A006475), workaround recalibrate the
PLLs with some SerDes configuration
Both these errata are only applicable for b4 rev1.
So, make workaround for these errata conditional,
depending upon soc version.
Signed-off-by: Shaveta Leekha
---
arch/powerpc/cpu/mpc85xx/cmd_errata.c |8 ++
arch/powerpc/include/asm/config_mpc85xx.h |2 +
arch/powerpc/include/asm/immap_85xx.h | 19 +++-
board/freescale/b4860qds/b4860qds.c | 193 +
4 files changed, 220 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7693899..d0a1c51 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -229,6 +229,14 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
if (IS_SVR_REV(svr, 1, 0))
puts("Work-around for Erratum A005871 enabled\n");
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006475
+ if (SVR_MAJ(get_svr()) == 1)
+ puts("Work-around for Erratum A006475 enabled\n");
+#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006384
+ if (SVR_MAJ(get_svr()) == 1)
+ puts("Work-around for Erratum A006384 enabled\n");
+#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
/* This work-around is implemented in PBI, so just check for it */
check_erratum_a4849(svr);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 0ec1417..2f47b3f 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -662,6 +662,8 @@
#define CONFIG_SYS_FSL_ERRATUM_A005871
#define CONFIG_SYS_FSL_ERRATUM_A006379
#define CONFIG_SYS_FSL_ERRATUM_A006593
+#define CONFIG_SYS_FSL_ERRATUM_A006475
+#define CONFIG_SYS_FSL_ERRATUM_A006384
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe00
#ifdef CONFIG_PPC_B4860
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index e0efc7e..edd7888 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2495,6 +2495,7 @@ typedef struct serdes_corenet {
#define SRDS_RSTCTL_SDEN 0x0020
#define SRDS_RSTCTL_SDRST_B0x0040
#define SRDS_RSTCTL_PLLRST_B 0x0080
+#define SRDS_RSTCTL_RSTERR_SHIFT 29
u32 pllcr0; /* PLL Control Register 0 */
#define SRDS_PLLCR0_POFF 0x8000
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x7000
@@ -2504,6 +2505,7 @@ typedef struct serdes_corenet {
#define SRDS_PLLCR0_RFCK_SEL_150 0x3000
#define SRDS_PLLCR0_RFCK_SEL_161_130x4000
#define SRDS_PLLCR0_RFCK_SEL_122_880x5000
+#define SRDS_PLLCR0_DCBIAS_OUT_EN 0x0200
#define SRDS_PLLCR0_FRATE_SEL_MASK 0x000f
#define SRDS_PLLCR0_FRATE_SEL_50x
#define SRDS_PLLCR0_FRATE_SEL_3_75 0x0005
@@ -2511,9 +2513,22 @@ typedef struct serdes_corenet {
#define SRDS_PLLCR0_FRATE_SEL_40x0007
#define SRDS_PLLCR0_FRATE_SEL_3_12 0x0009
#define SRDS_PLLCR0_FRATE_SEL_30x000a
+#define SRDS_PLLCR0_DCBIAS_OVRD0x00F0
+#define SRDS_PLLCR0_DCBIAS_OVRD_SHIFT 4
u32 pllcr1; /* PLL Control Register 1 */
-#define SRDS_PLLCR1_PLL_BWSEL 0x0800
- u32 res_0c; /* 0x00c */
+#define SRDS_PLLCR1_BCAP_EN0x2000
+#define SRDS_PLLCR1_BCAP_OVD 0x1000
+#define SRDS_PLLCR1_PLL_FCAP 0x001F8000
+#define SRDS_PLLCR1_PLL_FCAP_SHIFT 15
+#define SRDS_PLLCR1_PLL_BWSEL 0x0800
+#define SRDS_PLLCR1_BYP_CAL0x0200
+ u32 pllsr2; /* At 0x00c, PLL Status Register 2 */
+#define SRDS_PLLSR2_BCAP_EN0x0080
+#define SRDS_PLLSR2_BCAP_EN_SHIFT 23
+#define SRDS_PLLSR2_FCAP 0x003F
+#define SRDS_PLLSR2_FCAP_SHIFT 16
+#define SRDS_PLLSR2_DCBIAS 0x000F
+#define SRDS_PLLSR2_DCBIAS_SHIFT 16
u32 pllcr3;
u32 pllcr4;
u8 res_18[0x20-0x18];
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index 15b3f62..264d8c7 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -286,6 +286,182 @@ int configure_vsc3316_3308(void)
return 0;
}
+static int calibrate_pll(serdes_corenet_t *srds_regs, int pll_num)
+{
+ u32 rst_err;
+
+ /* Steps For SerDes PLLs reset and reconfiguration
+* or PLL power-up procedure
+*/
+ debug("CALIBRATE PLL:%d\n", pll_num);
+ clrbits_be32(&srds_regs->bank[pll_num].rstctl,
+ SRDS_RSTCTL_SDRST_B);
+ udelay(10);
+
[U-Boot] [PATCH 2/2] B4860qds: Set SerDes2 refclk2 at to 156.25MHz for XFI to work
- Change setting of SerDes2 refclk2 to have the default value
as it is coming on board that is 156.25MHz, for XFI to work
- Also change PLL_NUM variable to the one defined in
config_mpc85xx.h for B4860 and B4420
Signed-off-by: Shaveta Leekha
---
board/freescale/b4860qds/b4860qds.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index 9d51864..15b3f62 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -29,7 +29,6 @@
#define CLK_MUX_SEL_MASK 0x4
#define ETH_PHY_CLK_OUT0x4
-#define PLL_NUM2
DECLARE_GLOBAL_DATA_PTR;
@@ -384,7 +383,7 @@ int config_serdes1_refclks(void)
/* Steps For SerDes PLLs reset and reconfiguration after
* changing SerDes's refclks
*/
- for (i = 0; i < PLL_NUM; i++) {
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
debug("For PLL%d reset and reconfiguration after"
" changing refclks\n", i+1);
clrbits_be32(&srds_regs->bank[i].rstctl,
@@ -451,7 +450,7 @@ int config_serdes2_refclks(void)
if (!ret) {
ret = set_serdes_refclk(IDT_SERDES2_ADDRESS, 2,
SERDES_REFCLK_100,
- SERDES_REFCLK_100, 0);
+ SERDES_REFCLK_156_25, 0);
if (ret) {
printf("IDT8T49N222A configuration failed.\n");
goto out;
@@ -465,7 +464,7 @@ int config_serdes2_refclks(void)
/* Steps For SerDes PLLs reset and reconfiguration after
* changing SerDes's refclks
*/
- for (i = 0; i < PLL_NUM; i++) {
+ for (i = 0; i < CONFIG_SYS_FSL_SRDS_NUM_PLLS; i++) {
clrbits_be32(&srds2_regs->bank[i].rstctl,
SRDS_RSTCTL_SDRST_B);
udelay(10);
--
1.7.6.GIT
___
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[U-Boot] [PATCH 1/2] B4860/B4420: Add PLL_NUM define for B4420/B4860 to use SerDes2 Refclks re-configuration
- B4860 has two PLL per SerDes whereas B4420 has one PLL
per SerDes, add their defines in
arch/powerpc/include/asm/config_mpc85xx.h
Signed-off-by: Shaveta Leekha
---
arch/powerpc/include/asm/config_mpc85xx.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h
b/arch/powerpc/include/asm/config_mpc85xx.h
index 56587ae..0ec1417 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -667,6 +667,7 @@
#ifdef CONFIG_PPC_B4860
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 4
#define CONFIG_MAX_CPUS4
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 }
#define CONFIG_SYS_NUM_FM1_DTSEC 6
@@ -679,6 +680,7 @@
#define CONFIG_SYS_FSL_SRIO_LIODN
#else
#define CONFIG_MAX_CPUS2
+#define CONFIG_SYS_FSL_SRDS_NUM_PLLS 1
#define CONFIG_SYS_FSL_CORES_PER_CLUSTER 2
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 }
--
1.7.6.GIT
___
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[U-Boot] [PATCH] board/b4860qds: Add support to make Aurora work on B4860QDS
1) Add new SerDes1 protocols having Aurora in them
2) Add VSC cross point connections for Aurora to work with
CPRI and SGMIIs
3) Configure VSC crossbar switch to connect SerDes1
lanes to aurora on board, by checking SerDes1 protocols
4) SerDes1 Refclks have been set properly to make
Aurora, CPRI and SGMIIs to work together properly
Signed-off-by: Shaveta Leekha
---
arch/powerpc/cpu/mpc85xx/b4860_serdes.c | 32 +
board/freescale/b4860qds/b4860qds.c | 75 -
board/freescale/b4860qds/b4860qds_crossbar_con.h |8 ++
3 files changed, 111 insertions(+), 4 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index 6ff6a70..c96ad0b 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -18,6 +18,24 @@ struct serdes_config {
#ifdef CONFIG_PPC_B4860
static struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
+ {0x02, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x04, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x05, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x06, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x08, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x09, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x0A, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x0B, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x0C, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x0D, {CPRI8, CPRI7, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1}},
{0x0E, {CPRI8, CPRI7, CPRI6, CPRI5,
@@ -44,8 +62,22 @@ static struct serdes_config serdes1_cfg_tbl[] = {
{0x34, {AURORA, AURORA,
SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x39, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x3A, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x3C, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x3D, {AURORA, AURORA, CPRI6, CPRI5,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{0x3E, {CPRI8, CPRI7, CPRI6, CPRI5,
CPRI4, CPRI3, CPRI2, CPRI1}},
+ {0x5C, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
+ {0x5D, {AURORA, AURORA,
+ SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC4,
+ CPRI4, CPRI3, CPRI2, CPRI1} },
{}
};
static struct serdes_config serdes2_cfg_tbl[] = {
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index f6b012d..f6faa24 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -151,6 +151,53 @@ int configure_vsc3316_3308(void)
}
break;
+ case 0x02:
+ case 0x04:
+ case 0x05:
+ case 0x06:
+ case 0x08:
+ case 0x09:
+ case 0x0A:
+ case 0x0B:
+ case 0x0C:
+ case 0x30:
+ case 0x32:
+ case 0x33:
+ case 0x34:
+ case 0x39:
+ case 0x3A:
+ case 0x3C:
+ case 0x3D:
+ case 0x5C:
+ case 0x5D:
+ /*
+* Configuration:
+* SERDES: 1
+* Lanes: A,B: AURORA
+* Lanes: C,d: SGMII
+* Lanes: E,F,G,H: CPRI
+*/
+ debug("Configuring crossbar for Aurora, SGMII 3 and 4,"
+ " and CPRI. srds_prctl:%x\n", serdes1_prtcl);
+ num_vsc16_con = NUM_CON_VSC3316;
+ /* Configure VSC3316 crossbar switch */
+ ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+ if (!ret) {
+ ret = vsc3316_config(VSC3316_TX_ADDRESS,
+ vsc16_tx_sfp_sgmii_aurora,
+ num_vsc16_con);
+ if (ret)
+ return ret;
+ ret = vsc3316_config(VSC3316_RX_ADDRESS,
+ vsc16_rx_sfp_sgmii_aurora,
+ num_vsc16_con);
+ if (ret)
+ return ret;
+ } else {
+ return ret;
+ }
+ break;
+
#ifdef CONFIG_PPC_B4420
case 0x18:
/*
@@ -245,7 +292,7 @@ int config_
[U-Boot] [PATCH] board/freescale/common: IDT8T49N222A configuration code
Add code for configuring IDT8T49N222A device for various output refclks
- The IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer
with
alarm and monitoring functions suitable for networking and
communications applications. It is able to generate wide range of output
frequencies.
- In B4860QDS, it has been used to generate different refclks to SerDes
modules
- Programming of these devices are performed by I2C interface.
Signed-off-by: Shaveta Leekha
---
board/freescale/common/Makefile |1 +
board/freescale/common/idt8t49n222a_serdes_clk.c | 220 ++
board/freescale/common/idt8t49n222a_serdes_clk.h | 120
3 files changed, 341 insertions(+), 0 deletions(-)
create mode 100644 board/freescale/common/idt8t49n222a_serdes_clk.c
create mode 100644 board/freescale/common/idt8t49n222a_serdes_clk.h
diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile
index 37236d0..a550e5a 100644
--- a/board/freescale/common/Makefile
+++ b/board/freescale/common/Makefile
@@ -70,6 +70,7 @@ COBJS-$(CONFIG_P4080DS) += ics307_clk.o
COBJS-$(CONFIG_P5020DS)+= ics307_clk.o
COBJS-$(CONFIG_P5040DS)+= ics307_clk.o
COBJS-$(CONFIG_VSC_CROSSBAR)+= vsc3316_3308.o
+COBJS-$(CONFIG_IDT8T49N222A) += idt8t49n222a_serdes_clk.o
# deal with common files for P-series corenet based devices
SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o
diff --git a/board/freescale/common/idt8t49n222a_serdes_clk.c
b/board/freescale/common/idt8t49n222a_serdes_clk.c
new file mode 100644
index 000..8798c87
--- /dev/null
+++ b/board/freescale/common/idt8t49n222a_serdes_clk.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Shaveta Leekha
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include "idt8t49n222a_serdes_clk.h"
+
+#define DEVICE_ID_REG 0x00
+
+static int check_pll_status(u8 idt_addr)
+{
+ u8 val = 0;
+ int ret;
+
+ ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
+ if (ret < 0) {
+ printf("IDT:0x%x could not read status register from device.\n",
+ idt_addr);
+ return ret;
+ }
+
+ if (val & 0x04) {
+ debug("idt8t49n222a PLL is LOCKED: %x\n", val);
+ } else {
+ printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
+ return -1;
+ }
+
+ return 0;
+}
+
+int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
+ enum serdes_refclk refclk1,
+ enum serdes_refclk refclk2, u8 feedback)
+{
+ u8 dev_id = 0;
+ int i, ret;
+
+ debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
+ idt_addr);
+
+ ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
+ if (ret < 0) {
+ debug("IDT:0x%x could not read DEV_ID from device.\n",
+ idt_addr);
+ return ret;
+ }
+
+ if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
+ debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
+ idt_addr);
+ }
+
+ if (serdes_num != 1 && serdes_num != 2) {
+ debug("serdes_num should be 1 for SerDes1 and"
+ " 2 for SerDes2.\n");
+ return -1;
+ }
+
+ if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
+ || (refclk1 != SERDES_REFCLK_122_88
+ && refclk2 == SERDES_REFCLK_122_88)) {
+ debug("Only one refclk at 122.88MHz is not supported."
+ " Please set both refclk1 & refclk2 to 122.88MHz"
+ " or both not to 122.88MHz.\n");
+ return -1;
+ }
+
+ if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
+ && refclk1 != SERDES_REFCLK_125
+ &&
[U-Boot] [PATCH] board/b4860qds: Add support for configuring SerDes1 Refclks
1) Add support in B4860 board files for using IDT driver where
IDT8T49N222A is a low phase noise Frequency Translator / Synthesizer
that generate different refclks for SerDes modules, used this driver
for reconfiguring SerDes1 Refclks(based on SerDes1 protocols)
for CPRI to work. CPRI works on 122.88MHz and default refclks coming
on board are not suitable for it
2) Move SerDes1 refclk1 source selection from eth_b4860qds.c file
to b4860qds board file, as SerDes1 Refclk1 would come from
PHY MUX in case of certain protocols, that have been checked here.
This change would make on board SGMIIs to work
3) Add I2C addresses for IDT8T49N222A devices in board/include file
4) Add define for PCA-I2C bus multiplexer, on which IDT devices exist
Signed-off-by: Shaveta Leekha
---
board/freescale/b4860qds/b4860qds.c | 112 +++
board/freescale/b4860qds/eth_b4860qds.c |2 -
include/configs/B4860QDS.h |7 ++
3 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/board/freescale/b4860qds/b4860qds.c
b/board/freescale/b4860qds/b4860qds.c
index a39c17a..e901a0f 100644
--- a/board/freescale/b4860qds/b4860qds.c
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -37,12 +37,14 @@
#include "../common/qixis.h"
#include "../common/vsc3316_3308.h"
+#include "../common/idt8t49n222a_serdes_clk.h"
#include "b4860qds.h"
#include "b4860qds_qixis.h"
#include "b4860qds_crossbar_con.h"
#define CLK_MUX_SEL_MASK 0x4
#define ETH_PHY_CLK_OUT0x4
+#define PLL_NUM2
DECLARE_GLOBAL_DATA_PTR;
@@ -268,6 +270,106 @@ int configure_vsc3316_3308(void)
return 0;
}
+int config_serdes1_refclks(void)
+{
+ ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+ serdes_corenet_t *srds_regs =
+ (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+ u32 serdes1_prtcl, lane;
+ unsigned int flag_sgmii_prtcl = 0;
+ int ret, i;
+
+ serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+ FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+ if (!serdes1_prtcl) {
+ printf("SERDES1 is not enabled\n");
+ return -1;
+ }
+ serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+ debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+ /* Clear SRDS_RSTCTL_RST bit for both PLLs before changing refclks
+*/
+ for (i = 0; i < PLL_NUM; i++)
+ clrbits_be32(&srds_regs->bank[i].rstctl, SRDS_RSTCTL_RST);
+ /* Reconfigure IDT idt8t49n222a device for CPRI to work
+* For this SerDes1's Refclk1 and refclk2 need to be set
+* to 122.88MHz
+*/
+ switch (serdes1_prtcl) {
+ case 0x2A:
+ case 0x2C:
+ case 0x2D:
+ case 0x2E:
+ debug("Configuring idt8t49n222a for CPRI SerDes clks:"
+ " for srds_prctl:%x\n", serdes1_prtcl);
+ ret = select_i2c_ch_pca(I2C_CH_IDT);
+ if (!ret) {
+ ret = set_serdes_refclk(IDT_SERDES1_ADDRESS, 1,
+ SERDES_REFCLK_122_88,
+ SERDES_REFCLK_122_88, 0);
+ if (ret) {
+ printf("IDT8T49N222A configuration failed.\n");
+ return ret;
+ } else
+ printf("IDT8T49N222A configured.\n");
+ } else {
+ return ret;
+ }
+ select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+ /* Change SerDes1's Refclk1 to 125MHz for on board
+* SGMIIs to work
+*/
+ for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
+ enum srds_prtcl lane_prtcl = serdes_get_prtcl
+ (0, serdes1_prtcl, lane);
+ switch (lane_prtcl) {
+ case SGMII_FM1_DTSEC1:
+ case SGMII_FM1_DTSEC2:
+ case SGMII_FM1_DTSEC3:
+ case SGMII_FM1_DTSEC4:
+ case SGMII_FM1_DTSEC5:
+ case SGMII_FM1_DTSEC6:
+ flag_sgmii_prtcl++;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (flag_sgmii_prtcl)
+ QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+
+ /* Steps For SerDes PLLs reset and reconfiguration after
+* changing SerDes's refclks
+*/
+ for (i = 0; i < PLL_NUM; i++) {
+ debug
[U-Boot] [PATCH] powerpc/asm: Move function declaration of 'serdes_get_prtcl' to fsl_serdes.h
It allows files not in the same path to use this function as required by B4 board file Signed-off-by: Shaveta Leekha --- arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h |1 - arch/powerpc/include/asm/fsl_serdes.h |1 + 2 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h index 2258f41..485427a 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.h @@ -22,5 +22,4 @@ int is_serdes_prtcl_valid(int serdes, u32 prtcl); int serdes_lane_enabled(int lane); -enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); #endif /* __FSL_CORENET2_SERDES_H */ diff --git a/arch/powerpc/include/asm/fsl_serdes.h b/arch/powerpc/include/asm/fsl_serdes.h index ccb91fb..d428e90 100644 --- a/arch/powerpc/include/asm/fsl_serdes.h +++ b/arch/powerpc/include/asm/fsl_serdes.h @@ -103,6 +103,7 @@ void fsl_serdes_init(void); #ifdef CONFIG_FSL_CORENET #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 int serdes_get_first_lane(u32 sd, enum srds_prtcl device); +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane); #else int serdes_get_first_lane(enum srds_prtcl device); #endif -- 1.7.6.GIT ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] powerpc/mpc85xx: Add defines for serdes RSTCTL register
Also change the define name SRDS_RSTCTL_SDPD to
SRDS_RSTCTL_SDEN, which stands for SerDes enable
as mentioned in SerDes module guide
Signed-off-by: Shaveta Leekha
---
arch/powerpc/include/asm/immap_85xx.h |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/include/asm/immap_85xx.h
b/arch/powerpc/include/asm/immap_85xx.h
index db70d04..e236e7a 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2542,7 +2542,9 @@ typedef struct serdes_corenet {
#define SRDS_RSTCTL_RSTDONE0x4000
#define SRDS_RSTCTL_RSTERR 0x2000
#define SRDS_RSTCTL_SWRST 0x1000
-#define SRDS_RSTCTL_SDPD 0x0020
+#define SRDS_RSTCTL_SDEN 0x0020
+#define SRDS_RSTCTL_SDRST_B0x0040
+#define SRDS_RSTCTL_PLLRST_B 0x0080
u32 pllcr0; /* PLL Control Register 0 */
#define SRDS_PLLCR0_POFF 0x8000
#define SRDS_PLLCR0_RFCK_SEL_MASK 0x7000
--
1.7.6.GIT
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