Re: [PATCH v5 1/2] arm: mediatek: add mt8195 SOC support
Hello,
What happened to this series? Has it been abandoned? Also, is it
possible to get memory size installed to the board dynamically?
Best regards,
Shengyu
在 2023/8/4 19:04, Macpaul Lin 写道:
From: Fabien Parent
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent
Signed-off-by: Macpaul Lin
Reviewed-by: Simon Glass
---
MAINTAINERS| 2 +
arch/arm/dts/mt8195.dtsi | 370 +
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile| 1 +
arch/arm/mach-mediatek/mt8195/Kconfig | 13 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 97 +++
7 files changed, 498 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Kconfig
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
Changes for v3:
- Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
Changes for v4:
- No change.
Changes for v5:
- Fix Copyright year to 2023.
- Fix memory map in dram_init() to support 8GB onboard memory.
- Add '#if !IS_ENABLED(CONFIG_SYSRESET)' with reset_cpu().
- Correct reset_cpu() function prototype.
- rebase patchset to v2023-10.rc1
- Add missing arch/arm/mach-mediatek/mt8195/Kconfig.
diff --git a/MAINTAINERS b/MAINTAINERS
index 47581cf6fb..4d0f017e7e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -369,8 +369,10 @@ ARM MEDIATEK
M:Ryder Lee
M:Weijie Gao
M:Chunfeng Yun
+M: Macpaul Lin
R:GSS_MTK_Uboot_upstream
S:Maintained
+F: arch/arm/dts/mt8195.dtsi
F:arch/arm/mach-mediatek/
F:arch/arm/include/asm/arch-mediatek/
F:board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 00..14cb28d008
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Copyright (C) 2023 BayLibre, SAS
+ * Author: Ben Ho
+ * Erin Lo
+ * Fabien Parent
+ * Macpaul Lin
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+
Re: [PATCH v4 2/5] board: add support for Milk-V Mars CM
Sorry, seems this is a false warning as fdt_fixup_ethernet() would do this.
Best regards
在 2024/5/10 23:01, Shengyu Qu 写道:
Btw I didn't have a code path to pass the MAC address to kernel. So does
it actually exist?
Best regards,
Shengyu
在 2024/5/10 13:52, Heinrich Schuchardt 写道:
We already support the VisionFive 2 and the Milk-V Mars board by
patching the VisionFive 2 device tree. With this patch the same
is done for the Milk-V Mars CM.
Signed-off-by: Heinrich Schuchardt
Tested-by: E. Shattow
Reviewed-by: E. Shattow
---
v4:
no change
v3:
no change
v2:
rename spl_fdt_fixup_marc() to spl_fdt_fixup_mars_cm()
rename device-trees for Mars CM and Mars CM Lite
change model and compatible properties
---
board/starfive/visionfive2/spl.c | 28 ++-
.../visionfive2/starfive_visionfive2.c | 11 +++-
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/board/starfive/visionfive2/spl.c
b/board/starfive/visionfive2/spl.c
index ca61b5be227..b555189556a 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -129,6 +129,30 @@ void spl_fdt_fixup_mars(void *fdt)
}
}
+void spl_fdt_fixup_mars_cm(void *fdt)
+{
+ const char *compat;
+ const char *model;
+
+ spl_fdt_fixup_mars(fdt);
+
+ if (!get_mmc_size_from_eeprom()) {
+ int offset;
+
+ model = "Milk-V Mars CM Lite";
+ compat = "milkv,mars-cm-lite\0starfive,jh7110";
+
+ offset = fdt_path_offset(fdt,
"/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
+ /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */
+ fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
+ } else {
+ model = "Milk-V Mars CM";
+ compat = "milkv,mars-cm\0starfive,jh7110";
+ }
+ fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat,
sizeof(compat));
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
+}
+
void spl_fdt_fixup_version_a(void *fdt)
{
static const char compat[] =
"starfive,visionfive-2-v1.2a\0starfive,jh7110";
@@ -236,7 +260,9 @@ void spl_perform_fixups(struct spl_image_info
*spl_image)
pr_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
+ if (!strncmp(product_id, "MARC", 4)) {
+ spl_fdt_fixup_mars_cm(spl_image->fdt_addr);
+ } else if (!strncmp(product_id, "MARS", 4)) {
spl_fdt_fixup_mars(spl_image->fdt_addr);
} else if (!strncmp(product_id, "VF7110", 6)) {
version = get_pcb_revision_from_eeprom();
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
index a86bca533b2..6be53489626 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -19,6 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
#define FDTFILE_MILK_V_MARS \
"starfive/jh7110-milkv-mars.dtb"
+#define FDTFILE_MILK_V_MARS_CM \
+ "starfive/jh7110-milkv-mars-cm.dtb"
+#define FDTFILE_MILK_V_MARS_CM_LITE \
+ "starfive/jh7110-milkv-mars-cm-lite.dtb"
#define FDTFILE_VISIONFIVE2_1_2A \
"starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
#define FDTFILE_VISIONFIVE2_1_3B \
@@ -61,7 +65,12 @@ static void set_fdtfile(void)
log_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
+ if (!strncmp(product_id, "MARC", 4)) {
+ if (get_mmc_size_from_eeprom())
+ fdtfile = FDTFILE_MILK_V_MARS_CM;
+ else
+ fdtfile = FDTFILE_MILK_V_MARS_CM_LITE;
+ } else if (!strncmp(product_id, "MARS", 4)) {
fdtfile = FDTFILE_MILK_V_MARS;
} else if (!strncmp(product_id, "VF7110", 6)) {
version = get_pcb_revision_from_eeprom();
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Re: [PATCH v4 2/5] board: add support for Milk-V Mars CM
在 2024/5/10 23:01, Shengyu Qu 写道: Btw I didn't have a code path to pass the MAC address to kernel. So does Typo, have->find it actually exist? Best regards, Shengyu OpenPGP_0xE3520CC91929C8E7.asc Description: OpenPGP public key OpenPGP_signature.asc Description: OpenPGP digital signature
Re: [PATCH v4 2/5] board: add support for Milk-V Mars CM
Btw I didn't have a code path to pass the MAC address to kernel. So does it
actually exist?
Best regards,
Shengyu
在 2024/5/10 13:52, Heinrich Schuchardt 写道:
We already support the VisionFive 2 and the Milk-V Mars board by
patching the VisionFive 2 device tree. With this patch the same
is done for the Milk-V Mars CM.
Signed-off-by: Heinrich Schuchardt
Tested-by: E. Shattow
Reviewed-by: E. Shattow
---
v4:
no change
v3:
no change
v2:
rename spl_fdt_fixup_marc() to spl_fdt_fixup_mars_cm()
rename device-trees for Mars CM and Mars CM Lite
change model and compatible properties
---
board/starfive/visionfive2/spl.c | 28 ++-
.../visionfive2/starfive_visionfive2.c| 11 +++-
2 files changed, 37 insertions(+), 2 deletions(-)
diff --git a/board/starfive/visionfive2/spl.c b/board/starfive/visionfive2/spl.c
index ca61b5be227..b555189556a 100644
--- a/board/starfive/visionfive2/spl.c
+++ b/board/starfive/visionfive2/spl.c
@@ -129,6 +129,30 @@ void spl_fdt_fixup_mars(void *fdt)
}
}
+void spl_fdt_fixup_mars_cm(void *fdt)
+{
+ const char *compat;
+ const char *model;
+
+ spl_fdt_fixup_mars(fdt);
+
+ if (!get_mmc_size_from_eeprom()) {
+ int offset;
+
+ model = "Milk-V Mars CM Lite";
+ compat = "milkv,mars-cm-lite\0starfive,jh7110";
+
+ offset = fdt_path_offset(fdt,
"/soc/pinctrl/mmc0-pins/mmc0-pins-rest");
+ /* GPIOMUX(22, GPOUT_SYS_SDIO0_RST, GPOEN_ENABLE, GPI_NONE) */
+ fdt_setprop_u32(fdt, offset, "pinmux", 0xff130016);
+ } else {
+ model = "Milk-V Mars CM";
+ compat = "milkv,mars-cm\0starfive,jh7110";
+ }
+ fdt_setprop(fdt, fdt_path_offset(fdt, "/"), "compatible", compat,
sizeof(compat));
+ fdt_setprop_string(fdt, fdt_path_offset(fdt, "/"), "model", model);
+}
+
void spl_fdt_fixup_version_a(void *fdt)
{
static const char compat[] =
"starfive,visionfive-2-v1.2a\0starfive,jh7110";
@@ -236,7 +260,9 @@ void spl_perform_fixups(struct spl_image_info *spl_image)
pr_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
+ if (!strncmp(product_id, "MARC", 4)) {
+ spl_fdt_fixup_mars_cm(spl_image->fdt_addr);
+ } else if (!strncmp(product_id, "MARS", 4)) {
spl_fdt_fixup_mars(spl_image->fdt_addr);
} else if (!strncmp(product_id, "VF7110", 6)) {
version = get_pcb_revision_from_eeprom();
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
index a86bca533b2..6be53489626 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -19,6 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
#define FDTFILE_MILK_V_MARS \
"starfive/jh7110-milkv-mars.dtb"
+#define FDTFILE_MILK_V_MARS_CM \
+ "starfive/jh7110-milkv-mars-cm.dtb"
+#define FDTFILE_MILK_V_MARS_CM_LITE \
+ "starfive/jh7110-milkv-mars-cm-lite.dtb"
#define FDTFILE_VISIONFIVE2_1_2A \
"starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
#define FDTFILE_VISIONFIVE2_1_3B \
@@ -61,7 +65,12 @@ static void set_fdtfile(void)
log_err("Can't read EEPROM\n");
return;
}
- if (!strncmp(product_id, "MARS", 4)) {
+ if (!strncmp(product_id, "MARC", 4)) {
+ if (get_mmc_size_from_eeprom())
+ fdtfile = FDTFILE_MILK_V_MARS_CM;
+ else
+ fdtfile = FDTFILE_MILK_V_MARS_CM_LITE;
+ } else if (!strncmp(product_id, "MARS", 4)) {
fdtfile = FDTFILE_MILK_V_MARS;
} else if (!strncmp(product_id, "VF7110", 6)) {
version = get_pcb_revision_from_eeprom();
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Re: [PATCH] configs: visionfive2: Disable ENV_IS_NOWHERE
LGTM.
Maintainers, please also apply this patch to 2024.04 branch when
accepting it.
Best regards,
Shengyu
The VisionFive 2 board supports saving the u-boot environment settings
are saved to on-board SPI flash. However the defconfig enables both
ENV_IS_NOWHERE and ENV_IS_IN_SPI_FLASH, preventing the "saveenv" command
to work. Fix that by disabling ENV_IS_NOWHERE.
Fixes: 7d79bed00c9e ("configs: starfive: Enable environment in SPI flash
support")
Reported-by: E Shattow
Signed-off-by: Aurelien Jarno
---
configs/starfive_visionfive2_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index 1b7d57bac7..c68f3c2def 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -77,7 +77,6 @@ CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_BOOTSTAGE=y
CONFIG_OF_BOARD=y
CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_NOWHERE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SECT_SIZE_AUTO=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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Re: [PATCH 1/1] riscv: set fdtfile on VisionFive 2
Hello Leo,
This patch seems only landed in next branch, not master. It is seriously
needed to make visionfive 2 working properly. Could you merge it to
master branch?
Best regards,
Shengyu
Multiple revisions of the StarFive VisionFive 2 board exist. They can be
identified by reading their EEPROM.
Linux uses two differently named device-tree files. To load the correct
device-tree we need to set $fdtfile to the device-tree file name that
matches the board revision.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Leo Yu-Chi Liang
Tested-by: Milan P. Stanić
---
arch/riscv/Kconfig| 1 +
.../visionfive2/starfive_visionfive2.c| 43 ++-
2 files changed, 42 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6771d8d919..1c62c2345b 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -26,6 +26,7 @@ config TARGET_SIFIVE_UNMATCHED
config TARGET_STARFIVE_VISIONFIVE2
bool "Support StarFive VisionFive2 Board"
+ select BOARD_LATE_INIT
config TARGET_TH1520_LPI4A
bool "Support Sipeed's TH1520 Lichee PI 4A Board"
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
index d609262b67..05d8d2d657 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -5,14 +5,20 @@
*/
#include
-#include
-#include
#include
#include
+#include
+#include
+#include
+#include
#include
#define JH7110_L2_PREFETCHER_BASE_ADDR 0x203
#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
+#define FDTFILE_VISIONFIVE2_1_2A \
+ "starfive/jh7110-starfive-visionfive-2-v1.2a.dtb"
+#define FDTFILE_VISIONFIVE2_1_3B \
+ "starfive/jh7110-starfive-visionfive-2-v1.3b.dtb"
/* enable U74-mc hart1~hart4 prefetcher */
static void enable_prefetcher(void)
@@ -33,6 +39,31 @@ static void enable_prefetcher(void)
}
}
+/**
+ * set_fdtfile() - set the $fdtfile variable based on the board revision
+ */
+static void set_fdtfile(void)
+{
+ u8 version;
+ const char *fdtfile;
+
+ version = get_pcb_revision_from_eeprom();
+ switch (version) {
+ case 'a':
+ case 'A':
+ fdtfile = FDTFILE_VISIONFIVE2_1_2A;
+ break;
+
+ case 'b':
+ case 'B':
+ default:
+ fdtfile = FDTFILE_VISIONFIVE2_1_3B;
+ break;
+ };
+
+ env_set("fdtfile", fdtfile);
+}
+
int board_init(void)
{
enable_caches();
@@ -41,6 +72,14 @@ int board_init(void)
return 0;
}
+int board_late_init(void)
+{
+ if (CONFIG_IS_ENABLED(ID_EEPROM))
+ set_fdtfile();
+
+ return 0;
+}
+
void *board_fdt_blob_setup(int *err)
{
*err = 0;
[PATCH v1 2/2] board: visionfive2: Fixup memory size passed to kernel
Use fdt_fixup_memory to make the memory size data from dtb match
the actual size.
Signed-off-by: Shengyu Qu
Tested-by: Milan P. Stanić
---
board/starfive/visionfive2/starfive_visionfive2.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/board/starfive/visionfive2/starfive_visionfive2.c
b/board/starfive/visionfive2/starfive_visionfive2.c
index 9847e0efdb..700b60ac74 100644
--- a/board/starfive/visionfive2/starfive_visionfive2.c
+++ b/board/starfive/visionfive2/starfive_visionfive2.c
@@ -12,7 +12,9 @@
#include
#include
#include
+#include
+DECLARE_GLOBAL_DATA_PTR;
#define JH7110_L2_PREFETCHER_BASE_ADDR 0x203
#define JH7110_L2_PREFETCHER_HART_OFFSET 0x2000
@@ -76,3 +78,8 @@ void *board_fdt_blob_setup(int *err)
return (ulong *)&_end;
}
+
+int ft_board_setup(void *blob, struct bd_info *bd)
+{
+ return fdt_fixup_memory(blob, 0x4000, gd->ram_size);
+}
--
2.42.0
[PATCH v1 1/2] configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP
Enable CONFIG_OF_BOARD_SETUP, so we could use ft_board_setup() to fixup memory size passed to kernel. Signed-off-by: Shengyu Qu Tested-by: Milan P. Stanić --- configs/starfive_visionfive2_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 2376dad538..4d1459a3c2 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000 CONFIG_ARCH_RV64I=y CONFIG_CMODEL_MEDANY=y CONFIG_RISCV_SMODE=y +CONFIG_OF_BOARD_SETUP=y # CONFIG_OF_BOARD_FIXUP is not set CONFIG_FIT=y CONFIG_DISTRO_DEFAULTS=y -- 2.42.0
[PATCH v1 0/2] Fix memory size problem on Visionfive 2
Currently, we pass u-boot device tree to kernel on Starfive Visionfive 2 , and this is wrong since u-boot dts is not sync with Linux for this board. Jami's patch[1] fixes this problem, but we are still sending unmodified version to kernel that doesn't have a correct memory size info. This series are based on Jami's work and provide a fix for that. [1] https://patchwork.ozlabs.org/project/uboot/cover/20230911153253.20701-1-jamipkettu...@gmail.com/ Shengyu Qu (2): configs: visionfive2: Enable CONFIG_OF_BOARD_SETUP board: visionfive2: Fixup memory size passed to kernel board/starfive/visionfive2/starfive_visionfive2.c | 7 +++ configs/starfive_visionfive2_defconfig| 1 + 2 files changed, 8 insertions(+) -- 2.42.0
Re: [PATCH RFC 0/2] board: visionfive2: Select fdtfile based on revision
Hello Jami, I made a fix for memory size problem based on your series, but I can't try that because I'm using 4GB version. Could you test this? https://github.com/Headcrabed/u-boot/tree/ddr_fix_v1 Best regards, Shengyu From: Jami Kettunen Currently booting a mainline Linux kernel via extlinux with fdtdir set doesn't load a proper DTB but passes on the U-Boot one to the kernel which as far as I know is very incorrect and prevents user (normally distro) provided DTB usage in a sensible/generic way. A uEnv.txt or similar manual environment changes were not used and should not be required to boot the board as per: https://u-boot.readthedocs.io/en/latest/develop/distro.html This also currently needs a kernel patch[1] for my board to have the full 8GB of memory available to Linux instead of just 4GB it shows with these patches alone. [1] https://gitlab.alpinelinux.org/nmeum/alpine-visionfive/-/blob/main/starfive/linux-starfive/set-8GB-RAM.patch Jami Kettunen (2): board: visionfive2: Select fdtfile based on revision configs: visionfive2: Enable MISC_INIT_R .../visionfive2/starfive_visionfive2.c| 25 +++ configs/starfive_visionfive2_defconfig| 1 + 2 files changed, 26 insertions(+)
Re: [PATCH RFC 0/2] board: visionfive2: Select fdtfile based on revision
Hello Jami, For DDR size problem, I think we could enable CONFIG_OF_BOARD_SETUP, then use ft_board_setup() to apply fdt_fixup_memory()? Just like what they did in spl.c: https://patchwork.ozlabs.org/project/uboot/patch/20230615093652.23161-12-yanhong.w...@starfivetech.com/ Best regards, Shengyu (This mail is sent twice because the first one didn't use reply all) >From: Jami Kettunen > >Currently booting a mainline Linux kernel via extlinux with fdtdir set >doesn't load a proper DTB but passes on the U-Boot one to the kernel >which as far as I know is very incorrect and prevents user (normally >distro) provided DTB usage in a sensible/generic way. > >A uEnv.txt or similar manual environment changes were not used and >should not be required to boot the board as per: >https://u-boot.readthedocs.io/en/latest/develop/distro.html > >This also currently needs a kernel patch[1] for my board to have the >full 8GB of memory available to Linux instead of just 4GB it shows with >these patches alone. > >[1] >https://gitlab.alpinelinux.org/nmeum/alpine-visionfive/-/blob/main/starfive/linux-starfive/set-8GB-RAM.patch > >Jami Kettunen (2): > board: visionfive2: Select fdtfile based on revision > configs: visionfive2: Enable MISC_INIT_R > > .../visionfive2/starfive_visionfive2.c| 25 +++ > configs/starfive_visionfive2_defconfig| 1 + > 2 files changed, 26 insertions(+) >
[PATCH v6 4/4] configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default
SPL_SYS_MALLOC_CLEAR_ON_INIT would enable SYS_MALLOC_CLEAR_ON_INIT by default, but that's not need on JH7110, so disable that. Signed-off-by: Shengyu Qu --- configs/starfive_visionfive2_defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index e9b63e5b84..efe3c2205a 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -58,6 +58,8 @@ CONFIG_SYS_SPL_MALLOC=y CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x8000 CONFIG_SYS_SPL_MALLOC_SIZE=0x40 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_SYS_MALLOC_CLEAR_ON_INIT=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION=0x2 CONFIG_SPL_I2C=y -- 2.42.0
[PATCH v6 3/4] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT
Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 8469ee7de5..e5549a01b8 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -28,3 +28,4 @@ config STARFIVE_JH7110 imply SPL_LOAD_FIT imply SPL_OPENSBI imply SPL_RISCV_ACLINT + imply SPL_SYS_MALLOC_CLEAR_ON_INIT -- 2.42.0
[PATCH v6 2/4] dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT
To support SPL_SYS_MALLOC_CLEAR_ON_INIT, we have to modify
#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
to #if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
Reviewed-by: Tom Rini
---
common/dlmalloc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 0f9b7262d5..dcecdb8623 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -631,7 +631,7 @@ void mem_malloc_init(ulong start, ulong size)
debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start,
mem_malloc_end);
-#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
+#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
memset((void *)mem_malloc_start, 0x0, size);
#endif
malloc_bin_reloc();
@@ -2153,7 +2153,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size;
/* check if expand_top called, in which case don't need to clear */
-#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
+#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
#if MORECORE_CLEARS
mchunkptr oldtop = top;
INTERNAL_SIZE_T oldtopsize = chunksize(top);
@@ -2184,7 +2184,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size;
csz = chunksize(p);
-#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
+#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
#if MORECORE_CLEARS
if (p == oldtop && csz > oldtopsize)
{
--
2.42.0
[PATCH v6 1/4] Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT
Add SPL version of SYS_MALLOC_CLEAR_ON_INIT, this would help devices that need to clear ram before use to work correctly. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu --- Changes since v5: - Fix whitespace --- Kconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/Kconfig b/Kconfig index 91170bf8d2..6ba605a564 100644 --- a/Kconfig +++ b/Kconfig @@ -372,6 +372,17 @@ if EXPERT When disabling this, please check if malloc calls, maybe should be replaced by calloc - if one expects zeroed memory. +config SPL_SYS_MALLOC_CLEAR_ON_INIT + bool "Init with zeros the memory reserved for malloc (slow) in SPL" + depends on SPL + default SYS_MALLOC_CLEAR_ON_INIT + help + Same as SYS_MALLOC_CLEAR_ON_INIT, but for SPL. It's possible to + Enable it without SYS_MALLOC_CLEAR_ON_INIT. It's useful for boards + that must have particular memory regions zero'ed before first use. + If SYS_SPL_MALLOC_START is configured to be in such region, this + option should be enabled. + config SYS_MALLOC_DEFAULT_TO_INIT bool "Default malloc to init while reserving the memory for it" help -- 2.42.0
[PATCH v6 0/4] arch: riscv: jh7110: Correctly zero L2 LIM
This series is the sixth version of Bo Gan's L2 LIM series. Background information: JH7110 SPL runs in L2 LIM (2M in size mapped at 0x800). It consists of 16 0x2 sized regions, each one can be used as either L2 cache way or SRAM (not both). From top to bottom, there're ways 0-15. The way 0 is always enabled, at most 0x1e can be used. In SPL, we don't enable any cache ways, thus all 15 (except way 0) ways can be used. However, due to HW requirement, we must zero the LIM before use. This is because ECC is applied to LIM, and if not cleared first, the ECC part is invalid, which can trigger ECC errors when reading/writing data. There are several issues currently. We clear L2 LIM from __bss_end to 0x81F in `harts_early_init`. This is wrong because: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing `board_init_f_init_reserve`, while other harts're in the middle of zeroing L2 LIM. (data-race) To fix this, we split the job, such that there's one and only one owner of zeroing a specific region (No data-race). A new SPL config option `SPL_ZERO_MEM_BEFORE_USE` is introduced. Allowing The zeroing to happen in the same code path. (much easier to reason about). Besides, currently we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we add support SYS_MALLOC_CLEAR_ON_INIT in SPL, and imply SPL_SYS_MALLOC_CLEAR_ON_INIT on JH7110 as default. Changes since v1: - Separate single patch into several patches Changes since v2: - Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE) Changes since v3: - Revert v3's fix since original implementation is actually right Changes since v4: - Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT - Remove already merged patches Changes since v5: - Fix whitespace in patch 1 - Disable SYS_MALLOC_CLEAR_ON_INIT by default on Visionfive 2 Shengyu Qu (4): Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT configs: starfive: Disable SYS_MALLOC_CLEAR_ON_INIT by default Kconfig| 11 +++ arch/riscv/cpu/jh7110/Kconfig | 1 + common/dlmalloc.c | 6 +++--- configs/starfive_visionfive2_defconfig | 2 ++ 4 files changed, 17 insertions(+), 3 deletions(-) -- 2.42.0
[PATCH v5 3/3] riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT
Starfive JH7110 needs to clear L2 LIM to zero before use or ECC error would be triggered. Currently, we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we imply SPL_SYS_MALLOC_CLEAR_ON_INIT as default. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 8469ee7de5..e5549a01b8 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -28,3 +28,4 @@ config STARFIVE_JH7110 imply SPL_LOAD_FIT imply SPL_OPENSBI imply SPL_RISCV_ACLINT + imply SPL_SYS_MALLOC_CLEAR_ON_INIT -- 2.38.1.windows.1
[PATCH v5 2/3] dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT
To support SPL_SYS_MALLOC_CLEAR_ON_INIT, we have to modify
#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
to #if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
common/dlmalloc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 0f9b7262d5..dcecdb8623 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c
@@ -631,7 +631,7 @@ void mem_malloc_init(ulong start, ulong size)
debug("using memory %#lx-%#lx for malloc()\n", mem_malloc_start,
mem_malloc_end);
-#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
+#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
memset((void *)mem_malloc_start, 0x0, size);
#endif
malloc_bin_reloc();
@@ -2153,7 +2153,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size;
/* check if expand_top called, in which case don't need to clear */
-#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
+#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
#if MORECORE_CLEARS
mchunkptr oldtop = top;
INTERNAL_SIZE_T oldtopsize = chunksize(top);
@@ -2184,7 +2184,7 @@ Void_t* cALLOc(n, elem_size) size_t n; size_t elem_size;
csz = chunksize(p);
-#ifdef CONFIG_SYS_MALLOC_CLEAR_ON_INIT
+#if CONFIG_IS_ENABLED(SYS_MALLOC_CLEAR_ON_INIT)
#if MORECORE_CLEARS
if (p == oldtop && csz > oldtopsize)
{
--
2.38.1.windows.1
[PATCH v5 1/3] Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT
Add SPL version of SYS_MALLOC_CLEAR_ON_INIT, this would help devices that need to clear ram before use to work correctly. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu --- Kconfig | 11 +++ 1 file changed, 11 insertions(+) diff --git a/Kconfig b/Kconfig index 91170bf8d2..588acbaf9b 100644 --- a/Kconfig +++ b/Kconfig @@ -372,6 +372,17 @@ if EXPERT When disabling this, please check if malloc calls, maybe should be replaced by calloc - if one expects zeroed memory. + config SPL_SYS_MALLOC_CLEAR_ON_INIT + bool "Init with zeros the memory reserved for malloc (slow) in SPL" + depends on SPL + default SYS_MALLOC_CLEAR_ON_INIT + help + Same as SYS_MALLOC_CLEAR_ON_INIT, but for SPL. It's possible to + Enable it without SYS_MALLOC_CLEAR_ON_INIT. It's useful for boards + that must have particular memory regions zero'ed before first use. + If SYS_SPL_MALLOC_START is configured to be in such region, this + option should be enabled. + config SYS_MALLOC_DEFAULT_TO_INIT bool "Default malloc to init while reserving the memory for it" help -- 2.38.1.windows.1
[PATCH v5 0/3] arch: riscv: jh7110: Correctly zero L2 LIM
This series is the fifth version of Bo Gan's L2 LIM series. Background information: JH7110 SPL runs in L2 LIM (2M in size mapped at 0x800). It consists of 16 0x2 sized regions, each one can be used as either L2 cache way or SRAM (not both). From top to bottom, there're ways 0-15. The way 0 is always enabled, at most 0x1e can be used. In SPL, we don't enable any cache ways, thus all 15 (except way 0) ways can be used. However, due to HW requirement, we must zero the LIM before use. This is because ECC is applied to LIM, and if not cleared first, the ECC part is invalid, which can trigger ECC errors when reading/writing data. There are several issues currently. We clear L2 LIM from __bss_end to 0x81F in `harts_early_init`. This is wrong because: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing `board_init_f_init_reserve`, while other harts're in the middle of zeroing L2 LIM. (data-race) To fix this, we split the job, such that there's one and only one owner of zeroing a specific region (No data-race). A new SPL config option `SPL_ZERO_MEM_BEFORE_USE` is introduced. Allowing The zeroing to happen in the same code path. (much easier to reason about). Besides, currently we use DDR ram for SPL malloc arena on Visionfive 2 board in defconfig, but it's also possible to use L2 LIM as SPL malloc arena. To avoid triggering ECC error in this scenario, we add support SYS_MALLOC_CLEAR_ON_INIT in SPL, and imply SPL_SYS_MALLOC_CLEAR_ON_INIT on JH7110 as default. Changes since v1: - Separate single patch into several patches Changes since v2: - Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE) Changes since v3: - Revert v3's fix since original implementation is actually right Changes since v4: - Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT - Remove already merged patches Shengyu Qu (3): Kconfig: Add SPL_SYS_MALLOC_CLEAR_ON_INIT dlmalloc: Add support for SPL_SYS_MALLOC_CLEAR_ON_INIT riscv: cpu: jh7110: Imply SPL_SYS_MALLOC_CLEAR_ON_INIT Kconfig | 11 +++ arch/riscv/cpu/jh7110/Kconfig | 1 + common/dlmalloc.c | 6 +++--- 3 files changed, 15 insertions(+), 3 deletions(-) -- 2.38.1.windows.1
[PATCH v1 2/2] doc: board: starfive: Add more info about supported driver
Since PLDA PCIE driver is added and VL805 support is enabled in defconfig for Starfive Visionfive 2, modify the document to keep consistent. Signed-off-by: Shengyu Qu --- doc/board/starfive/visionfive2.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/doc/board/starfive/visionfive2.rst b/doc/board/starfive/visionfive2.rst index 941899a0a4..460f23aec3 100644 --- a/doc/board/starfive/visionfive2.rst +++ b/doc/board/starfive/visionfive2.rst @@ -20,6 +20,8 @@ The support for following drivers are already enabled: 3. StarFive JH7110 reset Driver. 4. Cadence QSPI controller Driver. 5. MMC SPI Driver for MMC/SD support. +6. PLDA PCIE controller driver. +7. On-board VL805 PCIE-USB controller driver. Booting from MMC using U-Boot SPL - -- 2.42.0
[PATCH v1 1/2] configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2
Although PCIE driver already exists, board defconfig isn't configured to
enable PCIE enum on boot, thus USB storage device and NVME drive are not
supported by default. So modify defconfig to enable PCIE auto enum, then
start USB subsystem and scan nvme drive on boot.
Signed-off-by: Shengyu Qu
---
configs/starfive_visionfive2_defconfig | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index e9b63e5b84..3002c96f0e 100644
--- a/configs/starfive_visionfive2_defconfig
+++ b/configs/starfive_visionfive2_defconfig
@@ -30,6 +30,7 @@ CONFIG_SPL_SPI=y
CONFIG_SYS_LOAD_ADDR=0x8200
CONFIG_SYS_PCI_64BIT=y
CONFIG_PCI=y
+CONFIG_PCI_INIT_R=y
CONFIG_TARGET_STARFIVE_VISIONFIVE2=y
CONFIG_SPL_OPENSBI_LOAD_ADDR=0x4000
CONFIG_ARCH_RV64I=y
@@ -43,7 +44,7 @@ CONFIG_SD_BOOT=y
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 debug rootwait earlycon=sbi"
CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="setenv fdt_addr ${fdtcontroladdr};fdt addr ${fdtcontroladdr};"
+CONFIG_PREBOOT="nvme scan; usb start; setenv fdt_addr ${fdtcontroladdr}; fdt
addr ${fdtcontroladdr};"
CONFIG_DEFAULT_FDT_FILE="starfive/jh7110-starfive-visionfive-2.dtb"
CONFIG_DISPLAY_CPUINFO=y
CONFIG_DISPLAY_BOARDINFO=y
@@ -124,4 +125,9 @@ CONFIG_TIMER_EARLY=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_PCI=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_PCI=y
+CONFIG_USB_STORAGE=y
CONFIG_USB_KEYBOARD=y
--
2.42.0
[PATCH v1 0/2] Enable PCIE and USB by default on Visionfive 2
Since PLDA PCIE driver and dts already merged in upstream for JH7110, add relative defconfig item for Starfive Visionfive 2 and make document consist with actual code. Shengyu Qu (2): configs: starfive: Enable PCIE auto enum and NVME/USB stuff for Starfive Visionfive 2 doc: board: starfive: Add more info about supported driver configs/starfive_visionfive2_defconfig | 8 +++- doc/board/starfive/visionfive2.rst | 2 ++ 2 files changed, 9 insertions(+), 1 deletion(-) -- 2.42.0
[PATCH v4 3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 4d9581165b..2e26d0731f 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -13,6 +13,7 @@ config STARFIVE_JH7110 select SUPPORT_SPL select SPL_RAM if SPL select SPL_STARFIVE_DDR + select SPL_ZERO_MEM_BEFORE_USE select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD -- 2.41.0
[PATCH v4 2/3] riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing code has
following issues:
1. Each hart (in the middle of a function call) overwriting its own
stack and other harts' stacks.
(data-race and data-corruption)
2. Lottery winner hart can be doing "board_init_f_init_reserve",
while other harts are in the middle of zeroing L2 LIM.
(data-race)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
Changes since v2:
- Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE)
Changes since v3:
- Revert v3's fix since original implementation is actually right
---
arch/riscv/cpu/jh7110/spl.c | 25 -
arch/riscv/cpu/start.S | 12
common/init/board_init.c| 3 +++
3 files changed, 15 insertions(+), 25 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 72adcefa0e..4047b10efe 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -13,7 +13,6 @@
#include
#define CSR_U74_FEATURE_DISABLE0x7c1
-#define L2_LIM_MEM_END 0x81FUL
DECLARE_GLOBAL_DATA_PTR;
@@ -59,9 +58,6 @@ int spl_soc_init(void)
void harts_early_init(void)
{
- ulong *ptr;
- u8 *tmp;
- ulong len, remain;
/*
* Feature Disable CSR
*
@@ -70,25 +66,4 @@ void harts_early_init(void)
*/
if (CONFIG_IS_ENABLED(RISCV_MMODE))
csr_write(CSR_U74_FEATURE_DISABLE, 0);
-
- /* clear L2 LIM memory
-* set __bss_end to 0x81F region to zero
-* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
-* If it is not cleared, the ECC part is invalid, and an ECC error
-* will be reported when reading data.
-*/
- ptr = (ulong *)&__bss_end;
- len = L2_LIM_MEM_END - (ulong)&__bss_end;
- remain = len % sizeof(ulong);
- len /= sizeof(ulong);
-
- while (len--)
- *ptr++ = 0;
-
- /* clear the remain bytes */
- if (remain) {
- tmp = (u8 *)ptr;
- while (remain--)
- *tmp++ = 0;
- }
}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 59d58a5a57..30cf674370 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,6 +111,18 @@ call_board_init_f:
* It's essential before any function call, otherwise, we get data-race.
*/
+/* clear stack if necessary */
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+clear_stack:
+ li t1, 1
+ sllit1, t1, CONFIG_STACK_SIZE_SHIFT
+ sub t1, sp, t1
+clear_stack_loop:
+ SREGzero, 0(t1) /* t1 is always 16 byte aligned */
+ addit1, t1, REGBYTES
+ blt t1, sp, clear_stack_loop
+#endif
+
call_board_init_f_0:
/* find top of reserve space */
#if CONFIG_IS_ENABLED(SMP)
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 96ffb79a98..ab8c508ad8 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -162,6 +162,9 @@ void board_init_f_init_reserve(ulong base)
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+ memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN));
+#endif
#endif
if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
--
2.41.0
[PATCH v4 1/3] riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before using them. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu Reviewed-by: Leo Yu-Chi Liang --- arch/riscv/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 867cbcbe74..6771d8d919 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -64,6 +64,14 @@ config SPL_SYS_DCACHE_OFF help Do not enable data cache in SPL. +config SPL_ZERO_MEM_BEFORE_USE + bool "Zero memory before use" + depends on SPL + default n + help + Zero stack/GD/malloc area in SPL before using them, this is needed for + Sifive core devices that uses L2 cache to store SPL. + # board-specific options below source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -- 2.41.0
[PATCH v4 0/3] arch: riscv: jh7110: Correctly zero L2 LIM
This series is the second version of Bo Gan's L2 LIM series. Original author hasn't sent v2 for almost 2 months, so I decided to take over this series. Background information: JH7110 SPL runs in L2 LIM (2M in size mapped at 0x800). It consists of 16 0x2 sized regions, each one can be used as either L2 cache way or SRAM (not both). From top to bottom, there're ways 0-15. The way 0 is always enabled, at most 0x1e can be used. In SPL, we don't enable any cache ways, thus all 15 (except way 0) ways can be used. However, due to HW requirement, we must zero the LIM before use. This is because ECC is applied to LIM, and if not cleared first, the ECC part is invalid, which can trigger ECC errors when reading/writing data. There are several issues currently. We clear L2 LIM from __bss_end to 0x81F in `harts_early_init`. This is wrong because: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing `board_init_f_init_reserve`, while other harts're in the middle of zeroing L2 LIM. (data-race) To fix this, we split the job, such that there's one and only one owner of zeroing a specific region (No data-race). A new SPL config option `SPL_ZERO_MEM_BEFORE_USE` is introduced. Allowing The zeroing to happen in the same code path. (much easier to reason about). Changes since v1: - Separate single patch into several patches Changes since v2: - Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE) Changes since v3: - Revert v3's fix since original implementation is actually right Shengyu Qu (3): riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch/riscv/Kconfig| 8 arch/riscv/cpu/jh7110/Kconfig | 1 + arch/riscv/cpu/jh7110/spl.c | 25 - arch/riscv/cpu/start.S| 12 common/init/board_init.c | 3 +++ 5 files changed, 24 insertions(+), 25 deletions(-) -- 2.41.0
Re: [PATCH v3 2/3] riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
Hi Leo,
Seems you are right. I'll send v4 to fix this. Thank you.
Best regards,
Shengyu
Hi Shengyu,
On Tue, Aug 08, 2023 at 08:39:56PM +0800, Shengyu Qu wrote:
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing code has
following issues:
1. Each hart (in the middle of a function call) overwriting its own
stack and other harts' stacks.
(data-race and data-corruption)
2. Lottery winner hart can be doing "board_init_f_init_reserve",
while other harts are in the middle of zeroing L2 LIM.
(data-race)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
Changes since v2:
- Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE)
---
arch/riscv/cpu/jh7110/spl.c | 25 -
arch/riscv/cpu/start.S | 12
common/init/board_init.c| 3 +++
3 files changed, 15 insertions(+), 25 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 72adcefa0e..4047b10efe 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -13,7 +13,6 @@
#include
#define CSR_U74_FEATURE_DISABLE 0x7c1
-#define L2_LIM_MEM_END 0x81FUL
DECLARE_GLOBAL_DATA_PTR;
@@ -59,9 +58,6 @@ int spl_soc_init(void)
void harts_early_init(void)
{
- ulong *ptr;
- u8 *tmp;
- ulong len, remain;
/*
* Feature Disable CSR
*
@@ -70,25 +66,4 @@ void harts_early_init(void)
*/
if (CONFIG_IS_ENABLED(RISCV_MMODE))
csr_write(CSR_U74_FEATURE_DISABLE, 0);
-
- /* clear L2 LIM memory
-* set __bss_end to 0x81F region to zero
-* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
-* If it is not cleared, the ECC part is invalid, and an ECC error
-* will be reported when reading data.
-*/
- ptr = (ulong *)&__bss_end;
- len = L2_LIM_MEM_END - (ulong)&__bss_end;
- remain = len % sizeof(ulong);
- len /= sizeof(ulong);
-
- while (len--)
- *ptr++ = 0;
-
- /* clear the remain bytes */
- if (remain) {
- tmp = (u8 *)ptr;
- while (remain--)
- *tmp++ = 0;
- }
}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 59d58a5a57..930309d8d2 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,6 +111,18 @@ call_board_init_f:
* It's essential before any function call, otherwise, we get data-race.
*/
+/* clear stack if necessary */
+#if CONFIG_IS_ENABLED(SPL_ZERO_MEM_BEFORE_USE)
I think what you have in v2 patch was the correct one.
Could you refer to include/linux/kconfig.h to check if
this usage fits your expectation ?
+clear_stack:
+ li t1, 1
+ sllit1, t1, CONFIG_STACK_SIZE_SHIFT
+ sub t1, sp, t1
+clear_stack_loop:
+ SREGzero, 0(t1) /* t1 is always 16 byte aligned */
+ addit1, t1, REGBYTES
+ blt t1, sp, clear_stack_loop
+#endif
+
call_board_init_f_0:
/* find top of reserve space */
#if CONFIG_IS_ENABLED(SMP)
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 96ffb79a98..51d9ec9a13 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -162,6 +162,9 @@ void board_init_f_init_reserve(ulong base)
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
+#if CONFIG_IS_ENABLED(SPL_ZERO_MEM_BEFORE_USE)
Ditto.
Best regards,
Leo
+ memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN));
+#endif
#endif
if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
--
2.41.0
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Description: OpenPGP public key
OpenPGP_signature
Description: OpenPGP digital signature
[PATCH v1] configs: starfive: Enable environment in SPI flash support
On Starfive Visionfive 2, the u-boot environment settings are saved to on-board SPI flash. Enable relative configs by default and set offset and size according to upstream linux dts. Signed-off-by: Shengyu Qu --- configs/starfive_visionfive2_defconfig | 9 + 1 file changed, 9 insertions(+) diff --git a/configs/starfive_visionfive2_defconfig b/configs/starfive_visionfive2_defconfig index 5d8a8e28cb..5e2e9b3489 100644 --- a/configs/starfive_visionfive2_defconfig +++ b/configs/starfive_visionfive2_defconfig @@ -6,6 +6,15 @@ CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8000 CONFIG_SF_DEFAULT_SPEED=1 +CONFIG_ENV_SUPPORT=y +CONFIG_SAVEENV=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_NOWHERE=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SECT_SIZE_AUTO=y +CONFIG_ENV_SIZE=0x1 +CONFIG_ENV_OFFSET=0xf +CONFIG_ENV_SECT_SIZE=0x1 CONFIG_SPL_DM_SPI=y CONFIG_DEFAULT_DEVICE_TREE="jh7110-starfive-visionfive-2" CONFIG_SPL_TEXT_BASE=0x800 -- 2.41.0
[PATCH v3 3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 4d9581165b..2e26d0731f 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -13,6 +13,7 @@ config STARFIVE_JH7110 select SUPPORT_SPL select SPL_RAM if SPL select SPL_STARFIVE_DDR + select SPL_ZERO_MEM_BEFORE_USE select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD -- 2.41.0
[PATCH v3 2/3] riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing code has
following issues:
1. Each hart (in the middle of a function call) overwriting its own
stack and other harts' stacks.
(data-race and data-corruption)
2. Lottery winner hart can be doing "board_init_f_init_reserve",
while other harts are in the middle of zeroing L2 LIM.
(data-race)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
Changes since v2:
- Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE)
---
arch/riscv/cpu/jh7110/spl.c | 25 -
arch/riscv/cpu/start.S | 12
common/init/board_init.c| 3 +++
3 files changed, 15 insertions(+), 25 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 72adcefa0e..4047b10efe 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -13,7 +13,6 @@
#include
#define CSR_U74_FEATURE_DISABLE0x7c1
-#define L2_LIM_MEM_END 0x81FUL
DECLARE_GLOBAL_DATA_PTR;
@@ -59,9 +58,6 @@ int spl_soc_init(void)
void harts_early_init(void)
{
- ulong *ptr;
- u8 *tmp;
- ulong len, remain;
/*
* Feature Disable CSR
*
@@ -70,25 +66,4 @@ void harts_early_init(void)
*/
if (CONFIG_IS_ENABLED(RISCV_MMODE))
csr_write(CSR_U74_FEATURE_DISABLE, 0);
-
- /* clear L2 LIM memory
-* set __bss_end to 0x81F region to zero
-* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
-* If it is not cleared, the ECC part is invalid, and an ECC error
-* will be reported when reading data.
-*/
- ptr = (ulong *)&__bss_end;
- len = L2_LIM_MEM_END - (ulong)&__bss_end;
- remain = len % sizeof(ulong);
- len /= sizeof(ulong);
-
- while (len--)
- *ptr++ = 0;
-
- /* clear the remain bytes */
- if (remain) {
- tmp = (u8 *)ptr;
- while (remain--)
- *tmp++ = 0;
- }
}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 59d58a5a57..930309d8d2 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,6 +111,18 @@ call_board_init_f:
* It's essential before any function call, otherwise, we get data-race.
*/
+/* clear stack if necessary */
+#if CONFIG_IS_ENABLED(SPL_ZERO_MEM_BEFORE_USE)
+clear_stack:
+ li t1, 1
+ sllit1, t1, CONFIG_STACK_SIZE_SHIFT
+ sub t1, sp, t1
+clear_stack_loop:
+ SREGzero, 0(t1) /* t1 is always 16 byte aligned */
+ addit1, t1, REGBYTES
+ blt t1, sp, clear_stack_loop
+#endif
+
call_board_init_f_0:
/* find top of reserve space */
#if CONFIG_IS_ENABLED(SMP)
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 96ffb79a98..51d9ec9a13 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -162,6 +162,9 @@ void board_init_f_init_reserve(ulong base)
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
+#if CONFIG_IS_ENABLED(SPL_ZERO_MEM_BEFORE_USE)
+ memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN));
+#endif
#endif
if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
--
2.41.0
[PATCH v3 1/3] riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before using them. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu --- arch/riscv/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 867cbcbe74..6771d8d919 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -64,6 +64,14 @@ config SPL_SYS_DCACHE_OFF help Do not enable data cache in SPL. +config SPL_ZERO_MEM_BEFORE_USE + bool "Zero memory before use" + depends on SPL + default n + help + Zero stack/GD/malloc area in SPL before using them, this is needed for + Sifive core devices that uses L2 cache to store SPL. + # board-specific options below source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -- 2.41.0
[PATCH v3 0/3] arch: riscv: jh7110: Correctly zero L2 LIM
This series is the second version of Bo Gan's L2 LIM series. Original author hasn't sent v2 for almost 2 months, so I decided to take over this series. Background information: JH7110 SPL runs in L2 LIM (2M in size mapped at 0x800). It consists of 16 0x2 sized regions, each one can be used as either L2 cache way or SRAM (not both). From top to bottom, there're ways 0-15. The way 0 is always enabled, at most 0x1e can be used. In SPL, we don't enable any cache ways, thus all 15 (except way 0) ways can be used. However, due to HW requirement, we must zero the LIM before use. This is because ECC is applied to LIM, and if not cleared first, the ECC part is invalid, which can trigger ECC errors when reading/writing data. There are several issues currently. We clear L2 LIM from __bss_end to 0x81F in `harts_early_init`. This is wrong because: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing `board_init_f_init_reserve`, while other harts're in the middle of zeroing L2 LIM. (data-race) To fix this, we split the job, such that there's one and only one owner of zeroing a specific region (No data-race). A new SPL config option `SPL_ZERO_MEM_BEFORE_USE` is introduced. Allowing The zeroing to happen in the same code path. (much easier to reason about). Changes since v1: - Separate single patch into several patches Changes since v2: - Fix typo (ZERO_MEM_BEFORE_USE to SPL_ZERO_MEM_BEFORE_USE) Shengyu Qu (3): riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch/riscv/Kconfig| 8 arch/riscv/cpu/jh7110/Kconfig | 1 + arch/riscv/cpu/jh7110/spl.c | 25 - arch/riscv/cpu/start.S| 12 common/init/board_init.c | 3 +++ 5 files changed, 24 insertions(+), 25 deletions(-) -- 2.41.0
[PATCH v2 2/3] riscv: Add ZERO_MEM_BEFORE_USE implementation
Add the actual support code for ZERO_MEM_BEFORE_USE and remove existing
Starfive JH7110's L2 LIM clean code, since existing code has following
issues:
1. Each hart (in the middle of a function call) overwriting its own
stack and other harts' stacks.
(data-race and data-corruption)
2. Lottery winner hart can be doing "board_init_f_init_reserve",
while other harts are in the middle of zeroing L2 LIM.
(data-race)
Signed-off-by: Bo Gan
Signed-off-by: Shengyu Qu
---
arch/riscv/cpu/jh7110/spl.c | 25 -
arch/riscv/cpu/start.S | 12
common/init/board_init.c| 3 +++
3 files changed, 15 insertions(+), 25 deletions(-)
diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c
index 72adcefa0e..4047b10efe 100644
--- a/arch/riscv/cpu/jh7110/spl.c
+++ b/arch/riscv/cpu/jh7110/spl.c
@@ -13,7 +13,6 @@
#include
#define CSR_U74_FEATURE_DISABLE0x7c1
-#define L2_LIM_MEM_END 0x81FUL
DECLARE_GLOBAL_DATA_PTR;
@@ -59,9 +58,6 @@ int spl_soc_init(void)
void harts_early_init(void)
{
- ulong *ptr;
- u8 *tmp;
- ulong len, remain;
/*
* Feature Disable CSR
*
@@ -70,25 +66,4 @@ void harts_early_init(void)
*/
if (CONFIG_IS_ENABLED(RISCV_MMODE))
csr_write(CSR_U74_FEATURE_DISABLE, 0);
-
- /* clear L2 LIM memory
-* set __bss_end to 0x81F region to zero
-* The L2 Cache Controller supports ECC. ECC is applied to SRAM.
-* If it is not cleared, the ECC part is invalid, and an ECC error
-* will be reported when reading data.
-*/
- ptr = (ulong *)&__bss_end;
- len = L2_LIM_MEM_END - (ulong)&__bss_end;
- remain = len % sizeof(ulong);
- len /= sizeof(ulong);
-
- while (len--)
- *ptr++ = 0;
-
- /* clear the remain bytes */
- if (remain) {
- tmp = (u8 *)ptr;
- while (remain--)
- *tmp++ = 0;
- }
}
diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 59d58a5a57..30cf674370 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -111,6 +111,18 @@ call_board_init_f:
* It's essential before any function call, otherwise, we get data-race.
*/
+/* clear stack if necessary */
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+clear_stack:
+ li t1, 1
+ sllit1, t1, CONFIG_STACK_SIZE_SHIFT
+ sub t1, sp, t1
+clear_stack_loop:
+ SREGzero, 0(t1) /* t1 is always 16 byte aligned */
+ addit1, t1, REGBYTES
+ blt t1, sp, clear_stack_loop
+#endif
+
call_board_init_f_0:
/* find top of reserve space */
#if CONFIG_IS_ENABLED(SMP)
diff --git a/common/init/board_init.c b/common/init/board_init.c
index 96ffb79a98..ab8c508ad8 100644
--- a/common/init/board_init.c
+++ b/common/init/board_init.c
@@ -162,6 +162,9 @@ void board_init_f_init_reserve(ulong base)
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
/* go down one 'early malloc arena' */
gd->malloc_base = base;
+#if CONFIG_IS_ENABLED(ZERO_MEM_BEFORE_USE)
+ memset((void *)base, '\0', CONFIG_VAL(SYS_MALLOC_F_LEN));
+#endif
#endif
if (CONFIG_IS_ENABLED(SYS_REPORT_STACK_F_USAGE))
--
2.41.0
[PATCH v2 3/3] riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE
Add Kconfig item for Starfive JH7110 to select SPL_ZERO_MEM_BEFORE_USE. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu --- arch/riscv/cpu/jh7110/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/cpu/jh7110/Kconfig b/arch/riscv/cpu/jh7110/Kconfig index 4d9581165b..2e26d0731f 100644 --- a/arch/riscv/cpu/jh7110/Kconfig +++ b/arch/riscv/cpu/jh7110/Kconfig @@ -13,6 +13,7 @@ config STARFIVE_JH7110 select SUPPORT_SPL select SPL_RAM if SPL select SPL_STARFIVE_DDR + select SPL_ZERO_MEM_BEFORE_USE select PINCTRL_STARFIVE_JH7110 imply MMC imply MMC_BROKEN_CD -- 2.41.0
[PATCH v2 1/3] riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE
Add a Kconfig item to allow SPL to clear stack/GD/malloc area before using them. Signed-off-by: Bo Gan Signed-off-by: Shengyu Qu --- arch/riscv/Kconfig | 8 1 file changed, 8 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 867cbcbe74..6771d8d919 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -64,6 +64,14 @@ config SPL_SYS_DCACHE_OFF help Do not enable data cache in SPL. +config SPL_ZERO_MEM_BEFORE_USE + bool "Zero memory before use" + depends on SPL + default n + help + Zero stack/GD/malloc area in SPL before using them, this is needed for + Sifive core devices that uses L2 cache to store SPL. + # board-specific options below source "board/AndesTech/ae350/Kconfig" source "board/emulation/qemu-riscv/Kconfig" -- 2.41.0
[PATCH v2 0/3] arch: riscv: jh7110: Correctly zero L2 LIM
This series is the second version of Bo Gan's L2 LIM series. Original author hasn't sent v2 for almost 2 months, so I decided to take over this series. Background information: JH7110 SPL runs in L2 LIM (2M in size mapped at 0x800). It consists of 16 0x2 sized regions, each one can be used as either L2 cache way or SRAM (not both). From top to bottom, there're ways 0-15. The way 0 is always enabled, at most 0x1e can be used. In SPL, we don't enable any cache ways, thus all 15 (except way 0) ways can be used. However, due to HW requirement, we must zero the LIM before use. This is because ECC is applied to LIM, and if not cleared first, the ECC part is invalid, which can trigger ECC errors when reading/writing data. There are several issues currently. We clear L2 LIM from __bss_end to 0x81F in `harts_early_init`. This is wrong because: 1. Each hart (in the middle of a function call) overwriting its own stack and other harts' stacks. (data-race and data-corruption) 2. Lottery winner hart can be doing `board_init_f_init_reserve`, while other harts're in the middle of zeroing L2 LIM. (data-race) Changes since v1: - Seperate single patch into several patches Shengyu Qu (3): riscv: Kconfig: Add SPL_ZERO_MEM_BEFORE_USE riscv: Add ZERO_MEM_BEFORE_USE implementation riscv: cpu: jh7110: Select SPL_ZERO_MEM_BEFORE_USE arch/riscv/Kconfig| 8 arch/riscv/cpu/jh7110/Kconfig | 1 + arch/riscv/cpu/jh7110/spl.c | 25 - arch/riscv/cpu/start.S| 12 common/init/board_init.c | 3 +++ 5 files changed, 24 insertions(+), 25 deletions(-) -- 2.41.0
