[v6 17/17] arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +++-
arch/arm/mach-socfpga/Makefile | 28 ++
...lex_vab_defconfig => socfpga_n5x_atf_defconfig} | 12 +-
...fpga_agilex_defconfig => socfpga_n5x_defconfig} | 13 +-
...lex_vab_defconfig => socfpga_n5x_vab_defconfig} | 11 +
5 files changed, 61 insertions(+), 24 deletions(-)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_atf_defconfig} (87%)
copy configs/{socfpga_agilex_defconfig => socfpga_n5x_defconfig} (83%)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_vab_defconfig} (87%)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0c35406232..f4791c1ebe 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,7 +8,7 @@ config NR_DRAM_BANKS
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
- depends on TARGET_SOCFPGA_AGILEX
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512_ALGO
@@ -91,6 +91,22 @@ config TARGET_SOCFPGA_GEN5
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF
+config TARGET_SOCFPGA_N5X
+ bool
+ select ARMV8_MULTIENTRY
+ select ARMV8_SET_SMPEN
+ select BINMAN if SPL_ATF
+ select CLK
+ select FPGA_INTEL_SDM_MAILBOX
+ select NCORE_CACHE
+ select SPL_ALTERA_SDRAM
+ select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
+
+config TARGET_SOCFPGA_N5X_SOCDK
+ bool "Intel eASIC SoCDK (N5X)"
+ select TARGET_SOCFPGA_N5X
+
config TARGET_SOCFPGA_SOC64
bool
@@ -185,6 +201,7 @@ config SYS_BOARD
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -194,6 +211,7 @@ config SYS_BOARD
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
+ default "intel" if TARGET_SOCFPGA_N5X_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -223,6 +241,7 @@ config SYS_CONFIG_NAME
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 58afde950f..ec38b64dd4 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation
-# Copyright (C) 2017-2020 Intel Corporation
+# Copyright (C) 2017-2021 Intel Corporation
obj-y += board.o
obj-y += clock_manager.o
@@ -56,6 +56,21 @@ obj-y+= wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += clock_manager_n5x.o
+obj-y += lowlevel_init_soc64.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += system_manager_soc64.o
+obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
+obj-y += wrap_handoff_soc64.o
+obj-y += wrap_pll_config_soc64.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
@@ -64,18 +79,21 @@ obj-y += wrap_iocsr_config.o
obj-y += wrap_pinmux_config.o
obj-y += wrap_sdram_config.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_SOC64
+obj-y += firewall.o
+obj-y += spl_soc64.o
+endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += spl_a10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-obj-y += firewall.o
obj-y += spl_s10.o
-obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-obj-y += firewall.o
obj-y += spl_agilex.o
-obj-y += spl_soc64.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += spl_n5x.o
endif
else
obj-$(CONFIG_SPL_AT
[v6 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v6:
- Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi
- Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi,
It is defined in socfpga_n5x_socdk.dtsi
- Remove the incorrect clkmgr compatible name in socfpga_n5x_socdk.dtsi
v5:
- Obsolete 5th version of patch because it set the wrong compatible name for
clkmgr in device tree.
v4:
- Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts
to u-boot.dtsi. Linux socfpga_n5x_socdk.dts:
https://github.com/altera-opensource/linux-socfpga/blob/socfpga-5.4.114-lts/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
v3:
- Update comment for memory example code
- Move all common dts settings for N5X from
socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi
- Remove unused parameter "u-boot,boot0"
v2:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
n5x data accordingly.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 191 +
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 63 +++
...fpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} | 59 +++
4 files changed, 275 insertions(+), 39 deletions(-)
create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (82%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 537c96bf5b..681cad2727 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -400,6 +400,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb\
+ socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
new file mode 100644
index 00..d377ae5f69
--- /dev/null
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+#include
+
+/{
+ memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ ccu: cache-controller@f700 {
+ compatible = "arteris,ncore-ccu";
+ reg = <0xf700 0x100900>;
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ dram_eosc_clk: dram-eosc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+ };
+
+ memclkmgr: mem-clock-controller@f804 {
+ compatible = "intel,n5x-mem-clkmgr";
+ reg = <0xf804 0x1000>;
+ #clock-cells = <0>;
+ clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
+ };
+ };
+};
+
+&clkmgr {
+ compatible = "intel,n5x-clkmgr";
+ u-boot,dm-pre-reloc;
+};
+
+&gmac0 {
+ clocks = <&clkmgr N5X_EMAC0_CLK>;
+};
+
+&gmac1 {
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ clocks = <&clkmgr N5X_EMAC1_CLK>;
+};
+
+&gmac2 {
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ clocks = <&clkmgr N5X_EMAC2_CLK>;
+};
+
+&i2c0 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c4 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&memclkmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc {
+ clocks = <&clkmgr N5X_L4_MP_CLK>,
+<&clkmgr N5X_SDMMC_CLK>;
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&pdma {
+ clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name
[v6 16/17] include: configs: Add Intel N5X device CONFIGs
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socfpga_n5x_socdk.h
new file mode 100644
index 00..c295e91e3d
--- /dev/null
+++ b/include/configs/socfpga_n5x_socdk.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_N5X_H__
+#define __CONFIG_SOCFGPA_N5X_H__
+
+#include
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "fdt_addr=110\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then" \
+ " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; fi; fi\0" \
+ "scriptaddr=0x0210\0" \
+ "scriptfile=u-boot.scr\0" \
+ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+ "then source ${scriptaddr}; fi\0"
+
+#endif /* __CONFIG_SOCFGPA_N5X_H__ */
--
2.13.0
[v6 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
From: Tien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach/system_manager_soc64.h| 10 +-
drivers/ddr/altera/Makefile|3 +-
drivers/ddr/altera/sdram_n5x.c | 2298
drivers/ddr/altera/sdram_soc64.c | 70 +
drivers/ddr/altera/sdram_soc64.h |1 +
6 files changed, 2386 insertions(+), 2 deletions(-)
create mode 100644 drivers/ddr/altera/sdram_n5x.c
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
index adab65bc96..5cb7f23f8f 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -115,10 +115,16 @@ struct socfpga_firwall_l4_sys {
/* Firewall MPU DDR SCR registers */
#define FW_MPU_DDR_SCR_EN 0x00
#define FW_MPU_DDR_SCR_EN_SET 0x04
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT0x18
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
+
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD0xff
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index fc4e17821b..a8009664fe 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2021 Intel Corporation
*/
#ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -28,8 +28,12 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c
#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
#define SYSMGR_SOC64_DMA_L3MASTER 0x74
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SYSMGR_SOC64_DDR_MODE 0xb8
+#else
#define SYSMGR_SOC64_HMC_CLK 0xb4
#define SYSMGR_SOC64_IO_PA_CTRL0xb8
+#endif
#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0
#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4
#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8
@@ -143,4 +147,8 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#defineSYSMGR_SOC64_DDR_MODE_MSK BIT(0)
+#endif
+
#endif /* _SYSTEM_MANAGER_SOC64_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 39dfee5d5a..9fa5d85a27 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -4,11 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# (C) Copyright 2010, Thomas Chou
-# Copyright (C) 2014 Altera Corporation
+# Copyright (C) 2014-2021 Altera Corporation
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
endif
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
new file mode 100644
index 00..ac13ac4319
--- /dev/null
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -0,0 +1,2298 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "sdram_soc64.h"
+#include
+#include
+#include
[v6 14/17] board: intel: Add socdk board support for Intel N5X device
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
create mode 100644 board/intel/n5x-socdk/MAINTAINERS
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile (50%)
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c (52%)
diff --git a/board/intel/n5x-socdk/MAINTAINERS
b/board/intel/n5x-socdk/MAINTAINERS
new file mode 100644
index 00..c1059f092c
--- /dev/null
+++ b/board/intel/n5x-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chee Tien Fong
+M: Lim Siew Chin
+S: Maintained
+F: board/intel/n5x-socdk/
+F: include/configs/socfpga_n5x_socdk.h
+F: configs/socfpga_n5x_atf_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile
b/board/intel/n5x-socdk/Makefile
similarity index 50%
copy from board/altera/stratix10-socdk/Makefile
copy to board/intel/n5x-socdk/Makefile
index 02a9cadf76..accfdcddcb 100644
--- a/board/altera/stratix10-socdk/Makefile
+++ b/board/intel/n5x-socdk/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2016-2017 Intel Corporation
+# Copyright (C) 2020-2021 Intel Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
diff --git a/board/altera/stratix10-socdk/socfpga.c
b/board/intel/n5x-socdk/socfpga.c
similarity index 52%
copy from board/altera/stratix10-socdk/socfpga.c
copy to board/intel/n5x-socdk/socfpga.c
index 043fc543f1..985ba190d0 100644
--- a/board/altera/stratix10-socdk/socfpga.c
+++ b/board/intel/n5x-socdk/socfpga.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
--
2.13.0
[v6 13/17] arm: socfpga: Add SPL for Intel N5X device
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_n5x.c
similarity index 83%
copy from arch/arm/mach-socfpga/spl_agilex.c
copy to arch/arm/mach-socfpga/spl_n5x.c
index ee5a9dc1e2..d056871d29 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -1,27 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,27 +53,35 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
+ preloader_console_init();
+
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
- debug("Clock init failed: %d\n", ret);
+ printf("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 1, &dev);
+ if (ret) {
+ printf("Memory clock init failed: %d\n", ret);
hang();
}
- preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();
+
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
- debug("CCU init failed: %d\n", ret);
+ printf("CCU init failed: %d\n", ret);
hang();
}
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
- debug("DRAM init failed: %d\n", ret);
+ printf("DRAM init failed: %d\n", ret);
hang();
}
#endif
--
2.13.0
[v6 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index a08f0953e5..cc656db97c 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2019 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -182,6 +182,7 @@ void sdram_size_check(struct bd_info *bd)
phys_size_t total_ram_check = 0;
phys_size_t ram_check = 0;
phys_addr_t start = 0;
+ phys_size_t size, remaining_size;
int bank;
/* Sanity check ensure correct SDRAM size specified */
@@ -189,10 +190,27 @@ void sdram_size_check(struct bd_info *bd)
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = bd->bi_dram[bank].start;
+ remaining_size = bd->bi_dram[bank].size;
while (ram_check < bd->bi_dram[bank].size) {
- ram_check += get_ram_size((void *)(start + ram_check),
-(phys_size_t)SZ_1G);
+ size = min((phys_addr_t)SZ_1G,
+ (phys_addr_t)remaining_size);
+
+ /*
+* Ensure the size is power of two, this is requirement
+* to run get_ram_size() / memory test
+*/
+ if (size != 0 && ((size & (size - 1)) == 0)) {
+ ram_check += get_ram_size((void *)
+ (start + ram_check), size);
+ remaining_size = bd->bi_dram[bank].size -
+ ram_check;
+ } else {
+ puts("DDR: Memory test requires SDRAM size ");
+ puts("in power of two!\n");
+ hang();
+ }
}
+
total_ram_check += ram_check;
ram_check = 0;
}
--
2.13.0
[v6 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5779c55621..58afde950f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,7 +32,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
@@ -45,7 +45,7 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += clock_manager_agilex.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
diff --git a/arch/arm/mach-socfpga/misc_s10.c
b/arch/arm/mach-socfpga/misc_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/misc_s10.c
rename to arch/arm/mach-socfpga/misc_soc64.c
index 50c7f19ae1..7b973a79e8 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -6,16 +6,16 @@
#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
#include
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
--
2.13.0
[v6 09/17] arm: socfpga: Add clock manager for Intel N5X device
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed, 29 insertions(+), 17 deletions(-)
copy arch/arm/mach-socfpga/{clock_manager_agilex.c => clock_manager_n5x.c}
(64%)
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
b/arch/arm/mach-socfpga/clock_manager_n5x.c
similarity index 64%
copy from arch/arm/mach-socfpga/clock_manager_agilex.c
copy to arch/arm/mach-socfpga/clock_manager_n5x.c
index e035c09aae..4f098533e7 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_n5x.c
@@ -1,19 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -25,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id)
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(socfpga_agilex_clk),
+ DM_DRIVER_GET(socfpga_n5x_clk),
&dev);
if (ret)
return 0;
@@ -39,8 +38,7 @@ static ulong cm_get_rate_dm(u32 id)
clk_free(&clk);
- if ((rate == (unsigned long)-ENOSYS) ||
- (rate == (unsigned long)-ENXIO) ||
+ if ((rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO)) {
debug("%s id %u: clk_get_rate err: %ld\n",
__func__, id, rate);
@@ -57,26 +55,26 @@ static u32 cm_get_rate_dm_khz(u32 id)
unsigned long cm_get_mpu_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_MPU_CLK);
+ return cm_get_rate_dm(N5X_MPU_CLK);
}
unsigned int cm_get_l4_sys_free_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+ return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
- cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+ cm_get_rate_dm_khz(N5X_MPU_CLK));
printf("L4 Main %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
printf("L4 sys free %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
printf("L4 MP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MP_CLK));
printf("L4 SP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SP_CLK));
printf("SDMMC %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+ cm_get_rate_dm_khz(N5X_SDMMC_CLK));
}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index d0b172a30e..a8cb07a1c4 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#include
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#include
#endif
#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
new file mode 100644
index 00..54615ae8f7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#ifndef _CLOCK_MANAGER_N5X_
+#define _CLOCK_MANAGER_N5X_
+
+#include
+#include "../../../../../drivers/clk/altera/clk-n5x.h"
+
+#endif /* _CLOCK_MANAGER_N5X_ */
--
2.13.0
[v6 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h | 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h| 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
5 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 2f9b471af3..d0b172a30e 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
+unsigned long cm_get_mpu_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
index 386e82a4e3..4feae3dda9 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -6,8 +6,6 @@
#ifndef _CLOCK_MANAGER_AGILEX_
#define _CLOCK_MANAGER_AGILEX_
-unsigned long cm_get_mpu_clk_hz(void);
-
#include
#include "../../../../../drivers/clk/altera/clk-agilex.h"
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index 798d3741bd..553ebe660d 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -68,7 +68,6 @@ int cm_basic_init(const void *blob);
#include
unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned long cm_get_mpu_clk_hz(void);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 4cc1268b4c..d53095a7da 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -96,7 +96,6 @@ struct cm_config {
#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 98c3bf1b03..7f10296dc7 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -11,7 +11,6 @@
#include
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
--
2.13.0
[v6 07/17] drivers: clk: Add memory clock driver for Intel N5X device
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84
3 files changed, 221 insertions(+)
create mode 100644 drivers/clk/altera/clk-mem-n5x.c
create mode 100644 drivers/clk/altera/clk-mem-n5x.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 38cd730685..33db092918 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c
new file mode 100644
index 00..ca44998641
--- /dev/null
+++ b/drivers/clk/altera/clk-mem-n5x.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include "clk-mem-n5x.h"
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_mem_clk_plat {
+ void __iomem *regs;
+};
+
+void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
+{
+ u32 inter_val;
+ u32 retry = 0;
+
+ do {
+ inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
+
+ /* Wait for stable lock */
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+
+ if (retry >= 10)
+ return;
+ } while (1);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_mem_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+ /* Put PLLs in bypass */
+ clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
+
+ /* Put PLLs in Reset */
+ CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup mem PLL */
+ CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
+ CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
+
+ /* Take PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+}
+
+static int socfpga_mem_clk_enable(struct clk *clk)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
+
+ clk_mem_basic_init(clk->dev, cm_default_cfg);
+
+ clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
+ MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ MEMCLKMGR_MEMPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_mem_write_bypass_mempll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
+ MEMCLKMGR_INTER_MEMPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
+ MEMCLKMGR_EXTCNTRST_ALLCNTRST);
+
+ return 0;
+}
+
+static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_mem_clk_ops = {
+ .enable = socfpga_mem_clk_enable
+};
+
+static const struct udevice_id socfpga_mem_clk_match[] = {
+ { .compatible = "intel,n5x-mem-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_n5x_mem_clk) = {
+ .name = "mem-clk-n5x",
+ .id = UCLASS_CLK,
+ .of_match = socfpga_mem_clk_match,
+ .ops= &socfpga_mem_clk_ops,
+ .of_to_plat = socfp
[v6 06/17] arm: socfpga: Get clock manager base address for Intel N5X device
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index f8d3d48ee8..9c19157de7 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void)
#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
ret = socfpga_get_base_addr("intel,agilex-clkmgr",
&socfpga_clkmgr_base);
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+ ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+ &socfpga_clkmgr_base);
#else
ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
#endif
--
2.13.0
[v6 05/17] drivers: clk: Add clock driver for Intel N5X device
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217 +++
include/dt-bindings/clock/n5x-clock.h | 71 +
4 files changed, 779 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/altera/clk-n5x.c
create mode 100644 drivers/clk/altera/clk-n5x.h
create mode 100644 include/dt-bindings/clock/n5x-clock.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 96215ad5c4..38cd730685 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Marek Vasut
+# Copyright (C) 2018-2021 Marek Vasut
#
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
new file mode 100644
index 00..bdcbbaae91
--- /dev/null
+++ b/drivers/clk/altera/clk-n5x.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_plat {
+ void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+ cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+ /* Always force clock manager into boot mode before any configuration */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+#else
+ /* Skip clock configuration in SSBL if it's not in boot mode */
+ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
+ return;
+#endif
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Put both PLLs in Reset */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup main PLL */
+ CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral */
+ CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+ CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+
+ /* Take both PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+ CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
+ CM_REG_WRITEL(plat, cfg->alt_s2fuser0ct
[v6 04/17] arm: socfpga: Add handoff data support for Intel N5X device
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38 +-
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +--
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +++--
3 files changed, 140 insertions(+), 48 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 3750216a9a..902fc6bfb5 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2020 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -23,8 +23,36 @@
#define SOC64_HANDOFF_OFFSET_DATA 0x10
#define SOC64_HANDOFF_SIZE 4096
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SOC64_HANDOFF_BASE 0xFFE5F000
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
+
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE 0xFFE5C000
+#define SOC64_HANDOFF_DDR_MAGIC0x4852
+#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC 0x4C54434D
+#define SOC64_HANDOFF_DDR_UMCTL2_DDR4_TYPE 0x3452
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_0_TYPE 0x3044504C
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_1_TYPE 0x3144504C
+#define SOC64_HANDOFF_DDR_MEMRESET_BASE(SOC64_HANDOFF_DDR_BASE
+ 0xC)
+#define SOC64_HANDOFF_DDR_UMCTL2_SECTION (SOC64_HANDOFF_DDR_BASE + 0x10)
+#define SOC64_HANDOFF_DDR_PHY_MAGIC0x43594850
+#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC0x45594850
+#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_TYPE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_BASE_ADDR_OFFSET 0xC
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_1D_SECTION0xFFE5
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_1D_SECTION0xFFE58000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_2D_SECTION0xFFE44000
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_2D_SECTION0xFFE4C000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_LENGTHSZ_32K
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_LENGTHSZ_16K
+#endif
+
#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
@@ -52,11 +80,11 @@
#include
enum endianness {
LITTLE_ENDIAN = 0,
- BIG_ENDIAN
+ BIG_ENDIAN,
+ UNKNOWN_ENDIANNESS
};
-int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
-int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
-enum endianness big_endian);
+int socfpga_get_handoff_size(void *handoff_address);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len);
#endif
#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
index 3b5e774e2d..958bb5107b 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -66,10 +66,10 @@ void populate_sysmgr_fpgaintf_module(void)
void populate_sysmgr_pinmux(void)
{
u32 len, i;
- u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX,
BIG_ENDIAN);
- u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL,
BIG_ENDIAN);
- u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA,
BIG_ENDIAN);
- u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY,
BIG_ENDIAN);
+ u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX);
+ u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL);
+ u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA);
+ u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY);
len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
len = (len > len_fpga) ? len : len_fpga;
@@ -79,7 +79,7 @@ void populate_sysmgr_pinmux(void)
/* setup the pin sel */
len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux :
SOC64_HANDOFF_MUX_LEN;
- socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len,
BIG_ENDIAN);
+ socfpga_han
[v6 03/17] arm: socfpga: Add base address for Intel N5X device
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index f89066d771..3f899fcfa3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -10,7 +10,8 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801 #define SOCFPGA_SDR_ADDRESS0xf8011000 -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 -- 2.13.0
[v6 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h| 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h =>
base_addr_soc64.h} (89%)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
similarity index 89%
rename from arch/arm/mach-socfpga/include/mach/base_addr_s10.h
rename to arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index d3eca65e97..f89066d771 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
-#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
-#define _SOCFPGA_S10_BASE_HARDWARE_H_
+#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
#define SOCFPGA_CCU_ADDRESS0xf700
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
@@ -44,4 +44,4 @@
#define GICD_BASE 0xfffc1000
#define GICC_BASE 0xfffc2000
-#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
+#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index 38fd775b5b..0b0470ebc1 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -7,7 +7,7 @@
#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
-#include
+#include
#include
#include
--
2.13.0
[v6 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_atf_defconfig | 2 +-
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 36eecdc057..7267163222 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -116,17 +116,18 @@ void board_fit_image_post_process(const void *fit, int
node, void **p_image,
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(bootm_headers_t *images)
{
- if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
- !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
- /*
-* Ensure the OS is always booted from FIT and with
-* VAB signed certificate
-*/
- if (!images->fit_uname_cfg) {
+ if (!images->fit_uname_cfg) {
+ if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
+
!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
+ /*
+* Ensure the OS is always booted from FIT and with
+* VAB signed certificate
+*/
printf("Please use FIT with VAB signed images!\n");
hang();
}
-
+ } else {
+ /* Update fdt_addr in enviroment variable */
env_set_hex("fdt_addr", (ulong)images->ft_addr);
debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
}
diff --git a/configs/socfpga_agilex_atf_defconfig
b/configs/socfpga_agilex_atf_defconfig
index 39e3eba461..6bff8e75a9 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/socfpga_stratix10_atf_defconfig
b/configs/socfpga_stratix10_atf_defconfig
index ab83e246bd..2bb0aec53c 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
--
2.13.0
[v6 00/17] Add Intel N5X SoC support
This is the 6th version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot without ATF for debugging purpose,
ATF boot, and ATF boot with VAB enabled.
[1]:
https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Patch status:
Have changes: Patch 15
Other patches unchanged.
Detail changelog can find in commit message.
v5->v6:
Patch 15:
- Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi
- Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi,
It is defined in socfpga_n5x_socdk.dtsi
- Remove the incorrect clkmgr compatible name in socfpga_n5x_socdk.dtsi
History:
[v1]
https://patchwork.ozlabs.org/project/uboot/cover/20210331143908.48211-1-elly.siew.chin@intel.com/
[v2]
https://patchwork.ozlabs.org/project/uboot/cover/20210430073814.193576-1-elly.siew.chin@intel.com/
[v3]
https://patchwork.ozlabs.org/project/uboot/cover/20210613084852.30868-1-elly.siew.chin@intel.com/
[v4]
https://patchwork.ozlabs.org/project/uboot/cover/20210712094921.16950-1-elly.siew.chin@intel.com/
[v5]
https://patchwork.ozlabs.org/project/uboot/cover/20210809071841.187051-1-elly.siew.chin@intel.com/
Siew Chin Lim (14):
arm: socfpga: Move linux_qspi_enable from bootcommand to
board_prep_linux function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
drivers: clk: Add clock driver for Intel N5X device
arm: socfpga: Get clock manager base address for Intel N5X device
drivers: clk: Add memory clock driver for Intel N5X device
arm: socfpga: Move cm_get_mpu_clk_hz function declaration to
clock_manager.h
arm: socfpga: Add clock manager for Intel N5X device
arm: socfpga: Changed misc_s10.c to misc_soc64.c
arm: socfpga: Add SPL for Intel N5X device
board: intel: Add socdk board support for Intel N5X device
arm: dts: Add base dtsi and devkit dts for Intel N5X device
include: configs: Add Intel N5X device CONFIGs
arm: socfpga: Enable Intel N5X device build
Tien Fong Chee (3):
arm: socfpga: Add handoff data support for Intel N5X device
ddr: socfpga: Enable memory test on memory size less than 1GB
ddr: altera: Add SDRAM driver for Intel N5X device
arch/arm/dts/Makefile |1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 191 ++
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 63 +
arch/arm/dts/socfpga_n5x_socdk.dts | 122 ++
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile | 32 +-
arch/arm/mach-socfpga/board.c | 17 +-
arch/arm/mach-socfpga/clock_manager_n5x.c | 80 +
.../mach/{base_addr_s10.h => base_addr_soc64.h}| 11 +-
arch/arm/mach-socfpga/include/mach/clock_manager.h |3 +
.../include/mach/clock_manager_agilex.h|2 -
.../include/mach/clock_manager_arria10.h |1 -
.../mach-socfpga/include/mach/clock_manager_gen5.h |1 -
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12 +
.../mach-socfpga/include/mach/clock_manager_s10.h |1 -
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38 +-
.../include/mach/system_manager_soc64.h| 10 +-
arch/arm/mach-socfpga/misc.c |3 +
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +-
arch/arm/mach-socfpga/spl_n5x.c| 94 +
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +-
board/intel/n5x-socdk/MAINTAINERS |7 +
board/intel/n5x-socdk/Makefile |7 +
board/intel/n5x-socdk/socfpga.c|7 +
configs/socfpga_agilex_atf_defconfig |2 +-
...lex_atf_defconfig => socfpga_n5x_atf_defconfig} | 13 +-
..._agilex_atf_defconfig => socfpga_n5x_defconfig} | 28 +-
...lex_atf_defconfig => socfpga_n5x_vab_defconfig} | 14 +-
configs/socfpga_stratix10_atf_defconfig|2 +-
drivers/clk/altera/Makefile|4 +-
drivers/clk/altera/clk-mem-n5x.c | 136 ++
drivers/clk/altera/clk-mem-n5x.h | 84 +
drivers/clk/altera/clk-n5x.c | 489 +
drivers/clk/altera/clk-n5x.h | 217 ++
drivers/ddr/altera/Makefile|3 +-
drivers/ddr/altera/sdram_n5x.c | 2298
drivers/ddr/altera/sdram_soc64.c | 94 +-
drivers/ddr/altera/sdram_soc64.h
[v5 17/17] arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +++-
arch/arm/mach-socfpga/Makefile | 28 ++
...lex_vab_defconfig => socfpga_n5x_atf_defconfig} | 12 +-
...fpga_agilex_defconfig => socfpga_n5x_defconfig} | 13 +-
...lex_vab_defconfig => socfpga_n5x_vab_defconfig} | 11 +
5 files changed, 61 insertions(+), 24 deletions(-)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_atf_defconfig} (87%)
copy configs/{socfpga_agilex_defconfig => socfpga_n5x_defconfig} (83%)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_vab_defconfig} (87%)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0c35406232..f4791c1ebe 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,7 +8,7 @@ config NR_DRAM_BANKS
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
- depends on TARGET_SOCFPGA_AGILEX
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512_ALGO
@@ -91,6 +91,22 @@ config TARGET_SOCFPGA_GEN5
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF
+config TARGET_SOCFPGA_N5X
+ bool
+ select ARMV8_MULTIENTRY
+ select ARMV8_SET_SMPEN
+ select BINMAN if SPL_ATF
+ select CLK
+ select FPGA_INTEL_SDM_MAILBOX
+ select NCORE_CACHE
+ select SPL_ALTERA_SDRAM
+ select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
+
+config TARGET_SOCFPGA_N5X_SOCDK
+ bool "Intel eASIC SoCDK (N5X)"
+ select TARGET_SOCFPGA_N5X
+
config TARGET_SOCFPGA_SOC64
bool
@@ -185,6 +201,7 @@ config SYS_BOARD
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -194,6 +211,7 @@ config SYS_BOARD
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
+ default "intel" if TARGET_SOCFPGA_N5X_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -223,6 +241,7 @@ config SYS_CONFIG_NAME
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 58afde950f..ec38b64dd4 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation
-# Copyright (C) 2017-2020 Intel Corporation
+# Copyright (C) 2017-2021 Intel Corporation
obj-y += board.o
obj-y += clock_manager.o
@@ -56,6 +56,21 @@ obj-y+= wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += clock_manager_n5x.o
+obj-y += lowlevel_init_soc64.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += system_manager_soc64.o
+obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
+obj-y += wrap_handoff_soc64.o
+obj-y += wrap_pll_config_soc64.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
@@ -64,18 +79,21 @@ obj-y += wrap_iocsr_config.o
obj-y += wrap_pinmux_config.o
obj-y += wrap_sdram_config.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_SOC64
+obj-y += firewall.o
+obj-y += spl_soc64.o
+endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += spl_a10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-obj-y += firewall.o
obj-y += spl_s10.o
-obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-obj-y += firewall.o
obj-y += spl_agilex.o
-obj-y += spl_soc64.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += spl_n5x.o
endif
else
obj-$(CONFIG_SPL_AT
[v5 16/17] include: configs: Add Intel N5X device CONFIGs
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socfpga_n5x_socdk.h
new file mode 100644
index 00..c295e91e3d
--- /dev/null
+++ b/include/configs/socfpga_n5x_socdk.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_N5X_H__
+#define __CONFIG_SOCFGPA_N5X_H__
+
+#include
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "fdt_addr=110\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then" \
+ " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; fi; fi\0" \
+ "scriptaddr=0x0210\0" \
+ "scriptfile=u-boot.scr\0" \
+ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+ "then source ${scriptaddr}; fi\0"
+
+#endif /* __CONFIG_SOCFGPA_N5X_H__ */
--
2.13.0
[v5 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v5:
- Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi
- Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi,
It is defined in socfpga_n5x_socdk.dtsi
v4:
- Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts
to u-boot.dtsi. Linux socfpga_n5x_socdk.dts:
https://github.com/altera-opensource/linux-socfpga/blob/socfpga-5.4.114-lts/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
v3:
- Update comment for memory example code
- Move all common dts settings for N5X from
socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi
- Remove unused parameter "u-boot,boot0"
v2:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
n5x data accordingly.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 191 +
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 63 +++
...fpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} | 110 ++--
4 files changed, 303 insertions(+), 62 deletions(-)
create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (51%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 537c96bf5b..681cad2727 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -400,6 +400,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb\
+ socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
new file mode 100644
index 00..d377ae5f69
--- /dev/null
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+#include
+
+/{
+ memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ ccu: cache-controller@f700 {
+ compatible = "arteris,ncore-ccu";
+ reg = <0xf700 0x100900>;
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ dram_eosc_clk: dram-eosc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+ };
+
+ memclkmgr: mem-clock-controller@f804 {
+ compatible = "intel,n5x-mem-clkmgr";
+ reg = <0xf804 0x1000>;
+ #clock-cells = <0>;
+ clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
+ };
+ };
+};
+
+&clkmgr {
+ compatible = "intel,n5x-clkmgr";
+ u-boot,dm-pre-reloc;
+};
+
+&gmac0 {
+ clocks = <&clkmgr N5X_EMAC0_CLK>;
+};
+
+&gmac1 {
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ clocks = <&clkmgr N5X_EMAC1_CLK>;
+};
+
+&gmac2 {
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ clocks = <&clkmgr N5X_EMAC2_CLK>;
+};
+
+&i2c0 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c4 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&memclkmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc {
+ clocks = <&clkmgr N5X_L4_MP_CLK>,
+<&clkmgr N5X_SDMMC_CLK>;
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&pdma {
+ clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
+&rst {
+ compatible = "altr,rst-mgr";
+ altr,modrst-offset = <0x20>;
+
[v5 14/17] board: intel: Add socdk board support for Intel N5X device
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
create mode 100644 board/intel/n5x-socdk/MAINTAINERS
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile (50%)
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c (52%)
diff --git a/board/intel/n5x-socdk/MAINTAINERS
b/board/intel/n5x-socdk/MAINTAINERS
new file mode 100644
index 00..c1059f092c
--- /dev/null
+++ b/board/intel/n5x-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chee Tien Fong
+M: Lim Siew Chin
+S: Maintained
+F: board/intel/n5x-socdk/
+F: include/configs/socfpga_n5x_socdk.h
+F: configs/socfpga_n5x_atf_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile
b/board/intel/n5x-socdk/Makefile
similarity index 50%
copy from board/altera/stratix10-socdk/Makefile
copy to board/intel/n5x-socdk/Makefile
index 02a9cadf76..accfdcddcb 100644
--- a/board/altera/stratix10-socdk/Makefile
+++ b/board/intel/n5x-socdk/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2016-2017 Intel Corporation
+# Copyright (C) 2020-2021 Intel Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
diff --git a/board/altera/stratix10-socdk/socfpga.c
b/board/intel/n5x-socdk/socfpga.c
similarity index 52%
copy from board/altera/stratix10-socdk/socfpga.c
copy to board/intel/n5x-socdk/socfpga.c
index 043fc543f1..985ba190d0 100644
--- a/board/altera/stratix10-socdk/socfpga.c
+++ b/board/intel/n5x-socdk/socfpga.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
--
2.13.0
[v5 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
From: Tien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach/system_manager_soc64.h| 10 +-
drivers/ddr/altera/Makefile|3 +-
drivers/ddr/altera/sdram_n5x.c | 2298
drivers/ddr/altera/sdram_soc64.c | 70 +
drivers/ddr/altera/sdram_soc64.h |1 +
6 files changed, 2386 insertions(+), 2 deletions(-)
create mode 100644 drivers/ddr/altera/sdram_n5x.c
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
index adab65bc96..5cb7f23f8f 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -115,10 +115,16 @@ struct socfpga_firwall_l4_sys {
/* Firewall MPU DDR SCR registers */
#define FW_MPU_DDR_SCR_EN 0x00
#define FW_MPU_DDR_SCR_EN_SET 0x04
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT0x18
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
+
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD0xff
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index fc4e17821b..a8009664fe 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2021 Intel Corporation
*/
#ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -28,8 +28,12 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c
#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
#define SYSMGR_SOC64_DMA_L3MASTER 0x74
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SYSMGR_SOC64_DDR_MODE 0xb8
+#else
#define SYSMGR_SOC64_HMC_CLK 0xb4
#define SYSMGR_SOC64_IO_PA_CTRL0xb8
+#endif
#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0
#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4
#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8
@@ -143,4 +147,8 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#defineSYSMGR_SOC64_DDR_MODE_MSK BIT(0)
+#endif
+
#endif /* _SYSTEM_MANAGER_SOC64_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 39dfee5d5a..9fa5d85a27 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -4,11 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# (C) Copyright 2010, Thomas Chou
-# Copyright (C) 2014 Altera Corporation
+# Copyright (C) 2014-2021 Altera Corporation
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
endif
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
new file mode 100644
index 00..ac13ac4319
--- /dev/null
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -0,0 +1,2298 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "sdram_soc64.h"
+#include
+#include
+#include
[v5 13/17] arm: socfpga: Add SPL for Intel N5X device
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_n5x.c
similarity index 83%
copy from arch/arm/mach-socfpga/spl_agilex.c
copy to arch/arm/mach-socfpga/spl_n5x.c
index ee5a9dc1e2..d056871d29 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -1,27 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,27 +53,35 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
+ preloader_console_init();
+
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
- debug("Clock init failed: %d\n", ret);
+ printf("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 1, &dev);
+ if (ret) {
+ printf("Memory clock init failed: %d\n", ret);
hang();
}
- preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();
+
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
- debug("CCU init failed: %d\n", ret);
+ printf("CCU init failed: %d\n", ret);
hang();
}
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
- debug("DRAM init failed: %d\n", ret);
+ printf("DRAM init failed: %d\n", ret);
hang();
}
#endif
--
2.13.0
[v5 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5779c55621..58afde950f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,7 +32,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
@@ -45,7 +45,7 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += clock_manager_agilex.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
diff --git a/arch/arm/mach-socfpga/misc_s10.c
b/arch/arm/mach-socfpga/misc_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/misc_s10.c
rename to arch/arm/mach-socfpga/misc_soc64.c
index 50c7f19ae1..7b973a79e8 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -6,16 +6,16 @@
#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
#include
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
--
2.13.0
[v5 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index a08f0953e5..cc656db97c 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2019 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -182,6 +182,7 @@ void sdram_size_check(struct bd_info *bd)
phys_size_t total_ram_check = 0;
phys_size_t ram_check = 0;
phys_addr_t start = 0;
+ phys_size_t size, remaining_size;
int bank;
/* Sanity check ensure correct SDRAM size specified */
@@ -189,10 +190,27 @@ void sdram_size_check(struct bd_info *bd)
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = bd->bi_dram[bank].start;
+ remaining_size = bd->bi_dram[bank].size;
while (ram_check < bd->bi_dram[bank].size) {
- ram_check += get_ram_size((void *)(start + ram_check),
-(phys_size_t)SZ_1G);
+ size = min((phys_addr_t)SZ_1G,
+ (phys_addr_t)remaining_size);
+
+ /*
+* Ensure the size is power of two, this is requirement
+* to run get_ram_size() / memory test
+*/
+ if (size != 0 && ((size & (size - 1)) == 0)) {
+ ram_check += get_ram_size((void *)
+ (start + ram_check), size);
+ remaining_size = bd->bi_dram[bank].size -
+ ram_check;
+ } else {
+ puts("DDR: Memory test requires SDRAM size ");
+ puts("in power of two!\n");
+ hang();
+ }
}
+
total_ram_check += ram_check;
ram_check = 0;
}
--
2.13.0
[v5 09/17] arm: socfpga: Add clock manager for Intel N5X device
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed, 29 insertions(+), 17 deletions(-)
copy arch/arm/mach-socfpga/{clock_manager_agilex.c => clock_manager_n5x.c}
(64%)
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
b/arch/arm/mach-socfpga/clock_manager_n5x.c
similarity index 64%
copy from arch/arm/mach-socfpga/clock_manager_agilex.c
copy to arch/arm/mach-socfpga/clock_manager_n5x.c
index e035c09aae..4f098533e7 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_n5x.c
@@ -1,19 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -25,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id)
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(socfpga_agilex_clk),
+ DM_DRIVER_GET(socfpga_n5x_clk),
&dev);
if (ret)
return 0;
@@ -39,8 +38,7 @@ static ulong cm_get_rate_dm(u32 id)
clk_free(&clk);
- if ((rate == (unsigned long)-ENOSYS) ||
- (rate == (unsigned long)-ENXIO) ||
+ if ((rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO)) {
debug("%s id %u: clk_get_rate err: %ld\n",
__func__, id, rate);
@@ -57,26 +55,26 @@ static u32 cm_get_rate_dm_khz(u32 id)
unsigned long cm_get_mpu_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_MPU_CLK);
+ return cm_get_rate_dm(N5X_MPU_CLK);
}
unsigned int cm_get_l4_sys_free_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+ return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
- cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+ cm_get_rate_dm_khz(N5X_MPU_CLK));
printf("L4 Main %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
printf("L4 sys free %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
printf("L4 MP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MP_CLK));
printf("L4 SP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SP_CLK));
printf("SDMMC %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+ cm_get_rate_dm_khz(N5X_SDMMC_CLK));
}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index d0b172a30e..a8cb07a1c4 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#include
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#include
#endif
#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
new file mode 100644
index 00..54615ae8f7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#ifndef _CLOCK_MANAGER_N5X_
+#define _CLOCK_MANAGER_N5X_
+
+#include
+#include "../../../../../drivers/clk/altera/clk-n5x.h"
+
+#endif /* _CLOCK_MANAGER_N5X_ */
--
2.13.0
[v5 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h | 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h| 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
5 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 2f9b471af3..d0b172a30e 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
+unsigned long cm_get_mpu_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
index 386e82a4e3..4feae3dda9 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -6,8 +6,6 @@
#ifndef _CLOCK_MANAGER_AGILEX_
#define _CLOCK_MANAGER_AGILEX_
-unsigned long cm_get_mpu_clk_hz(void);
-
#include
#include "../../../../../drivers/clk/altera/clk-agilex.h"
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index 798d3741bd..553ebe660d 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -68,7 +68,6 @@ int cm_basic_init(const void *blob);
#include
unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned long cm_get_mpu_clk_hz(void);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 4cc1268b4c..d53095a7da 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -96,7 +96,6 @@ struct cm_config {
#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 98c3bf1b03..7f10296dc7 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -11,7 +11,6 @@
#include
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
--
2.13.0
[v5 07/17] drivers: clk: Add memory clock driver for Intel N5X device
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84
3 files changed, 221 insertions(+)
create mode 100644 drivers/clk/altera/clk-mem-n5x.c
create mode 100644 drivers/clk/altera/clk-mem-n5x.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 38cd730685..33db092918 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c
new file mode 100644
index 00..ca44998641
--- /dev/null
+++ b/drivers/clk/altera/clk-mem-n5x.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include "clk-mem-n5x.h"
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_mem_clk_plat {
+ void __iomem *regs;
+};
+
+void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
+{
+ u32 inter_val;
+ u32 retry = 0;
+
+ do {
+ inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
+
+ /* Wait for stable lock */
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+
+ if (retry >= 10)
+ return;
+ } while (1);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_mem_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+ /* Put PLLs in bypass */
+ clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
+
+ /* Put PLLs in Reset */
+ CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup mem PLL */
+ CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
+ CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
+
+ /* Take PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+}
+
+static int socfpga_mem_clk_enable(struct clk *clk)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
+
+ clk_mem_basic_init(clk->dev, cm_default_cfg);
+
+ clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
+ MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ MEMCLKMGR_MEMPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_mem_write_bypass_mempll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
+ MEMCLKMGR_INTER_MEMPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
+ MEMCLKMGR_EXTCNTRST_ALLCNTRST);
+
+ return 0;
+}
+
+static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_mem_clk_ops = {
+ .enable = socfpga_mem_clk_enable
+};
+
+static const struct udevice_id socfpga_mem_clk_match[] = {
+ { .compatible = "intel,n5x-mem-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_n5x_mem_clk) = {
+ .name = "mem-clk-n5x",
+ .id = UCLASS_CLK,
+ .of_match = socfpga_mem_clk_match,
+ .ops= &socfpga_mem_clk_ops,
+ .of_to_plat = socfp
[v5 06/17] arm: socfpga: Get clock manager base address for Intel N5X device
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index f8d3d48ee8..9c19157de7 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void)
#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
ret = socfpga_get_base_addr("intel,agilex-clkmgr",
&socfpga_clkmgr_base);
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+ ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+ &socfpga_clkmgr_base);
#else
ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
#endif
--
2.13.0
[v5 04/17] arm: socfpga: Add handoff data support for Intel N5X device
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38 +-
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +--
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +++--
3 files changed, 140 insertions(+), 48 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 3750216a9a..902fc6bfb5 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2020 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -23,8 +23,36 @@
#define SOC64_HANDOFF_OFFSET_DATA 0x10
#define SOC64_HANDOFF_SIZE 4096
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SOC64_HANDOFF_BASE 0xFFE5F000
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
+
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE 0xFFE5C000
+#define SOC64_HANDOFF_DDR_MAGIC0x4852
+#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC 0x4C54434D
+#define SOC64_HANDOFF_DDR_UMCTL2_DDR4_TYPE 0x3452
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_0_TYPE 0x3044504C
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_1_TYPE 0x3144504C
+#define SOC64_HANDOFF_DDR_MEMRESET_BASE(SOC64_HANDOFF_DDR_BASE
+ 0xC)
+#define SOC64_HANDOFF_DDR_UMCTL2_SECTION (SOC64_HANDOFF_DDR_BASE + 0x10)
+#define SOC64_HANDOFF_DDR_PHY_MAGIC0x43594850
+#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC0x45594850
+#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_TYPE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_BASE_ADDR_OFFSET 0xC
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_1D_SECTION0xFFE5
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_1D_SECTION0xFFE58000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_2D_SECTION0xFFE44000
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_2D_SECTION0xFFE4C000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_LENGTHSZ_32K
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_LENGTHSZ_16K
+#endif
+
#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
@@ -52,11 +80,11 @@
#include
enum endianness {
LITTLE_ENDIAN = 0,
- BIG_ENDIAN
+ BIG_ENDIAN,
+ UNKNOWN_ENDIANNESS
};
-int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
-int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
-enum endianness big_endian);
+int socfpga_get_handoff_size(void *handoff_address);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len);
#endif
#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
index 3b5e774e2d..958bb5107b 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -66,10 +66,10 @@ void populate_sysmgr_fpgaintf_module(void)
void populate_sysmgr_pinmux(void)
{
u32 len, i;
- u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX,
BIG_ENDIAN);
- u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL,
BIG_ENDIAN);
- u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA,
BIG_ENDIAN);
- u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY,
BIG_ENDIAN);
+ u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX);
+ u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL);
+ u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA);
+ u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY);
len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
len = (len > len_fpga) ? len : len_fpga;
@@ -79,7 +79,7 @@ void populate_sysmgr_pinmux(void)
/* setup the pin sel */
len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux :
SOC64_HANDOFF_MUX_LEN;
- socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len,
BIG_ENDIAN);
+ socfpga_han
[v5 05/17] drivers: clk: Add clock driver for Intel N5X device
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217 +++
include/dt-bindings/clock/n5x-clock.h | 71 +
4 files changed, 779 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/altera/clk-n5x.c
create mode 100644 drivers/clk/altera/clk-n5x.h
create mode 100644 include/dt-bindings/clock/n5x-clock.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 96215ad5c4..38cd730685 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Marek Vasut
+# Copyright (C) 2018-2021 Marek Vasut
#
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
new file mode 100644
index 00..bdcbbaae91
--- /dev/null
+++ b/drivers/clk/altera/clk-n5x.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_plat {
+ void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+ cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+ /* Always force clock manager into boot mode before any configuration */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+#else
+ /* Skip clock configuration in SSBL if it's not in boot mode */
+ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
+ return;
+#endif
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Put both PLLs in Reset */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup main PLL */
+ CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral */
+ CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+ CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+
+ /* Take both PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+ CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
+ CM_REG_WRITEL(plat, cfg->alt_s2fuser0ct
[v5 03/17] arm: socfpga: Add base address for Intel N5X device
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index f89066d771..3f899fcfa3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -10,7 +10,8 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801 #define SOCFPGA_SDR_ADDRESS0xf8011000 -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 -- 2.13.0
[v5 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_atf_defconfig | 2 +-
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 36eecdc057..7267163222 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -116,17 +116,18 @@ void board_fit_image_post_process(const void *fit, int
node, void **p_image,
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(bootm_headers_t *images)
{
- if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
- !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
- /*
-* Ensure the OS is always booted from FIT and with
-* VAB signed certificate
-*/
- if (!images->fit_uname_cfg) {
+ if (!images->fit_uname_cfg) {
+ if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
+
!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
+ /*
+* Ensure the OS is always booted from FIT and with
+* VAB signed certificate
+*/
printf("Please use FIT with VAB signed images!\n");
hang();
}
-
+ } else {
+ /* Update fdt_addr in enviroment variable */
env_set_hex("fdt_addr", (ulong)images->ft_addr);
debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
}
diff --git a/configs/socfpga_agilex_atf_defconfig
b/configs/socfpga_agilex_atf_defconfig
index 39e3eba461..6bff8e75a9 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/socfpga_stratix10_atf_defconfig
b/configs/socfpga_stratix10_atf_defconfig
index ab83e246bd..2bb0aec53c 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
--
2.13.0
[v5 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h| 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h =>
base_addr_soc64.h} (89%)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
similarity index 89%
rename from arch/arm/mach-socfpga/include/mach/base_addr_s10.h
rename to arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index d3eca65e97..f89066d771 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
-#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
-#define _SOCFPGA_S10_BASE_HARDWARE_H_
+#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
#define SOCFPGA_CCU_ADDRESS0xf700
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
@@ -44,4 +44,4 @@
#define GICD_BASE 0xfffc1000
#define GICC_BASE 0xfffc2000
-#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
+#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index 38fd775b5b..0b0470ebc1 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -7,7 +7,7 @@
#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
-#include
+#include
#include
#include
--
2.13.0
[v5 00/17] Add Intel N5X SoC support
This is the 5th version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot without ATF for debugging purpose,
ATF boot, and ATF boot with VAB enabled.
[1]:
https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Patch status:
Have changes: Patch 15
Other patches unchanged.
Detail changelog can find in commit message.
v4->v5:
Patch 15:
- Sort the node name in alphanumeric order in socfpga_n5x_socdk-u-boot.dtsi
- Remove duplicated qspi node from socfpga_n5x_socdk-u-boot.dtsi,
It is defined in socfpga_n5x_socdk.dtsi
History:
[v1]
https://patchwork.ozlabs.org/project/uboot/cover/20210331143908.48211-1-elly.siew.chin@intel.com/
[v2]
https://patchwork.ozlabs.org/project/uboot/cover/20210430073814.193576-1-elly.siew.chin@intel.com/
[v3]
https://patchwork.ozlabs.org/project/uboot/cover/20210613084852.30868-1-elly.siew.chin@intel.com/
[v4]
https://patchwork.ozlabs.org/project/uboot/cover/20210712094921.16950-1-elly.siew.chin@intel.com/
Siew Chin Lim (14):
arm: socfpga: Move linux_qspi_enable from bootcommand to
board_prep_linux function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
drivers: clk: Add clock driver for Intel N5X device
arm: socfpga: Get clock manager base address for Intel N5X device
drivers: clk: Add memory clock driver for Intel N5X device
arm: socfpga: Move cm_get_mpu_clk_hz function declaration to
clock_manager.h
arm: socfpga: Add clock manager for Intel N5X device
arm: socfpga: Changed misc_s10.c to misc_soc64.c
arm: socfpga: Add SPL for Intel N5X device
board: intel: Add socdk board support for Intel N5X device
arm: dts: Add base dtsi and devkit dts for Intel N5X device
include: configs: Add Intel N5X device CONFIGs
arm: socfpga: Enable Intel N5X device build
Tien Fong Chee (3):
arm: socfpga: Add handoff data support for Intel N5X device
ddr: socfpga: Enable memory test on memory size less than 1GB
ddr: altera: Add SDRAM driver for Intel N5X device
arch/arm/dts/Makefile |1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 191 ++
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 63 +
arch/arm/dts/socfpga_n5x_socdk.dts | 127 ++
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile | 32 +-
arch/arm/mach-socfpga/board.c | 17 +-
arch/arm/mach-socfpga/clock_manager_n5x.c | 80 +
.../mach/{base_addr_s10.h => base_addr_soc64.h}| 11 +-
arch/arm/mach-socfpga/include/mach/clock_manager.h |3 +
.../include/mach/clock_manager_agilex.h|2 -
.../include/mach/clock_manager_arria10.h |1 -
.../mach-socfpga/include/mach/clock_manager_gen5.h |1 -
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12 +
.../mach-socfpga/include/mach/clock_manager_s10.h |1 -
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38 +-
.../include/mach/system_manager_soc64.h| 10 +-
arch/arm/mach-socfpga/misc.c |3 +
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +-
arch/arm/mach-socfpga/spl_n5x.c| 94 +
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +-
board/intel/n5x-socdk/MAINTAINERS |7 +
board/intel/n5x-socdk/Makefile |7 +
board/intel/n5x-socdk/socfpga.c|7 +
configs/socfpga_agilex_atf_defconfig |2 +-
...lex_atf_defconfig => socfpga_n5x_atf_defconfig} | 13 +-
..._agilex_atf_defconfig => socfpga_n5x_defconfig} | 28 +-
...lex_atf_defconfig => socfpga_n5x_vab_defconfig} | 14 +-
configs/socfpga_stratix10_atf_defconfig|2 +-
drivers/clk/altera/Makefile|4 +-
drivers/clk/altera/clk-mem-n5x.c | 136 ++
drivers/clk/altera/clk-mem-n5x.h | 84 +
drivers/clk/altera/clk-n5x.c | 489 +
drivers/clk/altera/clk-n5x.h | 217 ++
drivers/ddr/altera/Makefile|3 +-
drivers/ddr/altera/sdram_n5x.c | 2298
drivers/ddr/altera/sdram_soc64.c | 94 +-
drivers/ddr/altera/sdram_soc64.h |1 +
include/configs/socfpga_n5x_socdk.h| 45 +
include/configs/socfpga_soc64_common.h |2 +-
include/dt-bindings/clock/n5x-clock.h
[PATCH] command: Fix SMC and HVC maximum number of arguments
smc and hvc commands take upto 8 user input arguments, the maximum number of arguments of the U_BOOT_CMD macro should set to 9. Besides, fix the typo (arg7 -> arg6) in hvc command's help message. Signed-off-by: Siew Chin Lim --- cmd/smccc.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cmd/smccc.c b/cmd/smccc.c index 0b19f6c68c..0ff9a08021 100644 --- a/cmd/smccc.c +++ b/cmd/smccc.c @@ -50,7 +50,7 @@ static int do_call(struct cmd_tbl *cmdtp, int flag, int argc, #ifdef CONFIG_CMD_SMC U_BOOT_CMD( - smc,8, 2, do_call, + smc,9, 2, do_call, "Issue a Secure Monitor Call", " [arg1 ... arg6] [id]\n" " - fid Function ID\n" @@ -61,9 +61,9 @@ U_BOOT_CMD( #ifdef CONFIG_CMD_HVC U_BOOT_CMD( - hvc,8, 2, do_call, + hvc,9, 2, do_call, "Issue a Hypervisor Call", - " [arg1...arg7] [id]\n" + " [arg1...arg6] [id]\n" " - fid Function ID\n" " - arg HVC arguments, passed to X1-X6 (default to zero)\n" " - id Session ID, passed to W7 (defaults to zero)\n" -- 2.13.0
[v4 17/17] arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +++-
arch/arm/mach-socfpga/Makefile | 28 ++
...lex_vab_defconfig => socfpga_n5x_atf_defconfig} | 12 +-
...fpga_agilex_defconfig => socfpga_n5x_defconfig} | 13 +-
...lex_vab_defconfig => socfpga_n5x_vab_defconfig} | 11 +
5 files changed, 61 insertions(+), 24 deletions(-)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_atf_defconfig} (87%)
copy configs/{socfpga_agilex_defconfig => socfpga_n5x_defconfig} (83%)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_vab_defconfig} (87%)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0c35406232..f4791c1ebe 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,7 +8,7 @@ config NR_DRAM_BANKS
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
- depends on TARGET_SOCFPGA_AGILEX
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512_ALGO
@@ -91,6 +91,22 @@ config TARGET_SOCFPGA_GEN5
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF
+config TARGET_SOCFPGA_N5X
+ bool
+ select ARMV8_MULTIENTRY
+ select ARMV8_SET_SMPEN
+ select BINMAN if SPL_ATF
+ select CLK
+ select FPGA_INTEL_SDM_MAILBOX
+ select NCORE_CACHE
+ select SPL_ALTERA_SDRAM
+ select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
+
+config TARGET_SOCFPGA_N5X_SOCDK
+ bool "Intel eASIC SoCDK (N5X)"
+ select TARGET_SOCFPGA_N5X
+
config TARGET_SOCFPGA_SOC64
bool
@@ -185,6 +201,7 @@ config SYS_BOARD
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
@@ -194,6 +211,7 @@ config SYS_BOARD
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
+ default "intel" if TARGET_SOCFPGA_N5X_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -223,6 +241,7 @@ config SYS_CONFIG_NAME
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
+ default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 58afde950f..ec38b64dd4 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation
-# Copyright (C) 2017-2020 Intel Corporation
+# Copyright (C) 2017-2021 Intel Corporation
obj-y += board.o
obj-y += clock_manager.o
@@ -56,6 +56,21 @@ obj-y+= wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += clock_manager_n5x.o
+obj-y += lowlevel_init_soc64.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += system_manager_soc64.o
+obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
+obj-y += wrap_handoff_soc64.o
+obj-y += wrap_pll_config_soc64.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
@@ -64,18 +79,21 @@ obj-y += wrap_iocsr_config.o
obj-y += wrap_pinmux_config.o
obj-y += wrap_sdram_config.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_SOC64
+obj-y += firewall.o
+obj-y += spl_soc64.o
+endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += spl_a10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-obj-y += firewall.o
obj-y += spl_s10.o
-obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-obj-y += firewall.o
obj-y += spl_agilex.o
-obj-y += spl_soc64.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += spl_n5x.o
endif
else
obj-$(CONFIG_SPL_AT
[v4 16/17] include: configs: Add Intel N5X device CONFIGs
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socfpga_n5x_socdk.h
new file mode 100644
index 00..c295e91e3d
--- /dev/null
+++ b/include/configs/socfpga_n5x_socdk.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_N5X_H__
+#define __CONFIG_SOCFGPA_N5X_H__
+
+#include
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "fdt_addr=110\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then" \
+ " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; fi; fi\0" \
+ "scriptaddr=0x0210\0" \
+ "scriptfile=u-boot.scr\0" \
+ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+ "then source ${scriptaddr}; fi\0"
+
+#endif /* __CONFIG_SOCFGPA_N5X_H__ */
--
2.13.0
[v4 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v4:
- Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts
to u-boot.dtsi. Linux socfpga_n5x_socdk.dts:
https://github.com/altera-opensource/linux-socfpga/blob/socfpga-5.4.114-lts/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
v3:
- Update comment for memory example code
- Move all common dts settings for N5X from
socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi
- Remove unused parameter "u-boot,boot0"
v2:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
n5x data accordingly.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 192 +
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 100 +++
arch/arm/dts/socfpga_n5x_socdk.dts | 88 +
4 files changed, 381 insertions(+)
create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_n5x_socdk.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7ce3ae6caa..9bf64e207c 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -397,6 +397,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb\
+ socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
new file mode 100644
index 00..3e3859c0bf
--- /dev/null
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+#include
+
+/{
+ memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ ccu: cache-controller@f700 {
+ compatible = "arteris,ncore-ccu";
+ reg = <0xf700 0x100900>;
+ u-boot,dm-pre-reloc;
+ };
+
+ clocks {
+ dram_eosc_clk: dram-eosc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+ };
+
+ memclkmgr: mem-clock-controller@f804 {
+ compatible = "intel,n5x-mem-clkmgr";
+ reg = <0xf804 0x1000>;
+ #clock-cells = <0>;
+ clocks = <&dram_eosc_clk>, <&f2s_free_clk>;
+ };
+ };
+};
+
+&clkmgr {
+ compatible = "intel,n5x-clkmgr";
+ u-boot,dm-pre-reloc;
+};
+
+&gmac0 {
+ clocks = <&clkmgr N5X_EMAC0_CLK>;
+};
+
+&gmac1 {
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ clocks = <&clkmgr N5X_EMAC1_CLK>;
+};
+
+&gmac2 {
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ clocks = <&clkmgr N5X_EMAC2_CLK>;
+};
+
+&i2c0 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c4 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&memclkmgr {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc {
+ clocks = <&clkmgr N5X_L4_MP_CLK>,
+<&clkmgr N5X_SDMMC_CLK>;
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&pdma {
+ clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&spi0 {
+ clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&spi1 {
+ clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&timer0 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&timer1 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&timer2 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&timer3 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+
[v4 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
From: Tien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach/system_manager_soc64.h| 10 +-
drivers/ddr/altera/Makefile|3 +-
drivers/ddr/altera/sdram_n5x.c | 2298
drivers/ddr/altera/sdram_soc64.c | 70 +
drivers/ddr/altera/sdram_soc64.h |1 +
6 files changed, 2386 insertions(+), 2 deletions(-)
create mode 100644 drivers/ddr/altera/sdram_n5x.c
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
index adab65bc96..5cb7f23f8f 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -115,10 +115,16 @@ struct socfpga_firwall_l4_sys {
/* Firewall MPU DDR SCR registers */
#define FW_MPU_DDR_SCR_EN 0x00
#define FW_MPU_DDR_SCR_EN_SET 0x04
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT0x18
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
+
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD0xff
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index fc4e17821b..a8009664fe 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2021 Intel Corporation
*/
#ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -28,8 +28,12 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c
#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
#define SYSMGR_SOC64_DMA_L3MASTER 0x74
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SYSMGR_SOC64_DDR_MODE 0xb8
+#else
#define SYSMGR_SOC64_HMC_CLK 0xb4
#define SYSMGR_SOC64_IO_PA_CTRL0xb8
+#endif
#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0
#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4
#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8
@@ -143,4 +147,8 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#defineSYSMGR_SOC64_DDR_MODE_MSK BIT(0)
+#endif
+
#endif /* _SYSTEM_MANAGER_SOC64_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 39dfee5d5a..9fa5d85a27 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -4,11 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# (C) Copyright 2010, Thomas Chou
-# Copyright (C) 2014 Altera Corporation
+# Copyright (C) 2014-2021 Altera Corporation
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
endif
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
new file mode 100644
index 00..ac13ac4319
--- /dev/null
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -0,0 +1,2298 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "sdram_soc64.h"
+#include
+#include
+#include
[v4 14/17] board: intel: Add socdk board support for Intel N5X device
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
create mode 100644 board/intel/n5x-socdk/MAINTAINERS
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile (50%)
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c (52%)
diff --git a/board/intel/n5x-socdk/MAINTAINERS
b/board/intel/n5x-socdk/MAINTAINERS
new file mode 100644
index 00..c1059f092c
--- /dev/null
+++ b/board/intel/n5x-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chee Tien Fong
+M: Lim Siew Chin
+S: Maintained
+F: board/intel/n5x-socdk/
+F: include/configs/socfpga_n5x_socdk.h
+F: configs/socfpga_n5x_atf_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile
b/board/intel/n5x-socdk/Makefile
similarity index 50%
copy from board/altera/stratix10-socdk/Makefile
copy to board/intel/n5x-socdk/Makefile
index 02a9cadf76..accfdcddcb 100644
--- a/board/altera/stratix10-socdk/Makefile
+++ b/board/intel/n5x-socdk/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2016-2017 Intel Corporation
+# Copyright (C) 2020-2021 Intel Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
diff --git a/board/altera/stratix10-socdk/socfpga.c
b/board/intel/n5x-socdk/socfpga.c
similarity index 52%
copy from board/altera/stratix10-socdk/socfpga.c
copy to board/intel/n5x-socdk/socfpga.c
index 043fc543f1..985ba190d0 100644
--- a/board/altera/stratix10-socdk/socfpga.c
+++ b/board/intel/n5x-socdk/socfpga.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
--
2.13.0
[v4 13/17] arm: socfpga: Add SPL for Intel N5X device
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_n5x.c
similarity index 83%
copy from arch/arm/mach-socfpga/spl_agilex.c
copy to arch/arm/mach-socfpga/spl_n5x.c
index ee5a9dc1e2..d056871d29 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -1,27 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,27 +53,35 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
+ preloader_console_init();
+
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
- debug("Clock init failed: %d\n", ret);
+ printf("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 1, &dev);
+ if (ret) {
+ printf("Memory clock init failed: %d\n", ret);
hang();
}
- preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();
+
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
- debug("CCU init failed: %d\n", ret);
+ printf("CCU init failed: %d\n", ret);
hang();
}
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
- debug("DRAM init failed: %d\n", ret);
+ printf("DRAM init failed: %d\n", ret);
hang();
}
#endif
--
2.13.0
[v4 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index a08f0953e5..cc656db97c 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2019 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -182,6 +182,7 @@ void sdram_size_check(struct bd_info *bd)
phys_size_t total_ram_check = 0;
phys_size_t ram_check = 0;
phys_addr_t start = 0;
+ phys_size_t size, remaining_size;
int bank;
/* Sanity check ensure correct SDRAM size specified */
@@ -189,10 +190,27 @@ void sdram_size_check(struct bd_info *bd)
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = bd->bi_dram[bank].start;
+ remaining_size = bd->bi_dram[bank].size;
while (ram_check < bd->bi_dram[bank].size) {
- ram_check += get_ram_size((void *)(start + ram_check),
-(phys_size_t)SZ_1G);
+ size = min((phys_addr_t)SZ_1G,
+ (phys_addr_t)remaining_size);
+
+ /*
+* Ensure the size is power of two, this is requirement
+* to run get_ram_size() / memory test
+*/
+ if (size != 0 && ((size & (size - 1)) == 0)) {
+ ram_check += get_ram_size((void *)
+ (start + ram_check), size);
+ remaining_size = bd->bi_dram[bank].size -
+ ram_check;
+ } else {
+ puts("DDR: Memory test requires SDRAM size ");
+ puts("in power of two!\n");
+ hang();
+ }
}
+
total_ram_check += ram_check;
ram_check = 0;
}
--
2.13.0
[v4 09/17] arm: socfpga: Add clock manager for Intel N5X device
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...{clock_manager_agilex.c => clock_manager_n5x.c} | 32 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 ++
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12
3 files changed, 29 insertions(+), 17 deletions(-)
copy arch/arm/mach-socfpga/{clock_manager_agilex.c => clock_manager_n5x.c}
(64%)
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
b/arch/arm/mach-socfpga/clock_manager_n5x.c
similarity index 64%
copy from arch/arm/mach-socfpga/clock_manager_agilex.c
copy to arch/arm/mach-socfpga/clock_manager_n5x.c
index e035c09aae..4f098533e7 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_n5x.c
@@ -1,19 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -25,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id)
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(socfpga_agilex_clk),
+ DM_DRIVER_GET(socfpga_n5x_clk),
&dev);
if (ret)
return 0;
@@ -39,8 +38,7 @@ static ulong cm_get_rate_dm(u32 id)
clk_free(&clk);
- if ((rate == (unsigned long)-ENOSYS) ||
- (rate == (unsigned long)-ENXIO) ||
+ if ((rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO)) {
debug("%s id %u: clk_get_rate err: %ld\n",
__func__, id, rate);
@@ -57,26 +55,26 @@ static u32 cm_get_rate_dm_khz(u32 id)
unsigned long cm_get_mpu_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_MPU_CLK);
+ return cm_get_rate_dm(N5X_MPU_CLK);
}
unsigned int cm_get_l4_sys_free_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+ return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
- cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+ cm_get_rate_dm_khz(N5X_MPU_CLK));
printf("L4 Main %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
printf("L4 sys free %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
printf("L4 MP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MP_CLK));
printf("L4 SP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SP_CLK));
printf("SDMMC %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+ cm_get_rate_dm_khz(N5X_SDMMC_CLK));
}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index d0b172a30e..a8cb07a1c4 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#include
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#include
#endif
#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
new file mode 100644
index 00..54615ae8f7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#ifndef _CLOCK_MANAGER_N5X_
+#define _CLOCK_MANAGER_N5X_
+
+#include
+#include "../../../../../drivers/clk/altera/clk-n5x.h"
+
+#endif /* _CLOCK_MANAGER_N5X_ */
--
2.13.0
[v4 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5779c55621..58afde950f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,7 +32,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
@@ -45,7 +45,7 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += clock_manager_agilex.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
diff --git a/arch/arm/mach-socfpga/misc_s10.c
b/arch/arm/mach-socfpga/misc_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/misc_s10.c
rename to arch/arm/mach-socfpga/misc_soc64.c
index 50c7f19ae1..7b973a79e8 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -6,16 +6,16 @@
#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
#include
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
--
2.13.0
[v4 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h | 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h| 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
5 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 2f9b471af3..d0b172a30e 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
+unsigned long cm_get_mpu_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
index 386e82a4e3..4feae3dda9 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -6,8 +6,6 @@
#ifndef _CLOCK_MANAGER_AGILEX_
#define _CLOCK_MANAGER_AGILEX_
-unsigned long cm_get_mpu_clk_hz(void);
-
#include
#include "../../../../../drivers/clk/altera/clk-agilex.h"
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index 798d3741bd..553ebe660d 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -68,7 +68,6 @@ int cm_basic_init(const void *blob);
#include
unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned long cm_get_mpu_clk_hz(void);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 4cc1268b4c..d53095a7da 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -96,7 +96,6 @@ struct cm_config {
#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 98c3bf1b03..7f10296dc7 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -11,7 +11,6 @@
#include
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
--
2.13.0
[v4 07/17] drivers: clk: Add memory clock driver for Intel N5X device
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84
3 files changed, 221 insertions(+)
create mode 100644 drivers/clk/altera/clk-mem-n5x.c
create mode 100644 drivers/clk/altera/clk-mem-n5x.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 38cd730685..33db092918 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c
new file mode 100644
index 00..ca44998641
--- /dev/null
+++ b/drivers/clk/altera/clk-mem-n5x.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include "clk-mem-n5x.h"
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_mem_clk_plat {
+ void __iomem *regs;
+};
+
+void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
+{
+ u32 inter_val;
+ u32 retry = 0;
+
+ do {
+ inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
+
+ /* Wait for stable lock */
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+
+ if (retry >= 10)
+ return;
+ } while (1);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_mem_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+ /* Put PLLs in bypass */
+ clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
+
+ /* Put PLLs in Reset */
+ CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup mem PLL */
+ CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
+ CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
+
+ /* Take PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+}
+
+static int socfpga_mem_clk_enable(struct clk *clk)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
+
+ clk_mem_basic_init(clk->dev, cm_default_cfg);
+
+ clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
+ MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ MEMCLKMGR_MEMPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_mem_write_bypass_mempll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
+ MEMCLKMGR_INTER_MEMPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
+ MEMCLKMGR_EXTCNTRST_ALLCNTRST);
+
+ return 0;
+}
+
+static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_mem_clk_ops = {
+ .enable = socfpga_mem_clk_enable
+};
+
+static const struct udevice_id socfpga_mem_clk_match[] = {
+ { .compatible = "intel,n5x-mem-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_n5x_mem_clk) = {
+ .name = "mem-clk-n5x",
+ .id = UCLASS_CLK,
+ .of_match = socfpga_mem_clk_match,
+ .ops= &socfpga_mem_clk_ops,
+ .of_to_plat = socfp
[v4 06/17] arm: socfpga: Get clock manager base address for Intel N5X device
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 64a7c9d652..9305bec38a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void)
#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
ret = socfpga_get_base_addr("intel,agilex-clkmgr",
&socfpga_clkmgr_base);
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+ ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+ &socfpga_clkmgr_base);
#else
ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
#endif
--
2.13.0
[v4 05/17] drivers: clk: Add clock driver for Intel N5X device
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217 +++
include/dt-bindings/clock/n5x-clock.h | 71 +
4 files changed, 779 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/altera/clk-n5x.c
create mode 100644 drivers/clk/altera/clk-n5x.h
create mode 100644 include/dt-bindings/clock/n5x-clock.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 96215ad5c4..38cd730685 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Marek Vasut
+# Copyright (C) 2018-2021 Marek Vasut
#
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
new file mode 100644
index 00..bdcbbaae91
--- /dev/null
+++ b/drivers/clk/altera/clk-n5x.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_plat {
+ void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+ cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+ /* Always force clock manager into boot mode before any configuration */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+#else
+ /* Skip clock configuration in SSBL if it's not in boot mode */
+ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
+ return;
+#endif
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Put both PLLs in Reset */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup main PLL */
+ CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral */
+ CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+ CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+
+ /* Take both PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+ CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPIODBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_sdmmcctr, CLKMGR_ALTR_SDMMCCTR);
+ CM_REG_WRITEL(plat, cfg->alt_s2fuser0ct
[v4 04/17] arm: socfpga: Add handoff data support for Intel N5X device
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38 +-
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +--
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +++--
3 files changed, 140 insertions(+), 48 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 3750216a9a..902fc6bfb5 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2020 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -23,8 +23,36 @@
#define SOC64_HANDOFF_OFFSET_DATA 0x10
#define SOC64_HANDOFF_SIZE 4096
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SOC64_HANDOFF_BASE 0xFFE5F000
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
+
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE 0xFFE5C000
+#define SOC64_HANDOFF_DDR_MAGIC0x4852
+#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC 0x4C54434D
+#define SOC64_HANDOFF_DDR_UMCTL2_DDR4_TYPE 0x3452
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_0_TYPE 0x3044504C
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_1_TYPE 0x3144504C
+#define SOC64_HANDOFF_DDR_MEMRESET_BASE(SOC64_HANDOFF_DDR_BASE
+ 0xC)
+#define SOC64_HANDOFF_DDR_UMCTL2_SECTION (SOC64_HANDOFF_DDR_BASE + 0x10)
+#define SOC64_HANDOFF_DDR_PHY_MAGIC0x43594850
+#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC0x45594850
+#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_TYPE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_BASE_ADDR_OFFSET 0xC
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_1D_SECTION0xFFE5
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_1D_SECTION0xFFE58000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_2D_SECTION0xFFE44000
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_2D_SECTION0xFFE4C000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_LENGTHSZ_32K
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_LENGTHSZ_16K
+#endif
+
#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
@@ -52,11 +80,11 @@
#include
enum endianness {
LITTLE_ENDIAN = 0,
- BIG_ENDIAN
+ BIG_ENDIAN,
+ UNKNOWN_ENDIANNESS
};
-int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
-int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
-enum endianness big_endian);
+int socfpga_get_handoff_size(void *handoff_address);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len);
#endif
#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
index 3b5e774e2d..958bb5107b 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -66,10 +66,10 @@ void populate_sysmgr_fpgaintf_module(void)
void populate_sysmgr_pinmux(void)
{
u32 len, i;
- u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX,
BIG_ENDIAN);
- u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL,
BIG_ENDIAN);
- u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA,
BIG_ENDIAN);
- u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY,
BIG_ENDIAN);
+ u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX);
+ u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL);
+ u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA);
+ u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY);
len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
len = (len > len_fpga) ? len : len_fpga;
@@ -79,7 +79,7 @@ void populate_sysmgr_pinmux(void)
/* setup the pin sel */
len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux :
SOC64_HANDOFF_MUX_LEN;
- socfpga_handoff_read((void *)SOC64_HANDOFF_MUX, handoff_table, len,
BIG_ENDIAN);
+ socfpga_han
[v4 03/17] arm: socfpga: Add base address for Intel N5X device
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index f89066d771..3f899fcfa3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -10,7 +10,8 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801 #define SOCFPGA_SDR_ADDRESS0xf8011000 -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 -- 2.13.0
[v4 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h| 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h =>
base_addr_soc64.h} (89%)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
similarity index 89%
rename from arch/arm/mach-socfpga/include/mach/base_addr_s10.h
rename to arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index d3eca65e97..f89066d771 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
-#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
-#define _SOCFPGA_S10_BASE_HARDWARE_H_
+#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
#define SOCFPGA_CCU_ADDRESS0xf700
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
@@ -44,4 +44,4 @@
#define GICD_BASE 0xfffc1000
#define GICC_BASE 0xfffc2000
-#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
+#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index 38fd775b5b..0b0470ebc1 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -7,7 +7,7 @@
#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
-#include
+#include
#include
#include
--
2.13.0
[v4 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_atf_defconfig | 2 +-
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 36eecdc057..7267163222 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -116,17 +116,18 @@ void board_fit_image_post_process(const void *fit, int
node, void **p_image,
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(bootm_headers_t *images)
{
- if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
- !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
- /*
-* Ensure the OS is always booted from FIT and with
-* VAB signed certificate
-*/
- if (!images->fit_uname_cfg) {
+ if (!images->fit_uname_cfg) {
+ if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
+
!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
+ /*
+* Ensure the OS is always booted from FIT and with
+* VAB signed certificate
+*/
printf("Please use FIT with VAB signed images!\n");
hang();
}
-
+ } else {
+ /* Update fdt_addr in enviroment variable */
env_set_hex("fdt_addr", (ulong)images->ft_addr);
debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
}
diff --git a/configs/socfpga_agilex_atf_defconfig
b/configs/socfpga_agilex_atf_defconfig
index 6921575635..95899adc1a 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/socfpga_stratix10_atf_defconfig
b/configs/socfpga_stratix10_atf_defconfig
index cd1b6f9bba..00803cc406 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
--
2.13.0
[v4 00/17] Add Intel N5X SoC support
This is the 4th version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot without ATF for debugging purpose,
ATF boot, and ATF boot with VAB enabled.
[1]:
https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Patch status:
Have changes: Patch 15
Other patches unchanged.
Detail changelog can find in commit message.
v3->v4:
Patch 15:
- Reuse socfpga_n5x_socdk.dts from Linux and add U-boot specifc dts
to u-boot.dtsi. Linux socfpga_n5x_socdk.dts:
https://github.com/altera-opensource/linux-socfpga/blob/socfpga-5.4.114-lts/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
History:
[v1]
https://patchwork.ozlabs.org/project/uboot/cover/20210331143908.48211-1-elly.siew.chin@intel.com/
[v2]
https://patchwork.ozlabs.org/project/uboot/cover/20210430073814.193576-1-elly.siew.chin@intel.com/
[v3]
https://patchwork.ozlabs.org/project/uboot/cover/20210613084852.30868-1-elly.siew.chin@intel.com/
Siew Chin Lim (14):
arm: socfpga: Move linux_qspi_enable from bootcommand to
board_prep_linux function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
drivers: clk: Add clock driver for Intel N5X device
arm: socfpga: Get clock manager base address for Intel N5X device
drivers: clk: Add memory clock driver for Intel N5X device
arm: socfpga: Move cm_get_mpu_clk_hz function declaration to
clock_manager.h
arm: socfpga: Add clock manager for Intel N5X device
arm: socfpga: Changed misc_s10.c to misc_soc64.c
arm: socfpga: Add SPL for Intel N5X device
board: intel: Add socdk board support for Intel N5X device
arm: dts: Add base dtsi and devkit dts for Intel N5X device
include: configs: Add Intel N5X device CONFIGs
arm: socfpga: Enable Intel N5X device build
Tien Fong Chee (3):
arm: socfpga: Add handoff data support for Intel N5X device
ddr: socfpga: Enable memory test on memory size less than 1GB
ddr: altera: Add SDRAM driver for Intel N5X device
arch/arm/dts/Makefile |1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 192 ++
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 100 +
arch/arm/dts/socfpga_n5x_socdk.dts | 88 +
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile | 32 +-
arch/arm/mach-socfpga/board.c | 17 +-
arch/arm/mach-socfpga/clock_manager_n5x.c | 80 +
.../mach/{base_addr_s10.h => base_addr_soc64.h}| 11 +-
arch/arm/mach-socfpga/include/mach/clock_manager.h |3 +
.../include/mach/clock_manager_agilex.h|2 -
.../include/mach/clock_manager_arria10.h |1 -
.../mach-socfpga/include/mach/clock_manager_gen5.h |1 -
.../mach-socfpga/include/mach/clock_manager_n5x.h | 12 +
.../mach-socfpga/include/mach/clock_manager_s10.h |1 -
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 38 +-
.../include/mach/system_manager_soc64.h| 10 +-
arch/arm/mach-socfpga/misc.c |3 +
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +-
arch/arm/mach-socfpga/spl_n5x.c| 94 +
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c | 132 +-
board/intel/n5x-socdk/MAINTAINERS |7 +
board/intel/n5x-socdk/Makefile |7 +
board/intel/n5x-socdk/socfpga.c|7 +
configs/socfpga_agilex_atf_defconfig |2 +-
...lex_atf_defconfig => socfpga_n5x_atf_defconfig} | 13 +-
..._agilex_atf_defconfig => socfpga_n5x_defconfig} | 28 +-
...lex_atf_defconfig => socfpga_n5x_vab_defconfig} | 14 +-
configs/socfpga_stratix10_atf_defconfig|2 +-
drivers/clk/altera/Makefile|4 +-
drivers/clk/altera/clk-mem-n5x.c | 136 ++
drivers/clk/altera/clk-mem-n5x.h | 84 +
drivers/clk/altera/clk-n5x.c | 489 +
drivers/clk/altera/clk-n5x.h | 217 ++
drivers/ddr/altera/Makefile|3 +-
drivers/ddr/altera/sdram_n5x.c | 2298
drivers/ddr/altera/sdram_soc64.c | 94 +-
drivers/ddr/altera/sdram_soc64.h |1 +
include/configs/socfpga_n5x_socdk.h| 45 +
include/configs/socfpga_soc64_common.h |2 +-
include/dt-bindings/clock/n5x-clock.h | 71 +
43 files changed, 4280 insertions
[v3 17/17] arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile| 28 +++
...ab_defconfig => socfpga_n5x_atf_defconfig} | 12
...agilex_defconfig => socfpga_n5x_defconfig} | 14 --
...ab_defconfig => socfpga_n5x_vab_defconfig} | 11
5 files changed, 61 insertions(+), 25 deletions(-)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_atf_defconfig} (87%)
copy configs/{socfpga_agilex_defconfig => socfpga_n5x_defconfig} (82%)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_vab_defconfig} (87%)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0c35406232..a4d733c756 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,7 +8,7 @@ config NR_DRAM_BANKS
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
- depends on TARGET_SOCFPGA_AGILEX
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512_ALGO
@@ -91,6 +91,22 @@ config TARGET_SOCFPGA_GEN5
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF
+config TARGET_SOCFPGA_N5X
+ bool
+ select ARMV8_MULTIENTRY
+ select ARMV8_SET_SMPEN
+ select BINMAN if SPL_ATF
+ select CLK
+ select FPGA_INTEL_SDM_MAILBOX
+ select NCORE_CACHE
+ select SPL_ALTERA_SDRAM
+ select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
+
+config TARGET_SOCFPGA_N5X_SOCDK
+ bool "Intel eASIC SoCDK (N5X)"
+ select TARGET_SOCFPGA_N5X
+
config TARGET_SOCFPGA_SOC64
bool
@@ -183,6 +199,7 @@ config SYS_BOARD
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
@@ -194,6 +211,7 @@ config SYS_BOARD
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
+ default "intel" if TARGET_SOCFPGA_N5X_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -221,6 +239,7 @@ config SYS_CONFIG_NAME
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 58afde950f..ec38b64dd4 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation
-# Copyright (C) 2017-2020 Intel Corporation
+# Copyright (C) 2017-2021 Intel Corporation
obj-y += board.o
obj-y += clock_manager.o
@@ -56,6 +56,21 @@ obj-y+= wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += clock_manager_n5x.o
+obj-y += lowlevel_init_soc64.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += system_manager_soc64.o
+obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
+obj-y += wrap_handoff_soc64.o
+obj-y += wrap_pll_config_soc64.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
@@ -64,18 +79,21 @@ obj-y += wrap_iocsr_config.o
obj-y += wrap_pinmux_config.o
obj-y += wrap_sdram_config.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_SOC64
+obj-y += firewall.o
+obj-y += spl_soc64.o
+endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += spl_a10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-obj-y += firewall.o
obj-y += spl_s10.o
-obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-obj-y += firewall.o
obj-y += spl_agilex.o
-obj-y += spl_soc64.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += spl_n5x.o
endif
else
obj-$(CONFIG_SPL_ATF) += secur
[v3 16/17] include: configs: Add Intel N5X device CONFIGs
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socfpga_n5x_socdk.h
new file mode 100644
index 00..c295e91e3d
--- /dev/null
+++ b/include/configs/socfpga_n5x_socdk.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_N5X_H__
+#define __CONFIG_SOCFGPA_N5X_H__
+
+#include
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "fdt_addr=110\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then" \
+ " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; fi; fi\0" \
+ "scriptaddr=0x0210\0" \
+ "scriptfile=u-boot.scr\0" \
+ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+ "then source ${scriptaddr}; fi\0"
+
+#endif /* __CONFIG_SOCFGPA_N5X_H__ */
--
2.19.0
[v3 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v3:
- Update comment for memory example code
- Move all common dts settings for N5X from
socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi
- Remove unused parameter "u-boot,boot0"
v2:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
n5x data accordingly.
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 175 ++
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi| 67 +++
...agilex_socdk.dts => socfpga_n5x_socdk.dts} | 25 ++-
4 files changed, 262 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/dts/socfpga_n5x-u-boot.dtsi
create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (81%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 096068261d..8a513e2a87 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -393,6 +393,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb\
+ socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
diff --git a/arch/arm/dts/socfpga_n5x-u-boot.dtsi
b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
new file mode 100644
index 00..d144116e71
--- /dev/null
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -0,0 +1,175 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
+/{
+ memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ u-boot,dm-pre-reloc;
+ };
+
+ soc {
+ u-boot,dm-pre-reloc;
+
+ ccu: cache-controller@f700 {
+ compatible = "arteris,ncore-ccu";
+ reg = <0xf700 0x100900>;
+ u-boot,dm-pre-reloc;
+ };
+ };
+};
+
+&clkmgr {
+ compatible = "intel,n5x-clkmgr";
+ u-boot,dm-pre-reloc;
+};
+
+
+&gmac1 {
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ clocks = <&clkmgr N5X_EMAC1_CLK>;
+};
+
+&gmac2 {
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ clocks = <&clkmgr N5X_EMAC2_CLK>;
+};
+
+&i2c0 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&i2c4 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ reset-names = "i2c";
+};
+
+&memclkmgr {
+ u-boot,dm-pre-reloc;
+};
+
+
+&mmc {
+ clocks = <&clkmgr N5X_L4_MP_CLK>,
+<&clkmgr N5X_SDMMC_CLK>;
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&pdma {
+ clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&spi0 {
+ clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&spi1 {
+ clocks = <&clkmgr N5X_L4_MAIN_CLK>;
+};
+
+&timer0 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&timer1 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&timer2 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&timer3 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
+&rst {
+ compatible = "altr,rst-mgr";
+ altr,modrst-offset = <0x20>;
+ u-boot,dm-pre-reloc;
+};
+
+&sdr {
+ compatible = "intel,sdr-ctl-n5x";
+ resets = <&rst DDRSCH_RESET>;
+ clocks = <&memclkmgr>;
+ clock-names = "mem_clk";
+ u-boot,dm-pre-reloc;
+};
+
+&sysmgr {
+ compatible = "altr,sys-mgr", "syscon";
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 {
+ clocks = <&clkmgr N5X_L4_SP_CLK>;
+};
+
+&usb0 {
+ clocks = <&clkmgr N5X_USB_CLK>;
+ disable-over-current;
+ u-boot,dm-pre-reloc;
+};
+
+&usb1 {
+ cloc
[v3 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
From: Tien Fong Chee
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v3:
- Sorting header
- Used prefix OPM_xxx
- Simplify the code with do...while loop.
- Created common function for processing handoff
- Adding function of calibration data feedback to LPDDR4 controllers
v2:
- Move is_ddr_init_skipped and its helper functions to DDR driver and
converted function to positive checking
- Using GENMASK() macro
- Fixed typo
- Return status of subfunction
- Changed dm to n5x
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach/system_manager_soc64.h | 10 +-
drivers/ddr/altera/Makefile |3 +-
drivers/ddr/altera/sdram_n5x.c| 2298 +
drivers/ddr/altera/sdram_soc64.c | 70 +
drivers/ddr/altera/sdram_soc64.h |1 +
6 files changed, 2386 insertions(+), 2 deletions(-)
create mode 100644 drivers/ddr/altera/sdram_n5x.c
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
index adab65bc96..5cb7f23f8f 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -115,10 +115,16 @@ struct socfpga_firwall_l4_sys {
/* Firewall MPU DDR SCR registers */
#define FW_MPU_DDR_SCR_EN 0x00
#define FW_MPU_DDR_SCR_EN_SET 0x04
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT0x18
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
+
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD0xff
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index fc4e17821b..a8009664fe 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2021 Intel Corporation
*/
#ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -28,8 +28,12 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c
#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
#define SYSMGR_SOC64_DMA_L3MASTER 0x74
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SYSMGR_SOC64_DDR_MODE 0xb8
+#else
#define SYSMGR_SOC64_HMC_CLK 0xb4
#define SYSMGR_SOC64_IO_PA_CTRL0xb8
+#endif
#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0
#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4
#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8
@@ -143,4 +147,8 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#defineSYSMGR_SOC64_DDR_MODE_MSK BIT(0)
+#endif
+
#endif /* _SYSTEM_MANAGER_SOC64_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 39dfee5d5a..9fa5d85a27 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -4,11 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# (C) Copyright 2010, Thomas Chou
-# Copyright (C) 2014 Altera Corporation
+# Copyright (C) 2014-2021 Altera Corporation
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
endif
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
new file
[v3 14/17] board: intel: Add socdk board support for Intel N5X device
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
.../{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
create mode 100644 board/intel/n5x-socdk/MAINTAINERS
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile (50%)
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c (52%)
diff --git a/board/intel/n5x-socdk/MAINTAINERS
b/board/intel/n5x-socdk/MAINTAINERS
new file mode 100644
index 00..c1059f092c
--- /dev/null
+++ b/board/intel/n5x-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chee Tien Fong
+M: Lim Siew Chin
+S: Maintained
+F: board/intel/n5x-socdk/
+F: include/configs/socfpga_n5x_socdk.h
+F: configs/socfpga_n5x_atf_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile
b/board/intel/n5x-socdk/Makefile
similarity index 50%
copy from board/altera/stratix10-socdk/Makefile
copy to board/intel/n5x-socdk/Makefile
index 02a9cadf76..accfdcddcb 100644
--- a/board/altera/stratix10-socdk/Makefile
+++ b/board/intel/n5x-socdk/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2016-2017 Intel Corporation
+# Copyright (C) 2020-2021 Intel Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
diff --git a/board/altera/stratix10-socdk/socfpga.c
b/board/intel/n5x-socdk/socfpga.c
similarity index 52%
copy from board/altera/stratix10-socdk/socfpga.c
copy to board/intel/n5x-socdk/socfpga.c
index 043fc543f1..985ba190d0 100644
--- a/board/altera/stratix10-socdk/socfpga.c
+++ b/board/intel/n5x-socdk/socfpga.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
--
2.19.0
[v3 13/17] arm: socfpga: Add SPL for Intel N5X device
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
.../mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 +++
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_n5x.c
similarity index 83%
copy from arch/arm/mach-socfpga/spl_agilex.c
copy to arch/arm/mach-socfpga/spl_n5x.c
index ee5a9dc1e2..d056871d29 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -1,27 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,27 +53,35 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
+ preloader_console_init();
+
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
- debug("Clock init failed: %d\n", ret);
+ printf("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 1, &dev);
+ if (ret) {
+ printf("Memory clock init failed: %d\n", ret);
hang();
}
- preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();
+
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
- debug("CCU init failed: %d\n", ret);
+ printf("CCU init failed: %d\n", ret);
hang();
}
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
- debug("DRAM init failed: %d\n", ret);
+ printf("DRAM init failed: %d\n", ret);
hang();
}
#endif
--
2.19.0
[v3 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index a08f0953e5..cc656db97c 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2019 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -182,6 +182,7 @@ void sdram_size_check(struct bd_info *bd)
phys_size_t total_ram_check = 0;
phys_size_t ram_check = 0;
phys_addr_t start = 0;
+ phys_size_t size, remaining_size;
int bank;
/* Sanity check ensure correct SDRAM size specified */
@@ -189,10 +190,27 @@ void sdram_size_check(struct bd_info *bd)
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = bd->bi_dram[bank].start;
+ remaining_size = bd->bi_dram[bank].size;
while (ram_check < bd->bi_dram[bank].size) {
- ram_check += get_ram_size((void *)(start + ram_check),
-(phys_size_t)SZ_1G);
+ size = min((phys_addr_t)SZ_1G,
+ (phys_addr_t)remaining_size);
+
+ /*
+* Ensure the size is power of two, this is requirement
+* to run get_ram_size() / memory test
+*/
+ if (size != 0 && ((size & (size - 1)) == 0)) {
+ ram_check += get_ram_size((void *)
+ (start + ram_check), size);
+ remaining_size = bd->bi_dram[bank].size -
+ ram_check;
+ } else {
+ puts("DDR: Memory test requires SDRAM size ");
+ puts("in power of two!\n");
+ hang();
+ }
}
+
total_ram_check += ram_check;
ram_check = 0;
}
--
2.19.0
[v3 09/17] arm: socfpga: Add clock manager for Intel N5X device
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...k_manager_agilex.c => clock_manager_n5x.c} | 32 +--
.../mach-socfpga/include/mach/clock_manager.h | 2 ++
.../include/mach/clock_manager_n5x.h | 12 +++
3 files changed, 29 insertions(+), 17 deletions(-)
copy arch/arm/mach-socfpga/{clock_manager_agilex.c => clock_manager_n5x.c}
(64%)
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
b/arch/arm/mach-socfpga/clock_manager_n5x.c
similarity index 64%
copy from arch/arm/mach-socfpga/clock_manager_agilex.c
copy to arch/arm/mach-socfpga/clock_manager_n5x.c
index e035c09aae..4f098533e7 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_n5x.c
@@ -1,19 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -25,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id)
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(socfpga_agilex_clk),
+ DM_DRIVER_GET(socfpga_n5x_clk),
&dev);
if (ret)
return 0;
@@ -39,8 +38,7 @@ static ulong cm_get_rate_dm(u32 id)
clk_free(&clk);
- if ((rate == (unsigned long)-ENOSYS) ||
- (rate == (unsigned long)-ENXIO) ||
+ if ((rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO)) {
debug("%s id %u: clk_get_rate err: %ld\n",
__func__, id, rate);
@@ -57,26 +55,26 @@ static u32 cm_get_rate_dm_khz(u32 id)
unsigned long cm_get_mpu_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_MPU_CLK);
+ return cm_get_rate_dm(N5X_MPU_CLK);
}
unsigned int cm_get_l4_sys_free_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+ return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
- cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+ cm_get_rate_dm_khz(N5X_MPU_CLK));
printf("L4 Main %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
printf("L4 sys free %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
printf("L4 MP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MP_CLK));
printf("L4 SP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SP_CLK));
printf("SDMMC %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+ cm_get_rate_dm_khz(N5X_SDMMC_CLK));
}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index d0b172a30e..a8cb07a1c4 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#include
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#include
#endif
#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
new file mode 100644
index 00..54615ae8f7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#ifndef _CLOCK_MANAGER_N5X_
+#define _CLOCK_MANAGER_N5X_
+
+#include
+#include "../../../../../drivers/clk/altera/clk-n5x.h"
+
+#endif /* _CLOCK_MANAGER_N5X_ */
--
2.19.0
[v3 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5779c55621..58afde950f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,7 +32,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
@@ -45,7 +45,7 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += clock_manager_agilex.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
diff --git a/arch/arm/mach-socfpga/misc_s10.c
b/arch/arm/mach-socfpga/misc_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/misc_s10.c
rename to arch/arm/mach-socfpga/misc_soc64.c
index 50c7f19ae1..7b973a79e8 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -6,16 +6,16 @@
#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
#include
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
--
2.19.0
[v3 07/17] drivers: clk: Add memory clock driver for Intel N5X device
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
v3:
- Use BIT() and GENMASK() macro for all *MASK macro
v2:
- common.h need to be included before clock_manager.h
- For consistency, use small letter fo 0x0c and 0x1c in macros
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84 +++
3 files changed, 221 insertions(+)
create mode 100644 drivers/clk/altera/clk-mem-n5x.c
create mode 100644 drivers/clk/altera/clk-mem-n5x.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 38cd730685..33db092918 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c
new file mode 100644
index 00..ca44998641
--- /dev/null
+++ b/drivers/clk/altera/clk-mem-n5x.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include "clk-mem-n5x.h"
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_mem_clk_plat {
+ void __iomem *regs;
+};
+
+void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
+{
+ u32 inter_val;
+ u32 retry = 0;
+
+ do {
+ inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
+
+ /* Wait for stable lock */
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+
+ if (retry >= 10)
+ return;
+ } while (1);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_mem_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+ /* Put PLLs in bypass */
+ clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
+
+ /* Put PLLs in Reset */
+ CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup mem PLL */
+ CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
+ CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
+
+ /* Take PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+}
+
+static int socfpga_mem_clk_enable(struct clk *clk)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
+
+ clk_mem_basic_init(clk->dev, cm_default_cfg);
+
+ clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
+ MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ MEMCLKMGR_MEMPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_mem_write_bypass_mempll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
+ MEMCLKMGR_INTER_MEMPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
+ MEMCLKMGR_EXTCNTRST_ALLCNTRST);
+
+ return 0;
+}
+
+static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_mem_clk_ops = {
+ .enable = socfpga_mem_clk_enable
+};
+
+static const struct udevice_id socfpga_mem_clk_match[] = {
+ { .compatible = "intel,n5x-mem-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_n5x_mem_clk) = {
+ .name = "mem-clk-n5x"
[v3 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h | 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h| 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
5 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 2f9b471af3..d0b172a30e 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
+unsigned long cm_get_mpu_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
index 386e82a4e3..4feae3dda9 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -6,8 +6,6 @@
#ifndef _CLOCK_MANAGER_AGILEX_
#define _CLOCK_MANAGER_AGILEX_
-unsigned long cm_get_mpu_clk_hz(void);
-
#include
#include "../../../../../drivers/clk/altera/clk-agilex.h"
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index 798d3741bd..553ebe660d 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -68,7 +68,6 @@ int cm_basic_init(const void *blob);
#include
unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned long cm_get_mpu_clk_hz(void);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 4cc1268b4c..d53095a7da 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -96,7 +96,6 @@ struct cm_config {
#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 98c3bf1b03..7f10296dc7 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -11,7 +11,6 @@
#include
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
--
2.19.0
[v3 04/17] arm: socfpga: Add handoff data support for Intel N5X device
From: Tien Fong Chee
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v3
- Adding helper function for getting endianness type.
v2:
- Enabled auto detect the endianness from the magic word
- Merged and simplifying the big and little endian flow
---
.../mach-socfpga/include/mach/handoff_soc64.h | 38 -
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +--
arch/arm/mach-socfpga/wrap_handoff_soc64.c| 132 +-
3 files changed, 140 insertions(+), 48 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 3750216a9a..902fc6bfb5 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2020 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -23,8 +23,36 @@
#define SOC64_HANDOFF_OFFSET_DATA 0x10
#define SOC64_HANDOFF_SIZE 4096
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SOC64_HANDOFF_BASE 0xFFE5F000
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
+
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE 0xFFE5C000
+#define SOC64_HANDOFF_DDR_MAGIC0x4852
+#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC 0x4C54434D
+#define SOC64_HANDOFF_DDR_UMCTL2_DDR4_TYPE 0x3452
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_0_TYPE 0x3044504C
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_1_TYPE 0x3144504C
+#define SOC64_HANDOFF_DDR_MEMRESET_BASE(SOC64_HANDOFF_DDR_BASE
+ 0xC)
+#define SOC64_HANDOFF_DDR_UMCTL2_SECTION (SOC64_HANDOFF_DDR_BASE + 0x10)
+#define SOC64_HANDOFF_DDR_PHY_MAGIC0x43594850
+#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC0x45594850
+#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_TYPE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_BASE_ADDR_OFFSET 0xC
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_1D_SECTION0xFFE5
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_1D_SECTION0xFFE58000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_2D_SECTION0xFFE44000
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_2D_SECTION0xFFE4C000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_LENGTHSZ_32K
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_LENGTHSZ_16K
+#endif
+
#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
@@ -52,11 +80,11 @@
#include
enum endianness {
LITTLE_ENDIAN = 0,
- BIG_ENDIAN
+ BIG_ENDIAN,
+ UNKNOWN_ENDIANNESS
};
-int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
-int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
-enum endianness big_endian);
+int socfpga_get_handoff_size(void *handoff_address);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len);
#endif
#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
index 3b5e774e2d..958bb5107b 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -66,10 +66,10 @@ void populate_sysmgr_fpgaintf_module(void)
void populate_sysmgr_pinmux(void)
{
u32 len, i;
- u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX,
BIG_ENDIAN);
- u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL,
BIG_ENDIAN);
- u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA,
BIG_ENDIAN);
- u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY,
BIG_ENDIAN);
+ u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX);
+ u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL);
+ u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA);
+ u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY);
len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
len = (len > len_fpga) ? len : len_fpga;
@@ -79,7 +79,7 @@ void populate_sysmgr_pinmux(void)
/* setup the pin sel */
len = (l
[v3 05/17] drivers: clk: Add clock driver for Intel N5X device
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
v3:
- Use BIT() macro for CLKMGR_INTER_*_MASK macro
v2:
- common.h need to be included before clock_manager.h
- Remove unnecessary comment : write 1 to clear
- Remove unnecessary () in the code
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217
include/dt-bindings/clock/n5x-clock.h | 71
4 files changed, 779 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/altera/clk-n5x.c
create mode 100644 drivers/clk/altera/clk-n5x.h
create mode 100644 include/dt-bindings/clock/n5x-clock.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 96215ad5c4..38cd730685 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Marek Vasut
+# Copyright (C) 2018-2021 Marek Vasut
#
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
new file mode 100644
index 00..bdcbbaae91
--- /dev/null
+++ b/drivers/clk/altera/clk-n5x.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_plat {
+ void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+ cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+ /* Always force clock manager into boot mode before any configuration */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+#else
+ /* Skip clock configuration in SSBL if it's not in boot mode */
+ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
+ return;
+#endif
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Put both PLLs in Reset */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup main PLL */
+ CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral */
+ CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+ CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+
+ /* Take both PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+ CM_REG_WRI
[v3 06/17] arm: socfpga: Get clock manager base address for Intel N5X device
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 64a7c9d652..9305bec38a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void)
#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
ret = socfpga_get_base_addr("intel,agilex-clkmgr",
&socfpga_clkmgr_base);
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+ ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+ &socfpga_clkmgr_base);
#else
ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
#endif
--
2.19.0
[v3 03/17] arm: socfpga: Add base address for Intel N5X device
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index f89066d771..3f899fcfa3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -10,7 +10,8 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801 #define SOCFPGA_SDR_ADDRESS0xf8011000 -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 -- 2.19.0
[v3 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h| 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h =>
base_addr_soc64.h} (89%)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
similarity index 89%
rename from arch/arm/mach-socfpga/include/mach/base_addr_s10.h
rename to arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index d3eca65e97..f89066d771 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
-#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
-#define _SOCFPGA_S10_BASE_HARDWARE_H_
+#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
#define SOCFPGA_CCU_ADDRESS0xf700
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
@@ -44,4 +44,4 @@
#define GICD_BASE 0xfffc1000
#define GICC_BASE 0xfffc2000
-#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
+#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index 5afdb10454..f0b7884ebc 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -7,7 +7,7 @@
#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
-#include
+#include
#include
#include
--
2.19.0
[v3 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_atf_defconfig | 2 +-
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 650122fcd4..f5a3f2ad62 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -115,17 +115,18 @@ void board_fit_image_post_process(void **p_image, size_t
*p_size)
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(bootm_headers_t *images)
{
- if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
- !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
- /*
-* Ensure the OS is always booted from FIT and with
-* VAB signed certificate
-*/
- if (!images->fit_uname_cfg) {
+ if (!images->fit_uname_cfg) {
+ if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
+
!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
+ /*
+* Ensure the OS is always booted from FIT and with
+* VAB signed certificate
+*/
printf("Please use FIT with VAB signed images!\n");
hang();
}
-
+ } else {
+ /* Update fdt_addr in enviroment variable */
env_set_hex("fdt_addr", (ulong)images->ft_addr);
debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
}
diff --git a/configs/socfpga_agilex_atf_defconfig
b/configs/socfpga_agilex_atf_defconfig
index 29e3fb865e..a4b9c23919 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/socfpga_stratix10_atf_defconfig
b/configs/socfpga_stratix10_atf_defconfig
index 9f2f220c3a..3a05d4f486 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
--
2.19.0
[v3 00/17] Add Intel N5X SoC support
This is the 3rd version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot without ATF for debugging purpose,
ATF boot, and ATF boot with VAB enabled.
[1]:
https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Patch status:
Have changes: Patch 4, 5, 7, 12, 15
Other patches unchanged.
Detail changelog can find in commit message.
v2->v3:
Patch 4:
- Adding helper function for getting endianness type.
Patch 5:
- Use BIT() macro for CLKMGR_INTER_*_MASK macro
Patch 7:
- Use BIT() and GENMASK() macro for all *MASK macro
Patch 12:
- Sorting header
- Used prefix OPM_xxx
- Simplify the code with do...while loop.
- Created common function for processing handoff
- Adding function of calibration data feedback to LPDDR4 controllers
Patch 15:
- Update comment for memory example code
- Move all common dts settings for N5X from
socfpga_n5x_socdk.dts to socfpga_n5x-u-boot.dtsi
- Remove unused parameter "u-boot,boot0"
History:
[v1]
https://patchwork.ozlabs.org/project/uboot/cover/20210331143908.48211-1-elly.siew.chin@intel.com/
[v2]
https://patchwork.ozlabs.org/project/uboot/cover/20210430073814.193576-1-elly.siew.chin@intel.com/
Siew Chin Lim (14):
arm: socfpga: Move linux_qspi_enable from bootcommand to
board_prep_linux function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
drivers: clk: Add clock driver for Intel N5X device
arm: socfpga: Get clock manager base address for Intel N5X device
drivers: clk: Add memory clock driver for Intel N5X device
arm: socfpga: Move cm_get_mpu_clk_hz function declaration to
clock_manager.h
arm: socfpga: Add clock manager for Intel N5X device
arm: socfpga: Changed misc_s10.c to misc_soc64.c
arm: socfpga: Add SPL for Intel N5X device
board: intel: Add socdk board support for Intel N5X device
arm: dts: Add base dtsi and devkit dts for Intel N5X device
include: configs: Add Intel N5X device CONFIGs
arm: socfpga: Enable Intel N5X device build
Tien Fong Chee (3):
arm: socfpga: Add handoff data support for Intel N5X device
ddr: socfpga: Enable memory test on memory size less than 1GB
ddr: altera: Add SDRAM driver for Intel N5X device
arch/arm/dts/Makefile |1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 175 ++
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi| 67 +
arch/arm/dts/socfpga_n5x_socdk.dts| 154 ++
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile| 32 +-
arch/arm/mach-socfpga/board.c | 17 +-
arch/arm/mach-socfpga/clock_manager_n5x.c | 80 +
.../{base_addr_s10.h => base_addr_soc64.h}| 11 +-
.../mach-socfpga/include/mach/clock_manager.h |3 +
.../include/mach/clock_manager_agilex.h |2 -
.../include/mach/clock_manager_arria10.h |1 -
.../include/mach/clock_manager_gen5.h |1 -
.../include/mach/clock_manager_n5x.h | 12 +
.../include/mach/clock_manager_s10.h |1 -
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../mach-socfpga/include/mach/handoff_soc64.h | 38 +-
.../include/mach/system_manager_soc64.h | 10 +-
arch/arm/mach-socfpga/misc.c |3 +
.../mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +-
arch/arm/mach-socfpga/spl_n5x.c | 94 +
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c| 132 +-
board/intel/n5x-socdk/MAINTAINERS |7 +
board/intel/n5x-socdk/Makefile|7 +
board/intel/n5x-socdk/socfpga.c |7 +
configs/socfpga_agilex_atf_defconfig |2 +-
...tf_defconfig => socfpga_n5x_atf_defconfig} | 13 +-
...ex_atf_defconfig => socfpga_n5x_defconfig} | 29 +-
...tf_defconfig => socfpga_n5x_vab_defconfig} | 14 +-
configs/socfpga_stratix10_atf_defconfig |2 +-
drivers/clk/altera/Makefile |4 +-
drivers/clk/altera/clk-mem-n5x.c | 136 +
drivers/clk/altera/clk-mem-n5x.h | 84 +
drivers/clk/altera/clk-n5x.c | 489
drivers/clk/altera/clk-n5x.h | 217 ++
drivers/ddr/altera/Makefile |3 +-
drivers/ddr/altera/sdram_n5x.c| 2298 +
drivers/ddr/altera/sdram_soc64.c | 94 +-
drivers/ddr/altera/sdram_soc64.h |1 +
include/configs/socfpga_n5x_socdk.h | 45 +
include/configs/socfpga_soc64_common.h|2 +-
include/dt-bindings/clock/n5x-clock.h | 71 +
43 fi
[v2 17/17] arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
v2:
- Move linux_qspi_enable from bootcommand
---
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile| 28 +++
...ab_defconfig => socfpga_n5x_atf_defconfig} | 12
...agilex_defconfig => socfpga_n5x_defconfig} | 14 --
...ab_defconfig => socfpga_n5x_vab_defconfig} | 11
5 files changed, 61 insertions(+), 25 deletions(-)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_atf_defconfig} (87%)
copy configs/{socfpga_agilex_defconfig => socfpga_n5x_defconfig} (82%)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_vab_defconfig} (87%)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0c35406232..a4d733c756 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,7 +8,7 @@ config NR_DRAM_BANKS
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
- depends on TARGET_SOCFPGA_AGILEX
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512_ALGO
@@ -91,6 +91,22 @@ config TARGET_SOCFPGA_GEN5
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF
+config TARGET_SOCFPGA_N5X
+ bool
+ select ARMV8_MULTIENTRY
+ select ARMV8_SET_SMPEN
+ select BINMAN if SPL_ATF
+ select CLK
+ select FPGA_INTEL_SDM_MAILBOX
+ select NCORE_CACHE
+ select SPL_ALTERA_SDRAM
+ select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
+
+config TARGET_SOCFPGA_N5X_SOCDK
+ bool "Intel eASIC SoCDK (N5X)"
+ select TARGET_SOCFPGA_N5X
+
config TARGET_SOCFPGA_SOC64
bool
@@ -183,6 +199,7 @@ config SYS_BOARD
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
@@ -194,6 +211,7 @@ config SYS_BOARD
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
+ default "intel" if TARGET_SOCFPGA_N5X_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -221,6 +239,7 @@ config SYS_CONFIG_NAME
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 58afde950f..ec38b64dd4 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation
-# Copyright (C) 2017-2020 Intel Corporation
+# Copyright (C) 2017-2021 Intel Corporation
obj-y += board.o
obj-y += clock_manager.o
@@ -56,6 +56,21 @@ obj-y+= wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += clock_manager_n5x.o
+obj-y += lowlevel_init_soc64.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += system_manager_soc64.o
+obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
+obj-y += wrap_handoff_soc64.o
+obj-y += wrap_pll_config_soc64.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
@@ -64,18 +79,21 @@ obj-y += wrap_iocsr_config.o
obj-y += wrap_pinmux_config.o
obj-y += wrap_sdram_config.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_SOC64
+obj-y += firewall.o
+obj-y += spl_soc64.o
+endif
ifdef CONFIG_TARGET_SOCFPGA_ARRIA10
obj-y += spl_a10.o
endif
ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
-obj-y += firewall.o
obj-y += spl_s10.o
-obj-y += spl_soc64.o
endif
ifdef CONFIG_TARGET_SOCFPGA_AGILEX
-obj-y += firewall.o
obj-y += spl_agilex.o
-obj-y += spl_soc64.o
+endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += spl
[v2 16/17] include: configs: Add Intel N5X device CONFIGs
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socfpga_n5x_socdk.h
new file mode 100644
index 00..c295e91e3d
--- /dev/null
+++ b/include/configs/socfpga_n5x_socdk.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_N5X_H__
+#define __CONFIG_SOCFGPA_N5X_H__
+
+#include
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "fdt_addr=110\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then" \
+ " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; fi; fi\0" \
+ "scriptaddr=0x0210\0" \
+ "scriptfile=u-boot.scr\0" \
+ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+ "then source ${scriptaddr}; fi\0"
+
+#endif /* __CONFIG_SOCFGPA_N5X_H__ */
--
2.19.0
[v2 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from tool.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Move is_ddr_init_skipped and its helper functions to DDR driver and
converted function to positive checking
- Using GENMASK() macro
- Fixed typo
- Return status of subfunction
- Changed dm to n5x
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach/system_manager_soc64.h | 10 +-
drivers/ddr/altera/Makefile |3 +-
drivers/ddr/altera/sdram_n5x.c| 2299 +
drivers/ddr/altera/sdram_soc64.c | 70 +
drivers/ddr/altera/sdram_soc64.h |1 +
6 files changed, 2387 insertions(+), 2 deletions(-)
create mode 100644 drivers/ddr/altera/sdram_n5x.c
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
index adab65bc96..5cb7f23f8f 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -115,10 +115,16 @@ struct socfpga_firwall_l4_sys {
/* Firewall MPU DDR SCR registers */
#define FW_MPU_DDR_SCR_EN 0x00
#define FW_MPU_DDR_SCR_EN_SET 0x04
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT0x18
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
+
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD0xff
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index fc4e17821b..a8009664fe 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2021 Intel Corporation
*/
#ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -28,8 +28,12 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c
#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
#define SYSMGR_SOC64_DMA_L3MASTER 0x74
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SYSMGR_SOC64_DDR_MODE 0xb8
+#else
#define SYSMGR_SOC64_HMC_CLK 0xb4
#define SYSMGR_SOC64_IO_PA_CTRL0xb8
+#endif
#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0
#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4
#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8
@@ -143,4 +147,8 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#defineSYSMGR_SOC64_DDR_MODE_MSK BIT(0)
+#endif
+
#endif /* _SYSTEM_MANAGER_SOC64_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 39dfee5d5a..9fa5d85a27 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -4,11 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# (C) Copyright 2010, Thomas Chou
-# Copyright (C) 2014 Altera Corporation
+# Copyright (C) 2014-2021 Altera Corporation
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
endif
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
new file mode 100644
index 00..f86342e4ef
--- /dev/null
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -0,0 +1,2299 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#include
[v2 14/17] board: intel: Add socdk board support for Intel N5X device
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
.../{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
create mode 100644 board/intel/n5x-socdk/MAINTAINERS
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile (50%)
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c (52%)
diff --git a/board/intel/n5x-socdk/MAINTAINERS
b/board/intel/n5x-socdk/MAINTAINERS
new file mode 100644
index 00..c1059f092c
--- /dev/null
+++ b/board/intel/n5x-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chee Tien Fong
+M: Lim Siew Chin
+S: Maintained
+F: board/intel/n5x-socdk/
+F: include/configs/socfpga_n5x_socdk.h
+F: configs/socfpga_n5x_atf_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile
b/board/intel/n5x-socdk/Makefile
similarity index 50%
copy from board/altera/stratix10-socdk/Makefile
copy to board/intel/n5x-socdk/Makefile
index 02a9cadf76..accfdcddcb 100644
--- a/board/altera/stratix10-socdk/Makefile
+++ b/board/intel/n5x-socdk/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2016-2017 Intel Corporation
+# Copyright (C) 2020-2021 Intel Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
diff --git a/board/altera/stratix10-socdk/socfpga.c
b/board/intel/n5x-socdk/socfpga.c
similarity index 52%
copy from board/altera/stratix10-socdk/socfpga.c
copy to board/intel/n5x-socdk/socfpga.c
index 043fc543f1..985ba190d0 100644
--- a/board/altera/stratix10-socdk/socfpga.c
+++ b/board/intel/n5x-socdk/socfpga.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
--
2.19.0
[v2 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
n5x data accordingly.
---
arch/arm/dts/Makefile | 1 +
...ex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} | 13 ++-
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi| 67 +++
...agilex_socdk.dts => socfpga_n5x_socdk.dts} | 110 +-
4 files changed, 182 insertions(+), 9 deletions(-)
copy arch/arm/dts/{socfpga_agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} (85%)
create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (57%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index aec5020a0f..2e13277816 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -381,6 +381,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb\
+ socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
similarity index 85%
copy from arch/arm/dts/socfpga_agilex-u-boot.dtsi
copy to arch/arm/dts/socfpga_n5x-u-boot.dtsi
index 08f7cf7f7a..2f63f4a4e6 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -2,7 +2,7 @@
/*
* U-Boot additions
*
- * Copyright (C) 2019-2020 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*/
#include "socfpga_soc64_fit-u-boot.dtsi"
@@ -53,6 +53,10 @@
reset-names = "i2c";
};
+&memclkmgr {
+ u-boot,dm-pre-reloc;
+};
+
&mmc {
resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
};
@@ -76,11 +80,10 @@
};
&sdr {
- compatible = "intel,sdr-ctl-agilex";
- reg = <0xf8000400 0x80>,
- <0xf801 0x190>,
- <0xf8011000 0x500>;
+ compatible = "intel,sdr-ctl-n5x";
resets = <&rst DDRSCH_RESET>;
+ clocks = <&memclkmgr>;
+ clock-names = "mem_clk";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
new file mode 100644
index 00..57509f083e
--- /dev/null
+++ b/arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include "socfpga_n5x-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = &qspi;
+ i2c0 = &i2c1;
+ };
+
+ memory {
+ /*
+* Memory type: DDR4
+* 16GB
+* <0 0x 0 0x8000>,
+* <4 0x8000 3 0x8000>;
+*
+* 8GB
+* <0 0x 0 0x8000>,
+* <2 0x8000 1 0x8000>;
+*
+* 4GB
+* <0 0x 0 0x8000>,
+* <1 0x8000 0 0x8000>;
+*
+* Memory type: LPDDR4 (non-interleaving mode)
+* Total memory size 3GB, usable = 2.5GB, 0.5GB trade off for
secure
+* region.
+*/
+ reg = <0 0x 0 0x6000>,
+ <0x10 0x0010 0 0x4000>;
+ };
+};
+
+&flash0 {
+ compatible = "jedec,spi-nor";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&nand {
+ u-boot,dm-pre-reloc;
+};
+
+&mmc {
+ drvsel = <3>;
+ smplsel = <0>;
+ u-boot,dm-pre-reloc;
+};
+
+&qspi {
+ status = "okay";
+};
+
+&watchdog0 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts
b/arch/arm/dts/socfpga_n5x_socdk.dts
similarity index 57%
copy from arch/arm/dts/socfpga_agilex_socdk.dts
copy to arch/arm/dts/socfpga_n5x_socdk.dts
index bcdeecc0e0..30130bb910 100644
--- a/arch/arm/dts/socfpga_agilex_socdk.dts
+++ b/arch/arm/dts/socfpga_n5x_socdk.dts
@@ -1,11 +1,12 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019, Intel Corporation
+ * Copyright (C) 2020-2021, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
+#include
/ {
- model = "SoCFPGA Agilex SoCDK";
+ model = "eASIC N5X SoC
[v2 13/17] arm: socfpga: Add SPL for Intel N5X device
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
.../mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 +++
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_n5x.c
similarity index 83%
copy from arch/arm/mach-socfpga/spl_agilex.c
copy to arch/arm/mach-socfpga/spl_n5x.c
index ee5a9dc1e2..d056871d29 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -1,27 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,27 +53,35 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
+ preloader_console_init();
+
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
- debug("Clock init failed: %d\n", ret);
+ printf("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 1, &dev);
+ if (ret) {
+ printf("Memory clock init failed: %d\n", ret);
hang();
}
- preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();
+
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
- debug("CCU init failed: %d\n", ret);
+ printf("CCU init failed: %d\n", ret);
hang();
}
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
- debug("DRAM init failed: %d\n", ret);
+ printf("DRAM init failed: %d\n", ret);
hang();
}
#endif
--
2.19.0
[v2 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
v2:
- Renamed local variable “total_size” to “remaining_size”
---
drivers/ddr/altera/sdram_soc64.c | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index a08f0953e5..cc656db97c 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2019 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -182,6 +182,7 @@ void sdram_size_check(struct bd_info *bd)
phys_size_t total_ram_check = 0;
phys_size_t ram_check = 0;
phys_addr_t start = 0;
+ phys_size_t size, remaining_size;
int bank;
/* Sanity check ensure correct SDRAM size specified */
@@ -189,10 +190,27 @@ void sdram_size_check(struct bd_info *bd)
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = bd->bi_dram[bank].start;
+ remaining_size = bd->bi_dram[bank].size;
while (ram_check < bd->bi_dram[bank].size) {
- ram_check += get_ram_size((void *)(start + ram_check),
-(phys_size_t)SZ_1G);
+ size = min((phys_addr_t)SZ_1G,
+ (phys_addr_t)remaining_size);
+
+ /*
+* Ensure the size is power of two, this is requirement
+* to run get_ram_size() / memory test
+*/
+ if (size != 0 && ((size & (size - 1)) == 0)) {
+ ram_check += get_ram_size((void *)
+ (start + ram_check), size);
+ remaining_size = bd->bi_dram[bank].size -
+ ram_check;
+ } else {
+ puts("DDR: Memory test requires SDRAM size ");
+ puts("in power of two!\n");
+ hang();
+ }
}
+
total_ram_check += ram_check;
ram_check = 0;
}
--
2.19.0
[v2 10/17] arm: socfpga: Changed misc_s10.c to misc_soc64.c
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 4 ++--
arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
rename arch/arm/mach-socfpga/{misc_s10.c => misc_soc64.c} (100%)
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 5779c55621..58afde950f 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -32,7 +32,7 @@ ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
obj-y += clock_manager_s10.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-y += system_manager_soc64.o
@@ -45,7 +45,7 @@ ifdef CONFIG_TARGET_SOCFPGA_AGILEX
obj-y += clock_manager_agilex.o
obj-y += lowlevel_init_soc64.o
obj-y += mailbox_s10.o
-obj-y += misc_s10.o
+obj-y += misc_soc64.o
obj-y += mmu-arm64_s10.o
obj-y += reset_manager_s10.o
obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
diff --git a/arch/arm/mach-socfpga/misc_s10.c
b/arch/arm/mach-socfpga/misc_soc64.c
similarity index 100%
rename from arch/arm/mach-socfpga/misc_s10.c
rename to arch/arm/mach-socfpga/misc_soc64.c
index 50c7f19ae1..7b973a79e8 100644
--- a/arch/arm/mach-socfpga/misc_s10.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -6,16 +6,16 @@
#include
#include
-#include
-#include
-#include
-#include
-#include
-#include
#include
#include
#include
#include
+#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
--
2.19.0
[v2 09/17] arm: socfpga: Add clock manager for Intel N5X device
Add clock manager for N5X.
Signed-off-by: Siew Chin Lim
---
...k_manager_agilex.c => clock_manager_n5x.c} | 32 +--
.../mach-socfpga/include/mach/clock_manager.h | 2 ++
.../include/mach/clock_manager_n5x.h | 12 +++
3 files changed, 29 insertions(+), 17 deletions(-)
copy arch/arm/mach-socfpga/{clock_manager_agilex.c => clock_manager_n5x.c}
(64%)
create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex.c
b/arch/arm/mach-socfpga/clock_manager_n5x.c
similarity index 64%
copy from arch/arm/mach-socfpga/clock_manager_agilex.c
copy to arch/arm/mach-socfpga/clock_manager_n5x.c
index e035c09aae..4f098533e7 100644
--- a/arch/arm/mach-socfpga/clock_manager_agilex.c
+++ b/arch/arm/mach-socfpga/clock_manager_n5x.c
@@ -1,19 +1,18 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -25,7 +24,7 @@ static ulong cm_get_rate_dm(u32 id)
int ret;
ret = uclass_get_device_by_driver(UCLASS_CLK,
- DM_DRIVER_GET(socfpga_agilex_clk),
+ DM_DRIVER_GET(socfpga_n5x_clk),
&dev);
if (ret)
return 0;
@@ -39,8 +38,7 @@ static ulong cm_get_rate_dm(u32 id)
clk_free(&clk);
- if ((rate == (unsigned long)-ENOSYS) ||
- (rate == (unsigned long)-ENXIO) ||
+ if ((rate == (unsigned long)-ENXIO) ||
(rate == (unsigned long)-EIO)) {
debug("%s id %u: clk_get_rate err: %ld\n",
__func__, id, rate);
@@ -57,26 +55,26 @@ static u32 cm_get_rate_dm_khz(u32 id)
unsigned long cm_get_mpu_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_MPU_CLK);
+ return cm_get_rate_dm(N5X_MPU_CLK);
}
unsigned int cm_get_l4_sys_free_clk_hz(void)
{
- return cm_get_rate_dm(AGILEX_L4_SYS_FREE_CLK);
+ return cm_get_rate_dm(N5X_L4_SYS_FREE_CLK);
}
void cm_print_clock_quick_summary(void)
{
printf("MPU %10d kHz\n",
- cm_get_rate_dm_khz(AGILEX_MPU_CLK));
+ cm_get_rate_dm_khz(N5X_MPU_CLK));
printf("L4 Main %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MAIN_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MAIN_CLK));
printf("L4 sys free %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SYS_FREE_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SYS_FREE_CLK));
printf("L4 MP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_MP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_MP_CLK));
printf("L4 SP %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_L4_SP_CLK));
+ cm_get_rate_dm_khz(N5X_L4_SP_CLK));
printf("SDMMC %8d kHz\n",
- cm_get_rate_dm_khz(AGILEX_SDMMC_CLK));
+ cm_get_rate_dm_khz(N5X_SDMMC_CLK));
}
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index d0b172a30e..a8cb07a1c4 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#include
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#include
#endif
#endif /* _CLOCK_MANAGER_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
new file mode 100644
index 00..54615ae8f7
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_n5x.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#ifndef _CLOCK_MANAGER_N5X_
+#define _CLOCK_MANAGER_N5X_
+
+#include
+#include "../../../../../drivers/clk/altera/clk-n5x.h"
+
+#endif /* _CLOCK_MANAGER_N5X_ */
--
2.19.0
[v2 08/17] arm: socfpga: Move cm_get_mpu_clk_hz function declaration to clock_manager.h
Move cm_get_mpu_clk_hz function declaration from individual device's
clock manager header file to common clock_manager.h.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 1 +
arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h | 2 --
arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h | 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h| 1 -
arch/arm/mach-socfpga/include/mach/clock_manager_s10.h | 1 -
5 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 2f9b471af3..d0b172a30e 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -12,6 +12,7 @@ phys_addr_t socfpga_get_clkmgr_addr(void);
void cm_wait_for_lock(u32 mask);
int cm_wait_for_fsm(void);
void cm_print_clock_quick_summary(void);
+unsigned long cm_get_mpu_clk_hz(void);
unsigned int cm_get_qspi_controller_clk_hz(void);
#if defined(CONFIG_TARGET_SOCFPGA_SOC64)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
index 386e82a4e3..4feae3dda9 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex.h
@@ -6,8 +6,6 @@
#ifndef _CLOCK_MANAGER_AGILEX_
#define _CLOCK_MANAGER_AGILEX_
-unsigned long cm_get_mpu_clk_hz(void);
-
#include
#include "../../../../../drivers/clk/altera/clk-agilex.h"
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
index 798d3741bd..553ebe660d 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_arria10.h
@@ -68,7 +68,6 @@ int cm_basic_init(const void *blob);
#include
unsigned int cm_get_l4_sp_clk_hz(void);
-unsigned long cm_get_mpu_clk_hz(void);
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
index 4cc1268b4c..d53095a7da 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_gen5.h
@@ -96,7 +96,6 @@ struct cm_config {
#define CLKMGR_PERPLL_EN CLKMGR_GEN5_PERPLL_EN
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
index 98c3bf1b03..7f10296dc7 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
@@ -11,7 +11,6 @@
#include
/* Clock speed accessors */
-unsigned long cm_get_mpu_clk_hz(void);
unsigned long cm_get_sdram_clk_hz(void);
unsigned int cm_get_l4_sp_clk_hz(void);
unsigned int cm_get_mmc_controller_clk_hz(void);
--
2.19.0
[v2 07/17] drivers: clk: Add memory clock driver for Intel N5X device
Add memory clock manager driver for N5X. Provides memory clock
initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
v2:
- common.h need to be included before clock_manager.h
- For consistency, use small letter fo 0x0c and 0x1c in macros
---
drivers/clk/altera/Makefile | 1 +
drivers/clk/altera/clk-mem-n5x.c | 136 +++
drivers/clk/altera/clk-mem-n5x.h | 84 +++
3 files changed, 221 insertions(+)
create mode 100644 drivers/clk/altera/clk-mem-n5x.c
create mode 100644 drivers/clk/altera/clk-mem-n5x.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 38cd730685..33db092918 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
diff --git a/drivers/clk/altera/clk-mem-n5x.c b/drivers/clk/altera/clk-mem-n5x.c
new file mode 100644
index 00..ca44998641
--- /dev/null
+++ b/drivers/clk/altera/clk-mem-n5x.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include "clk-mem-n5x.h"
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_mem_clk_plat {
+ void __iomem *regs;
+};
+
+void clk_mem_wait_for_lock(struct socfpga_mem_clk_plat *plat, u32 mask)
+{
+ u32 inter_val;
+ u32 retry = 0;
+
+ do {
+ inter_val = CM_REG_READL(plat, MEMCLKMGR_STAT) & mask;
+
+ /* Wait for stable lock */
+ if (inter_val == mask)
+ retry++;
+ else
+ retry = 0;
+
+ if (retry >= 10)
+ return;
+ } while (1);
+}
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+void clk_mem_write_bypass_mempll(struct socfpga_mem_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, MEMCLKMGR_MEMPLL_BYPASS);
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_mem_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+ /* Put PLLs in bypass */
+ clk_mem_write_bypass_mempll(plat, MEMCLKMGR_BYPASS_MEMPLL_ALL);
+
+ /* Put PLLs in Reset */
+ CM_REG_SETBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup mem PLL */
+ CM_REG_WRITEL(plat, cfg->mem_memdiv, MEMCLKMGR_MEMPLL_MEMDIV);
+ CM_REG_WRITEL(plat, cfg->mem_pllglob, MEMCLKMGR_MEMPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->mem_plldiv, MEMCLKMGR_MEMPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->mem_plloutdiv, MEMCLKMGR_MEMPLL_PLLOUTDIV);
+
+ /* Take PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_PLLCTRL,
+ MEMCLKMGR_PLLCTRL_BYPASS_MASK);
+}
+
+static int socfpga_mem_clk_enable(struct clk *clk)
+{
+ const struct cm_config *cm_default_cfg = cm_get_default_config();
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(clk->dev);
+
+ clk_mem_basic_init(clk->dev, cm_default_cfg);
+
+ clk_mem_wait_for_lock(plat, MEMCLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, CM_REG_READL(plat, MEMCLKMGR_MEMPLL_PLLGLOB) |
+ MEMCLKMGR_PLLGLOB_CLR_LOSTLOCK_BYPASS_MASK,
+ MEMCLKMGR_MEMPLL_PLLGLOB);
+
+ /* Take all PLLs out of bypass */
+ clk_mem_write_bypass_mempll(plat, 0);
+
+ /* Clear the loss of lock bits (write 1 to clear) */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_INTRCLR,
+ MEMCLKMGR_INTER_MEMPLLLOST_MASK);
+
+ /* Take all ping pong counters out of reset */
+ CM_REG_CLRBITS(plat, MEMCLKMGR_MEMPLL_EXTCNTRST,
+ MEMCLKMGR_EXTCNTRST_ALLCNTRST);
+
+ return 0;
+}
+
+static int socfpga_mem_clk_of_to_plat(struct udevice *dev)
+{
+ struct socfpga_mem_clk_plat *plat = dev_get_plat(dev);
+ fdt_addr_t addr;
+
+ addr = devfdt_get_addr(dev);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ plat->regs = (void __iomem *)addr;
+
+ return 0;
+}
+
+static struct clk_ops socfpga_mem_clk_ops = {
+ .enable = socfpga_mem_clk_enable
+};
+
+static const struct udevice_id socfpga_mem_clk_match[] = {
+ { .compatible = "intel,n5x-mem-clkmgr" },
+ {}
+};
+
+U_BOOT_DRIVER(socfpga_n5x_mem_clk) = {
+ .name = "mem-clk-n5x",
+ .id = UCLASS_CLK,
+
[v2 05/17] drivers: clk: Add clock driver for Intel N5X device
Add clock manager driver for N5X. Provides clock initialization
and get_rate functions.
Signed-off-by: Siew Chin Lim
---
v2:
- common.h need to be included before clock_manager.h
- Remove unnecessary comment : write 1 to clear
- Remove unnecessary () in the code
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-n5x.c | 489 ++
drivers/clk/altera/clk-n5x.h | 217
include/dt-bindings/clock/n5x-clock.h | 71
4 files changed, 779 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/altera/clk-n5x.c
create mode 100644 drivers/clk/altera/clk-n5x.h
create mode 100644 include/dt-bindings/clock/n5x-clock.h
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 96215ad5c4..38cd730685 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -1,7 +1,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-# Copyright (C) 2018 Marek Vasut
+# Copyright (C) 2018-2021 Marek Vasut
#
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
diff --git a/drivers/clk/altera/clk-n5x.c b/drivers/clk/altera/clk-n5x.c
new file mode 100644
index 00..bdcbbaae91
--- /dev/null
+++ b/drivers/clk/altera/clk-n5x.c
@@ -0,0 +1,489 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct socfpga_clk_plat {
+ void __iomem *regs;
+};
+
+/*
+ * function to write the bypass register which requires a poll of the
+ * busy bit
+ */
+static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
+ cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of the busy bit */
+static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val)
+{
+ CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
+ cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state of the clocks.
+ */
+static void clk_basic_init(struct udevice *dev,
+ const struct cm_config * const cfg)
+{
+ struct socfpga_clk_plat *plat = dev_get_plat(dev);
+
+ if (!cfg)
+ return;
+
+#if IS_ENABLED(CONFIG_SPL_BUILD)
+ /* Always force clock manager into boot mode before any configuration */
+ clk_write_ctrl(plat,
+ CM_REG_READL(plat, CLKMGR_CTRL) | CLKMGR_CTRL_BOOTMODE);
+#else
+ /* Skip clock configuration in SSBL if it's not in boot mode */
+ if (!(CM_REG_READL(plat, CLKMGR_CTRL) & CLKMGR_CTRL_BOOTMODE))
+ return;
+#endif
+
+ /* Put both PLLs in bypass */
+ clk_write_bypass_mainpll(plat, CLKMGR_BYPASS_MAINPLL_ALL);
+ clk_write_bypass_perpll(plat, CLKMGR_BYPASS_PERPLL_ALL);
+
+ /* Put both PLLs in Reset */
+ CM_REG_SETBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_SETBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ /* setup main PLL */
+ CM_REG_WRITEL(plat, cfg->main_pll_pllglob, CLKMGR_MAINPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->main_pll_plldiv, CLKMGR_MAINPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_plloutdiv, CLKMGR_MAINPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->main_pll_mpuclk, CLKMGR_MAINPLL_MPUCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocclk, CLKMGR_MAINPLL_NOCCLK);
+ CM_REG_WRITEL(plat, cfg->main_pll_nocdiv, CLKMGR_MAINPLL_NOCDIV);
+
+ /* setup peripheral */
+ CM_REG_WRITEL(plat, cfg->per_pll_pllglob, CLKMGR_PERPLL_PLLGLOB);
+ CM_REG_WRITEL(plat, cfg->per_pll_plldiv, CLKMGR_PERPLL_PLLDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_plloutdiv, CLKMGR_PERPLL_PLLOUTDIV);
+ CM_REG_WRITEL(plat, cfg->per_pll_emacctl, CLKMGR_PERPLL_EMACCTL);
+ CM_REG_WRITEL(plat, cfg->per_pll_gpiodiv, CLKMGR_PERPLL_GPIODIV);
+
+ /* Take both PLL out of reset and power up */
+ CM_REG_CLRBITS(plat, CLKMGR_MAINPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+ CM_REG_CLRBITS(plat, CLKMGR_PERPLL_PLLCTRL,
+ CLKMGR_PLLCTRL_BYPASS_MASK);
+
+ cm_wait_for_lock(CLKMGR_STAT_ALLPLL_LOCKED_MASK);
+
+ CM_REG_WRITEL(plat, cfg->alt_emacactr, CLKMGR_ALTR_EMACACTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacbctr, CLKMGR_ALTR_EMACBCTR);
+ CM_REG_WRITEL(plat, cfg->alt_emacptpctr, CLKMGR_ALTR_EMACPTPCTR);
+ CM_REG_WRITEL(plat, cfg->alt_gpiodbctr, CLKMGR_ALTR_GPI
[v2 06/17] arm: socfpga: Get clock manager base address for Intel N5X device
Add N5X clock manager to socfpga_get_managers_addr function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 64a7c9d652..9305bec38a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -254,6 +254,9 @@ void socfpga_get_managers_addr(void)
#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
ret = socfpga_get_base_addr("intel,agilex-clkmgr",
&socfpga_clkmgr_base);
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+ ret = socfpga_get_base_addr("intel,n5x-clkmgr",
+ &socfpga_clkmgr_base);
#else
ret = socfpga_get_base_addr("altr,clk-mgr", &socfpga_clkmgr_base);
#endif
--
2.19.0
[v2 04/17] arm: socfpga: Add handoff data support for Intel N5X device
N5X support both HPS handoff data and DDR handoff data.
Existing HPS handoff functions are restructured to support both existing
devices and N5X device.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
v2:
- Enabled auto detect the endianness from the magic word
- Merged and simplifying the big and little endian flow
---
.../mach-socfpga/include/mach/handoff_soc64.h | 38 +-
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +--
arch/arm/mach-socfpga/wrap_handoff_soc64.c| 126 +-
3 files changed, 136 insertions(+), 46 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 3750216a9a..902fc6bfb5 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2020 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -23,8 +23,36 @@
#define SOC64_HANDOFF_OFFSET_DATA 0x10
#define SOC64_HANDOFF_SIZE 4096
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+ IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SOC64_HANDOFF_BASE 0xFFE5F000
+#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
+
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE 0xFFE5C000
+#define SOC64_HANDOFF_DDR_MAGIC0x4852
+#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC 0x4C54434D
+#define SOC64_HANDOFF_DDR_UMCTL2_DDR4_TYPE 0x3452
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_0_TYPE 0x3044504C
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_1_TYPE 0x3144504C
+#define SOC64_HANDOFF_DDR_MEMRESET_BASE(SOC64_HANDOFF_DDR_BASE
+ 0xC)
+#define SOC64_HANDOFF_DDR_UMCTL2_SECTION (SOC64_HANDOFF_DDR_BASE + 0x10)
+#define SOC64_HANDOFF_DDR_PHY_MAGIC0x43594850
+#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC0x45594850
+#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_TYPE_OFFSET 0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_BASE_ADDR_OFFSET 0xC
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_1D_SECTION0xFFE5
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_1D_SECTION0xFFE58000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_2D_SECTION0xFFE44000
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_2D_SECTION0xFFE4C000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_LENGTHSZ_32K
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_LENGTHSZ_16K
+#endif
+
#define SOC64_HANDOFF_MUX (SOC64_HANDOFF_BASE + 0x10)
#define SOC64_HANDOFF_IOCTL(SOC64_HANDOFF_BASE + 0x1A0)
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
@@ -52,11 +80,11 @@
#include
enum endianness {
LITTLE_ENDIAN = 0,
- BIG_ENDIAN
+ BIG_ENDIAN,
+ UNKNOWN_ENDIANNESS
};
-int socfpga_get_handoff_size(void *handoff_address, enum endianness endian);
-int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
-enum endianness big_endian);
+int socfpga_get_handoff_size(void *handoff_address);
+int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len);
#endif
#endif /* _HANDOFF_SOC64_H_ */
diff --git a/arch/arm/mach-socfpga/system_manager_soc64.c
b/arch/arm/mach-socfpga/system_manager_soc64.c
index 3b5e774e2d..958bb5107b 100644
--- a/arch/arm/mach-socfpga/system_manager_soc64.c
+++ b/arch/arm/mach-socfpga/system_manager_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -66,10 +66,10 @@ void populate_sysmgr_fpgaintf_module(void)
void populate_sysmgr_pinmux(void)
{
u32 len, i;
- u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX,
BIG_ENDIAN);
- u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL,
BIG_ENDIAN);
- u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA,
BIG_ENDIAN);
- u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY,
BIG_ENDIAN);
+ u32 len_mux = socfpga_get_handoff_size((void *)SOC64_HANDOFF_MUX);
+ u32 len_ioctl = socfpga_get_handoff_size((void *)SOC64_HANDOFF_IOCTL);
+ u32 len_fpga = socfpga_get_handoff_size((void *)SOC64_HANDOFF_FPGA);
+ u32 len_delay = socfpga_get_handoff_size((void *)SOC64_HANDOFF_DELAY);
len = (len_mux > len_ioctl) ? len_mux : len_ioctl;
len = (len > len_fpga) ? len : len_fpga;
@@ -79,7 +79,7 @@ void populate_sysmgr_pinmux(void)
/* setup the pin sel */
len = (len_mux < SOC64_HANDOFF_MUX_LEN) ? len_mux :
SOC64_HANDOFF_MUX_LEN;
- socfpga_handoff_r
[v2 03/17] arm: socfpga: Add base address for Intel N5X device
Reuse base_addr_soc64.h for Intel N5X device, the address is the same as Agilex. Signed-off-by: Siew Chin Lim --- arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index f89066d771..3f899fcfa3 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -10,7 +10,8 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801 #define SOCFPGA_SDR_ADDRESS0xf8011000 -#ifdef CONFIG_TARGET_SOCFPGA_AGILEX +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 -- 2.19.0
[v2 01/17] arm: socfpga: Move linux_qspi_enable from bootcommand to board_prep_linux function
Move 'linux_qspi_enable' from bootcommand to board_prep_linux function when
OS booted from FIT image for Stratix 10 and Agilex. This flow is common for
all Intel SOC64 devices.
U-Boot will update 'fdt_addr' environment value based on FIT image in
board_prep_linux function, and 'linux_qspi_enable' will refer to 'fdt_addr'
environment value to retrieve the device tree node.
Signed-off-by: Siew Chin Lim
---
v2:
- New patch in n5x series, the change is needed to execute
'linux_qspi_enable' correctly in ATF boot flow
---
arch/arm/mach-socfpga/board.c | 17 +
configs/socfpga_agilex_atf_defconfig| 2 +-
configs/socfpga_stratix10_atf_defconfig | 2 +-
3 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 650122fcd4..f5a3f2ad62 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -115,17 +115,18 @@ void board_fit_image_post_process(void **p_image, size_t
*p_size)
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(bootm_headers_t *images)
{
- if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
- !IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
- /*
-* Ensure the OS is always booted from FIT and with
-* VAB signed certificate
-*/
- if (!images->fit_uname_cfg) {
+ if (!images->fit_uname_cfg) {
+ if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
+
!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
+ /*
+* Ensure the OS is always booted from FIT and with
+* VAB signed certificate
+*/
printf("Please use FIT with VAB signed images!\n");
hang();
}
-
+ } else {
+ /* Update fdt_addr in enviroment variable */
env_set_hex("fdt_addr", (ulong)images->ft_addr);
debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
}
diff --git a/configs/socfpga_agilex_atf_defconfig
b/configs/socfpga_agilex_atf_defconfig
index 0de65a22a0..e0a8714e3d 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socfpga_agilex_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_CACHE=y
CONFIG_SPL_SPI_LOAD=y
diff --git a/configs/socfpga_stratix10_atf_defconfig
b/configs/socfpga_stratix10_atf_defconfig
index c187987dd8..d0bc5e7909 100644
--- a/configs/socfpga_stratix10_atf_defconfig
+++ b/configs/socfpga_stratix10_atf_defconfig
@@ -22,7 +22,7 @@ CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="earlycon"
CONFIG_USE_BOOTCOMMAND=y
-CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run linux_qspi_enable; run
mmcfitboot"
+CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot"
CONFIG_SPL_CRC32_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
--
2.19.0
[v2 02/17] arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
Rename to common file name to used by all SOC64 devices and change
"_S10_" to "_SOC64_" in base_addr_soc64.h.
Signed-off-by: Siew Chin Lim
---
.../include/mach/{base_addr_s10.h => base_addr_soc64.h} | 8
include/configs/socfpga_soc64_common.h| 2 +-
2 files changed, 5 insertions(+), 5 deletions(-)
rename arch/arm/mach-socfpga/include/mach/{base_addr_s10.h =>
base_addr_soc64.h} (89%)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
similarity index 89%
rename from arch/arm/mach-socfpga/include/mach/base_addr_s10.h
rename to arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index d3eca65e97..f89066d771 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
-#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
-#define _SOCFPGA_S10_BASE_HARDWARE_H_
+#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
#define SOCFPGA_CCU_ADDRESS0xf700
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
@@ -44,4 +44,4 @@
#define GICD_BASE 0xfffc1000
#define GICC_BASE 0xfffc2000
-#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */
+#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/include/configs/socfpga_soc64_common.h
b/include/configs/socfpga_soc64_common.h
index 5afdb10454..f0b7884ebc 100644
--- a/include/configs/socfpga_soc64_common.h
+++ b/include/configs/socfpga_soc64_common.h
@@ -7,7 +7,7 @@
#ifndef __CONFIG_SOCFPGA_SOC64_COMMON_H__
#define __CONFIG_SOCFPGA_SOC64_COMMON_H__
-#include
+#include
#include
#include
--
2.19.0
[v2 00/17] Add Intel N5X SoC support
This is the 2nd version of patchset to add Intel N5X SoC[1] support.
Intel N5X SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in N5X are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Intel N5X SoC supports legacy boot without ATF for debugging purpose,
ATF boot, and ATF boot with VAB enabled.
[1]:
https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/diamond-mesa-soc-devices.html
Patch status:
Have changes: Patch 1, 4, 5, 7, 11, 12, 13, 15, 17
Other patches unchanged.
Detail changelog can find in commit message.
v1->v2:
Patch 1:
- New patch in n5x series, the change is needed to execute
'linux_qspi_enable' correctly in ATF boot flow
Patch 4:
- Enabled auto detect the endianness from the magic word
- Merged and simplifying the big and little endian flow
Patch 5:
- common.h need to be included before clock_manager.h
- Remove unnecessary comment : write 1 to clear
- Remove unnecessary () in the code
Patch 7:
- common.h need to be included before clock_manager.h
- For consistency, use small letter fo 0x0c and 0x1c in macros
Patch 11:
- Renamed local variable “total_size” to “remaining_size”
Patch 12:
- Move is_ddr_init_skipped and its helper functions to DDR driver and
converted function to positive checking
- Using GENMASK() macro
- Fixed typo
- Return status of subfunction
- Changed dm to n5x
Patch 13:
- No change on the file. Need review again for this patch.
common.h need to be included before clock_manager.h.
Patch 15:
- Remove socfpga_n5x.dtsi
- Reuse socfpga_agilex.dtsi in socfpga_n5x_socdk.dts and update
n5x data accordingly.
Patch 17:
- Move linux_qspi_enable from bootcommand
Siew Chin Lim (16):
arm: socfpga: Move linux_qspi_enable from bootcommand to
board_prep_linux function
arm: socfpga: Changed base_addr_s10.h to base_addr_soc64.h
arm: socfpga: Add base address for Intel N5X device
arm: socfpga: Add handoff data support for Intel N5X device
drivers: clk: Add clock driver for Intel N5X device
arm: socfpga: Get clock manager base address for Intel N5X device
drivers: clk: Add memory clock driver for Intel N5X device
arm: socfpga: Move cm_get_mpu_clk_hz function declaration to
clock_manager.h
arm: socfpga: Add clock manager for Intel N5X device
arm: socfpga: Changed misc_s10.c to misc_soc64.c
ddr: altera: Add SDRAM driver for Intel N5X device
arm: socfpga: Add SPL for Intel N5X device
board: intel: Add socdk board support for Intel N5X device
arm: dts: Add base dtsi and devkit dts for Intel N5X device
include: configs: Add Intel N5X device CONFIGs
arm: socfpga: Enable Intel N5X device build
Tien Fong Chee (1):
ddr: socfpga: Enable memory test on memory size less than 1GB
arch/arm/dts/Makefile |1 +
arch/arm/dts/socfpga_n5x-u-boot.dtsi | 101 +
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi| 67 +
arch/arm/dts/socfpga_n5x_socdk.dts| 243 ++
arch/arm/mach-socfpga/Kconfig | 21 +-
arch/arm/mach-socfpga/Makefile| 32 +-
arch/arm/mach-socfpga/board.c | 17 +-
arch/arm/mach-socfpga/clock_manager_n5x.c | 80 +
.../{base_addr_s10.h => base_addr_soc64.h}| 11 +-
.../mach-socfpga/include/mach/clock_manager.h |3 +
.../include/mach/clock_manager_agilex.h |2 -
.../include/mach/clock_manager_arria10.h |1 -
.../include/mach/clock_manager_gen5.h |1 -
.../include/mach/clock_manager_n5x.h | 12 +
.../include/mach/clock_manager_s10.h |1 -
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../mach-socfpga/include/mach/handoff_soc64.h | 38 +-
.../include/mach/system_manager_soc64.h | 10 +-
arch/arm/mach-socfpga/misc.c |3 +
.../mach-socfpga/{misc_s10.c => misc_soc64.c} | 12 +-
arch/arm/mach-socfpga/spl_n5x.c | 94 +
arch/arm/mach-socfpga/system_manager_soc64.c | 18 +-
arch/arm/mach-socfpga/wrap_handoff_soc64.c| 126 +-
board/intel/n5x-socdk/MAINTAINERS |7 +
board/intel/n5x-socdk/Makefile|7 +
board/intel/n5x-socdk/socfpga.c |7 +
configs/socfpga_agilex_atf_defconfig |2 +-
...tf_defconfig => socfpga_n5x_atf_defconfig} | 13 +-
...ex_atf_defconfig => socfpga_n5x_defconfig} | 29 +-
...tf_defconfig => socfpga_n5x_vab_defconfig} | 14 +-
configs/socfpga_stratix10_atf_defconfig |2 +-
drivers/clk/altera/Makefile |4 +-
drivers/clk/altera/clk-mem-n5x.c | 136 +
drivers/clk/altera/clk-mem-n5x.h | 84 +
drivers/clk/altera/clk-n5x.c | 489
drivers/clk/altera/clk-n5x.h | 217 ++
drivers/ddr/altera/Makefile |3 +-
drivers/ddr/altera/sdram_n5x.c| 2299 +
[PATCH] include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile
Legacy boot flow (SPL->U-Boot Proper->OS) boot to OS via Kernel Image and dtb files using booti command. ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file using bootm command. Change to use CONFIG_SPL_ATF to differentiate the bootfile of default environment variable. We shouldn't use CONFIG_FIT because it is enabled by default for U-Boot Proper. Signed-off-by: Siew Chin Lim --- include/configs/socfpga_soc64_common.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index f0b7884ebc..347620e1b5 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -82,7 +82,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void); * Environment variable */ -#ifdef CONFIG_FIT +#if IS_ENABLED(CONFIG_SPL_ATF) #define CONFIG_BOOTFILE "kernel.itb" #else #define CONFIG_BOOTFILE "Image" -- 2.19.0
[v1 17/17] arm: socfpga: Enable Intel N5X device build
Add defconfig for N5X to support legacy, ATF and VAB boot flow.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig | 20 +++-
arch/arm/mach-socfpga/Makefile | 22 +-
...lex_atf_defconfig => socfpga_n5x_atf_defconfig} | 10 +-
...fpga_agilex_defconfig => socfpga_n5x_defconfig} | 15 ++-
...lex_vab_defconfig => socfpga_n5x_vab_defconfig} | 10 +-
5 files changed, 56 insertions(+), 21 deletions(-)
copy configs/{socfpga_agilex_atf_defconfig => socfpga_n5x_atf_defconfig} (89%)
copy configs/{socfpga_agilex_defconfig => socfpga_n5x_defconfig} (80%)
copy configs/{socfpga_agilex_vab_defconfig => socfpga_n5x_vab_defconfig} (89%)
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 0c35406232..e773029595 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,7 +8,7 @@ config NR_DRAM_BANKS
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
- depends on TARGET_SOCFPGA_AGILEX
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512_ALGO
@@ -91,6 +91,21 @@ config TARGET_SOCFPGA_GEN5
imply SPL_SYS_MALLOC_SIMPLE
imply SPL_USE_TINY_PRINTF
+config TARGET_SOCFPGA_N5X
+ bool
+ select ARMV8_MULTIENTRY
+ select ARMV8_SET_SMPEN
+ select BINMAN if SPL_ATF
+ select CLK
+ select NCORE_CACHE
+ select SPL_ALTERA_SDRAM
+ select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
+
+config TARGET_SOCFPGA_N5X_SOCDK
+ bool "Intel SOCFPGA SoCDK (N5X)"
+ select TARGET_SOCFPGA_N5X
+
config TARGET_SOCFPGA_SOC64
bool
@@ -183,6 +198,7 @@ config SYS_BOARD
default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "is1" if TARGET_SOCFPGA_IS1
default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
@@ -194,6 +210,7 @@ config SYS_BOARD
config SYS_VENDOR
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
+ default "intel" if TARGET_SOCFPGA_N5X_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
@@ -221,6 +238,7 @@ config SYS_CONFIG_NAME
default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
+ default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
default "socfpga_is1" if TARGET_SOCFPGA_IS1
default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 58afde950f..8f6e88a161 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation
-# Copyright (C) 2017-2020 Intel Corporation
+# Copyright (C) 2017-2021 Intel Corporation
obj-y += board.o
obj-y += clock_manager.o
@@ -56,6 +56,21 @@ obj-y+= wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += clock_manager_n5x.o
+obj-y += lowlevel_init_soc64.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o
+obj-y += system_manager_soc64.o
+obj-y += timer_s10.o
+obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o
+obj-y += wrap_handoff_soc64.o
+obj-y += wrap_pll_config_soc64.o
+endif
+
ifdef CONFIG_SPL_BUILD
ifdef CONFIG_TARGET_SOCFPGA_GEN5
obj-y += spl_gen5.o
@@ -77,6 +92,11 @@ obj-y+= firewall.o
obj-y += spl_agilex.o
obj-y += spl_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_N5X
+obj-y += firewall.o
+obj-y += spl_n5x.o
+obj-y += spl_soc64.o
+endif
else
obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
obj-$(CONFIG_SPL_ATF) += smc_api.o
diff --git a/configs/socfpga_agilex_atf_defconfig
b/configs/socfpga_n5x_atf_defconfig
similarity index 89%
copy from configs/socfpga_agilex_atf_defconfig
copy to configs/socfpga_n5x_atf_defconfig
index e5b7f4b52a..12c50f5c33 100644
--- a/configs/socfpga_agilex_atf_defconfig
+++ b/configs/socf
[v1 16/17] include: configs: Add Intel N5X device CONFIGs
Add CONFIGs for N5X.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_n5x_socdk.h | 45 +
1 file changed, 45 insertions(+)
create mode 100644 include/configs/socfpga_n5x_socdk.h
diff --git a/include/configs/socfpga_n5x_socdk.h
b/include/configs/socfpga_n5x_socdk.h
new file mode 100644
index 00..c295e91e3d
--- /dev/null
+++ b/include/configs/socfpga_n5x_socdk.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#ifndef __CONFIG_SOCFGPA_N5X_H__
+#define __CONFIG_SOCFGPA_N5X_H__
+
+#include
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "loadaddr=" __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
+ "bootfile=" CONFIG_BOOTFILE "\0" \
+ "fdt_addr=110\0" \
+ "fdtimage=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
+ "mmcroot=/dev/mmcblk0p2\0" \
+ "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "mmcload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile};" \
+ "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
+ "mmcfitboot=setenv bootargs " CONFIG_BOOTARGS \
+ " root=${mmcroot} rw rootwait;" \
+ "bootm ${loadaddr}\0" \
+ "mmcfitload=mmc rescan;" \
+ "load mmc 0:1 ${loadaddr} ${bootfile}\0" \
+ "ramboot=setenv bootargs " CONFIG_BOOTARGS";" \
+ "booti ${loadaddr} - ${fdt_addr}\0" \
+ "linux_qspi_enable=if sf probe; then " \
+ "echo Enabling QSPI at Linux DTB...;" \
+ "fdt addr ${fdt_addr}; fdt resize;" \
+ "fdt set /soc/spi@ff8d2000 status okay;" \
+ "if fdt set /soc/clocks/qspi-clk clock-frequency" \
+ " ${qspi_clock}; then" \
+ " else fdt set /soc/clkmgr/clocks/qspi_clk clock-frequency" \
+ " ${qspi_clock}; fi; fi\0" \
+ "scriptaddr=0x0210\0" \
+ "scriptfile=u-boot.scr\0" \
+ "fatscript=if fatload mmc 0:1 ${scriptaddr} ${scriptfile};" \
+ "then source ${scriptaddr}; fi\0"
+
+#endif /* __CONFIG_SOCFGPA_N5X_H__ */
--
2.13.0
[v1 15/17] arm: dts: Add base dtsi and devkit dts for Intel N5X device
Add device tree for N5X.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/Makefile | 1 +
..._agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} | 13 ++--
.../dts/{socfpga_agilex.dtsi => socfpga_n5x.dtsi} | 90 +-
arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi | 67
...fpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} | 10 ++-
5 files changed, 135 insertions(+), 46 deletions(-)
copy arch/arm/dts/{socfpga_agilex-u-boot.dtsi => socfpga_n5x-u-boot.dtsi} (85%)
copy arch/arm/dts/{socfpga_agilex.dtsi => socfpga_n5x.dtsi} (88%)
create mode 100644 arch/arm/dts/socfpga_n5x_socdk-u-boot.dtsi
copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_n5x_socdk.dts} (92%)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c6710826a0..7443fde97d 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -380,6 +380,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=
\
socfpga_cyclone5_socrates.dtb \
socfpga_cyclone5_sr1500.dtb \
socfpga_cyclone5_vining_fpga.dtb\
+ socfpga_n5x_socdk.dtb \
socfpga_stratix10_socdk.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
diff --git a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
similarity index 85%
copy from arch/arm/dts/socfpga_agilex-u-boot.dtsi
copy to arch/arm/dts/socfpga_n5x-u-boot.dtsi
index 08f7cf7f7a..7ded8ceb9a 100644
--- a/arch/arm/dts/socfpga_agilex-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_n5x-u-boot.dtsi
@@ -2,7 +2,7 @@
/*
* U-Boot additions
*
- * Copyright (C) 2019-2020 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*/
#include "socfpga_soc64_fit-u-boot.dtsi"
@@ -53,6 +53,10 @@
reset-names = "i2c";
};
+&memclkmgr {
+ u-boot,dm-pre-reloc;
+};
+
&mmc {
resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
};
@@ -76,11 +80,10 @@
};
&sdr {
- compatible = "intel,sdr-ctl-agilex";
- reg = <0xf8000400 0x80>,
- <0xf801 0x190>,
- <0xf8011000 0x500>;
+ compatible = "intel,sdr-ctl-dm";
resets = <&rst DDRSCH_RESET>;
+ clocks = <&memclkmgr>;
+ clock-names = "mem_clk";
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/socfpga_agilex.dtsi b/arch/arm/dts/socfpga_n5x.dtsi
similarity index 88%
copy from arch/arm/dts/socfpga_agilex.dtsi
copy to arch/arm/dts/socfpga_n5x.dtsi
index c3ead2d72b..984524c79a 100644
--- a/arch/arm/dts/socfpga_agilex.dtsi
+++ b/arch/arm/dts/socfpga_n5x.dtsi
@@ -1,15 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019, Intel Corporation
+ * Copyright (C) 2020-2021, Intel Corporation
*/
/dts-v1/;
#include
#include
-#include
+#include
/ {
- compatible = "intel,socfpga-agilex";
+ compatible = "intel,socfpga-n5x";
#address-cells = <2>;
#size-cells = <2>;
@@ -103,7 +103,7 @@
};
clkmgr: clock-controller@ffd1 {
- compatible = "intel,agilex-clkmgr";
+ compatible = "intel,n5x-clkmgr";
reg = <0xffd1 0x1000>;
#clock-cells = <1>;
};
@@ -124,6 +124,11 @@
compatible = "fixed-clock";
};
+ dram_eosc_clk: dram-eosc-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
osc1: osc1 {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -136,7 +141,9 @@
};
};
gmac0: ethernet@ff80 {
- compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a",
"snps,dwmac";
+ compatible = "altr,socfpga-stmmac",
+"snps,dwmac-3.74a",
+"snps,dwmac";
reg = <0xff80 0x2000>;
interrupts = <0 90 4>;
interrupt-names = "macirq";
@@ -148,13 +155,15 @@
snps,multicast-filter-bins = <256>;
iommus = <&smmu 1>;
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
- clocks = <&clkmgr AGILEX_EMAC0_CLK>;
+
[v1 14/17] board: intel: Add socdk board support for Intel N5X device
Add N5X SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/n5x-socdk/MAINTAINERS | 7 +++
board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile | 2 +-
board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c | 2 +-
3 files changed, 9 insertions(+), 2 deletions(-)
create mode 100644 board/intel/n5x-socdk/MAINTAINERS
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/Makefile (50%)
copy board/{altera/stratix10-socdk => intel/n5x-socdk}/socfpga.c (52%)
diff --git a/board/intel/n5x-socdk/MAINTAINERS
b/board/intel/n5x-socdk/MAINTAINERS
new file mode 100644
index 00..c1059f092c
--- /dev/null
+++ b/board/intel/n5x-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Chee Tien Fong
+M: Lim Siew Chin
+S: Maintained
+F: board/intel/n5x-socdk/
+F: include/configs/socfpga_n5x_socdk.h
+F: configs/socfpga_n5x_atf_defconfig
diff --git a/board/altera/stratix10-socdk/Makefile
b/board/intel/n5x-socdk/Makefile
similarity index 50%
copy from board/altera/stratix10-socdk/Makefile
copy to board/intel/n5x-socdk/Makefile
index 02a9cadf76..accfdcddcb 100644
--- a/board/altera/stratix10-socdk/Makefile
+++ b/board/intel/n5x-socdk/Makefile
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2016-2017 Intel Corporation
+# Copyright (C) 2020-2021 Intel Corporation
#
# SPDX-License-Identifier: GPL-2.0
#
diff --git a/board/altera/stratix10-socdk/socfpga.c
b/board/intel/n5x-socdk/socfpga.c
similarity index 52%
copy from board/altera/stratix10-socdk/socfpga.c
copy to board/intel/n5x-socdk/socfpga.c
index 043fc543f1..985ba190d0 100644
--- a/board/altera/stratix10-socdk/socfpga.c
+++ b/board/intel/n5x-socdk/socfpga.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
--
2.13.0
[v1 12/17] ddr: altera: Add SDRAM driver for Intel N5X device
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from Quartus.
Configuration settings of memory clock manager is come from the HPS
handoff data in bitstream, however the register base address is defined
in device tree.
The calibration is fully done in HPS, which requires IMEM and DMEM
binaries loading to PHY SRAM for running this calibration, both
IMEM and DMEM binaries are also part of bitstream, this bitstream
would be loaded to OCRAM by SDM, and configured by DDR driver.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/firewall.h |6 +
.../include/mach/system_manager_soc64.h| 10 +-
drivers/ddr/altera/Makefile|3 +-
drivers/ddr/altera/sdram_n5x.c | 2316
drivers/ddr/altera/sdram_soc64.c | 10 +-
5 files changed, 2342 insertions(+), 3 deletions(-)
create mode 100644 drivers/ddr/altera/sdram_n5x.c
diff --git a/arch/arm/mach-socfpga/include/mach/firewall.h
b/arch/arm/mach-socfpga/include/mach/firewall.h
index adab65bc96..5cb7f23f8f 100644
--- a/arch/arm/mach-socfpga/include/mach/firewall.h
+++ b/arch/arm/mach-socfpga/include/mach/firewall.h
@@ -115,10 +115,16 @@ struct socfpga_firwall_l4_sys {
/* Firewall MPU DDR SCR registers */
#define FW_MPU_DDR_SCR_EN 0x00
#define FW_MPU_DDR_SCR_EN_SET 0x04
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASE 0x10
+#define FW_MPU_DDR_SCR_MPUREGION0ADDR_BASEEXT 0x14
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMIT0x18
#define FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT 0x1c
+
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASE 0x90
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT 0x94
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT 0x98
#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT 0x9c
+#define FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMITEXT_FIELD0xff
#define MPUREGION0_ENABLE BIT(0)
#define NONMPUREGION0_ENABLE BIT(8)
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
index fc4e17821b..a8009664fe 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2019-2021 Intel Corporation
*/
#ifndef _SYSTEM_MANAGER_SOC64_H_
@@ -28,8 +28,12 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_SOC64_FPGAINTF_EN2 0x6c
#define SYSMGR_SOC64_FPGAINTF_EN3 0x70
#define SYSMGR_SOC64_DMA_L3MASTER 0x74
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SYSMGR_SOC64_DDR_MODE 0xb8
+#else
#define SYSMGR_SOC64_HMC_CLK 0xb4
#define SYSMGR_SOC64_IO_PA_CTRL0xb8
+#endif
#define SYSMGR_SOC64_NOC_TIMEOUT 0xc0
#define SYSMGR_SOC64_NOC_IDLEREQ_SET 0xc4
#define SYSMGR_SOC64_NOC_IDLEREQ_CLR 0xc8
@@ -143,4 +147,8 @@ void populate_sysmgr_pinmux(void);
#define SYSMGR_WDDBG_PAUSE_ALL_CPU 0x0F0F0F0F
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#defineSYSMGR_SOC64_DDR_MODE_MSK BIT(0)
+#endif
+
#endif /* _SYSTEM_MANAGER_SOC64_H_ */
diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile
index 39dfee5d5a..9fa5d85a27 100644
--- a/drivers/ddr/altera/Makefile
+++ b/drivers/ddr/altera/Makefile
@@ -4,11 +4,12 @@
# Wolfgang Denk, DENX Software Engineering, w...@denx.de.
#
# (C) Copyright 2010, Thomas Chou
-# Copyright (C) 2014 Altera Corporation
+# Copyright (C) 2014-2021 Altera Corporation
ifdef CONFIG_$(SPL_)ALTERA_SDRAM
obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o
endif
diff --git a/drivers/ddr/altera/sdram_n5x.c b/drivers/ddr/altera/sdram_n5x.c
new file mode 100644
index 00..a50c8f43f4
--- /dev/null
+++ b/drivers/ddr/altera/sdram_n5x.c
@@ -0,0 +1,2316 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020-2021 Intel Corporation
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "sdram_soc64.h"
[v1 13/17] arm: socfpga: Add SPL for Intel N5X device
Add SPL for N5X.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} | 37 ++-
1 file changed, 22 insertions(+), 15 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_n5x.c} (83%)
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_n5x.c
similarity index 83%
copy from arch/arm/mach-socfpga/spl_agilex.c
copy to arch/arm/mach-socfpga/spl_n5x.c
index ee5a9dc1e2..d056871d29 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_n5x.c
@@ -1,27 +1,26 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
+ * Copyright (C) 2020-2021 Intel Corporation
*
*/
-#include
-#include
-#include
-#include
-#include
-#include
#include
-#include
-#include
-#include
#include
#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
#include
+#include
+#include
+#include
+#include
+#include
DECLARE_GLOBAL_DATA_PTR;
@@ -54,27 +53,35 @@ void board_init_f(ulong dummy)
sysmgr_pinmux_init();
+ preloader_console_init();
+
ret = uclass_get_device(UCLASS_CLK, 0, &dev);
if (ret) {
- debug("Clock init failed: %d\n", ret);
+ printf("Clock init failed: %d\n", ret);
+ hang();
+ }
+
+ ret = uclass_get_device(UCLASS_CLK, 1, &dev);
+ if (ret) {
+ printf("Memory clock init failed: %d\n", ret);
hang();
}
- preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();
+
ret = uclass_get_device(UCLASS_CACHE, 0, &dev);
if (ret) {
- debug("CCU init failed: %d\n", ret);
+ printf("CCU init failed: %d\n", ret);
hang();
}
#if CONFIG_IS_ENABLED(ALTERA_SDRAM)
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
if (ret) {
- debug("DRAM init failed: %d\n", ret);
+ printf("DRAM init failed: %d\n", ret);
hang();
}
#endif
--
2.13.0
[v1 11/17] ddr: socfpga: Enable memory test on memory size less than 1GB
From: Tien Fong Chee
Minimum 1GB memory size is required in current memory test, so this patch
improves the memory test for processing memory size less than 1GB, and
the size in power of two.
Signed-off-by: Tien Fong Chee
---
drivers/ddr/altera/sdram_soc64.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index a08f0953e5..171cde0e6b 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -182,6 +182,7 @@ void sdram_size_check(struct bd_info *bd)
phys_size_t total_ram_check = 0;
phys_size_t ram_check = 0;
phys_addr_t start = 0;
+ phys_size_t size, total_size;
int bank;
/* Sanity check ensure correct SDRAM size specified */
@@ -189,10 +190,23 @@ void sdram_size_check(struct bd_info *bd)
for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start = bd->bi_dram[bank].start;
+ total_size = bd->bi_dram[bank].size;
while (ram_check < bd->bi_dram[bank].size) {
- ram_check += get_ram_size((void *)(start + ram_check),
-(phys_size_t)SZ_1G);
+ size = min((phys_addr_t)SZ_1G, (phys_addr_t)total_size);
+
+ /*
+* Ensure the size is power of two, this is requirement
to run
+* get_ram_size() / memory test
+*/
+ if (size != 0 && ((size & (size - 1)) == 0)) {
+ ram_check += get_ram_size((void *)(start +
ram_check), size);
+ total_size = bd->bi_dram[bank].size - ram_check;
+ } else {
+ puts("DDR: Memory test requires SDRAM size in
power of two!\n");
+ hang();
+ }
}
+
total_ram_check += ram_check;
ram_check = 0;
}
--
2.13.0
[v1 10/17] arm: socfpga: Add SDRAM driver helper function for Intel N5X device
Add is_ddr_init_skipped function to check if need to skip DDR
initialization for N5X. This patch is preparation for N5X DDR
driver support.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/include/mach/misc.h | 4 ++
arch/arm/mach-socfpga/misc_soc64.c| 67 ++-
2 files changed, 70 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index 649d2f6ce2..c41b7c14cd 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -44,6 +44,10 @@ void socfpga_sdram_remap_zero(void);
int is_fpga_config_ready(void);
#endif
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+bool is_ddr_init_skipped(void);
+#endif
+
void do_bridge_reset(int enable, unsigned int mask);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
diff --git a/arch/arm/mach-socfpga/misc_soc64.c
b/arch/arm/mach-socfpga/misc_soc64.c
index 7b973a79e8..d3945e55aa 100644
--- a/arch/arm/mach-socfpga/misc_soc64.c
+++ b/arch/arm/mach-socfpga/misc_soc64.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*
*/
@@ -19,6 +19,13 @@
DECLARE_GLOBAL_DATA_PTR;
+/* Reset type */
+enum reset_type {
+ POR_RESET,
+ WARM_RESET,
+ COLD_RESET
+};
+
/*
* FPGA programming support for SoC FPGA Stratix 10
*/
@@ -88,3 +95,61 @@ void do_bridge_reset(int enable, unsigned int mask)
socfpga_bridges_reset(enable);
}
+
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+static bool is_ddr_retention_enabled(u32 boot_scratch_cold0_reg)
+{
+ return boot_scratch_cold0_reg &
+ ALT_SYSMGR_SCRATCH_REG_0_DDR_RETENTION_MASK;
+}
+
+static bool is_ddr_bitstream_sha_matching(u32 boot_scratch_cold0_reg)
+{
+ return boot_scratch_cold0_reg & ALT_SYSMGR_SCRATCH_REG_0_DDR_SHA_MASK;
+}
+
+static enum reset_type get_reset_type(u32 boot_scratch_cold0_reg)
+{
+ return (boot_scratch_cold0_reg &
+ ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK) >>
+ ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT;
+}
+
+bool is_ddr_init_skipped(void)
+{
+ u32 reg = readl(socfpga_get_sysmgr_addr() +
+ SYSMGR_SOC64_BOOT_SCRATCH_COLD0);
+
+ if (get_reset_type(reg) == POR_RESET) {
+ debug("%s: POR reset is triggered\n", __func__);
+ debug("%s: DDR init is required\n", __func__);
+ return false;
+ }
+
+ if (get_reset_type(reg) == WARM_RESET) {
+ debug("%s: Warm reset is triggered\n", __func__);
+ debug("%s: DDR init is skipped\n", __func__);
+ return true;
+ }
+
+ if (get_reset_type(reg) == COLD_RESET) {
+ debug("%s: Cold reset is triggered\n", __func__);
+
+ if (is_ddr_retention_enabled(reg)) {
+ debug("%s: DDR retention bit is set\n", __func__);
+
+ if (is_ddr_bitstream_sha_matching(reg)) {
+ debug("%s: Matching in DDR bistream\n",
+ __func__);
+ debug("%s: DDR init is skipped\n", __func__);
+ return true;
+ }
+
+ debug("%s: Mismatch in DDR bistream\n", __func__);
+ }
+ }
+
+ debug("%s: DDR init is required\n", __func__);
+ return false;
+}
+#endif
--
2.13.0
