Re: [U-Boot] [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

[Suresh Gupta]

Hi Jagan,

> 
> 
> > -Original Message-
> > From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> > Sent: Friday, August 11, 2017 4:44 PM
> > To: Suresh Gupta <suresh.gu...@nxp.com>
> > Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>;
> > york...@freescale.com; Anupam Kumar <anupam.kuma...@nxp.com>
> > Subject: Re: [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO
> >
> > On Mon, Jun 5, 2017 at 2:37 PM, Suresh Gupta <suresh.gu...@nxp.com>
> wrote:
> > > In some of the QSPI controller version, there must be atleast 128bit
> > > data available in TX FIFO for any pop operation otherwise error bit
> > > will be set. The code will not make any behavior change for previous
> > > controller as the transfer data size in ipcr register is still the
> > > same.
> > >
> > > Patch is tested on LS1046A which do not require 16 bytes aligned and
> > > LS1088A which require 16 bytes aligned data in TX FIFO
> > >
> > > Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> > > Signed-off-by: Anupam Kumar <anupam.kuma...@nxp.com>
> >
> > Can some one Tested and verified the result?

Please pick this patch, we have the same patch in our SDK from last 2 months 
and do not face any issue.

> >
> > thanks!
> > --
> > Jagan Teki
> > Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> > Maintainer Hyderabad, India.
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Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

Hi Jagan, 

Sorry for late reply to your queries, 
I copied your query here to make continuation of mail.

> > > Don't know whether you tried this or not.
> > >
> > > - Erase bottom 4K sectors using 4K
> > > - Erase middle sectors using SE
> > > - Erase top 4K sectors using 4K

We are able to manage a flash to run in hybrid mode (IE default mode) and in 
this mode few top 4K sectors get erased by 4K command but no other sectors get 
erased with 4K cmd.
In non hybrid mode, we are able to erase all flash uniformly with  SE cmd but 
4K is not working. 

So we need to remove the SECT_4K flag for s25fs512s if we want uniform commad 
command for full flash. 
Also, we need a patch [1] to disable hybrid mode/disable 4K erase.

[1] https://lists.denx.de/pipermail/u-boot/2017-March/285010.html

Thanks
SuresH


> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Suresh
> Gupta
> Sent: Monday, June 12, 2017 7:33 PM
> To: Jagan Teki <jagannadh.t...@gmail.com>
> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>; Yao Yuan
> <yao.y...@nxp.com>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K
> flag
> 
> 
> 
> > -Original Message-
> > From: Suresh Gupta
> > Sent: Monday, June 12, 2017 2:18 PM
> > To: 'Jagan Teki' <jagannadh.t...@gmail.com>
> > Cc: Jagan Teki <ja...@amarulasolutions.com>; york sun
> > <york@nxp.com>; u-boot@lists.denx.de; Jagan Teki
> > <ja...@openedev.com>; Yao Yuan <yao.y...@nxp.com>
> > Subject: RE: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove
> > SECT_4K flag
> >
> >
> >
> > > -Original Message-
> > > From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> > > Sent: Monday, June 12, 2017 11:37 AM
> > > To: Suresh Gupta <suresh.gu...@nxp.com>
> > > Cc: Jagan Teki <ja...@amarulasolutions.com>; york sun
> > > <york....@nxp.com>; u-boot@lists.denx.de; Jagan Teki
> > > <ja...@openedev.com>; Yao Yuan <yao.y...@nxp.com>
> > > Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and
> > > remove SECT_4K flag
> > >
> > > Hi Suresh,
> > >
> > > On Thu, Jun 8, 2017 at 1:00 PM, Suresh Gupta <suresh.gu...@nxp.com>
> > wrote:
> > > > 
> > > >> >
> > > >> > So best way is to disable hybrid mode and configure flash in
> > > >> > Uniform Sector Architecture
> > > >>
> > > >> OK, then send patches to Linux and U-Boot will review and take
> > > >> other suggestions too.
> > > >>
> > > >
> > > > Thanks Jagan,
> > > > I will send U-boot patches (after testing) by early next week.
> > > >
> > > > My next point :) to discuss is "32-bit address options".
> > > > This particular flash do not support below commands
> > > > /* Bank addr access commands */
> > > > #ifdef CONFIG_SPI_FLASH_BAR
> > > > # define CMD_BANKADDR_BRWR  0x17
> > > > # define CMD_BANKADDR_BRRD  0x16
> > > > # define CMD_EXTNADDR_WREAR 0xC5
> > > > # define CMD_EXTNADDR_RDEAR 0xC8
> > > > #endif
> > > >
> > > > Instead  of above S25FS512S flash support 32-bit address commands
> > > > like 4READ, 4P4E and many more which require 32 bit address
> > > > directly pass on
> > > wires.
> > > >
> > > > Jagan,
> > > > So, Do we have any plan to fix this?
> > > > Yao Yuan already send one patch [1] for same.
> > > > I think this is a decent approach [1]. If required I will resend
> > > > this patch with
> > > little changes.
> > >
> > > Don't know whether you tried this or not.
> > >
> > > - Erase bottom 4K sectors using 4K
> > > - Erase middle sectors using SE
> > > - Erase top 4K sectors using 4K
> >
> > I will try all combinations and let you know the results.
> >
> Jagan,
> The problem here is, I have all board in which we disable hybrid mode and we
> write this in nonvolatile register.
> So on my boards 4K erase (0x20) is not working on any of the sectors.
> Please suggest.
> 
> Hybrid mode of this flash supports,
>   - Physical set of eight 4-kbytes sectors and
>   - one 224-kbytes sector at the top or bottom of address space 
> with
>   - all remaining sectors of 256 kbytes.
> So even if we are able to erase eight sectors via cmd 4K and rest via 256
> kbyte(0xd8) Then what about one sector of 224 Kbytes.
> And how we tell user about this erase pattern.
> 
> Again, my suggestion is to disable hybrid mode (volatile) and we may revisit 
> if
> anyone come up with different approach
> Please suggest.
> 
> Thanks
> SuresH
> 
> 
> > >
> > > thanks!
> > > --
> > > Jagan Teki
> > > Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> > > Maintainer Hyderabad, India.
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Re: [U-Boot] SPI NAND support

[Suresh Gupta]

Thanks Jagan for your response. 
NXP is coming up with SPI-NAND in their new SOCs/boards and we are in 
discussion that how we add this support in u-boot. 

Thanks
SuresH 

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, September 12, 2017 12:43 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de
> Subject: Re: [U-Boot] SPI NAND support
> 
> On Tue, Sep 12, 2017 at 10:56 AM, Suresh Gupta <suresh.gu...@nxp.com>
> wrote:
> > Hi All,
> >
> > Do we have NAND support in SPI framework. Please provide me pointers so
> that I analyze/understand that for my purpose.
> 
> Currently not, we're working on driver-model based SPI Flash handling..that
> might be a starting point to add spi-nand (but not sure). And if you have any
> thoughts please post the changes or inputs.
> 
> Do you have any-idea about hardware that support spi-nand in market?
> 
> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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[U-Boot] SPI NAND support

[Suresh Gupta]

Hi All,

Do we have NAND support in SPI framework. Please provide me pointers so that I 
analyze/understand that for my purpose. 

Thanks 
SuresH
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[U-Boot] SPI NAND Support

[Suresh Gupta]

Hi Jagan,

Do we have NAND support in our SPI framework of u-boot. Please provide me some 
pointers if any so that I incorporate our controller with that driver.

Thanks
SuresH
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[U-Boot] [PATCH v4] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Change in v4:
 - change Timeout from 1000ms to 100ms 


Changes in v3:
 - replace printf to debug
 - return whatever return from wait_for_bit, before it was -EBUSY

Changes in v2:

 - Add wait_for_bit instead of while
 - move the busy check code to fsl_qspi_claim_bus form qspi_xfer


 drivers/spi/fsl_qspi.c | 28 +++-
 drivers/spi/fsl_qspi.h |  4 
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1dfa89a..8753ed9 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "fsl_qspi.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -991,7 +992,7 @@ static int fsl_qspi_probe(struct udevice *bus)
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
-   int i;
+   int i, ret;
 
dm_spi_bus = bus->uclass_priv;
 
@@ -1011,6 +1012,18 @@ static int fsl_qspi_probe(struct udevice *bus)
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
 
+   /* make sure controller is not busy anywhere */
+   ret = wait_for_bit(__func__, >regs->sr,
+  QSPI_SR_BUSY_MASK |
+  QSPI_SR_AHB_ACC_MASK |
+  QSPI_SR_IP_ACC_MASK,
+  false, 100, false);
+
+   if (ret) {
+   debug("ERROR : The controller is busy\n");
+   return ret;
+   }
+
mcr_val = qspi_read32(priv->flags, >regs->mcr);
qspi_write32(priv->flags, >regs->mcr,
 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
@@ -1156,10 +1169,23 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
struct fsl_qspi_priv *priv;
struct udevice *bus;
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   int ret;
 
bus = dev->parent;
priv = dev_get_priv(bus);
 
+   /* make sure controller is not busy anywhere */
+   ret = wait_for_bit(__func__, >regs->sr,
+  QSPI_SR_BUSY_MASK |
+  QSPI_SR_AHB_ACC_MASK |
+  QSPI_SR_IP_ACC_MASK,
+  false, 100, false);
+
+   if (ret) {
+   debug("ERROR : The controller is busy\n");
+   return ret;
+   }
+
priv->cur_amba_base = priv->amba_base[slave_plat->cs];
 
qspi_module_disable(priv, 0);
diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h
index 6cb3610..e468eb2 100644
--- a/drivers/spi/fsl_qspi.h
+++ b/drivers/spi/fsl_qspi.h
@@ -105,6 +105,10 @@ struct fsl_qspi_regs {
 #define QSPI_RBCT_RXBRD_SHIFT  8
 #define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
 
+#define QSPI_SR_AHB_ACC_SHIFT  2
+#define QSPI_SR_AHB_ACC_MASK   (1 << QSPI_SR_AHB_ACC_SHIFT)
+#define QSPI_SR_IP_ACC_SHIFT   1
+#define QSPI_SR_IP_ACC_MASK(1 << QSPI_SR_IP_ACC_SHIFT)
 #define QSPI_SR_BUSY_SHIFT 0
 #define QSPI_SR_BUSY_MASK  (1 << QSPI_SR_BUSY_SHIFT)
 
-- 
1.9.3

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Re: [U-Boot] [PATCH v3] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, August 30, 2017 7:54 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de; York Sun <york@nxp.com>
> Subject: Re: [PATCH v3] spi: fsl_qspi: Add controller busy check before new 
> spi
> operation
> 
> On Wed, Aug 30, 2017 at 2:00 PM, Suresh Gupta <suresh.gu...@nxp.com>
> wrote:
> > It is recommended to check either controller is free to take new spi
> > action. The IP_ACC and AHB_ACC bits indicates that the controller is
> > busy in IP or AHB mode respectively.
> > And the BUSY bit indicates that controller is currently busy handling
> > a transaction to an external flash device
> >
> > Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> > ---
> > Chnages in v3:
> >  - replace printf to debug
> >  - return whatever return from wait_for_bit, before it was -EBUSY
> >
> > Changes in v2:
> >
> >  - Add wait_for_bit instead of while
> >  - move the busy check code to fsl_qspi_claim_bus form qspi_xfer
> >
> >
> >  drivers/spi/fsl_qspi.c | 28 +++-
> > drivers/spi/fsl_qspi.h |  4 
> >  2 files changed, 31 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 1dfa89a..8f0f29e 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -14,6 +14,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include "fsl_qspi.h"
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> > @@ -991,7 +992,7 @@ static int fsl_qspi_probe(struct udevice *bus)
> > struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
> > struct fsl_qspi_priv *priv = dev_get_priv(bus);
> > struct dm_spi_bus *dm_spi_bus;
> > -   int i;
> > +   int i, ret;
> >
> > dm_spi_bus = bus->uclass_priv;
> >
> > @@ -1011,6 +1012,18 @@ static int fsl_qspi_probe(struct udevice *bus)
> > priv->flash_num = plat->flash_num;
> > priv->num_chipselect = plat->num_chipselect;
> >
> > +   /* make sure controller is not busy anywhere */
> > +   ret = wait_for_bit(__func__, >regs->sr,
> > +  QSPI_SR_BUSY_MASK |
> > +  QSPI_SR_AHB_ACC_MASK |
> > +  QSPI_SR_IP_ACC_MASK,
> > +  false, 1000, false);
> 
> 100ms not enough?
It should be, Will send new patch


> 
> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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[U-Boot] [PATCH v3] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Chnages in v3:
 - replace printf to debug
 - return whatever return from wait_for_bit, before it was -EBUSY

Changes in v2:

 - Add wait_for_bit instead of while
 - move the busy check code to fsl_qspi_claim_bus form qspi_xfer


 drivers/spi/fsl_qspi.c | 28 +++-
 drivers/spi/fsl_qspi.h |  4 
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1dfa89a..8f0f29e 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "fsl_qspi.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -991,7 +992,7 @@ static int fsl_qspi_probe(struct udevice *bus)
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
-   int i;
+   int i, ret;
 
dm_spi_bus = bus->uclass_priv;
 
@@ -1011,6 +1012,18 @@ static int fsl_qspi_probe(struct udevice *bus)
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
 
+   /* make sure controller is not busy anywhere */
+   ret = wait_for_bit(__func__, >regs->sr,
+  QSPI_SR_BUSY_MASK |
+  QSPI_SR_AHB_ACC_MASK |
+  QSPI_SR_IP_ACC_MASK,
+  false, 1000, false);
+
+   if (ret) {
+   debug("ERROR : The controller is busy\n");
+   return ret;
+   }
+
mcr_val = qspi_read32(priv->flags, >regs->mcr);
qspi_write32(priv->flags, >regs->mcr,
 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
@@ -1156,10 +1169,23 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
struct fsl_qspi_priv *priv;
struct udevice *bus;
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   int ret;
 
bus = dev->parent;
priv = dev_get_priv(bus);
 
+   /* make sure controller is not busy anywhere */
+   ret = wait_for_bit(__func__, >regs->sr,
+  QSPI_SR_BUSY_MASK |
+  QSPI_SR_AHB_ACC_MASK |
+  QSPI_SR_IP_ACC_MASK,
+  false, 1000, false);
+
+   if (ret) {
+   debug("ERROR : The controller is busy\n");
+   return ret;
+   }
+
priv->cur_amba_base = priv->amba_base[slave_plat->cs];
 
qspi_module_disable(priv, 0);
diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h
index 6cb3610..e468eb2 100644
--- a/drivers/spi/fsl_qspi.h
+++ b/drivers/spi/fsl_qspi.h
@@ -105,6 +105,10 @@ struct fsl_qspi_regs {
 #define QSPI_RBCT_RXBRD_SHIFT  8
 #define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
 
+#define QSPI_SR_AHB_ACC_SHIFT  2
+#define QSPI_SR_AHB_ACC_MASK   (1 << QSPI_SR_AHB_ACC_SHIFT)
+#define QSPI_SR_IP_ACC_SHIFT   1
+#define QSPI_SR_IP_ACC_MASK(1 << QSPI_SR_IP_ACC_SHIFT)
 #define QSPI_SR_BUSY_SHIFT 0
 #define QSPI_SR_BUSY_MASK  (1 << QSPI_SR_BUSY_SHIFT)
 
-- 
1.9.3

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Re: [U-Boot] [PATCH v2] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Tuesday, August 29, 2017 11:08 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de; York Sun <york@nxp.com>
> Subject: Re: [PATCH v2] spi: fsl_qspi: Add controller busy check before new 
> spi
> operation
> 
> On Tue, Aug 29, 2017 at 6:55 PM, Suresh Gupta <suresh.gu...@nxp.com>
> wrote:
> > It is recommended to check either controller is free to take new spi
> > action. The IP_ACC and AHB_ACC bits indicates that the controller is
> > busy in IP or AHB mode respectively.
> > And the BUSY bit indicates that controller is currently busy handling
> > a transaction to an external flash device
> >
> > Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> > ---
> > Changes in v2:
> >
> > - Add wait_for_bit instead of while
> > - move the busy check code to fsl_qspi_claim_bus form qspi_xfer
> >
> >  drivers/spi/fsl_qspi.c | 28 +++-
> > drivers/spi/fsl_qspi.h |  4 
> >  2 files changed, 31 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 1dfa89a..ed23aac 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -14,6 +14,7 @@
> >  #include 
> >  #include 
> >  #include 
> > +#include 
> >  #include "fsl_qspi.h"
> >
> >  DECLARE_GLOBAL_DATA_PTR;
> > @@ -991,7 +992,7 @@ static int fsl_qspi_probe(struct udevice *bus)
> > struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
> > struct fsl_qspi_priv *priv = dev_get_priv(bus);
> > struct dm_spi_bus *dm_spi_bus;
> > -   int i;
> > +   int i, ret;
> >
> > dm_spi_bus = bus->uclass_priv;
> >
> > @@ -1011,6 +1012,18 @@ static int fsl_qspi_probe(struct udevice *bus)
> > priv->flash_num = plat->flash_num;
> > priv->num_chipselect = plat->num_chipselect;
> >
> 
> I think in previous version, this code not added in probe is it? is this 
> because
> probe doing mcr and other reg operations?

The probe function changes the LUTs, change AHB configuration and change the 
endianness.  
So, changing above setting when the controller is busy in some AHB access will 
affect the running access.
> 
> > +   /* make sure controller is not busy anywhere */
> > +   ret = wait_for_bit(__func__, >regs->sr,
> > +  QSPI_SR_BUSY_MASK |
> > +  QSPI_SR_AHB_ACC_MASK |
> > +  QSPI_SR_IP_ACC_MASK,
> > +  false, 1000, false);
> > +
> > +   if (ret) {
> > +   printf("ERROR : The controller is busy\n");
> > +   return -EBUSY;
> > +   }
> 
> Better to drop printf or use debug and
The error above is trivial and after this error, the sf commands do not work.
And if we hide the message under debug, normal user will not understand the 
issue.  
As per me this should be printf, what you say? 

> wait_for_bit usually return -ETIMEDOUT
> or -EINTR on failure so just return ret.
Ok, I will make changes in next patch

> 
> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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[U-Boot] [PATCH] armv8: fsl-layerscape: Fix final MMU table for QSPI and IFC

[Suresh Gupta]

For QSPI and IFC addresses execution shouldn't be allowed
when u-boot running from DDR. Revise the MMU final table
to enforce execute-never bits.

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/cpu.h | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h 
b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index c4e5ecc..3d564d6 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -199,7 +199,8 @@ static struct mm_region final_map[] = {
},
{ CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
  CONFIG_SYS_FSL_QSPI_SIZE1,
- PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
  CONFIG_SYS_FSL_QSPI_SIZE2,
@@ -208,7 +209,8 @@ static struct mm_region final_map[] = {
},
{ CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
  CONFIG_SYS_FSL_IFC_SIZE2,
- PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE
+ PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
},
{ CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
  CONFIG_SYS_FSL_DCSR_SIZE,
-- 
1.9.3

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[U-Boot] [PATCH v2] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2:

- Add wait_for_bit instead of while
- move the busy check code to fsl_qspi_claim_bus form qspi_xfer

 drivers/spi/fsl_qspi.c | 28 +++-
 drivers/spi/fsl_qspi.h |  4 
 2 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1dfa89a..ed23aac 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -14,6 +14,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "fsl_qspi.h"
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -991,7 +992,7 @@ static int fsl_qspi_probe(struct udevice *bus)
struct fsl_qspi_platdata *plat = dev_get_platdata(bus);
struct fsl_qspi_priv *priv = dev_get_priv(bus);
struct dm_spi_bus *dm_spi_bus;
-   int i;
+   int i, ret;
 
dm_spi_bus = bus->uclass_priv;
 
@@ -1011,6 +1012,18 @@ static int fsl_qspi_probe(struct udevice *bus)
priv->flash_num = plat->flash_num;
priv->num_chipselect = plat->num_chipselect;
 
+   /* make sure controller is not busy anywhere */
+   ret = wait_for_bit(__func__, >regs->sr,
+  QSPI_SR_BUSY_MASK |
+  QSPI_SR_AHB_ACC_MASK |
+  QSPI_SR_IP_ACC_MASK,
+  false, 1000, false);
+
+   if (ret) {
+   printf("ERROR : The controller is busy\n");
+   return -EBUSY;
+   }
+
mcr_val = qspi_read32(priv->flags, >regs->mcr);
qspi_write32(priv->flags, >regs->mcr,
 QSPI_MCR_RESERVED_MASK | QSPI_MCR_MDIS_MASK |
@@ -1156,10 +1169,23 @@ static int fsl_qspi_claim_bus(struct udevice *dev)
struct fsl_qspi_priv *priv;
struct udevice *bus;
struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
+   int ret;
 
bus = dev->parent;
priv = dev_get_priv(bus);
 
+   /* make sure controller is not busy anywhere */
+   ret = wait_for_bit(__func__, >regs->sr,
+  QSPI_SR_BUSY_MASK |
+  QSPI_SR_AHB_ACC_MASK |
+  QSPI_SR_IP_ACC_MASK,
+  false, 1000, false);
+
+   if (ret) {
+   printf("ERROR : The controller is busy\n");
+   return -EBUSY;
+   }
+
priv->cur_amba_base = priv->amba_base[slave_plat->cs];
 
qspi_module_disable(priv, 0);
diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h
index 6cb3610..e468eb2 100644
--- a/drivers/spi/fsl_qspi.h
+++ b/drivers/spi/fsl_qspi.h
@@ -105,6 +105,10 @@ struct fsl_qspi_regs {
 #define QSPI_RBCT_RXBRD_SHIFT  8
 #define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
 
+#define QSPI_SR_AHB_ACC_SHIFT  2
+#define QSPI_SR_AHB_ACC_MASK   (1 << QSPI_SR_AHB_ACC_SHIFT)
+#define QSPI_SR_IP_ACC_SHIFT   1
+#define QSPI_SR_IP_ACC_MASK(1 << QSPI_SR_IP_ACC_SHIFT)
 #define QSPI_SR_BUSY_SHIFT 0
 #define QSPI_SR_BUSY_MASK  (1 << QSPI_SR_BUSY_SHIFT)
 
-- 
1.9.3

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Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, August 23, 2017 10:57 AM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>
> Subject: Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before
> new spi operation
> 
> On Tue, Aug 22, 2017 at 4:19 PM, Suresh Gupta <suresh.gu...@nxp.com>
> wrote:
> > Thanks  Jagan for reviewing the code.
> > Please find comments in line
> >
> >> -Original Message-
> >> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> >> Sent: Monday, August 21, 2017 7:53 PM
> >> To: Suresh Gupta <suresh.gu...@nxp.com>
> >> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>
> >> Subject: Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy
> >> check before new spi operation
> >>
> >> On Mon, Aug 21, 2017 at 3:56 PM, Suresh Gupta <suresh.gu...@nxp.com>
> >> wrote:
> >> > It is recommended to check either controller is free to take new
> >> > spi action. The IP_ACC and AHB_ACC bits indicates that the
> >> > controller is busy in IP or AHB mode respectively.
> >> > And the BUSY bit indicates that the controller is currently busy
> >> > handling a transaction to an external flash device
> >> >
> >> > Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> >> > ---
> >> >  drivers/spi/fsl_qspi.c | 26 ++
> >> > drivers/spi/fsl_qspi.h |  4 
> >> >  2 files changed, 30 insertions(+)
> >> >
> >> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> >> > 1dfa89a..69e9712 100644
> >> > --- a/drivers/spi/fsl_qspi.c
> >> > +++ b/drivers/spi/fsl_qspi.c
> >> > @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)
> >> > #endif  }
> >> >
> >> > +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {
> >> > +   u32 sr;
> >> > +   u32 retry = 5;
> >> > +
> >> > +   do {
> >> > +   sr = qspi_read32(priv->flags, >regs->sr);
> >> > +   if ((sr & QSPI_SR_BUSY_MASK) ||
> >>
> >> Does this bit need? we can check the busy-state with AHB_ACC and
> >> IP_ACC
> >
> > The definition of the three bits is
> > Bit2 - AHB_ACC: AHB Access: Asserted when the transaction currently
> executed was initiated by AHB bus.
> > Bit1 - IP_ACC: IP Access: Asserted when transaction currently executed was
> initiated by IP bus.
> > Bit0 - BUSY: Module Busy: Asserted when module is currently busy handling a
> transaction to an external flash device.
> >
> > Also, the below are statements mentioned in the IP Block Guide For AHB
> > Access: Since the read access is triggered via the AHB bus, the
> QSPI_SR[AHB_ACC]
> > status bit is set driving in turn the QSPI_SR[BUSY] bit 
> > until the
> transaction is finished.
> > For IP Access: Since the read access is triggered by an IP command the 
> > IP_ACC
> status bit and
> > the BUSY bit are both set (both are located in the Status 
> > Register
> (QSPI_SR) ).
> >
> > So, BUSY flag is set when the controller is busy in communication with FLASH
> and this is true for both IP and AHB mode.
> > That’s the reason checking all three status bits ensures us that controller 
> > is
> free.
> >
> >>
> >> > +   (sr & QSPI_SR_AHB_ACC_MASK) ||
> >> > +   (sr & QSPI_SR_IP_ACC_MASK)) {
> >> > +   debug("The controller is busy, sr = 0x%x\n", sr);
> >> > +   udelay(1);
> >> > +   } else {
> >> > +   break;
> >> > +   }
> >> > +   } while (--retry);
> >>
> >> These retry and infine loop doesn't seems OK, how about using wait_for_bit?
> > Ok, I will use below and send a new patch
> >
> > ret = wait_for_bit(__func__, regs->sr,
> >   QSPI_SR_BUSY_MASK |
> >   QSPI_SR_AHB_ACC_MASK |
> >   QSPI_SR_IP_ACC_MASK,
> >   false, 1000, false);
> >>
> >> > +
> >> > +   return (sr & QSPI_SR_BUSY_MASK) ||
> >> > +   (sr & QSPI_

Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

> -Original Message-
> From: York Sun
> Sent: Tuesday, August 22, 2017 9:56 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>; u-boot@lists.denx.de
> Cc: ja...@openedev.com; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com>
> Subject: Re: [PATCH] spi: fsl_qspi: Add controller busy check before new spi
> operation
> 
> On 08/21/2017 03:25 AM, Suresh Gupta wrote:
> > It is recommended to check either controller is free to take new spi
> > action. The IP_ACC and AHB_ACC bits indicates that the controller is
> > busy in IP or AHB mode respectively.
> > And the BUSY bit indicates that the controller is currently busy
> > handling a transaction to an external flash device
> >
> > Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> > ---
> >   drivers/spi/fsl_qspi.c | 26 ++
> >   drivers/spi/fsl_qspi.h |  4 
> >   2 files changed, 30 insertions(+)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 1dfa89a..69e9712 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)
> >   #endif
> >   }
> >
> > +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {
> > +   u32 sr;
> > +   u32 retry = 5;
> > +
> > +   do {
> > +   sr = qspi_read32(priv->flags, >regs->sr);
> > +   if ((sr & QSPI_SR_BUSY_MASK) ||
> > +   (sr & QSPI_SR_AHB_ACC_MASK) ||
> > +   (sr & QSPI_SR_IP_ACC_MASK)) {
> > +   debug("The controller is busy, sr = 0x%x\n", sr);
> > +   udelay(1);
> > +   } else {
> > +   break;
> > +   }
> > +   } while (--retry);
> 
> Does the 5 microsecond-delay make any difference?
> 
> > +
> > +   return (sr & QSPI_SR_BUSY_MASK) ||
> > +   (sr & QSPI_SR_AHB_ACC_MASK) || (sr &
> QSPI_SR_IP_ACC_MASK); }
> > +
> >   static void qspi_set_lut(struct fsl_qspi_priv *priv)
> >   {
> > struct fsl_qspi_regs *regs = priv->regs; @@ -765,6 +786,11 @@ int
> > qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
> >
> > WATCHDOG_RESET();
> >
> > +   if (qspi_controller_busy(priv)) {
> > +   printf("ERROR : The controller is busy\n");
> > +   return -EBUSY;
> > +   }
> 
> If the controller should never be busy for this operation, I wonder if you 
> really
> need a delay above.

As we see in our setup that controller get free after some time. So, I took 5 
microseconds as arbitrary number. 
Moreover, below statement [1] of BG points that controller gets free after 
prefetch completes. 

[1] Snapshot from RM: 
For any AHB access, the sequence pointed to by the QSPI_BFGENCR [SEQID] field 
is used for
the flash transaction initiated. The data is returned to the master as soon as 
the requested
amount is read from the serial flash. The controller however, continues to 
prefetch the
rest of the data in anticipation of a next consecutive request.
 
> 
> York
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Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

Thanks  Jagan for reviewing the code. 
Please find comments in line 

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Monday, August 21, 2017 7:53 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>
> Subject: Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before
> new spi operation
> 
> On Mon, Aug 21, 2017 at 3:56 PM, Suresh Gupta <suresh.gu...@nxp.com>
> wrote:
> > It is recommended to check either controller is free to take new spi
> > action. The IP_ACC and AHB_ACC bits indicates that the controller is
> > busy in IP or AHB mode respectively.
> > And the BUSY bit indicates that the controller is currently busy
> > handling a transaction to an external flash device
> >
> > Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> > ---
> >  drivers/spi/fsl_qspi.c | 26 ++
> > drivers/spi/fsl_qspi.h |  4 
> >  2 files changed, 30 insertions(+)
> >
> > diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index
> > 1dfa89a..69e9712 100644
> > --- a/drivers/spi/fsl_qspi.c
> > +++ b/drivers/spi/fsl_qspi.c
> > @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)
> > #endif  }
> >
> > +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {
> > +   u32 sr;
> > +   u32 retry = 5;
> > +
> > +   do {
> > +   sr = qspi_read32(priv->flags, >regs->sr);
> > +   if ((sr & QSPI_SR_BUSY_MASK) ||
> 
> Does this bit need? we can check the busy-state with AHB_ACC and IP_ACC

The definition of the three bits is 
Bit2 - AHB_ACC: AHB Access: Asserted when the transaction currently executed 
was initiated by AHB bus.
Bit1 - IP_ACC: IP Access: Asserted when transaction currently executed was 
initiated by IP bus.
Bit0 - BUSY: Module Busy: Asserted when module is currently busy handling a 
transaction to an external flash device.

Also, the below are statements mentioned in the IP Block Guide
For AHB Access: Since the read access is triggered via the AHB bus, the 
QSPI_SR[AHB_ACC] 
status bit is set driving in turn the QSPI_SR[BUSY] bit until 
the transaction is finished.
For IP Access: Since the read access is triggered by an IP command the IP_ACC 
status bit and
the BUSY bit are both set (both are located in the Status 
Register (QSPI_SR) ).

So, BUSY flag is set when the controller is busy in communication with FLASH 
and this is true for both IP and AHB mode.
That’s the reason checking all three status bits ensures us that controller is 
free.  

> 
> > +   (sr & QSPI_SR_AHB_ACC_MASK) ||
> > +   (sr & QSPI_SR_IP_ACC_MASK)) {
> > +   debug("The controller is busy, sr = 0x%x\n", sr);
> > +   udelay(1);
> > +   } else {
> > +   break;
> > +   }
> > +   } while (--retry);
> 
> These retry and infine loop doesn't seems OK, how about using wait_for_bit?
Ok, I will use below and send a new patch

ret = wait_for_bit(__func__, regs->sr,
  QSPI_SR_BUSY_MASK |
  QSPI_SR_AHB_ACC_MASK |
  QSPI_SR_IP_ACC_MASK,
  false, 1000, false);
> 
> > +
> > +   return (sr & QSPI_SR_BUSY_MASK) ||
> > +   (sr & QSPI_SR_AHB_ACC_MASK) || (sr &
> > + QSPI_SR_IP_ACC_MASK);
> 
> I didn't understand why these bits need to return? 
After wait_for_bit, this is not required 

> and when will the LUT trigger?
The check is added as it is recommended that before any new transaction, these 
bits should be 0 i.e. controller is not busy.
This check is required before all new types of transaction with FLASH. 
So I added this in qspi_xfer() which intern calls actual hardware operations 
like qspi_op_write, qspi_op_erase, qspi_ahb_read, qspi_op_rdsr etc., which 
triggers the LUT.  

> 
> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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Re: [U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

Hi York, 

Can I delegate this patch to you? Delegate to Jagan (SPI Maintainer) delays the 
acceptance process. 

Thanks 
SuresH

> -Original Message-
> From: Suresh Gupta [mailto:suresh.gu...@nxp.com]
> Sent: Monday, August 21, 2017 3:56 PM
> To: u-boot@lists.denx.de
> Cc: York Sun <york@nxp.com>; ja...@openedev.com; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com>; Suresh Gupta <suresh.gu...@nxp.com>
> Subject: [PATCH] spi: fsl_qspi: Add controller busy check before new spi
> operation
> 
> It is recommended to check either controller is free to take new spi action. 
> The
> IP_ACC and AHB_ACC bits indicates that the controller is busy in IP or AHB 
> mode
> respectively.
> And the BUSY bit indicates that the controller is currently busy handling a
> transaction to an external flash device
> 
> Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> ---
>  drivers/spi/fsl_qspi.c | 26 ++  
> drivers/spi/fsl_qspi.h
> |  4 
>  2 files changed, 30 insertions(+)
> 
> diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c index 
> 1dfa89a..69e9712
> 100644
> --- a/drivers/spi/fsl_qspi.c
> +++ b/drivers/spi/fsl_qspi.c
> @@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)  #endif  }
> 
> +static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv) {
> + u32 sr;
> + u32 retry = 5;
> +
> + do {
> + sr = qspi_read32(priv->flags, >regs->sr);
> + if ((sr & QSPI_SR_BUSY_MASK) ||
> + (sr & QSPI_SR_AHB_ACC_MASK) ||
> + (sr & QSPI_SR_IP_ACC_MASK)) {
> + debug("The controller is busy, sr = 0x%x\n", sr);
> + udelay(1);
> + } else {
> + break;
> + }
> + } while (--retry);
> +
> + return (sr & QSPI_SR_BUSY_MASK) ||
> + (sr & QSPI_SR_AHB_ACC_MASK) || (sr &
> QSPI_SR_IP_ACC_MASK); }
> +
>  static void qspi_set_lut(struct fsl_qspi_priv *priv)  {
>   struct fsl_qspi_regs *regs = priv->regs; @@ -765,6 +786,11 @@ int
> qspi_xfer(struct fsl_qspi_priv *priv, unsigned int bitlen,
> 
>   WATCHDOG_RESET();
> 
> + if (qspi_controller_busy(priv)) {
> + printf("ERROR : The controller is busy\n");
> + return -EBUSY;
> + }
> +
>   if (dout) {
>   if (flags & SPI_XFER_BEGIN) {
>   priv->cur_seqid = *(u8 *)dout;
> diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h index 
> 6cb3610..e468eb2
> 100644
> --- a/drivers/spi/fsl_qspi.h
> +++ b/drivers/spi/fsl_qspi.h
> @@ -105,6 +105,10 @@ struct fsl_qspi_regs {
>  #define QSPI_RBCT_RXBRD_SHIFT8
>  #define QSPI_RBCT_RXBRD_USEIPS   (1 <<
> QSPI_RBCT_RXBRD_SHIFT)
> 
> +#define QSPI_SR_AHB_ACC_SHIFT2
> +#define QSPI_SR_AHB_ACC_MASK (1 <<
> QSPI_SR_AHB_ACC_SHIFT)
> +#define QSPI_SR_IP_ACC_SHIFT 1
> +#define QSPI_SR_IP_ACC_MASK  (1 << QSPI_SR_IP_ACC_SHIFT)
>  #define QSPI_SR_BUSY_SHIFT   0
>  #define QSPI_SR_BUSY_MASK(1 << QSPI_SR_BUSY_SHIFT)
> 
> --
> 1.9.3

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[U-Boot] [PATCH] spi: fsl_qspi: Add controller busy check before new spi operation

[Suresh Gupta]

It is recommended to check either controller is free to take
new spi action. The IP_ACC and AHB_ACC bits indicates that
the controller is busy in IP or AHB mode respectively.
And the BUSY bit indicates that the controller is currently
busy handling a transaction to an external flash device

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
 drivers/spi/fsl_qspi.c | 26 ++
 drivers/spi/fsl_qspi.h |  4 
 2 files changed, 30 insertions(+)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index 1dfa89a..69e9712 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -165,6 +165,27 @@ static inline u32 qspi_endian_xchg(u32 data)
 #endif
 }
 
+static inline u32 qspi_controller_busy(struct fsl_qspi_priv *priv)
+{
+   u32 sr;
+   u32 retry = 5;
+
+   do {
+   sr = qspi_read32(priv->flags, >regs->sr);
+   if ((sr & QSPI_SR_BUSY_MASK) ||
+   (sr & QSPI_SR_AHB_ACC_MASK) ||
+   (sr & QSPI_SR_IP_ACC_MASK)) {
+   debug("The controller is busy, sr = 0x%x\n", sr);
+   udelay(1);
+   } else {
+   break;
+   }
+   } while (--retry);
+
+   return (sr & QSPI_SR_BUSY_MASK) ||
+   (sr & QSPI_SR_AHB_ACC_MASK) || (sr & QSPI_SR_IP_ACC_MASK);
+}
+
 static void qspi_set_lut(struct fsl_qspi_priv *priv)
 {
struct fsl_qspi_regs *regs = priv->regs;
@@ -765,6 +786,11 @@ int qspi_xfer(struct fsl_qspi_priv *priv, unsigned int 
bitlen,
 
WATCHDOG_RESET();
 
+   if (qspi_controller_busy(priv)) {
+   printf("ERROR : The controller is busy\n");
+   return -EBUSY;
+   }
+
if (dout) {
if (flags & SPI_XFER_BEGIN) {
priv->cur_seqid = *(u8 *)dout;
diff --git a/drivers/spi/fsl_qspi.h b/drivers/spi/fsl_qspi.h
index 6cb3610..e468eb2 100644
--- a/drivers/spi/fsl_qspi.h
+++ b/drivers/spi/fsl_qspi.h
@@ -105,6 +105,10 @@ struct fsl_qspi_regs {
 #define QSPI_RBCT_RXBRD_SHIFT  8
 #define QSPI_RBCT_RXBRD_USEIPS (1 << QSPI_RBCT_RXBRD_SHIFT)
 
+#define QSPI_SR_AHB_ACC_SHIFT  2
+#define QSPI_SR_AHB_ACC_MASK   (1 << QSPI_SR_AHB_ACC_SHIFT)
+#define QSPI_SR_IP_ACC_SHIFT   1
+#define QSPI_SR_IP_ACC_MASK(1 << QSPI_SR_IP_ACC_SHIFT)
 #define QSPI_SR_BUSY_SHIFT 0
 #define QSPI_SR_BUSY_MASK  (1 << QSPI_SR_BUSY_SHIFT)
 
-- 
1.9.3

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Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

> -Original Message-
> From: Suresh Gupta
> Sent: Monday, June 12, 2017 2:18 PM
> To: 'Jagan Teki' <jagannadh.t...@gmail.com>
> Cc: Jagan Teki <ja...@amarulasolutions.com>; york sun <york@nxp.com>;
> u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>; Yao Yuan
> <yao.y...@nxp.com>
> Subject: RE: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K
> flag
> 
> 
> 
> > -Original Message-
> > From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> > Sent: Monday, June 12, 2017 11:37 AM
> > To: Suresh Gupta <suresh.gu...@nxp.com>
> > Cc: Jagan Teki <ja...@amarulasolutions.com>; york sun
> > <york@nxp.com>; u-boot@lists.denx.de; Jagan Teki
> > <ja...@openedev.com>; Yao Yuan <yao.y...@nxp.com>
> > Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove
> > SECT_4K flag
> >
> > Hi Suresh,
> >
> > On Thu, Jun 8, 2017 at 1:00 PM, Suresh Gupta <suresh.gu...@nxp.com>
> wrote:
> > > 
> > >> >
> > >> > So best way is to disable hybrid mode and configure flash in
> > >> > Uniform Sector Architecture
> > >>
> > >> OK, then send patches to Linux and U-Boot will review and take
> > >> other suggestions too.
> > >>
> > >
> > > Thanks Jagan,
> > > I will send U-boot patches (after testing) by early next week.
> > >
> > > My next point :) to discuss is "32-bit address options".
> > > This particular flash do not support below commands
> > > /* Bank addr access commands */
> > > #ifdef CONFIG_SPI_FLASH_BAR
> > > # define CMD_BANKADDR_BRWR  0x17
> > > # define CMD_BANKADDR_BRRD  0x16
> > > # define CMD_EXTNADDR_WREAR 0xC5
> > > # define CMD_EXTNADDR_RDEAR 0xC8
> > > #endif
> > >
> > > Instead  of above S25FS512S flash support 32-bit address commands
> > > like 4READ, 4P4E and many more which require 32 bit address directly
> > > pass on
> > wires.
> > >
> > > Jagan,
> > > So, Do we have any plan to fix this?
> > > Yao Yuan already send one patch [1] for same.
> > > I think this is a decent approach [1]. If required I will resend
> > > this patch with
> > little changes.
> >
> > Don't know whether you tried this or not.
> >
> > - Erase bottom 4K sectors using 4K
> > - Erase middle sectors using SE
> > - Erase top 4K sectors using 4K
> 
> I will try all combinations and let you know the results.
> 
Jagan,
The problem here is, I have all board in which we disable hybrid mode and we 
write this in nonvolatile register.
So on my boards 4K erase (0x20) is not working on any of the sectors. 
Please suggest. 

Hybrid mode of this flash supports,
- Physical set of eight 4-kbytes sectors and 
  - one 224-kbytes sector at the top or bottom of address space 
with 
  - all remaining sectors of 256 kbytes. 
So even if we are able to erase eight sectors via cmd 4K and rest via 256 
kbyte(0xd8)
Then what about one sector of 224 Kbytes. 
And how we tell user about this erase pattern. 

Again, my suggestion is to disable hybrid mode (volatile) and we may revisit if 
anyone come up with different approach   
Please suggest. 

Thanks 
SuresH
 

> >
> > thanks!
> > --
> > Jagan Teki
> > Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> > Maintainer Hyderabad, India.
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Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Monday, June 12, 2017 11:37 AM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: Jagan Teki <ja...@amarulasolutions.com>; york sun <york@nxp.com>;
> u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>; Yao Yuan
> <yao.y...@nxp.com>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K
> flag
> 
> Hi Suresh,
> 
> On Thu, Jun 8, 2017 at 1:00 PM, Suresh Gupta <suresh.gu...@nxp.com> wrote:
> > 
> >> >
> >> > So best way is to disable hybrid mode and configure flash in
> >> > Uniform Sector Architecture
> >>
> >> OK, then send patches to Linux and U-Boot will review and take other
> >> suggestions too.
> >>
> >
> > Thanks Jagan,
> > I will send U-boot patches (after testing) by early next week.
> >
> > My next point :) to discuss is "32-bit address options".
> > This particular flash do not support below commands
> > /* Bank addr access commands */
> > #ifdef CONFIG_SPI_FLASH_BAR
> > # define CMD_BANKADDR_BRWR  0x17
> > # define CMD_BANKADDR_BRRD  0x16
> > # define CMD_EXTNADDR_WREAR 0xC5
> > # define CMD_EXTNADDR_RDEAR 0xC8
> > #endif
> >
> > Instead  of above S25FS512S flash support 32-bit address commands like
> > 4READ, 4P4E and many more which require 32 bit address directly pass on
> wires.
> >
> > Jagan,
> > So, Do we have any plan to fix this?
> > Yao Yuan already send one patch [1] for same.
> > I think this is a decent approach [1]. If required I will resend this patch 
> > with
> little changes.
> 
> Don't know whether you tried this or not.
> 
> - Erase bottom 4K sectors using 4K
> - Erase middle sectors using SE
> - Erase top 4K sectors using 4K

I will try all combinations and let you know the results. 

> 
> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

> >
> > So best way is to disable hybrid mode and configure flash in Uniform
> > Sector Architecture
> 
> OK, then send patches to Linux and U-Boot will review and take other
> suggestions too.
> 

Thanks Jagan,
I will send U-boot patches (after testing) by early next week. 

My next point :) to discuss is "32-bit address options".
This particular flash do not support below commands 
/* Bank addr access commands */
#ifdef CONFIG_SPI_FLASH_BAR
# define CMD_BANKADDR_BRWR  0x17
# define CMD_BANKADDR_BRRD  0x16
# define CMD_EXTNADDR_WREAR 0xC5
# define CMD_EXTNADDR_RDEAR 0xC8
#endif 

Instead  of above S25FS512S flash support 32-bit address commands like 
4READ, 4P4E and many more which require 32 bit address directly pass on wires. 

Jagan, 
So, Do we have any plan to fix this? 
Yao Yuan already send one patch [1] for same. 
I think this is a decent approach [1]. If required I will resend this patch 
with little changes.  


[1] https://patchwork.ozlabs.org/patch/676152/ 

Thanks 
SuresH

> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

> -Original Message-
> From: Jagan Teki [mailto:ja...@amarulasolutions.com]
> Sent: Wednesday, June 07, 2017 12:33 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: york sun <york@nxp.com>; Jagan Teki <jagannadh.t...@gmail.com>; u-
> b...@lists.denx.de; Jagan Teki <ja...@openedev.com>; Yao Yuan
> <yao.y...@nxp.com>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K
> flag
> 
> Hi Suresh,
> 
> This what I understood based on my previous datasheet read __attached__
> 
> In spansion S25FS-S family the physical sectors are grouped as normal and
> parameter sectors. Parameter sectors are 4kB in size with 8 set located at the
> bottom or top address of a device.
> Normal sectors are similar to other flash family with sizes of 64kB or 32 kB.
> 
> To erase whole flash using sector erase(D8h or DCh) won't effect the parameter
> sectors, so in order to erase these we must use 4K sector erase commands (20h
> or 21h) separately.
> 
> So the lower 8 4k sectors are unaffected even if we do sector erase(d8h)? What
> if we do 4k erase(20h) whole flash all effected?

Erasing flash with 4k erase(20h) do not erase the whole chip and also not able 
to erase address
Space of remaining sectors of 256 kbytes . this I tried with my experiments.

So best way is to disable hybrid mode and configure flash in Uniform Sector 
Architecture   
> 
> thanks!
> --
> Jagan Teki
> Senior Linux Kernel Engineer | Amarula Solutions U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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[U-Boot] [PATCH] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

[Suresh Gupta]

In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
Signed-off-by: Anupam Kumar <anupam.kuma...@nxp.com>
---
 drivers/spi/fsl_qspi.c | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index e61c67b..d596377 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -659,22 +659,20 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 
*txbuf, u32 len)
tx_size = (len > TX_BUFFER_SIZE) ?
TX_BUFFER_SIZE : len;
 
-   size = tx_size / 4;
-   for (i = 0; i < size; i++) {
+   size = tx_size / 16;
+   /*
+* There must be atleast 128bit data
+* available in TX FIFO for any pop operation
+*/
+   if (tx_size % 16)
+   size++;
+   for (i = 0; i < size * 4; i++) {
memcpy(, txbuf, 4);
data = qspi_endian_xchg(data);
qspi_write32(priv->flags, >tbdr, data);
txbuf += 4;
}
 
-   size = tx_size % 4;
-   if (size) {
-   data = 0;
-   memcpy(, txbuf, size);
-   data = qspi_endian_xchg(data);
-   qspi_write32(priv->flags, >tbdr, data);
-   }
-
qspi_write32(priv->flags, >ipcr,
 (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
while (qspi_read32(priv->flags, >sr) & QSPI_SR_BUSY_MASK)
-- 
1.9.3

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Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase

[Suresh Gupta]

Hi Jagan, 

As already discussed in this forum that flash "S25FS512S" have Hybrid sector 
option and to come out of this hybrid mode we required 
"spansion_s25fss_disable_4KB_erase" patch in which  we set bit 3 of 
"Configuration Register 3 Non-Volatile (CR3NV)/ Configuration Register-3 
Volatile (CR3V)".
This disable 4-kB Erase and configure flash in Uniform Sector Architecture. 

After removing this patch, we are facing issues in erasing initial sectors of 
flash. 
Please let me know what is your plan to fix this issue, Can I send patch again 
?   

Thanks 
SuresH

> -Original Message-
> From: york sun
> Sent: Friday, March 31, 2017 5:50 AM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: Mingkai Hu <mingkai...@nxp.com>; Jagan Teki
> <jagannadh.t...@gmail.com>; Jagan Teki <ja...@openedev.com>; u-
> b...@lists.denx.de
> Subject: Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase
> 
> On 03/27/2017 06:12 PM, Mingkai Hu wrote:
> >
> >> -Original Message-
> >> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> >> Sent: Tuesday, March 28, 2017 1:57 AM
> >> To: york sun <york@nxp.com>
> >> Cc: Jagan Teki <ja...@openedev.com>; u-boot@lists.denx.de; Mingkai Hu
> >> <mingkai...@nxp.com>
> >> Subject: Re: [U-Boot] sf: Remove spansion_s25fss_disable_4KB_erase
> >>
> >> On Mon, Mar 27, 2017 at 11:05 PM, york sun <york@nxp.com> wrote:
> >>> On 03/15/2017 06:44 PM, york@nxp.com wrote:
> >>>> On 01/27/2017 10:04 AM, Jagan Teki wrote:
> >>>>> On Mon, Jan 23, 2017 at 8:05 PM, york sun <york@nxp.com> wrote:
> >>>>>> On 12/12/2016 09:32 PM, Yao Yuan wrote:
> >>>>>>> Hi Jagan,
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>> Do you have any comments?
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>> Thanks for your work and you know it's important for QSPI with
> >>>>>>> S25FS512S.
> >>>>>>>
> >>>>>>>
> >>>>>>>
> >>>>>>> It seems S25FS512S can't support the SECT_4K, right?
> >>>>>>>
> >>>>>>> And it better to retain the disable_4kb, but we can add a flag
> >>>>>>> in dts to select whether enable it.
> >>>>>>>
> >>>>>>>
> >>>>>>
> >>>>>> Jagan,
> >>>>>>
> >>>>>> This is blocking me from using the board with this specific flash chip.
> >>>>>> Can you take a look? By reverting this single commit 116e005c, my
> >>>>>> board works again.
> >>>>>
> >>>>> I will try to work on this.
> >>>>>
> >>>>
> >>>> Guys,
> >>>>
> >>>> Where are we on this issue?
> >>>>
> >>>> York
> >>>>
> >>>
> >>> Can we revert this patch or have a fix?
> >>
> >> Just wanted to understand more about this, I've attached programming
> >> model in previous mail about this and based on that I've fixed with all 4K.
> >> Waiting for 'Yao Yuan' inputs on this.
> >>
> >
> > +Suresh to follow up this question.
> >
> 
> Suresh,
> 
> Can you follow up on this? This issue is blocking me from testing QSPI on
> LS1046ARDB. Even I revert this patch, I can only erase part of the flash.
> 
> York

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[U-Boot] [PATCH v3] spi: fsl_qspi: Copy 16 byte aligned data in TX FIFO

[Suresh Gupta]

In some of the QSPI controller version, there must be atleast
128bit data available in TX FIFO for any pop operation otherwise
error bit will be set. The code will not make any behavior change
for previous controller as the transfer data size in ipcr register
is still the same.

Patch is tested on LS1046A which do not require 16 bytes aligned and
LS1088A which require 16 bytes aligned data in TX FIFO

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---

Changes in v3:
- Change multi-line comment style

Changes in v2:
- Change commit message
- Add "if" condition in replace of "size += (tx_size % 16) != 0;"


 drivers/spi/fsl_qspi.c | 18 --
 1 file changed, 8 insertions(+), 10 deletions(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index e61c67b..9036795 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -659,22 +659,20 @@ static void qspi_op_write(struct fsl_qspi_priv *priv, u8 
*txbuf, u32 len)
tx_size = (len > TX_BUFFER_SIZE) ?
TX_BUFFER_SIZE : len;
 
-   size = tx_size / 4;
-   for (i = 0; i < size; i++) {
+   size = tx_size / 16;
+   /*
+* There must be atleast 128bit data
+* available in TX FIFO for any pop operation
+*/
+   if (tx_size % 16)
+   size++;
+   for (i = 0; i < size*4; i++) {
memcpy(, txbuf, 4);
data = qspi_endian_xchg(data);
qspi_write32(priv->flags, >tbdr, data);
txbuf += 4;
}
 
-   size = tx_size % 4;
-   if (size) {
-   data = 0;
-   memcpy(, txbuf, size);
-   data = qspi_endian_xchg(data);
-   qspi_write32(priv->flags, >tbdr, data);
-   }
-
qspi_write32(priv->flags, >ipcr,
 (seqid << QSPI_IPCR_SEQID_SHIFT) | tx_size);
while (qspi_read32(priv->flags, >sr) & QSPI_SR_BUSY_MASK)
-- 
1.9.3

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Re: [U-Boot] [PATCH] LS1012A: change the size of flash

[Suresh Gupta]

> -Original Message-
> From: york sun
> Sent: Tuesday, May 23, 2017 9:50 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>; u-boot@lists.denx.de
> Cc: ja...@openedev.com
> Subject: Re: [PATCH] LS1012A: change the size of flash
> 
> On 04/25/2017 02:20 AM, Suresh Gupta wrote:
> > LS1012A has S25FS512S flash of 64M size
> >
> > Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> > ---
> >  include/configs/ls1012a_common.h | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/configs/ls1012a_common.h
> > b/include/configs/ls1012a_common.h
> > index 0db926f..861cbc3 100644
> > --- a/include/configs/ls1012a_common.h
> > +++ b/include/configs/ls1012a_common.h
> > @@ -56,7 +56,7 @@
> >  #define QSPI0_AMBA_BASE0x4000
> >  #define CONFIG_SPI_FLASH_SPANSION
> >
> > -#define FSL_QSPI_FLASH_SIZE(1 << 24)
> > +#define FSL_QSPI_FLASH_SIZESZ_64M
> >  #define FSL_QSPI_FLASH_NUM 2
> >
> >  /*
> >
> 
> Suresh,
> 
> LS1012A doesn't have any flash built-in. Do you mean all boards supporting
> LS1012A have the same flash chip with 64MB in size? Please clarify.
> 
> York
York,
You are right, all boards has 64MB (S25FS512S) flash.
Sorry for confusion.

SuresH 
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Re: [U-Boot] [PATCH] LS2081ARDB: Enable CONFIG_SPI_FLASH_BAR option

[Suresh Gupta]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Friday, May 12, 2017 11:51 PM
> To: Yogesh Narayan Gaur <yogeshnarayan.g...@nxp.com>; Suresh Gupta
> <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH] LS2081ARDB: Enable CONFIG_SPI_FLASH_BAR option
> 
> On 05/11/2017 01:36 AM, Yogesh Gaur wrote:
> > On LS2081ARDB both QSPI and DSPI are having flash n25q512a of micron
> > family which supports EAR Read/Write cmds, thus enable
> CONFIG_SPI_FLASH_BAR config.
> > Else only lower 16MiB accessible for these flashes.
> >
> > Signed-off-by: Yogesh Gaur <yogeshnarayan.g...@nxp.com>
> > ---
> >  Depends on :
> >
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> >
> chwork.ozlabs.org%2Fpatch%2F755920%2F=01%7C01%7Cyork.sun%40nx
> p.co
> >
> m%7C6990807b3cc340bcf5d208d49848c6ee%7C686ea1d3bc2b4c6fa92cd99c5c
> 30163
> >
> 5%7C0=EIlAri7rShB22Yggt2juWDkBGK5PnxyO3RE9rfDEQlc%3D
> =0
> >
> >  include/configs/ls2080ardb.h | 5 +
> >  1 file changed, 5 insertions(+)
> >
> > diff --git a/include/configs/ls2080ardb.h
> > b/include/configs/ls2080ardb.h index 6abf54b..08ac9a9 100644
> > --- a/include/configs/ls2080ardb.h
> > +++ b/include/configs/ls2080ardb.h
> > @@ -299,6 +299,11 @@ unsigned long get_board_sys_clk(void);  #ifdef
> > CONFIG_FSL_QSPI  #ifdef CONFIG_TARGET_LS2081ARDB  #define
> > CONFIG_SPI_FLASH_STMICRO
> > +/*
> > + * On LS2081ARDB both QSPI and DSPI are having flash n25q512a of
> > +micron
> > + * family which supports EAR Read/Write cmds, thus enable below
> > +config  */ #define CONFIG_SPI_FLASH_BAR
> >  #else
> >  #define CONFIG_SPI_FLASH_SPANSION
> >  #endif
> >
> 
> Suresh,
> 
> Is this impacted by the same QSPI driver you are working on?
> 
> York

York,
You are right, LS2081ARDB have similar type of flashes which require 4byte 
address to access higher address. 
So required to disable CONFIG_SPI_FLASH_BAR config and add new set of commands 
and code changes. 

Thanks 
SuresH 
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Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Friday, May 12, 2017 11:23 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>; Jagan Teki
> <jagannadh.t...@gmail.com>
> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>; Yao Yuan
> <yao.y...@nxp.com>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K
> flag
> 
> On 04/27/2017 10:26 PM, Suresh Gupta wrote:
> >
> >
> >> -Original Message-
> >> From: York Sun [mailto:york@nxp.com]
> >> Sent: Thursday, April 27, 2017 10:18 PM
> >> To: Suresh Gupta <suresh.gu...@nxp.com>; Jagan Teki
> >> <jagannadh.t...@gmail.com>
> >> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>; Yao Yuan
> >> <yao.y...@nxp.com>
> >> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove
> >> SECT_4K flag
> >>
> >> On 04/26/2017 10:17 PM, Suresh Gupta wrote:
> >>>
> >>>
> >>
> >> 
> >>
> >>>>>
> >>>> Suresh,
> >>>>
> >>>> Did you test your patch after removing CONFIG_SPI_FLASH_BAR? Why
> >>>> doesn't this flash support BAR commands? How did it work before broken?
> >>>>
> >>>
> >>> York, the flash s25fs512s support 32 bit address to handle >16M
> >>> memory
> >> access.
> >>> With and without CONFIG_SPI_FLASH_BAR the u-boot only access up to
> >>> 16M of flash memory for this particular flash which is installed on
> >>> our boards
> >> (LS1012ARDB, LS1046ARDB, LS1088ARDB, LS2088ARDB).
> >>> So, anyhow we need to remove this CONFIG_SPI_FLASH_BAR from our
> >>> boards
> >> configs.
> >>>
> >>> For accessing >16M of flash memory (to support 32 bit address) I
> >>> already start discussion [2] with Jagan. Hopefully We have a
> >>> solution for that
> >> in near future.
> >>> [2] https://patchwork.ozlabs.org/patch/676152/
> >>>
> >>
> >> How did it (>16MB) work before?
> >>
> >> York
> >
> > According to me for this s25fs512s  particular flash,  >16M should not work 
> > in
> open source code.
> > If you have any commit id where it works, let me know.
> > I will try at my end and update you
> >
> 
> Suresh,
> 
> Where are we on this? The internal U-Boot has it working (previous SDK
> release). Did you check?
> 
> York
York,
It is working in internal U-boot which have set of patches which are not up 
streamed, one of which is similar to mine patch. 
Along with this, CONFIG_SPI_FLASH_BAR is disable and new flag ADDR_4B is added 
and couple of other changes.
All this is on our internal u-boot and never be working on open-source.
Yao send some of the patches to open source but are rejected by Jagan. 

So my intention is to make at least 16M memory access for this particular flash 
and then I start discussion 
with Jagan to include code to access this type of flash as we are coming with 
similar type of flashes in new platforms.   

Thanks
SuresH  

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Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Thursday, April 27, 2017 10:18 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>; Jagan Teki
> <jagannadh.t...@gmail.com>
> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>; Yao Yuan
> <yao.y...@nxp.com>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K
> flag
> 
> On 04/26/2017 10:17 PM, Suresh Gupta wrote:
> >
> >
> 
> 
> 
> >>>
> >> Suresh,
> >>
> >> Did you test your patch after removing CONFIG_SPI_FLASH_BAR? Why
> >> doesn't this flash support BAR commands? How did it work before broken?
> >>
> >
> > York, the flash s25fs512s support 32 bit address to handle >16M memory
> access.
> > With and without CONFIG_SPI_FLASH_BAR the u-boot only access up to 16M
> > of flash memory for this particular flash which is installed on our boards
> (LS1012ARDB, LS1046ARDB, LS1088ARDB, LS2088ARDB).
> > So, anyhow we need to remove this CONFIG_SPI_FLASH_BAR from our boards
> configs.
> >
> > For accessing >16M of flash memory (to support 32 bit address) I
> > already start discussion [2] with Jagan. Hopefully We have a solution for 
> > that
> in near future.
> > [2] https://patchwork.ozlabs.org/patch/676152/
> >
> 
> How did it (>16MB) work before?
> 
> York

According to me for this s25fs512s  particular flash,  >16M should not work in 
open source code. 
If you have any commit id where it works, let me know.
I will try at my end and update you 

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Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

> -Original Message-
> From: York Sun [mailto:york@nxp.com]
> Sent: Thursday, April 27, 2017 4:35 AM
> To: Suresh Gupta <suresh.gu...@nxp.com>; Jagan Teki
> <jagannadh.t...@gmail.com>
> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>; Yao Yuan
> <yao.y...@nxp.com>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K
> flag
> 
> On 04/26/2017 12:47 AM, Suresh Gupta wrote:
> >
> >
> >> -Original Message-
> >> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> >> Sent: Wednesday, April 26, 2017 1:01 PM
> >> To: Suresh Gupta <suresh.gu...@nxp.com>
> >> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>; york sun
> >> <york@nxp.com>; Yao Yuan <yao.y...@nxp.com>
> >> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove
> >> SECT_4K flag
> >>
> >> On Tue, Apr 25, 2017 at 2:51 PM, Suresh Gupta <suresh.gu...@nxp.com>
> >> wrote:
> >>> As per data sheet, S25FS512S support Uniform sector option or erase
> >>> size of 256 kbytes and Page Programming buffer of
> >>> 256 or 512 Bytes. So, flag SECT_4K have no significance for this
> >>> flash.
> >>>
> >>> Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> >>> ---
> >>>  drivers/mtd/spi/spi_flash_ids.c | 2 +-
> >>>  1 file changed, 1 insertion(+), 1 deletion(-)
> >>>
> >>> diff --git a/drivers/mtd/spi/spi_flash_ids.c
> >>> b/drivers/mtd/spi/spi_flash_ids.c index edca94e..7ca33e8 100644
> >>> --- a/drivers/mtd/spi/spi_flash_ids.c
> >>> +++ b/drivers/mtd/spi/spi_flash_ids.c
> >>> @@ -101,7 +101,7 @@ const struct spi_flash_info spi_flash_ids[] = {
> >>> {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024,   128, 
> >>> RD_FULL
> |
> >> WR_QPP) },
> >>> {"s25fl256s_64k",  INFO(0x010219, 0x4d01,  64 * 1024,   512, 
> >>> RD_FULL
> |
> >> WR_QPP) },
> >>> {"s25fs256s_64k",  INFO6(0x010219, 0x4d0181, 64 * 1024, 512,
> >>> RD_FULL
> >> | WR_QPP | SECT_4K) },
> >>> -   {"s25fs512s",  INFO6(0x010220, 0x4d0081, 128 * 1024, 512, 
> >>> RD_FULL
> |
> >> WR_QPP | SECT_4K) },
> >>> +   {"s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256,
> RD_FULL |
> >> WR_QPP) },
> >>
> >> Did you verify this? because we have an issue about this part
> >> number[1]
> >>
> >> [1] https://lists.denx.de/pipermail/u-boot/2016-December/276032.html
> >>
> >
> > I tested this patch on LS1012ARDB, LS1046ARDB and Ls1088ARDB boards
> having same flash.
> > I do aware of [1] but as per my testing all works fine with erase size of 
> > 256
> and block size of 256/512.
> >
> > As per datasheet,  [http://www.cypress.com/file/216376/download] also
> > mention below, The uniform erase blocks are 256. So anyhow we required this
> patch even we need to disable 4KB erase.
> >
> > Erase
> > – Hybrid sector option
> > – Physical set of eight 4-kbytes sectors and one 224-kbytes sector at
> > the top or bottom of address space with all remaining sectors of 256
> > kbytes – Uniform sector option – Uniform 256 kbyte blocks
> >
> Suresh,
> 
> Did you test your patch after removing CONFIG_SPI_FLASH_BAR? Why doesn't
> this flash support BAR commands? How did it work before broken?
> 

York, the flash s25fs512s support 32 bit address to handle >16M memory access. 
With and without CONFIG_SPI_FLASH_BAR the u-boot only access up to 16M of flash 
memory 
for this particular flash which is installed on our boards (LS1012ARDB, 
LS1046ARDB, LS1088ARDB, LS2088ARDB). 
So, anyhow we need to remove this CONFIG_SPI_FLASH_BAR from our boards configs. 

For accessing >16M of flash memory (to support 32 bit address) I already start 
discussion [2] with Jagan. Hopefully 
We have a solution for that in near future.  
[2] https://patchwork.ozlabs.org/patch/676152/

Thanks 
SuresH

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Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

> -Original Message-
> From: Jagan Teki [mailto:jagannadh.t...@gmail.com]
> Sent: Wednesday, April 26, 2017 1:01 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de; Jagan Teki <ja...@openedev.com>; york sun
> <york@nxp.com>; Yao Yuan <yao.y...@nxp.com>
> Subject: Re: [U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K
> flag
> 
> On Tue, Apr 25, 2017 at 2:51 PM, Suresh Gupta <suresh.gu...@nxp.com>
> wrote:
> > As per data sheet, S25FS512S support Uniform sector option or erase
> > size of 256 kbytes and Page Programming buffer of
> > 256 or 512 Bytes. So, flag SECT_4K have no significance for this
> > flash.
> >
> > Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
> > ---
> >  drivers/mtd/spi/spi_flash_ids.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/mtd/spi/spi_flash_ids.c
> > b/drivers/mtd/spi/spi_flash_ids.c index edca94e..7ca33e8 100644
> > --- a/drivers/mtd/spi/spi_flash_ids.c
> > +++ b/drivers/mtd/spi/spi_flash_ids.c
> > @@ -101,7 +101,7 @@ const struct spi_flash_info spi_flash_ids[] = {
> > {"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024,   128, 
> > RD_FULL |
> WR_QPP) },
> > {"s25fl256s_64k",  INFO(0x010219, 0x4d01,  64 * 1024,   512, 
> > RD_FULL |
> WR_QPP) },
> > {"s25fs256s_64k",  INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL
> | WR_QPP | SECT_4K) },
> > -   {"s25fs512s",  INFO6(0x010220, 0x4d0081, 128 * 1024, 512, 
> > RD_FULL |
> WR_QPP | SECT_4K) },
> > +   {"s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256, 
> > RD_FULL |
> WR_QPP) },
> 
> Did you verify this? because we have an issue about this part number[1]
> 
> [1] https://lists.denx.de/pipermail/u-boot/2016-December/276032.html
> 

I tested this patch on LS1012ARDB, LS1046ARDB and Ls1088ARDB boards having same 
flash. 
I do aware of [1] but as per my testing all works fine with erase size of 256  
and block size of 256/512.

As per datasheet,  [http://www.cypress.com/file/216376/download] also mention 
below, 
The uniform erase blocks are 256. So anyhow we required this patch even we need 
to disable 4KB erase. 

Erase
– Hybrid sector option
– Physical set of eight 4-kbytes sectors and one
224-kbytes sector at the top or bottom of address
space with all remaining sectors of 256 kbytes
– Uniform sector option
– Uniform 256 kbyte blocks

> thanks!
> --
> Jagan Teki
> Free Software Engineer | www.openedev.com U-Boot, Linux | Upstream
> Maintainer Hyderabad, India.
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[U-Boot] [PATCH] LS1012A: change the size of flash

[Suresh Gupta]

LS1012A has S25FS512S flash of 64M size

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
 include/configs/ls1012a_common.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h
index 0db926f..861cbc3 100644
--- a/include/configs/ls1012a_common.h
+++ b/include/configs/ls1012a_common.h
@@ -56,7 +56,7 @@
 #define QSPI0_AMBA_BASE0x4000
 #define CONFIG_SPI_FLASH_SPANSION
 
-#define FSL_QSPI_FLASH_SIZE(1 << 24)
+#define FSL_QSPI_FLASH_SIZESZ_64M
 #define FSL_QSPI_FLASH_NUM 2
 
 /*
-- 
1.9.3

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[U-Boot] [PATCH] sf: Fix s25fs512s erase size and remove SECT_4K flag

[Suresh Gupta]

As per data sheet, S25FS512S support Uniform sector option
or erase size of 256 kbytes and Page Programming buffer of
256 or 512 Bytes. So, flag SECT_4K have no significance
for this flash.

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
 drivers/mtd/spi/spi_flash_ids.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index edca94e..7ca33e8 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -101,7 +101,7 @@ const struct spi_flash_info spi_flash_ids[] = {
{"s25fl256s_256k", INFO(0x010219, 0x4d00, 256 * 1024,   128, RD_FULL | 
WR_QPP) },
{"s25fl256s_64k",  INFO(0x010219, 0x4d01,  64 * 1024,   512, RD_FULL | 
WR_QPP) },
{"s25fs256s_64k",  INFO6(0x010219, 0x4d0181, 64 * 1024, 512, RD_FULL | 
WR_QPP | SECT_4K) },
-   {"s25fs512s",  INFO6(0x010220, 0x4d0081, 128 * 1024, 512, RD_FULL | 
WR_QPP | SECT_4K) },
+   {"s25fs512s",  INFO6(0x010220, 0x4d0081, 256 * 1024, 256, RD_FULL | 
WR_QPP) },
{"s25fl512s_256k", INFO(0x010220, 0x4d00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
{"s25fl512s_64k",  INFO(0x010220, 0x4d01,  64 * 1024,  1024, RD_FULL | 
WR_QPP) },
{"s25fl512s_512k", INFO(0x010220, 0x4f00, 256 * 1024,   256, RD_FULL | 
WR_QPP) },
-- 
1.9.3

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Re: [U-Boot] [PATCH v1 1/4] sf: add ADDR_4B for 4byte address support

[Suresh Gupta]

Hello Jagan, 

[snip]

> >
> > Sorry for the late, It's better to not relay on specific flash and do
> > the 4-byte addressing. So, I've sent some patches based on this [1]
> > and will send the next version to wind-up all these changes. Please wait 
> > some
> time.
> >

Any update on supporting 4-byte addressing for flash with size of 16M+


> 
> Hi Jagan,
> 
> May I know is there any update for those 4-bytes addressing support in uboot?
> If your patch is ready, Can I get the patch set and then working for my QSPI 
> 64M
> flash support?
> 
> I think it will be very helpful.
> The 64MB flash support for our QSPI is very needed.
> 
> Thanks.
> 
> Yao.
> 
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Re: [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007

[Suresh Gupta]

OK York, will send new patch.. 

> -Original Message-
> From: york sun
> Sent: Tuesday, February 28, 2017 9:56 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de; Scott Wood <scott.w...@nxp.com>; Leo Li
> <leoyang...@nxp.com>; Sriram Dash <sriram.d...@nxp.com>; Rajesh Bhagat
> <rajesh.bha...@nxp.com>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
> 
> On 02/28/2017 02:52 AM, Suresh Gupta wrote:
> >
> >
> >> -Original Message-
> >> From: york sun
> >> Sent: Friday, February 24, 2017 10:31 PM
> >> To: Suresh Gupta <suresh.gu...@nxp.com>
> >> Cc: u-boot@lists.denx.de; Scott Wood <scott.w...@nxp.com>; Leo Li
> >> <leoyang...@nxp.com>; Sriram Dash <sriram.d...@nxp.com>; Rajesh
> >> Bhagat <rajesh.bha...@nxp.com>
> >> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum
> >> A-009007
> >>
> >> On 02/23/2017 11:19 PM, Suresh Gupta wrote:
> >>> Hi York,
> >>>
> >>> It is not good idea to change the values of all macro at this time
> >>> as the code
> >> tested on different platforms.
> >>
> >> I am not talking about any value change. You are using writew. Why
> >> not using
> >> out_be16 as you thought?
> >
> > For now all values in macro (like USB_PHY_RX_EQ_VAL_2) are swapped and
> > if I want to use out_be16, then I need to change values of all macros,
> > which intern require testing on all platform.
> > That's the reason, I don't want to make such changes and break the
> > working USB
> >
> 
> Suresh,
> 
> This erratum only applies to LS1043A, LS1046A, LS2080A. It wouldn't be too
> much trouble to verify all of them. I'd rather we do it right at the first 
> place than
> coming back to fix it. Are you in a rush to get this patch out?
> 
> Another thing, please drop defined(CONFIG_ARCH_LS2085A) for all the patches.
> We only use CONFIG_ARCH_LS2080A.
> 
> York
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Re: [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007

[Suresh Gupta]

> -Original Message-
> From: york sun
> Sent: Friday, February 24, 2017 10:31 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de; Scott Wood <scott.w...@nxp.com>; Leo Li
> <leoyang...@nxp.com>; Sriram Dash <sriram.d...@nxp.com>; Rajesh Bhagat
> <rajesh.bha...@nxp.com>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
> 
> On 02/23/2017 11:19 PM, Suresh Gupta wrote:
> > Hi York,
> >
> > It is not good idea to change the values of all macro at this time as the 
> > code
> tested on different platforms.
> 
> I am not talking about any value change. You are using writew. Why not using
> out_be16 as you thought?

For now all values in macro (like USB_PHY_RX_EQ_VAL_2) are swapped and
if I want to use out_be16, then I need to change values of all macros,
which intern require testing on all platform. 
That's the reason, I don't want to make such changes and break the working USB 
 
> 
> York
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Re: [U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007

[Suresh Gupta]

Hi York, 

It is not good idea to change the values of all macro at this time as the code 
tested on different platforms.
If required, I will remove the TODO statement. 

What you say. 

Thanks 
SuresH   

> -Original Message-
> From: york sun
> Sent: Thursday, February 23, 2017 11:18 PM
> To: Suresh Gupta <suresh.gu...@nxp.com>
> Cc: u-boot@lists.denx.de; Scott Wood <scott.w...@nxp.com>; Leo Li
> <leoyang...@nxp.com>; Sriram Dash <sriram.d...@nxp.com>; Rajesh Bhagat
> <rajesh.bha...@nxp.com>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
> 
> On 02/16/2017 01:12 PM, mailto:york@nxp.com wrote:
> > On 02/03/2017 06:08 AM, Suresh Gupta wrote:
> 
> 
> 
> >> +static void erratum_a009007(void)
> >> +{
> >> +/* TODO:implement the out_be16 instead of writew which is taking
> >> +little endian style */
> >
> > Did you mean to remind yourself to finish this before sending this
> > patch? You know we already have out_be16(), don't you?
> >
> 
> Suresh,
> 
> Are you going to send an update?
> 
> York
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[U-Boot] [PATCH v2 0/2] Add support for only one CS in fsl Quad SPI

[Suresh Gupta]

SOC’s like LS1012A has only one chip select signal out to connect
with flash and the 64M flash is attached to it. On boards the same
CS is connected to different flash via mux.
So at one time only one flash is active and it is not possible to
scan other flash at run time.  

Suresh Gupta (2):
  spi: fsl_qspi: Add support for one chip select
  armv8: dts: fsl-ls1012a: Change number of CS in SPI node

 arch/arm/dts/fsl-ls1012a.dtsi | 2 +-
 drivers/spi/fsl_qspi.c| 5 -
 2 files changed, 5 insertions(+), 2 deletions(-)

-- 
1.9.3

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[U-Boot] [PATCH v2 1/2] spi: fsl_qspi: Add support for one chip select

[Suresh Gupta]

SOC’s like LS1012A has only one chip select signal
out to connect with flash. So at one time only one
flash is active and it is not possible to scan other
flash at run time.

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
 drivers/spi/fsl_qspi.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/fsl_qspi.c b/drivers/spi/fsl_qspi.c
index b2a0583..e61c67b 100644
--- a/drivers/spi/fsl_qspi.c
+++ b/drivers/spi/fsl_qspi.c
@@ -1037,8 +1037,11 @@ static int fsl_qspi_probe(struct udevice *bus)
 * setting the size of these devices to 0.  This would ensure
 * that the complete memory map is assigned to only one flash device.
 */
-   qspi_write32(priv->flags, >regs->sfa1ad, priv->amba_base[1]);
+   qspi_write32(priv->flags, >regs->sfa1ad,
+priv->amba_base[0] + amba_size_per_chip);
switch (priv->num_chipselect) {
+   case 1:
+   break;
case 2:
qspi_write32(priv->flags, >regs->sfa2ad,
 priv->amba_base[1]);
-- 
1.9.3

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[U-Boot] [PATCH v2 2/2] armv8: dts: fsl-ls1012a: Change number of CS in SPI node

[Suresh Gupta]

LS1012A has only one chip select signal out to
connect with flash

Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
 arch/arm/dts/fsl-ls1012a.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index ed5ea54..23b3cec 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -114,7 +114,7 @@
reg = <0x0 0x155 0x0 0x1>,
<0x0 0x4000 0x0 0x400>;
reg-names = "QuadSPI", "QuadSPI-memory";
-   num-cs = <2>;
+   num-cs = <1>;
big-endian;
status = "disabled";
};
-- 
1.9.3

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[U-Boot] [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007

[Suresh Gupta]

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.
Changes in v3:
Change CONFIG_XXX to CONFIG_ARCH_XXX


 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 42 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  9 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  9 +
 4 files changed, 66 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index d5d6040..a27e310 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -25,6 +25,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -46,6 +47,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -77,6 +79,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
 
@@ -167,6 +170,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index c56cb72..9aab8a7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -120,6 +120,46 @@ static void erratum_a008997(void)
 #endif
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
+static void erratum_a009007(void)
+{
+/* TODO:implement the out_be16 instead of writew which is taking
+little endian style */
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+   void __iomem *usb_phy = (void __iomem *)USB_PHY1;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (void __iomem *)USB_PHY2;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (void __iomem *)USB_PHY3;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+   void __iomem *dcsr = (void __iomem *)DCSR_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1,
+  dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_1,
+  dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
 
 #if defined(CONFIG_FSL_LSCH3)
 /*
@@ -266,6 +306,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009008();
  

[U-Boot] [PATCH v3 6/8] armv7: Add workaround for USB erratum A-009798

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None
Changes in v3: None

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 10 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 9578e85..7e12565 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -54,6 +55,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index ee27b0c..7ae5b29 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 void s_init(void)
 {
 }
@@ -158,6 +167,7 @@ int arch_soc_init(void)
 
/* Erratum */
erratum_a009008();
+   erratum_a009798();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 6ea8c4b..8cafa07 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,7 @@ struct ccsr_gur {
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v3 8/8] armv7: Add workaround for USB erratum A-009007

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.
Changes in v3: None 

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index cbd4ab6..554b57b 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -62,6 +63,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 3d6cc5f..edb64d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+   void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c0e4372..9c4c926 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,10 +182,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI0x0024
 #define USB_PHY_LEVEL_OVRD_IN  0x002a
 #define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
+#define USB_PHY_RX_EQ_VAL_10x
+#define USB_PHY_RX_EQ_VAL_20x8000
+#define USB_PHY_RX_EQ_VAL_30x8004
+#define USB_PHY_RX_EQ_VAL_40x800C
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v3 2/8] armv8: Add workaround for USB erratum A-009798

[Suresh Gupta]

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig   |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h   |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h   |  1 +
 4 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index cceecf0..28a0015 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -23,6 +23,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -42,6 +43,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -71,6 +73,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
 
@@ -155,6 +158,9 @@ config SYS_FSL_ERRATUM_A010539
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1f460d7..8d86985 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -75,6 +75,25 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+   val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -218,6 +237,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+   erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -486,6 +506,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+   erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 62d7046..8bd40e8 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -342,6 +342,7 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR_USB2   0x07C
 #define SCFG_USB3PRM1CR_USB3   0x088
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index c23c317..3537ecb 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layer

[U-Boot] [PATCH v3 1/8] armv8: Add workaround for USB erratum A-009008

[Suresh Gupta]

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 25 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 4 files changed, 38 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 47897f4..cceecf0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -22,6 +22,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -40,6 +41,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -68,6 +70,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
+   select SYS_FSL_ERRATUM_A009008
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
 
@@ -149,6 +152,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 9489f85..1f460d7 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -52,6 +52,29 @@ bool soc_has_aiop(void)
return false;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -194,6 +217,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+   erratum_a009008();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -461,6 +485,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+   erratum_a009008();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8ad199f..62d7046 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -337,6 +337,12 @@ struct ccsr_gur {
 #define SCFG_USBPWRFAULT_USB2_SHIFT2
 #define SCFG_USBPWRFAULT_USB1_SHIFT0
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM1CR_USB3   0x088
+#define USB_TXVREFTUNE 0x9
+
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
diff --git a/

[U-Boot] [PATCH v3 0/8] Add workaround for USB PHY errata

[Suresh Gupta]

The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY

Suresh Gupta (8):
  armv8: Add workaround for USB erratum A-009008
  armv8: Add workaround for USB erratum A-009798
  armv8: Add workaround for USB erratum A-008997
  armv8: Add workaround for USB erratum A-009007
  armv7: Add workaround for USB erratum A-009008
  armv7: Add workaround for USB erratum A-009798
  armv7: Add workaround for USB erratum A-008997
  armv7: Add workaround for USB erratum A-009007

 arch/arm/cpu/armv7/ls102xa/Kconfig |  16 +++
 arch/arm/cpu/armv7/ls102xa/soc.c   |  51 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  24 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 117 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  20 
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  13 +++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h  |  19 
 7 files changed, 260 insertions(+)

-- 
1.9.3

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[U-Boot] [PATCH v3 7/8] armv7: Add workaround for USB erratum A-008997

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change settings required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.

Changes in v3: None

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 16 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  9 +
 3 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 7e12565..cbd4ab6 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -58,6 +59,9 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
+config SYS_FSL_ERRATUM_A008997
+   bool "Workaround for USB PHY erratum A008997"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 7ae5b29..3d6cc5f 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+   void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+  usb_phy + USB_PHY_TX_OVRD_DRV_LO);
+   writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+  usb_phy + USB_PHY_MPLL_OVRD_IN_HI);
+   writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+  usb_phy + USB_PHY_LEVEL_OVRD_IN);
+   writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+  usb_phy + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 void s_init(void)
 {
 }
@@ -168,6 +183,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 8cafa07..c0e4372 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,15 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PHY_BASE   0x0851
+#define USB_PHY_TX_OVRD_DRV_LO 0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI0x0024
+#define USB_PHY_LEVEL_OVRD_IN  0x002a
+#define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v3 3/8] armv8: Add workaround for USB erratum A-008997

[Suresh Gupta]

Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change settings required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None
Changes in V3: Change CONFIG_XXX to CONFIG_ARCH_XXX

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 29 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 41 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 28a0015..d5d6040 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -24,6 +24,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select ARCH_EARLY_INIT_R
@@ -44,6 +45,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
select ARCH_EARLY_INIT_R
@@ -74,6 +76,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
 
@@ -161,6 +164,9 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
+config SYS_FSL_ERRATUM_A008997
+   bool "Workaround for USB PHY erratum A008997"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 8d86985..c56cb72 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -94,6 +94,33 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG__ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -238,6 +265,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -507,6 +535,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a010539();
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 8bd40e8..2e52078 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -339,10 +339,14 @@ struct ccsr_gur {
 
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM2CR_USB1   0x074
 #define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM2CR_USB2   0x080
 #define SCFG_USB3PRM1CR_USB3   0x088
+#define SCFG_USB3PRM2CR_USB3   0x08c
 #define USB_TXVREFTUNE   

[U-Boot] [PATCH v3 5/8] armv7: Add workaround for USB erratum A-009008

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None
Changes in v3: None

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 13 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index b61f3cd..9578e85 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -50,6 +51,9 @@ config SECURE_BOOT
 config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8..ee27b0c 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void)
return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 void s_init(void)
 {
 }
@@ -146,6 +156,9 @@ int arch_soc_init(void)
 */
out_be32(>eddrtqcfg, 0x63b20042);
 
+   /* Erratum */
+   erratum_a009008();
+
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..6ea8c4b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@ struct ccsr_gur {
 #define SCFG_PMCINTECR_ETSECERRG1  0x0004
 #define SCFG_CLUSTERPMCR_WFIL2EN   0x8000
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR0x070
+#define USB_TXVREFTUNE 0x9
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u32 dpslpcr;
-- 
1.9.3

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[U-Boot] [PATCH v2 5/8] armv7: Add workaround for USB erratum A-009008

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 13 +
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 9ffb90e..40c6782 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -42,6 +43,9 @@ config SECURE_BOOT
 config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8..ee27b0c 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void)
return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 void s_init(void)
 {
 }
@@ -146,6 +156,9 @@ int arch_soc_init(void)
 */
out_be32(>eddrtqcfg, 0x63b20042);
 
+   /* Erratum */
+   erratum_a009008();
+
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..6ea8c4b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@ struct ccsr_gur {
 #define SCFG_PMCINTECR_ETSECERRG1  0x0004
 #define SCFG_CLUSTERPMCR_WFIL2EN   0x8000
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR0x070
+#define USB_TXVREFTUNE 0x9
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u32 dpslpcr;
-- 
1.9.3

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[U-Boot] [PATCH v2 4/8] armv8: Add workaround for USB erratum A-009007

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 42 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  9 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  9 +
 4 files changed, 66 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 537d721..935a3c1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -21,6 +21,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
 
@@ -39,6 +40,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
 
@@ -67,6 +69,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
 
 config FSL_LSCH2
bool
@@ -120,6 +123,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d01b957..49181c8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -120,6 +120,46 @@ static void erratum_a008997(void)
 #endif
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
+static void erratum_a009007(void)
+{
+/* TODO:implement the out_be16 instead of writew which is taking
+little endian style */
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   void __iomem *usb_phy = (void __iomem *)USB_PHY1;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (void __iomem *)USB_PHY2;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (void __iomem *)USB_PHY3;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   void __iomem *dcsr = (void __iomem *)DCSR_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1,
+  dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  dcsr + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_1,
+  dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  dcsr + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
 
 #if defined(CONFIG_FSL_LSCH3)
 /*
@@ -266,6 +306,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secur

[U-Boot] [PATCH v2 0/8] Add workaround for USB PHY errata

[Suresh Gupta]

The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY

Suresh Gupta (8):
  armv8: Add workaround for USB erratum A-009008
  armv8: Add workaround for USB erratum A-009798
  armv8: Add workaround for USB erratum A-008997
  armv8: Add workaround for USB erratum A-009007
  armv7: Add workaround for USB erratum A-009008
  armv7: Add workaround for USB erratum A-009798
  armv7: Add workaround for USB erratum A-008997
  armv7: Add workaround for USB erratum A-009007

 arch/arm/cpu/armv7/ls102xa/Kconfig |  16 +++
 arch/arm/cpu/armv7/ls102xa/soc.c   |  51 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  24 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 117 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  20 
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  13 +++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h  |  19 
 7 files changed, 260 insertions(+)

-- 
1.9.3

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[U-Boot] [PATCH v2 8/8] armv7: Add workaround for USB erratum A-009007

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index a68674f..b7d785e 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -54,6 +55,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 3d6cc5f..edb64d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+   void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c0e4372..9c4c926 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,10 +182,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI0x0024
 #define USB_PHY_LEVEL_OVRD_IN  0x002a
 #define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
+#define USB_PHY_RX_EQ_VAL_10x
+#define USB_PHY_RX_EQ_VAL_20x8000
+#define USB_PHY_RX_EQ_VAL_30x8004
+#define USB_PHY_RX_EQ_VAL_40x800C
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v2 2/8] armv8: Add workaround for USB erratum A-009798

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig   |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h   |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h   |  1 +
 4 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 666a3d1..10daaa2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -19,6 +19,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
 
@@ -35,6 +36,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
 
@@ -61,6 +63,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config FSL_LSCH2
bool
@@ -108,6 +111,9 @@ config SYS_FSL_ERRATUM_A010539
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 951ccba..910f345 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -75,6 +75,25 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+   val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -218,6 +237,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+   erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -395,6 +415,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+   erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index fe37bc1..ca4a31fe 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -341,6 +341,7 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR_USB2   0x07C
 #define SCFG_USB3PRM1CR_USB3   0x088
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 9aad471..d726256 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -138,6 +138,7 @@
 #define SCFG_USB3PRM1CR0x000
 #define SCFG_USB3PRM1CR

[U-Boot] [PATCH v2 8/8] armv7: Add workaround for USB erratum A-009007

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index a68674f..b7d785e 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -54,6 +55,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 3d6cc5f..edb64d5 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+   void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, usb_phy + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c0e4372..9c4c926 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,10 +182,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI0x0024
 #define USB_PHY_LEVEL_OVRD_IN  0x002a
 #define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
+#define USB_PHY_RX_EQ_VAL_10x
+#define USB_PHY_RX_EQ_VAL_20x8000
+#define USB_PHY_RX_EQ_VAL_30x8004
+#define USB_PHY_RX_EQ_VAL_40x800C
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v2 6/8] armv7: Add workaround for USB erratum A-009798

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 10 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 40c6782..b7e6e96 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -46,6 +47,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index ee27b0c..7ae5b29 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 void s_init(void)
 {
 }
@@ -158,6 +167,7 @@ int arch_soc_init(void)
 
/* Erratum */
erratum_a009008();
+   erratum_a009798();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 6ea8c4b..8cafa07 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,7 @@ struct ccsr_gur {
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v2 7/8] armv7: Add workaround for USB erratum A-008997

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change settings required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2:
Clean up the code after Scott comments, 
Previously in v1, we was defining the pointer as u32,
then casting it to u8, and then passing it to
a 16-bit accessor.

 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 16 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  9 +
 3 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index b7e6e96..a68674f 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -50,6 +51,9 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
+config SYS_FSL_ERRATUM_A008997
+   bool "Workaround for USB PHY erratum A008997"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 7ae5b29..3d6cc5f 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+   void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+  usb_phy + USB_PHY_TX_OVRD_DRV_LO);
+   writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+  usb_phy + USB_PHY_MPLL_OVRD_IN_HI);
+   writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+  usb_phy + USB_PHY_LEVEL_OVRD_IN);
+   writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+  usb_phy + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 void s_init(void)
 {
 }
@@ -168,6 +183,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 
return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 8cafa07..c0e4372 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,15 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PHY_BASE   0x0851
+#define USB_PHY_TX_OVRD_DRV_LO 0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI0x0024
+#define USB_PHY_LEVEL_OVRD_IN  0x002a
+#define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v2 2/8] armv8: Add workaround for USB erratum A-009798

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig   |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h   |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h   |  1 +
 4 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 666a3d1..10daaa2 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -19,6 +19,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
 
@@ -35,6 +36,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
 
@@ -61,6 +63,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config FSL_LSCH2
bool
@@ -108,6 +111,9 @@ config SYS_FSL_ERRATUM_A010539
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 951ccba..910f345 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -75,6 +75,25 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+   val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -218,6 +237,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+   erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -395,6 +415,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+   erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index fe37bc1..ca4a31fe 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -341,6 +341,7 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR_USB2   0x07C
 #define SCFG_USB3PRM1CR_USB3   0x088
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 9aad471..d726256 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -138,6 +138,7 @@
 #define SCFG_USB3PRM1CR0x000
 #define SCFG_USB3PRM1CR

[U-Boot] [PATCH v2 1/8] armv8: Add workaround for USB erratum A-009008

[Suresh Gupta]

From: Suresh Gupta <suresh.gu...@freescale.com>

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.gu...@nxp.com>
---
Changes in v2: None

 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 25 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 4 files changed, 38 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index de0b580..666a3d1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -18,6 +18,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
 
@@ -33,6 +34,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
select SYS_FSL_HAS_DDR4
select SYS_FSL_SRDS_2
 
@@ -58,6 +60,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009803
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010165
+   select SYS_FSL_ERRATUM_A009008
 
 config FSL_LSCH2
bool
@@ -102,6 +105,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 2f54625..951ccba 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -52,6 +52,29 @@ bool soc_has_aiop(void)
return false;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 #if defined(CONFIG_FSL_LSCH3)
 /*
  * This erratum requires setting a value to eddrtqcr1 to
@@ -194,6 +217,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+   erratum_a009008();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -370,6 +394,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+   erratum_a009008();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b3cfd89..fe37bc1 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -336,6 +336,12 @@ struct ccsr_gur {
 #define SCFG_USBPWRFAULT_USB2_SHIFT2
 #define SCFG_USBPWRFAULT_USB1_SHIFT0
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM1CR_USB3   0x088
+#define USB_TXVREFTUNE 0x9
+
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h

[U-Boot] [PATCH] Add workaround for USB PHY errata

[Suresh Gupta]

The patch set implement USB PHY errata workaround which are
required for LS series of freescale platforms which have
Synopsis UTMI PHY

Suresh Gupta (8):
  armv8: Add workaround for USB erratum A-009008
  armv8: Add workaround for USB erratum A-009798
  armv8: Add workaround for USB erratum A-008997
  armv8: Add workaround for USB erratum A-009007
  armv7: Add workaround for USB erratum A-009008
  armv7: Add workaround for USB erratum A-009798
  armv7: Add workaround for USB erratum A-008997
  armv7: Add workaround for USB erratum A-009007

 arch/arm/cpu/armv7/ls102xa/Kconfig |  16 +++
 arch/arm/cpu/armv7/ls102xa/soc.c   |  50 +
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  24 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 118 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  20 
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  12 +++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h  |  19 
 7 files changed, 259 insertions(+)

-- 
1.9.3

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[U-Boot] [PATCH] armv7: Add workaround for USB erratum A-008997

[Suresh Gupta]

Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change settings required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 16 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  9 +
 3 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index f816ed1..d8a8257 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -7,6 +7,7 @@ config ARCH_LS1021A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -39,6 +40,9 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
+config SYS_FSL_ERRATUM_A008997
+   bool "Workaround for USB PHY erratum A008997"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 2e64708..19eb361 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -79,6 +79,21 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+   u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_TX_OVRD_DRV_LO_VAL,
+  (u8 *)(usb_phy) + USB_PHY_TX_OVRD_DRV_LO);
+   writew(USB_PHY_MPLL_OVRD_IN_HI_VAL,
+  (u8 *)(usb_phy) + USB_PHY_MPLL_OVRD_IN_HI);
+   writew(USB_PHY_LEVEL_OVRD_IN_VAL,
+  (u8 *)(usb_phy) + USB_PHY_LEVEL_OVRD_IN);
+   writew(USB_PHY_TX_OVRD_IN_HI_VAL,
+  (u8 *)(usb_phy) + USB_PHY_TX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 void s_init(void)
 {
 }
@@ -168,6 +183,7 @@ int arch_soc_init(void)
/* Erratum */
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 8cafa07..c0e4372 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -177,6 +177,15 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PHY_BASE   0x0851
+#define USB_PHY_TX_OVRD_DRV_LO 0x2004
+#define USB_PHY_MPLL_OVRD_IN_HI0x0024
+#define USB_PHY_LEVEL_OVRD_IN  0x002a
+#define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
+#define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
+#define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
+#define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009798

[Suresh Gupta]

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receiver
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig   |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c | 21 +
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h   |  1 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h   |  1 +
 4 files changed, 29 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index ec3e50d..c62958e 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -13,6 +13,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config ARCH_LS1046A
bool
@@ -23,6 +24,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config ARCH_LS2080A
bool
@@ -33,6 +35,7 @@ config ARCH_LS2080A
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 config FSL_LSCH2
bool
@@ -59,6 +62,9 @@ config SYS_FSL_ERRATUM_A010539
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 88cced1..6b18252 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -49,6 +49,25 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4 , val & USB_SQRXTUNE);
+   val = gur_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4 , val & USB_SQRXTUNE);
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4 , val & USB_SQRXTUNE);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -215,6 +234,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008514();
erratum_a008336();
erratum_a009008();
+   erratum_a009798();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -392,6 +412,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009660();
erratum_a010539();
erratum_a009008();
+   erratum_a009798();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b8c9926..b72d47a 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -340,6 +340,7 @@ struct ccsr_gur {
 #define SCFG_USB3PRM1CR_USB2   0x07C
 #define SCFG_USB3PRM1CR_USB3   0x088
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 3683b39..a4bc036 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -135,6 +135,7 @@
 #define SCFG_USB3PRM1CR0x000
 #define SCFG_USB3PRM1CR_INIT   0x27672b2a
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 #define SCFG_QSPICLKCTLR   0x10
 
 #define TP_ITYP_AV 0x0001  /* Initiator available */
-- 
1.9.3

[U-Boot] [PATCH] armv8: Add workaround for USB erratum A-008997

[Suresh Gupta]

Low Frequency Periodic Signaling (LFPS) Peak-to-Peak Differential
Output Voltage Test Compliance fails using default transmitter settings

Change settings required for transmitter signal swings to pass
compliance tests.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 29 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  4 +++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  2 ++
 4 files changed, 41 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index c62958e..a2f3237 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -14,6 +14,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
 
 config ARCH_LS1046A
bool
@@ -25,6 +26,7 @@ config ARCH_LS1046A
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
 
 config ARCH_LS2080A
bool
@@ -36,6 +38,7 @@ config ARCH_LS2080A
select SYS_FSL_SRDS_2
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
+   select SYS_FSL_ERRATUM_A008997
 
 config FSL_LSCH2
bool
@@ -65,6 +68,9 @@ config SYS_FSL_ERRATUM_A009008
 config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
 
+config SYS_FSL_ERRATUM_A008997
+   bool "Workaround for USB PHY erratum A008997"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 6b18252..1d0354d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -68,6 +68,33 @@ static void erratum_a009798(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
 }
 
+static void erratum_a008997(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A008997
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB1 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB1 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB2 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB2 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+   val = scfg_in32(scfg + SCFG_USB3PRM2CR_USB3 / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR_USB3 / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM2CR / 4);
+   val &= ~(0x7F << 9);
+   scfg_out32(scfg + SCFG_USB3PRM2CR / 4,
+  val | (USB_PCSTXSWINGFULL << 9));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -235,6 +262,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a008336();
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -413,6 +441,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a010539();
erratum_a009008();
erratum_a009798();
+   erratum_a008997();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index b72d47a..a7e36cd 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -337,10 +337,14 @@ struct ccsr_gur {
 
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM2CR_USB1   0x074
 #define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM2CR_USB2   0x080
 #define SCFG_USB3PRM1CR_USB3   0x088
+#define SCFG_USB3PRM2CR_USB3   0x08c
 #define USB_TXVREFTUNE 0x9
 #define USB_SQRXTUNE   0xFC7F
+#define USB_PCSTXSWINGFULL 0x47
 
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index a4bc036..cdc08ed 100644
--- 

[U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009008

[Suresh Gupta]

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same value.

Signed-off-by: Sriram Dash 
---
 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  4 
 3 files changed, 20 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 28bf778..9f0188a 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -5,6 +5,7 @@ config ARCH_LS1021A
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
+   select SYS_FSL_ERRATUM_A009008
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -31,6 +32,9 @@ config NUM_DDR_CONTROLLERS
 config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 52fb6f8..c54daee 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -60,6 +60,16 @@ unsigned int get_soc_major_rev(void)
return major;
 }
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 void s_init(void)
 {
 }
@@ -146,6 +156,8 @@ int arch_soc_init(void)
 */
out_be32(>eddrtqcfg, 0x63b20042);
 
+   /* Erratum */
+   erratum_a009008();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c34fd63..6ea8c4b 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -173,6 +173,10 @@ struct ccsr_gur {
 #define SCFG_PMCINTECR_ETSECERRG1  0x0004
 #define SCFG_CLUSTERPMCR_WFIL2EN   0x8000
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR0x070
+#define USB_TXVREFTUNE 0x9
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
u32 dpslpcr;
-- 
1.9.3

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[U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009008

[Suresh Gupta]

USB High Speed (HS) EYE Height Adjustment
USB HS speed eye diagram fails with the default value at
many corners, particularly at a high temperature

Optimal eye at TXVREFTUNE value to 1001 is observed, change
set the same vale.

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 ++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 25 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  6 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  1 +
 4 files changed, 38 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index 94ec8d5..ec3e50d 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -12,6 +12,7 @@ config ARCH_LS1043A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
+   select SYS_FSL_ERRATUM_A009008
 
 config ARCH_LS1046A
bool
@@ -21,6 +22,7 @@ config ARCH_LS1046A
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_SRDS_2
+   select SYS_FSL_ERRATUM_A009008
 
 config ARCH_LS2080A
bool
@@ -30,6 +32,7 @@ config ARCH_LS2080A
select SYS_FSL_DDR_VER_50
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_SRDS_2
+   select SYS_FSL_ERRATUM_A009008
 
 config FSL_LSCH2
bool
@@ -53,6 +56,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"
 
+config SYS_FSL_ERRATUM_A009008
+   bool "Workaround for USB PHY erratum A009008"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index d68eeba..88cced1 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -26,6 +26,29 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+static void erratum_a009008(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009008
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB1 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB1 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB2 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB2 / 4, val|(USB_TXVREFTUNE << 6));
+   val = scfg_in32(scfg + SCFG_USB3PRM1CR_USB3 / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR_USB3 / 4, val|(USB_TXVREFTUNE << 6));
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = scfg_in32(scfg + SCFG_USB3PRM1CR / 4);
+   val &= ~(0xF << 6);
+   scfg_out32(scfg + SCFG_USB3PRM1CR / 4, val|(USB_TXVREFTUNE << 6));
+#endif
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -191,6 +214,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009203();
erratum_a008514();
erratum_a008336();
+   erratum_a009008();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -367,6 +391,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009929();
erratum_a009660();
erratum_a010539();
+   erratum_a009008();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index d88543d..b8c9926 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -335,6 +335,12 @@ struct ccsr_gur {
 #define SCFG_USBPWRFAULT_USB2_SHIFT2
 #define SCFG_USBPWRFAULT_USB1_SHIFT0
 
+#define SCFG_BASE  0x0157
+#define SCFG_USB3PRM1CR_USB1   0x070
+#define SCFG_USB3PRM1CR_USB2   0x07C
+#define SCFG_USB3PRM1CR_USB3   0x088
+#define USB_TXVREFTUNE 0x9
+
 #define SCFG_SNPCNFGCR_SECRDSNP0x8000
 #define SCFG_SNPCNFGCR_SECWRSNP0x4000
 #define SCFG_SNPCNFGCR_SATARDSNP   0x0080
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h 
b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 7acba27..3683b39 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -134,6 +134,7 @@
 #define SCFG_BASE  0x01fc
 #define SCFG_USB3PRM1CR0x000
 #define SCFG_USB3PRM1CR_INIT   0x27672b2a
+#define USB_TXVREFTUNE  

[U-Boot] [PATCH] armv8: Add workaround for USB erratum A-009007

[Suresh Gupta]

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig  |  6 +++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c| 43 ++
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  |  9 +
 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  8 
 4 files changed, 66 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig 
b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a2f3237..9965228 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -15,6 +15,7 @@ config ARCH_LS1043A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
 
 config ARCH_LS1046A
bool
@@ -27,6 +28,7 @@ config ARCH_LS1046A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
 
 config ARCH_LS2080A
bool
@@ -39,6 +41,7 @@ config ARCH_LS2080A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
 
 config FSL_LSCH2
bool
@@ -71,6 +74,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config MAX_CPUS
int "Maximum number of CPUs permitted for Layerscape"
default 4 if ARCH_LS1043A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c 
b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 1d0354d..1f08b89 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -95,6 +95,47 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+/* TODO:implement the out_be16 instead of writew which is taking
+little endian style */
+#if defined(CONFIG_LS1043A) || defined(CONFIG_LS1046A)
+   u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY1;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (u32 __iomem *)USB_PHY2;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   usb_phy = (u32 __iomem *)USB_PHY3;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#elif defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+   u32 __iomem *dcsr = (u32 __iomem *)DCSR_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  (u8 *)(dcsr) + DCSR_USB_PHY1 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_1,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4,
+  (u8 *)(dcsr) + DCSR_USB_PHY2 + DCSR_USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 bool soc_has_dp_ddr(void)
 {
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -263,6 +304,7 @@ void fsl_lsch3_early_init_f(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
 #ifdef CONFIG_CHAIN_OF_TRUST
/* In case of Secure Boot, the IBR configures the SMMU
* to allow only Secure transactions.
@@ -442,6 +484,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a009008();
erratum_a009798();

[U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009798

[Suresh Gupta]

The default setting for USB High Speed Squelch Threshold results
in a threshold close to or lower than 100mV. This leads to Receive
Compliance test failure for a 100mV threshold.

The changes shift the threshold from ~100mV towards ~130mV resulting
in passing of USB High Speed Receiver Sensitivity Compliance test

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 10 ++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  1 +
 3 files changed, 15 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 9f0188a..f816ed1 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -6,6 +6,7 @@ config ARCH_LS1021A
select SYS_FSL_DDR_BE
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A009008
+   select SYS_FSL_ERRATUM_A009798
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -35,6 +36,9 @@ config SYS_FSL_ERRATUM_A010315
 config SYS_FSL_ERRATUM_A009008
bool "Workaround for USB PHY erratum A009008"
 
+config SYS_FSL_ERRATUM_A009798
+   bool "Workaround for USB PHY erratum A009798"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index c54daee..2e64708 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -70,6 +70,15 @@ static void erratum_a009008(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A009008 */
 }
 
+static void erratum_a009798(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009798
+   u32 __iomem *scfg = (u32 __iomem *)SCFG_BASE;
+   u32 val = in_be32(scfg + SCFG_USB3PRM1CR / 4);
+   out_be32(scfg + SCFG_USB3PRM1CR / 4, val & USB_SQRXTUNE);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009798 */
+}
+
 void s_init(void)
 {
 }
@@ -158,6 +167,7 @@ int arch_soc_init(void)
 
/* Erratum */
erratum_a009008();
+   erratum_a009798();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 6ea8c4b..8cafa07 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -176,6 +176,7 @@ struct ccsr_gur {
 #define SCFG_BASE  0x0157
 #define SCFG_USB3PRM1CR0x070
 #define USB_TXVREFTUNE 0x9
+#define USB_SQRXTUNE   0xFC7F
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH] armv7: Add workaround for USB erratum A-009007

[Suresh Gupta]

Rx Compliance tests  may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash 
Signed-off-by: Rajesh Bhagat 
---
 arch/arm/cpu/armv7/ls102xa/Kconfig|  4 
 arch/arm/cpu/armv7/ls102xa/soc.c  | 12 
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  5 +
 3 files changed, 21 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index d8a8257..9313c11 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
+   select SYS_FSL_ERRATUM_A009007
 
 menu "LS102xA architecture"
depends on ARCH_LS1021A
@@ -43,6 +44,9 @@ config SYS_FSL_ERRATUM_A009798
 config SYS_FSL_ERRATUM_A008997
bool "Workaround for USB PHY erratum A008997"
 
+config SYS_FSL_ERRATUM_A009007
+   bool "Workaround for USB PHY erratum A009007"
+
 config SYS_FSL_SRDS_1
bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 19eb361..4754907 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -94,6 +94,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+   u32 __iomem *usb_phy = (u32 __iomem *)USB_PHY_BASE;
+   writew(USB_PHY_RX_EQ_VAL_1, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_2, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_3, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+   writew(USB_PHY_RX_EQ_VAL_4, (u8 *)(usb_phy) + USB_PHY_RX_OVRD_IN_HI);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
+
 void s_init(void)
 {
 }
@@ -184,6 +195,7 @@ int arch_soc_init(void)
erratum_a009008();
erratum_a009798();
erratum_a008997();
+   erratum_a009007();
return 0;
 }
 
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index c0e4372..9c4c926 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -182,10 +182,15 @@ struct ccsr_gur {
 #define USB_PHY_MPLL_OVRD_IN_HI0x0024
 #define USB_PHY_LEVEL_OVRD_IN  0x002a
 #define USB_PHY_TX_OVRD_IN_HI  0x2002
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
 #define USB_PHY_TX_OVRD_DRV_LO_VAL 0x784C
 #define USB_PHY_MPLL_OVRD_IN_HI_VAL0x0080
 #define USB_PHY_LEVEL_OVRD_IN_VAL  0xA9A5
 #define USB_PHY_TX_OVRD_IN_HI_VAL  0x0003
+#define USB_PHY_RX_EQ_VAL_10x
+#define USB_PHY_RX_EQ_VAL_20x8000
+#define USB_PHY_RX_EQ_VAL_30x8004
+#define USB_PHY_RX_EQ_VAL_40x800C
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
-- 
1.9.3

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[U-Boot] [PATCH v2] powerpc/usb: Workaround for erratum-A006261

[Suresh Gupta]

USB spec says that the minimum disconnect threshold should be
over 525 mV. However, internal USB PHY threshold value is below
this specified value. Due to this some devices disconnect at
run-time. Hence, phy settings are tweaked to increased disconnect
threshold to be above 525mV by using this workaround.

Signed-off-by: Suresh Gupta suresh.gu...@freescale.com
---
 Changes for v2:
- Incorporated missing SOC's affected by errata

 arch/powerpc/cpu/mpc85xx/cmd_errata.c |  4 ++
 arch/powerpc/cpu/mpc85xx/cpu_init.c   | 62 +++
 arch/powerpc/include/asm/config_mpc85xx.h |  7 
 arch/powerpc/include/asm/fsl_errata.h | 34 +
 include/fsl_usb.h | 23 +++-
 5 files changed, 128 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7693899..2a15802 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -265,6 +265,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
(SVR_REV(svr) = CONFIG_SYS_FSL_A004447_SVR_REV))
puts(Work-around for Erratum I2C-A004447 enabled\n);
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+   if (has_erratum_a006261())
+   puts(Work-around for Erratum A006261 enabled\n);
+#endif
return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b31efb7..81aeadd 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -36,6 +36,54 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
+{
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+   u32 xcvrprg = in_be32(usb_phy-port1.xcvrprg);
+
+   /* Increase Disconnect Threshold by 50mV */
+   xcvrprg = ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+   INC_DCNT_THRESHOLD_50MV;
+   /* Enable programming of USB High speed Disconnect threshold */
+   xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+   out_be32(usb_phy-port1.xcvrprg, xcvrprg);
+
+   xcvrprg = in_be32(usb_phy-port2.xcvrprg);
+   /* Increase Disconnect Threshold by 50mV */
+   xcvrprg = ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+   INC_DCNT_THRESHOLD_50MV;
+   /* Enable programming of USB High speed Disconnect threshold */
+   xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+   out_be32(usb_phy-port2.xcvrprg, xcvrprg);
+#else
+
+   u32 temp = 0;
+   u32 status = in_be32(usb_phy-status1);
+
+   u32 squelch_prog_rd_0_2 =
+   (status  CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+   u32 squelch_prog_rd_3_5 =
+   (status  CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+   setbits_be32(usb_phy-config1,
+CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+   setbits_be32(usb_phy-config2,
+CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+
+   temp = squelch_prog_rd_0_2  CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+   out_be32(usb_phy-config2, in_be32(usb_phy-config2) | temp);
+
+   temp = squelch_prog_rd_3_5  CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+   out_be32(usb_phy-config2, in_be32(usb_phy-config2) | temp);
+#endif
+}
+#endif
+
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -625,6 +673,10 @@ skip_l2:
{
struct ccsr_usb_phy __iomem *usb_phy1 =
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+   if (has_erratum_a006261())
+   fsl_erratum_a006261_workaround(usb_phy1);
+#endif
out_be32(usb_phy1-usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
@@ -633,6 +685,10 @@ skip_l2:
{
struct ccsr_usb_phy __iomem *usb_phy2 =
(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+   if (has_erratum_a006261())
+   fsl_erratum_a006261_workaround(usb_phy2);
+#endif
out_be32(usb_phy2-usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
@@ -672,8 +728,14 @@ skip_l2:
 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
setbits_be32(usb_phy-port2.pwrfltcfg,
 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+   if (has_erratum_a006261

[U-Boot] [PATCH] powerpc/usb: Workaround for erratum-A006261

[Suresh Gupta]

USB spec says that the minimum disconnect threshold should be
over 525 mV. However, internal USB PHY threshold value is below
this specified value. Due to this some devices disconnect at
run-time. Hence, phy settings are tweaked to increased disconnect
threshold to be above 525mV by using this workaround.

Signed-off-by: Suresh Gupta suresh.gu...@freescale.com
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c |  4 ++
 arch/powerpc/cpu/mpc85xx/cpu_init.c   | 62 +++
 arch/powerpc/include/asm/config_mpc85xx.h |  7 
 arch/powerpc/include/asm/fsl_errata.h | 31 
 include/fsl_usb.h | 23 +++-
 5 files changed, 125 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 7693899..2a15802 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -265,6 +265,10 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
(SVR_REV(svr) = CONFIG_SYS_FSL_A004447_SVR_REV))
puts(Work-around for Erratum I2C-A004447 enabled\n);
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+   if (has_erratum_a006261())
+   puts(Work-around for Erratum A006261 enabled\n);
+#endif
return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c 
b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index b31efb7..81aeadd 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -36,6 +36,54 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+void fsl_erratum_a006261_workaround(struct ccsr_usb_phy __iomem *usb_phy)
+{
+#ifdef CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE
+   u32 xcvrprg = in_be32(usb_phy-port1.xcvrprg);
+
+   /* Increase Disconnect Threshold by 50mV */
+   xcvrprg = ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+   INC_DCNT_THRESHOLD_50MV;
+   /* Enable programming of USB High speed Disconnect threshold */
+   xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+   out_be32(usb_phy-port1.xcvrprg, xcvrprg);
+
+   xcvrprg = in_be32(usb_phy-port2.xcvrprg);
+   /* Increase Disconnect Threshold by 50mV */
+   xcvrprg = ~CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_MASK |
+   INC_DCNT_THRESHOLD_50MV;
+   /* Enable programming of USB High speed Disconnect threshold */
+   xcvrprg |= CONFIG_SYS_FSL_USB_XCVRPRG_HS_DCNT_PROG_EN;
+   out_be32(usb_phy-port2.xcvrprg, xcvrprg);
+#else
+
+   u32 temp = 0;
+   u32 status = in_be32(usb_phy-status1);
+
+   u32 squelch_prog_rd_0_2 =
+   (status  CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_0)
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+   u32 squelch_prog_rd_3_5 =
+   (status  CONFIG_SYS_FSL_USB_SQUELCH_PROG_RD_3)
+CONFIG_SYS_FSL_USB_SQUELCH_PROG_MASK;
+
+   setbits_be32(usb_phy-config1,
+CONFIG_SYS_FSL_USB_HS_DISCNCT_INC);
+   setbits_be32(usb_phy-config2,
+CONFIG_SYS_FSL_USB_RX_AUTO_CAL_RD_WR_SEL);
+
+   temp = squelch_prog_rd_0_2  CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_0;
+   out_be32(usb_phy-config2, in_be32(usb_phy-config2) | temp);
+
+   temp = squelch_prog_rd_3_5  CONFIG_SYS_FSL_USB_SQUELCH_PROG_WR_3;
+   out_be32(usb_phy-config2, in_be32(usb_phy-config2) | temp);
+#endif
+}
+#endif
+
+
 #ifdef CONFIG_QE
 extern qe_iop_conf_t qe_iop_conf_tab[];
 extern void qe_config_iopin(u8 port, u8 pin, int dir,
@@ -625,6 +673,10 @@ skip_l2:
{
struct ccsr_usb_phy __iomem *usb_phy1 =
(void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+   if (has_erratum_a006261())
+   fsl_erratum_a006261_workaround(usb_phy1);
+#endif
out_be32(usb_phy1-usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
@@ -633,6 +685,10 @@ skip_l2:
{
struct ccsr_usb_phy __iomem *usb_phy2 =
(void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR;
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+   if (has_erratum_a006261())
+   fsl_erratum_a006261_workaround(usb_phy2);
+#endif
out_be32(usb_phy2-usb_enable_override,
CONFIG_SYS_FSL_USB_ENABLE_OVERRIDE);
}
@@ -672,8 +728,14 @@ skip_l2:
 CONFIG_SYS_FSL_USB_DRVVBUS_CR_EN);
setbits_be32(usb_phy-port2.pwrfltcfg,
 CONFIG_SYS_FSL_USB_PWRFLT_CR_EN);
+
+#ifdef CONFIG_SYS_FSL_ERRATUM_A006261
+   if (has_erratum_a006261())
+   fsl_erratum_a006261_workaround(usb_phy);
 #endif
 
+#endif