[U-Boot] usb start hangs

2017-01-06 Thread Tony O'Brien 
Hi -


We recently updated our U-Boot release to v2016.11 and now our USB devices 
don't work.  When usb start is executed with a device inserted it hangs at 
'scanning bus 0 for devices...' and doesn't recover.  Our product uses an NXP 
T2081 and I can reproduce this issue on the T2080RDB development board using 
the tip of U-Boot.  For testing I am using both an EMTEC 16GB USB thumb drive 
and an Edimax Fast Ethernet adapter.  The code always hangs at 
drivers/usb/host/ehci-hcd.c:557 in ehci_submit_async, just before the call to 
handshake.


I have traced the issue to 'Commit cb1629f91a48 powerpc: Disable flush or 
invalidate dcache by range for some SoCs', which is prior to the v2016.07 
release.  Commit ac337168ad81 mentioned in this patch removes the original 
empty functions for the MPC85xx (and others), allowing the functions to be 
used, but I don't know how they would have worked before this.


Either reverting cb1629f91a48 or adding '|| defined(MPC85xx) ' to the #if 
statements makes usb work again.


diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index 66cf02dbd0..ad28c7c369 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -65,7 +65,7 @@ ppcSync:
 * flush_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(flush_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
   li  r5,L1_CACHE_BYTES-1
   andcr3,r3,r5
   subfr4,r3,r4
@@ -89,7 +89,7 @@ _GLOBAL(flush_dcache_range)
 * invalidate_dcache_range(unsigned long start, unsigned long stop)
 */
_GLOBAL(invalidate_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
   li  r5,L1_CACHE_BYTES-1
   andcr3,r3,r5
   subfr4,r3,r4

Do you have any thoughts on this before I submit the patch?


Cheers,

Tony O'Brien
Senior Software/Hardware Engineer
Allied Telesis Labs
27 Nazareth Avenue
Christchurch 8024
New Zealand
Ph: +64-3-339 3000
DDI: +64-3-339 9210
Web: http://AlliedTelesis.com


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[U-Boot] [PATCH] powerpc: Enable flush and invalidate dcache by range for MPC85xx

2017-01-06 Thread Tony O'Brien 
Commit ac337168a unified functions to flush and invalidate dcache by
range. These two functions were no-ops for SoCs other than 4xx and
MPC86xx. Adding these functions seemed to be correct but introduced
issues in some drivers when the dcache was flushed. While the root
cause was under investigation, these functions were disabled in
Commit cb1629f91a for affected SoCs, including the MPC85xx, to make
the various drivers work.

On the T208x USB stopped working after v2016.07 was pulled.  After
re-enabling the dcache functions for the MPC85xx it started working
again.  The USB and DPPA Ethernet drivers have been seen as
operational after this change but other drivers cannot be tested.

Reviewed-by: Chris Packham 
Signed-off-by: Tony O'Brien 
Cc: Marek Vasut 
Cc: York Sun 
---
The USB and Ethernet functionality has been tested on both the
T2080RDB and our own design but we don't have the hardware to test
any of the other drivers.  We will wait and see if it causes us any
issues with other drivers.
 arch/powerpc/lib/ppccache.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/lib/ppccache.S b/arch/powerpc/lib/ppccache.S
index 66cf02dbd0..ad28c7c369 100644
--- a/arch/powerpc/lib/ppccache.S
+++ b/arch/powerpc/lib/ppccache.S
@@ -65,7 +65,7 @@ ppcSync:
  * flush_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(flush_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
li  r5,L1_CACHE_BYTES-1
andcr3,r3,r5
subfr4,r3,r4
@@ -89,7 +89,7 @@ _GLOBAL(flush_dcache_range)
  * invalidate_dcache_range(unsigned long start, unsigned long stop)
  */
 _GLOBAL(invalidate_dcache_range)
-#if defined(CONFIG_4xx) || defined(CONFIG_MPC86xx)
+#if defined(CONFIG_4xx) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
li  r5,L1_CACHE_BYTES-1
andcr3,r3,r5
subfr4,r3,r4
-- 
2.11.0

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[U-Boot] [PATCH v2] mpc85xx: pci: Implement workaround for Erratum A007815

2016-12-01 Thread Tony O'Brien 
The read-only-write-enable bit is set by default and must be cleared
to prevent overwriting read-only registers.  This should be done
immediately after resetting the PCI Express controller.

Reviewed-by: Hamish Martin 
Signed-off-by: Tony O'Brien 

---
Note that this does not implement the whole fix for this erratum,
just what is necessary for our implementation. Since we are using a
fixed RC configuration, no support has been added for EP mode or any
consideration of link-up/down events.
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++
 arch/powerpc/include/asm/config_mpc85xx.h | 1 +
 arch/powerpc/include/asm/fsl_pci.h| 4 +++-
 drivers/pci/fsl_pci_init.c| 7 +++
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 402a1ff..aabb56b 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -330,6 +330,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
puts("Work-around for Erratum A009663 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+   puts("Work-around for Erratum A007815 enabled\n");
+#endif
 
return 0;
 }
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index c92bc1e..c298e44 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -785,6 +785,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007815
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
diff --git a/arch/powerpc/include/asm/fsl_pci.h 
b/arch/powerpc/include/asm/fsl_pci.h
index 8bee8ca..cad341e 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -79,7 +79,9 @@ typedef struct ccsr_pci {
u32 pme_msg_dis;/* 0x024 - PCIE PME & message disable register 
*/
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable 
register */
u32 pm_command; /* 0x02c - PCIE PM Command register */
-   charres4[3016]; /* (- #xbf8  #x30)3016 */
+   charres3[2188]; /* (0x8bc - 0x30 = 2188) */
+   u32 dbi_ro_wr_en;   /* 0x8bc - DBI read only write enable reg */
+   charres4[824];  /* (0xbf8 - 0x8c0 = 824) */
u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
 
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 52792dc..af20cf0 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+   /* The Read-Only Write Enable bit defaults to 1 instead of 0.
+* Set to 0 to protect the read-only registers.
+*/
+   clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
+#endif
+
/* Use generic setup_device to initialize standard pci regs,
 * but do not allocate any windows since any BAR found (such
 * as PCSRBAR) is not in this cpu's memory space.
-- 
2.10.2

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[U-Boot] [PATCH] mpc85xx: pci: Implement workaround for Erratum A007815

2016-11-30 Thread Tony O'Brien 
The read-only-write-enable bit is set by default and must be cleared
to prevent overwriting read-only registers.  This should be done
immediately after resetting the PCI Express controller.

Reviewed-by: Hamish Martin 

---
Note that this does not implement the whole fix for this erratum,
just what is necessary for our implementation. Since we are using a
fixed RC configuration, no support has been added for EP mode or any
consideration of link-up/down events.

Signed-off-by: Tony O'Brien 
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++
 arch/powerpc/include/asm/config_mpc85xx.h | 1 +
 arch/powerpc/include/asm/fsl_pci.h| 4 +++-
 drivers/pci/fsl_pci_init.c| 7 +++
 4 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c 
b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 402a1ff..aabb56b 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -330,6 +330,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, 
char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A009663
puts("Work-around for Erratum A009663 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+   puts("Work-around for Erratum A007815 enabled\n");
+#endif
 
return 0;
 }
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h 
b/arch/powerpc/include/asm/config_mpc85xx.h
index c92bc1e..c298e44 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -785,6 +785,7 @@ defined(CONFIG_PPC_T1014) || defined(CONFIG_PPC_T1013)
 #define CONFIG_SYS_FSL_ERRATUM_A006593
 #define CONFIG_SYS_FSL_ERRATUM_A007186
 #define CONFIG_SYS_FSL_ERRATUM_A006379
+#define CONFIG_SYS_FSL_ERRATUM_A007815
 #define ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 
diff --git a/arch/powerpc/include/asm/fsl_pci.h 
b/arch/powerpc/include/asm/fsl_pci.h
index 8bee8ca..cad341e 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -79,7 +79,9 @@ typedef struct ccsr_pci {
u32 pme_msg_dis;/* 0x024 - PCIE PME & message disable register 
*/
u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable 
register */
u32 pm_command; /* 0x02c - PCIE PM Command register */
-   charres4[3016]; /* (- #xbf8  #x30)3016 */
+   charres3[2188]; /* (0x8bc - 0x30 = 2188) */
+   u32 dbi_ro_wr_en;   /* 0x8bc - DBI read only write enable reg */
+   charres4[824];  /* (0xbf8 - 0x8c0 = 824) */
u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */
u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */
 
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 52792dc..af20cf0 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -543,6 +543,13 @@ void fsl_pci_init(struct pci_controller *hose, struct 
fsl_pci_info *pci_info)
pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+   /* The Read-Only Write Enable bit defaults to 1 instead of 0.
+* Set to 0 to protect the read-only registers.
+*/
+   clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
+#endif
+
/* Use generic setup_device to initialize standard pci regs,
 * but do not allocate any windows since any BAR found (such
 * as PCSRBAR) is not in this cpu's memory space.
-- 
2.10.2

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