Re: [PATCH 2/4] riscv: dts: Add QSPI NAND device node
On 10/19/22 17:53, Padmarao Begari wrote:
> + flash0: spi-nand@0 {
the node should have generic name according to the dt specification,
so please s/spi-nand/flash.
--
Cheers,
ta
Re: [PATCH 4/4] spi: Add Microchip PolarFire SoC QSPI driver
Hi! On 10/19/22 17:53, Padmarao Begari wrote: > drivers/spi/microchip_qspi.c | 504 +++ The name is too generic, there are multiple QSPI IPs inside mchp. I would suggest to create an mchp directory and rename your c file to maybe something like mpfs-qspi? -- Cheers, ta
Re: Submitting patches
On 8/4/22 09:24, Martin Bonner wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > On Wed, 3 Aug 2022 at 19:14, Simon Glass wrote: > >> Hi Martin, >> >> On Wed, 3 Aug 2022 at 04:05, Martin Bonner >> wrote: >>> >>> I and my colleagues have a number of patches we would like to >>> contribute back to the community, however for various reasons >>> (principally operating inside corporate firewalls), it isn't possible >>> to use `git send-email`, and I haven't been able to create a plain >>> text email which is acceptable to `git am`. >> >> The workaround here is perhaps to create a gmail address for >> submissions. I think quite a few people do that. > > Interesting. I am using gmail (because I assumed that the corporate email > would mangle stuff), but I can't get it to work. bypass the company network as well if you can. Try disconnecting the VPN if you're working from home, or use your phone as a personal hotspot. > > Surprisingly, I think that Office365 email is actually _more_ compliant > with the way the u-boot process works. > > But a firewall that >> blocks 'git send-email' is not really compatible with open source >> collaboration, so I'd encourage you to get the problem resolved. >> > > That's completely impossible. Corporate IT will let us push patches :) > upstream if we like, but they absolutely are not going to change their > policies and infrastructure to let that happen. If I got tired of fighting them, I would bypass the company's infrastructure.
Re: [PATCH 0/9] Add DM support for atmel NAND driver
On 7/19/22 13:46, Balamanikandan Gunasundar wrote: > This patch series adds support for NAND flash. The series adds DM > support and replaces the existing NAND driver NAND_ATMEL. The drivers > are ported from Linux based on the work done by Boris brezillon If you're going to resubmit, it would be helpful to specify on top of which kernel version your work is based on. This would help to backport fixes or new support in the future. ta > > Balamanikandan Gunasundar (9): > nand: atmel: Add DM based NAND driver > nand: atmel: Add pmecc driver > mfd: syscon: Add atmel-matrix registers definition > memory: atmel-ebi: add Atmel EBI (External Bus Interface) driver > mfd: syscon: atmel-smc: Add driver for atmel SMC > configs: at91: sam9x60ek: Enable DM based nand driver > ARM: dts: at91: sam9x60: Add nodes for EBI and NAND > ARM: dts: at91: sam9x60ek: Enable NAND support > board: sam9x60ek: remove nand init from board file > > MAINTAINERS |1 + > arch/arm/dts/sam9x60.dtsi| 42 + > arch/arm/dts/sam9x60ek.dts | 103 + > board/atmel/sam9x60ek/sam9x60ek.c| 59 - > configs/sam9x60ek_mmc_defconfig |9 +- > configs/sam9x60ek_nandflash_defconfig|9 +- > configs/sam9x60ek_qspiflash_defconfig|8 +- > drivers/Kconfig |2 + > drivers/Makefile |1 + > drivers/memory/Kconfig |7 + > drivers/memory/Makefile |1 + > drivers/memory/atmel_ebi.c | 37 + > drivers/mfd/Kconfig |4 + > drivers/mfd/Makefile |1 + > drivers/mfd/atmel-smc.c | 364 +++ > drivers/mtd/nand/raw/Kconfig |8 + > drivers/mtd/nand/raw/Makefile|1 + > drivers/mtd/nand/raw/atmel/Makefile |5 + > drivers/mtd/nand/raw/atmel/nand-controller.c | 2300 ++ > drivers/mtd/nand/raw/atmel/pmecc.c | 969 > drivers/mtd/nand/raw/atmel/pmecc.h | 94 + > include/linux/mfd/syscon/atmel-matrix.h | 112 + > include/linux/mfd/syscon/atmel-smc.h | 119 + > 23 files changed, 4188 insertions(+), 68 deletions(-) > create mode 100644 drivers/memory/atmel_ebi.c > create mode 100644 drivers/mfd/Kconfig > create mode 100644 drivers/mfd/Makefile > create mode 100644 drivers/mfd/atmel-smc.c > create mode 100644 drivers/mtd/nand/raw/atmel/Makefile > create mode 100644 drivers/mtd/nand/raw/atmel/nand-controller.c > create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.c > create mode 100644 drivers/mtd/nand/raw/atmel/pmecc.h > create mode 100644 include/linux/mfd/syscon/atmel-matrix.h > create mode 100644 include/linux/mfd/syscon/atmel-smc.h >
Re: spi-nor dummy bytes for fast read command
On 1/13/21 4:06 AM, Bin Meng wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know the > content is safe > > Hi, Hi, > > It seems both U-Boot and Linux kernel spi-nor drivers have the same > assumption on dummy cycles required in a fast read command. > > In U-Boot spi_nor_read_data(), there is a logic to calculate the dummy > bytes needed for fast read command: > > /* convert the dummy cycles to the number of bytes */ > op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) / 8; > > This logic assumes the (nor->read_dummy * op.dummy.buswidth) is a > multiple of 8, otherwise this won't work. > > In Linux, the same logic exists in spi_nor_spimem_read_data(). > > Note on most flashes this is not a problem, however on some flashes > the dummy cycles for the fast read command is configurable. If the > dummy cycle is configured to some odd value which makes this > assumption false, then we get a non-working driver. > Right. We should use dummy cycles directly and get rid of the dummy bytes logic. I have this in my todo queue for linux. Cheers, ta
Re: [u-boot][PATCH 2/2] spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses
On Friday, March 20, 2020 11:37:59 AM EET tudor.amba...@microchip.com wrote:
> From: Tudor Ambarus
>
> This feature should not be enabled in release but can be useful for
> developers who need to monitor register accesses at some specific places.
>
> Helped me identify a bug in u-boot, by comparing the register accesses
> from the u-boot driver with the ones from its linux variant.
>
> Signed-off-by: Tudor Ambarus
> ---
> drivers/spi/atmel-quadspi.c | 114 ++--
> 1 file changed, 96 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
> index 4099ee87993d..3de367e6a0c8 100644
> --- a/drivers/spi/atmel-quadspi.c
> +++ b/drivers/spi/atmel-quadspi.c
> @@ -148,6 +148,7 @@ struct atmel_qspi {
> void __iomem *mem;
> resource_size_t mmap_size;
> const struct atmel_qspi_caps *caps;
> + struct udevice *dev;
> ulong bus_clk_rate;
> u32 mr;
> };
> @@ -169,6 +170,81 @@ static const struct atmel_qspi_mode atmel_qspi_modes[]
> = { { 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
> };
>
> +#ifdef VERBOSE_DEBUG
> +static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
> +{
> + switch (offset) {
> + case QSPI_CR:
> + return "CR";
> + case QSPI_MR:
> + return "MR";
> + case QSPI_RD:
> + return "MR";
> + case QSPI_TD:
> + return "TD";
> + case QSPI_SR:
> + return "SR";
> + case QSPI_IER:
> + return "IER";
> + case QSPI_IDR:
> + return "IDR";
> + case QSPI_IMR:
> + return "IMR";
> + case QSPI_SCR:
> + return "SCR";
> + case QSPI_IAR:
> + return "IAR";
> + case QSPI_ICR:
> + return "ICR/WICR";
> + case QSPI_IFR:
> + return "IFR";
> + case QSPI_RICR:
> + return "RICR";
> + case QSPI_SMR:
> + return "SMR";
> + case QSPI_SKR:
> + return "SKR";
> + case QSPI_WPMR:
> + return "WPMR";
> + case QSPI_WPSR:
> + return "WPSR";
> + case QSPI_VERSION:
> + return "VERSION";
> + default:
> + snprintf(tmp, sz, "0x%02x", offset);
> + break;
> + }
> +
> + return tmp;
> +}
> +#endif /* VERBOSE_DEBUG */
> +
> +static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
> +{
> + u32 value = readl(aq->regs + offset);
> +
> +#ifdef VERBOSE_DEBUG
> + char tmp[8];
The largest string that I print is "ICR/WICR" which is 8bytes, but I didn't
count the trailing null space, so the array should better be increased to 16
bytes, to avoid truncation.
> +
> + dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
> + atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
> +#endif /* VERBOSE_DEBUG */
> +
> + return value;
> +}
> +
> +static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
> +{
> +#ifdef VERBOSE_DEBUG
> + char tmp[8];
ditto
Jagan, if the rest looks good, would you do this change when applying? Let me
know if I have to resubmit, or if there are any suggestions.
Cheers,
ta
[u-boot][PATCH] spi: spi-mem: Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum
From: Tudor Ambarus
Commit: 0ebb261a0b2d ("spi: spi-mem: Add SPI_MEM_NO_DATA to the
spi_mem_data_dir enum")
in linux.
When defining spi_mem_op templates we don't necessarily know the size
that will be passed when the template is actually used, and basing the
supports_op() check on op->data.nbytes to know whether there will be
data transferred for a specific operation is not possible.
Add SPI_MEM_NO_DATA to the spi_mem_data_dir enum so that we can base
our checks on op->data.dir instead of op->data.nbytes.
This also fixes a bug identified with the atmel-quaspi driver.
The spi-nor core, when erasing sectors, fills the spi_mem_op template
using SPI_MEM_OP_NO_DATA, which initializes all the data members with
value zero. This is wrong because data.dir is treated as SPI_MEM_DATA_IN,
which translates in our driver to read accesses for erases (RICR), while
the controller expects write accesses (WICR).
Signed-off-by: Tudor Ambarus
---
drivers/spi/spi-mem.c | 2 +-
include/spi-mem.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index e900c997bd7f..ffbe20c5b1e6 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -153,7 +153,7 @@ bool spi_mem_default_supports_op(struct spi_slave *slave,
spi_check_buswidth_req(slave, op->dummy.buswidth, true))
return false;
- if (op->data.nbytes &&
+ if (op->data.dir != SPI_MEM_NO_DATA &&
spi_check_buswidth_req(slave, op->data.buswidth,
op->data.dir == SPI_MEM_DATA_OUT))
return false;
diff --git a/include/spi-mem.h b/include/spi-mem.h
index 36814efa8613..893f7bd73370 100644
--- a/include/spi-mem.h
+++ b/include/spi-mem.h
@@ -60,10 +60,12 @@
/**
* enum spi_mem_data_dir - describes the direction of a SPI memory data
*transfer from the controller perspective
+ * @SPI_MEM_NO_DATA: no data transferred
* @SPI_MEM_DATA_IN: data coming from the SPI memory
* @SPI_MEM_DATA_OUT: data sent the SPI memory
*/
enum spi_mem_data_dir {
+ SPI_MEM_NO_DATA,
SPI_MEM_DATA_IN,
SPI_MEM_DATA_OUT,
};
--
2.23.0
[u-boot][PATCH 2/2] spi: atmel-quadspi: Add verbose debug facilities to monitor register accesses
From: Tudor Ambarus
This feature should not be enabled in release but can be useful for
developers who need to monitor register accesses at some specific places.
Helped me identify a bug in u-boot, by comparing the register accesses
from the u-boot driver with the ones from its linux variant.
Signed-off-by: Tudor Ambarus
---
drivers/spi/atmel-quadspi.c | 114 ++--
1 file changed, 96 insertions(+), 18 deletions(-)
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index 4099ee87993d..3de367e6a0c8 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -148,6 +148,7 @@ struct atmel_qspi {
void __iomem *mem;
resource_size_t mmap_size;
const struct atmel_qspi_caps *caps;
+ struct udevice *dev;
ulong bus_clk_rate;
u32 mr;
};
@@ -169,6 +170,81 @@ static const struct atmel_qspi_mode atmel_qspi_modes[] = {
{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
};
+#ifdef VERBOSE_DEBUG
+static const char *atmel_qspi_reg_name(u32 offset, char *tmp, size_t sz)
+{
+ switch (offset) {
+ case QSPI_CR:
+ return "CR";
+ case QSPI_MR:
+ return "MR";
+ case QSPI_RD:
+ return "MR";
+ case QSPI_TD:
+ return "TD";
+ case QSPI_SR:
+ return "SR";
+ case QSPI_IER:
+ return "IER";
+ case QSPI_IDR:
+ return "IDR";
+ case QSPI_IMR:
+ return "IMR";
+ case QSPI_SCR:
+ return "SCR";
+ case QSPI_IAR:
+ return "IAR";
+ case QSPI_ICR:
+ return "ICR/WICR";
+ case QSPI_IFR:
+ return "IFR";
+ case QSPI_RICR:
+ return "RICR";
+ case QSPI_SMR:
+ return "SMR";
+ case QSPI_SKR:
+ return "SKR";
+ case QSPI_WPMR:
+ return "WPMR";
+ case QSPI_WPSR:
+ return "WPSR";
+ case QSPI_VERSION:
+ return "VERSION";
+ default:
+ snprintf(tmp, sz, "0x%02x", offset);
+ break;
+ }
+
+ return tmp;
+}
+#endif /* VERBOSE_DEBUG */
+
+static u32 atmel_qspi_read(struct atmel_qspi *aq, u32 offset)
+{
+ u32 value = readl(aq->regs + offset);
+
+#ifdef VERBOSE_DEBUG
+ char tmp[8];
+
+ dev_vdbg(aq->dev, "read 0x%08x from %s\n", value,
+atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
+#endif /* VERBOSE_DEBUG */
+
+ return value;
+}
+
+static void atmel_qspi_write(u32 value, struct atmel_qspi *aq, u32 offset)
+{
+#ifdef VERBOSE_DEBUG
+ char tmp[8];
+
+ dev_vdbg(aq->dev, "write 0x%08x into %s\n", value,
+atmel_qspi_reg_name(offset, tmp, sizeof(tmp)));
+#endif /* VERBOSE_DEBUG */
+
+ writel(value, aq->regs + offset);
+}
+
static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
const struct atmel_qspi_mode *mode)
{
@@ -289,32 +365,32 @@ static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
* Serial Memory Mode (SMM).
*/
if (aq->mr != QSPI_MR_SMM) {
- writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
+ atmel_qspi_write(QSPI_MR_SMM, aq, QSPI_MR);
aq->mr = QSPI_MR_SMM;
}
/* Clear pending interrupts */
- (void)readl(aq->regs + QSPI_SR);
+ (void)atmel_qspi_read(aq, QSPI_SR);
if (aq->caps->has_ricr) {
if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
ifr |= QSPI_IFR_APBTFRTYP_READ;
/* Set QSPI Instruction Frame registers */
- writel(iar, aq->regs + QSPI_IAR);
+ atmel_qspi_write(iar, aq, QSPI_IAR);
if (op->data.dir == SPI_MEM_DATA_IN)
- writel(icr, aq->regs + QSPI_RICR);
+ atmel_qspi_write(icr, aq, QSPI_RICR);
else
- writel(icr, aq->regs + QSPI_WICR);
- writel(ifr, aq->regs + QSPI_IFR);
+ atmel_qspi_write(icr, aq, QSPI_WICR);
+ atmel_qspi_write(ifr, aq, QSPI_IFR);
} else {
if (op->data.dir == SPI_MEM_DATA_OUT)
ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
/* Set QSPI Instruction Frame registers */
- writel(iar, aq->regs + QSPI_IAR);
- writel(icr, aq->regs + QSPI_ICR);
- writel(ifr, aq->regs + QSPI_IFR);
+ atmel_qspi_write(iar, aq, QSPI_IAR);
+ atmel_qspi_write(icr, aq, QSPI_ICR);
+ atmel_qspi_write(ifr, aq, QSPI_IFR);
}
return 0;
@@ -342,7 +418,7 @@ static int atmel_qspi_exec_op(struct spi_slave *slave,
/* Skip to the final steps if there is no data */
if (op->data.nbytes) {
/* Dummy read of QSPI_IFR to s
[u-boot][PATCH 1/2] spi: atmel-quadspi: fix possible MMIO window size overrun
From: Tudor Ambarus
The sama5d2 QSPI controller memory space is limited to 128MB:
0x9000_0-0x9800_0/0XD000_--0XD800_.
There are nor flashes that are bigger in size than the memory size
supported by the controller: Micron MT25QL02G (256 MB).
Check if the address exceeds the MMIO window size. An improvement
would be to add support for regular SPI mode and fall back to it
when the flash memories overrun the controller's memory space.
Fixes: 24c8ff4684c5 ("spi: Add Atmel QuadSPI driver")
Signed-off-by: Tudor Ambarus
---
drivers/spi/atmel-quadspi.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
index a09bf884e837..4099ee87993d 100644
--- a/drivers/spi/atmel-quadspi.c
+++ b/drivers/spi/atmel-quadspi.c
@@ -146,6 +146,7 @@ struct atmel_qspi_caps {
struct atmel_qspi {
void __iomem *regs;
void __iomem *mem;
+ resource_size_t mmap_size;
const struct atmel_qspi_caps *caps;
ulong bus_clk_rate;
u32 mr;
@@ -326,6 +327,14 @@ static int atmel_qspi_exec_op(struct spi_slave *slave,
u32 sr, imr, offset;
int err;
+ /*
+* Check if the address exceeds the MMIO window size. An improvement
+* would be to add support for regular SPI mode and fall back to it
+* when the flash memories overrun the controller's memory space.
+*/
+ if (op->addr.val + op->data.nbytes > aq->mmap_size)
+ return -ENOTSUPP;
+
err = atmel_qspi_set_cfg(aq, op, &offset);
if (err)
return err;
@@ -490,6 +499,8 @@ static int atmel_qspi_probe(struct udevice *dev)
if (IS_ERR(aq->mem))
return PTR_ERR(aq->mem);
+ aq->mmap_size = resource_size(&res);
+
ret = atmel_qspi_enable_clk(dev);
if (ret)
return ret;
--
2.23.0
[U-Boot] [PATCH v2 1/4] mtd: spi: spi-nor-core: Add SST vendor specific SFDP parser
From: Tudor Ambarus
JESD216 allow vendors to define their own SFDP tables.
Add SST SFDP parser. The vendor table is allocated using resource-managed
kmalloc - the table will be freed on driver detach. It will be accessible
by getting the UCLASS_SPI_FLASH's private data.
The SST's SFDP table is particularly of interest because contains
pre-programmed globally unique EUI-48 and EUI-64 identifiers.
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi/spi-nor-core.c | 46 --
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 46 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 5a8c08425566..ee77151f20de 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1588,6 +1588,7 @@ struct sfdp_parameter_header {
#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
+#define SFDP_SST_ID0x01bf /* Manufacturer specific Table */
#define SFDP_SIGNATURE 0x50444653U
#define SFDP_JESD216_MAJOR 1
@@ -1968,6 +1969,34 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
}
/**
+ * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
+ * SFDP table.
+ * @nor: pointer to a 'struct spi_nor'.
+ * @param_header: pointer to the SFDP parameter header.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int
+spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
+const struct sfdp_parameter_header *param_header)
+{
+ size_t size;
+ u32 addr;
+ int ret;
+
+ size = param_header->length * sizeof(u32);
+ addr = SFDP_PARAM_HEADER_PTP(param_header);
+
+ nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
+ if (!nor->manufacturer_sfdp)
+ return -ENOMEM;
+
+ ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
+
+ return ret;
+}
+
+/**
* spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
* @nor: pointer to a 'struct spi_nor'
* @params:pointer to the 'struct spi_nor_flash_parameter' to be
@@ -2063,12 +2092,25 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
dev_info(dev, "non-uniform erase sector maps are not
supported yet.\n");
break;
+ case SFDP_SST_ID:
+ err = spi_nor_parse_microchip_sfdp(nor, param_header);
+ break;
+
default:
break;
}
- if (err)
- goto exit;
+ if (err) {
+ dev_warn(dev, "Failed to parse optional parameter
table: %04x\n",
+SFDP_PARAM_HEADER_ID(param_header));
+ /*
+* Let's not drop all information we extracted so far
+* if optional table parsers fail. In case of failing,
+* each optional parser is responsible to roll back to
+* the previously known spi_nor data.
+*/
+ err = 0;
+ }
}
exit:
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index f9964a766456..1d911772917d 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -261,6 +261,7 @@ struct flash_info;
* @lock: the lock for the read/write/erase/lock/unlock operations
* @dev: point to a spi device, or a spi nor controller device.
* @info: spi-nor part JDEC MFR id and other info
+ * @manufacturer_sfdp: manufacturer specific SFDP table
* @page_size: the page size of the SPI NOR
* @addr_width:number of address bytes
* @erase_opcode: the opcode for erasing a sector
@@ -299,6 +300,7 @@ struct spi_nor {
struct udevice *dev;
struct spi_slave*spi;
const struct flash_info *info;
+ u8 *manufacturer_sfdp;
u32 page_size;
u8 addr_width;
u8 erase_opcode;
--
2.9.5
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[U-Boot] [PATCH v2 0/4] mtd: spi: spi-nor-core: Add SST vendor specific SFDP parser
From: Tudor Ambarus Parse manufacturer specific SFDP table. The SST SFDP table contains pre-programmed globally unique MAC addresses. Retrieve the MAC address from the SPI NOR flash and set it in ethaddr in env. v2: - s/SFDP_MICROCHIP_ID/SFDP_SST_ID - don't drop all information we extracted from BFPT if optional table parsers fail. In case of failing, each optional SFDP parser is responsible to roll back to the previously known spi_nor data. Tudor Ambarus (4): mtd: spi: spi-nor-core: Add SST vendor specific SFDP parser board: atmel: sama5d27_wlsom1_ek: Set ethaddr from spi-nor flash configs: sama5d27_wlsom1_ek: qspiflash: Enable SPI NOR ethaddr retrieval configs: sama5d27_wlsom1_ek: mmc: Enable SPI NOR ethaddr retrieval arch/arm/mach-at91/include/mach/at91_common.h | 1 + board/atmel/common/Makefile| 1 + board/atmel/common/mac-spi-nor.c | 127 + .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 3 + configs/sama5d27_wlsom1_ek_mmc_defconfig | 5 + configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 1 + drivers/mtd/spi/spi-nor-core.c | 46 +++- include/linux/mtd/spi-nor.h| 2 + 8 files changed, 184 insertions(+), 2 deletions(-) create mode 100644 board/atmel/common/mac-spi-nor.c -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] configs: sama5d27_wlsom1_ek: mmc: Enable SPI NOR ethaddr retrieval
From: Tudor Ambarus Enable the SPI NOR SFDP support and the Microchip QSPI driver. CONFIG_SPI_FLASH_SFDP_SUPPORT enables the SFDP Vendor parser, and for the SST case, the retrieval of the ethaddr from the SPI NOR flash. While touching the SPI NOR logic, sync with the sama5d27_wlsom1_ek_qspiflash_defconfig and enable CONFIG_SPI_FLASH_SPANSION. Signed-off-by: Tudor Ambarus --- configs/sama5d27_wlsom1_ek_mmc_defconfig | 5 + 1 file changed, 5 insertions(+) diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index ffafc21ab3ce..ad59e73999b5 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -65,8 +65,12 @@ CONFIG_DM_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=2 +CONFIG_SF_DEFAULT_SPEED=5000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHY_MICREL=y @@ -81,6 +85,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 3/4] configs: sama5d27_wlsom1_ek: qspiflash: Enable SPI NOR ethaddr retrieval
From: Tudor Ambarus CONFIG_SPI_FLASH_SFDP_SUPPORT enables the SFDP Vendor parser, and for the SST case, the retrieval of the ethaddr from the SPI NOR flash. Signed-off-by: Tudor Ambarus --- configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 3196a88f1131..26a06270b276 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -78,6 +78,7 @@ CONFIG_MMC_SDHCI_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=5000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 2/4] board: atmel: sama5d27_wlsom1_ek: Set ethaddr from spi-nor flash
From: Tudor Ambarus
The SST26VF064BEUI spi-nor flash is programmed at the factory with a
globally unique address stored in the SFDP vendor parameter table and
it is permanently writeprotected. Retrieve the EUI-48 address and set it
as ethaddr env.
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/include/mach/at91_common.h | 1 +
board/atmel/common/Makefile| 1 +
board/atmel/common/mac-spi-nor.c | 127 +
.../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 3 +
4 files changed, 132 insertions(+)
create mode 100644 board/atmel/common/mac-spi-nor.c
diff --git a/arch/arm/mach-at91/include/mach/at91_common.h
b/arch/arm/mach-at91/include/mach/at91_common.h
index e929b5e1d207..01e00c508a8a 100644
--- a/arch/arm/mach-at91/include/mach/at91_common.h
+++ b/arch/arm/mach-at91/include/mach/at91_common.h
@@ -40,6 +40,7 @@ void configure_ddrcfg_input_buffers(bool open);
#endif
int at91_set_ethaddr(int offset);
+void at91_spi_nor_set_ethaddr(void);
int at91_video_show_board_info(void);
#endif /* AT91_COMMON_H */
diff --git a/board/atmel/common/Makefile b/board/atmel/common/Makefile
index 4de0912f22e6..6bc8cabb8d6d 100644
--- a/board/atmel/common/Makefile
+++ b/board/atmel/common/Makefile
@@ -5,4 +5,5 @@
obj-y += board.o
obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o
+obj-$(CONFIG_SPI_FLASH_SFDP_SUPPORT) += mac-spi-nor.o
obj-$(CONFIG_DM_VIDEO) += video_display.o
diff --git a/board/atmel/common/mac-spi-nor.c b/board/atmel/common/mac-spi-nor.c
new file mode 100644
index ..96343678e0b6
--- /dev/null
+++ b/board/atmel/common/mac-spi-nor.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Tudor Ambarus
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define ETH_ADDR_SIZE 6
+
+#ifdef CONFIG_SPI_FLASH_SST
+#define SFDP_MICROCHIP_MANUF_ID0xbf
+#define SFDP_MICROCHIP_MEM_TYPE0x26
+#define SFDP_MICROCHIP_DEV_ID 0x43
+
+#define SFDP_MICROCHIP_EUI_OFFSET 0x60
+#define SFDP_MICROCHIP_EUI48 0x30
+
+struct sst26vf064beui {
+ u8 manufacturer_id;
+ u8 memory_type;
+ u8 device_id;
+ u8 reserved;
+};
+
+/**
+ * sst26vf064beui_check() - Check the validity of the EUI-48 information from
+ * the sst26vf064beui SPI NOR Microchip SFDP table.
+ * @manufacturer_sfdp: pointer to the Microchip manufacturer specific SFDP
+ * table.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int sst26vf064beui_check(const u8 *manufacturer_sfdp)
+{
+ struct sst26vf064beui *sst26vf064beui =
+ (struct sst26vf064beui *)manufacturer_sfdp;
+
+ if (sst26vf064beui->manufacturer_id != SFDP_MICROCHIP_MANUF_ID)
+ return -EINVAL;
+
+ if (sst26vf064beui->memory_type != SFDP_MICROCHIP_MEM_TYPE)
+ return -EINVAL;
+
+ if (sst26vf064beui->device_id != SFDP_MICROCHIP_DEV_ID)
+ return -EINVAL;
+
+ /*
+* Check if the EUI-48 MAC address is programmed in the next six address
+* locations.
+*/
+ if (manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET] !=
+ SFDP_MICROCHIP_EUI48)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * sst26vf064beui_get_ethaddr() - Get the ethernet address from the
+ * sst26vf064beui SPI NOR Microchip SFDP table.
+ * @manufacturer_sfdp: pointer to the Microchip manufacturer specific SFDP
+ * table.
+ * @ethaddr: pointer where to fill the ethernet address
+ * @size: size of the ethernet address.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int sst26vf064beui_get_ethaddr(const u8 *manufacturer_sfdp,
+ u8 *ethaddr, size_t size)
+{
+ u64 eui_table[2];
+ u64 *p = (u64 *)&manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET];
+ int i, ret;
+
+ ret = sst26vf064beui_check(manufacturer_sfdp);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < 2; i++)
+ eui_table[i] = le64_to_cpu(p[i]);
+
+ /* Ethaddr starts at offset one. */
+ memcpy(ethaddr, &((u8 *)eui_table)[1], size);
+
+ return 0;
+}
+#endif
+
+/**
+ * at91_spi_nor_set_ethaddr() - Retrieve and set the ethernet address from the
+ * SPI NOR manufacturer specific SFDP table.
+ */
+void at91_spi_nor_set_ethaddr(void)
+{
+ struct udevice *dev;
+ struct spi_nor *nor;
+ const char *ethaddr_name = "ethaddr";
+ u8 ethaddr[ETH_ADDR_SIZE] = {0};
+
+ if (env_get(ethaddr_name))
+ return;
+
+ if (uclass_first_device_err(UCLASS_SPI_FLASH, &dev))
+ return;
+
+ nor = dev_get_uclass_priv(dev);
+ if (!nor)
+ return;
+
+ if (!nor->manufacturer_sfdp)
+ return;
+
+#ifdef CONFIG_SPI_FLASH_SST
+
Re: [U-Boot] [PATCH 1/2] spi: cadence_qspi: Move to spi-mem framework
Hi, Simon, Vignesh,
On 10/17/2019 02:20 PM, Simon Goldschmidt wrote:
> On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
>> Current Cadence QSPI driver has few limitations. It assumes all read
>> operations to be in Quad mode and thus does not support SFDP parsing.
>> Also, adding support for new mode such as Octal mode would not be
>> possible with current configuration. Therefore move the driver over to
>> spi-mem
>> framework. This has added advantage that driver can be used to support
>> SPI NAND memories too.
>> Hence, move driver over to new spi-mem APIs.
>>
>> Please note that this gets rid of mode bit setting done when
>> CONFIG_SPL_SPI_XIP is defined as there does not seem to be any user to
>> that config option.
> I just have tried this on an socfgpa cylone5 board with an mt25ql256a, but
> it does not seem to work: when leaving spi-rx-bus-width and spi-tx-bus-width
> at 4 in my devicetree, SFDP parsing works, but reading data afterwards
> produces invalid results (I haven't tested what's wrong there).
>
> It works as expected when not parsing SFDP or setting the bus-width to 1.
> So the change itself probably works, but SFDP parsing is broken?
This can happen if the quad enable method is not correctly set/called. Would you
try the patch form below?
I don't see much benefit in having those guards, especially that we have
SPI_FLASH_SFDP_SUPPORT defined - it trims most of the SFDP logic.
More, these #ifdef guards are not scalable and with the addition of flashes that
support SFDP the #ifdefs will look uglier and uglier.
Cheers,
ta
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index e5b9899c64b2..3002f97a7342 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -188,7 +188,6 @@ static int read_fsr(struct spi_nor *nor)
* location. Return the configuration register value.
* Returns negative if error occurred.
*/
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
static int read_cr(struct spi_nor *nor)
{
int ret;
@@ -202,7 +201,6 @@ static int read_cr(struct spi_nor *nor)
return val;
}
-#endif
/*
* Write status register 1 byte
@@ -591,7 +589,6 @@ erase_err:
return ret;
}
-#if defined(CONFIG_SPI_FLASH_STMICRO) || defined(CONFIG_SPI_FLASH_SST)
/* Write status register and ensure bits in mask match written values */
static int write_sr_and_check(struct spi_nor *nor, u8 status_new, u8 mask)
{
@@ -877,7 +874,6 @@ static int stm_is_locked(struct spi_nor *nor, loff_t ofs,
uint64_t len)
return stm_is_locked_sr(nor, ofs, len, status);
}
-#endif /* CONFIG_SPI_FLASH_STMICRO */
static const struct flash_info *spi_nor_read_id(struct spi_nor *nor)
{
@@ -1116,7 +1112,6 @@ write_err:
return ret;
}
-#ifdef CONFIG_SPI_FLASH_MACRONIX
/**
* macronix_quad_enable() - set QE bit in Status Register.
* @nor: pointer to a 'struct spi_nor'
@@ -1153,9 +1148,7 @@ static int macronix_quad_enable(struct spi_nor *nor)
return 0;
}
-#endif
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
/*
* Write status Register and configuration register with 2 bytes
* The first byte will be written to the status register, while the
@@ -1269,7 +1262,6 @@ static int spansion_no_read_cr_quad_enable(struct spi_nor
*nor)
}
#endif /* CONFIG_SPI_FLASH_SFDP_SUPPORT */
-#endif /* CONFIG_SPI_FLASH_SPANSION */
struct spi_nor_read_command {
u8 num_mode_clocks;
@@ -1787,22 +1779,16 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
case BFPT_DWORD15_QER_NONE:
params->quad_enable = NULL;
break;
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case BFPT_DWORD15_QER_SR2_BIT1_BUGGY:
case BFPT_DWORD15_QER_SR2_BIT1_NO_RD:
params->quad_enable = spansion_no_read_cr_quad_enable;
break;
-#endif
-#ifdef CONFIG_SPI_FLASH_MACRONIX
case BFPT_DWORD15_QER_SR1_BIT6:
params->quad_enable = macronix_quad_enable;
break;
-#endif
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
case BFPT_DWORD15_QER_SR2_BIT1:
params->quad_enable = spansion_read_cr_quad_enable;
break;
-#endif
default:
return -EINVAL;
}
@@ -2013,20 +1999,16 @@ static int spi_nor_init_params(struct spi_nor *nor,
if (params->hwcaps.mask & (SNOR_HWCAPS_READ_QUAD |
SNOR_HWCAPS_PP_QUAD)) {
switch (JEDEC_MFR(info)) {
-#ifdef CONFIG_SPI_FLASH_MACRONIX
case SNOR_MFR_MACRONIX:
params->quad_enable = macronix_quad_enable;
break;
-#endif
case SNOR_MFR_ST:
case SNOR_MFR_MICRON:
break;
default:
-#if defined(CONFIG_SPI_FLASH_SPANSIO
Re: [U-Boot] [PATCH 1/4] mtd: spi: spi-nor-core: Add Microchip SFDP parser
On 10/09/2019 07:25 PM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
>
> On 09-Oct-19 9:20 PM, tudor.amba...@microchip.com wrote:
>> Hi, Vignesh,
>>
>> On 10/09/2019 03:04 PM, Vignesh Raghavendra wrote:
>>> External E-Mail
>>>
>>>
>>> Hi Tudor,
>>>
>>> On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote:
From: Tudor Ambarus
JESD216 allow vendors to define their own SFDP tables.
Add Microchip SFDP parser. The vendor table is allocated using
resource-managed kmalloc - the table will be freed on driver detach.
It will be accessible by getting the UCLASS_SPI_FLASH's private data.
The Michrochip's SFDP table is particularly of interest because contains
pre-programmed globally unique EUI-48 and EUI-64 identifiers.
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi/spi-nor-core.c | 35 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 37 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c
b/drivers/mtd/spi/spi-nor-core.c
index 1acff745d1a2..bade7d8a9f79 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1417,6 +1417,7 @@ struct sfdp_parameter_header {
#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table
*/
#define SFDP_SECTOR_MAP_ID0xff81 /* Sector Map Table */
+#define SFDP_MICROCHIP_ID 0x01bf /* Manufacturer specific Table */
>>> Is this ID unique enough such that no other vendor will use the same? I
>>> recall that MSB byte should be assigned to Vendor and 0x01 does not seem
>>> to be Microchip specific? Or did I miss something?
>>>
>>
>> It is unique.
>>
>> Quoting form JESD216 rev D, section "6.3.3 Definition of Parameter ID Field":
>> "The original JESD216 specification used only a one byte ID field to identify
>> the parameter table owner.
>> JESD216 revision A expanded the ID field to two bytes, MSB and LSB, because
>> a
>> single byte is
>> insufficient to uniquely identify all manufacturers ( vendors). The original
>> single byte parameter ID is
>> now referred to as the parameter ID LSB."
>>
>> In the Microchip's case, 01h is the Parameter ID MSB (respects the 01h-7fh
>> interval) and bfh is the Parameter ID LSB (has odd parity, which is correct).
>> Now I'm looking in the JEP106AZ standard (Standard Manufacturer’s
>> Identification Code): 01h MSB indicates the bank number (one), and bfh LSB
>> indicates the Manufacturer Identification code (which is bfh for SST).
>>
>
> Ah, thanks for the explanation! I was confused with bank number
> initially. Was also confused by the fact that there is an entry for
> Microchip Technology in JEP106AZ that reads 29. May be rename the macro
> to indicate SFDP_SST_ID?
Ok, will do so. Thanks!
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Re: [U-Boot] [PATCH 1/4] mtd: spi: spi-nor-core: Add Microchip SFDP parser
Hi, Vignesh, On 10/01/2019 11:59 AM, Tudor Ambarus - M18064 wrote: > @@ -1892,6 +1921,12 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor, > dev_info(dev, "non-uniform erase sector maps are not > supported yet.\n"); > break; > > + case SFDP_MICROCHIP_ID: > + err = spi_nor_parse_microchip_sfdp(nor, param_header); > + if (err) > + goto exit; This can be improved though. At this point the BFPT parser succeeded, and it would be a pity if we ignore the BFPT data when the vendor specific parser fails. The goto exit should be replaced by a break and a warning message to indicate when an optional parameter table fails. Please let me know if there are other comments, I'll send v2 if all the rest are ok. > + break; > + > default: > break; > } ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] mtd: spi: spi-nor-core: Add Microchip SFDP parser
Hi, Vignesh,
On 10/09/2019 03:04 PM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
> Hi Tudor,
>
> On 01/10/19 2:29 PM, tudor.amba...@microchip.com wrote:
>> From: Tudor Ambarus
>>
>> JESD216 allow vendors to define their own SFDP tables.
>>
>> Add Microchip SFDP parser. The vendor table is allocated using
>> resource-managed kmalloc - the table will be freed on driver detach.
>> It will be accessible by getting the UCLASS_SPI_FLASH's private data.
>>
>> The Michrochip's SFDP table is particularly of interest because contains
>> pre-programmed globally unique EUI-48 and EUI-64 identifiers.
>>
>> Signed-off-by: Tudor Ambarus
>> ---
>> drivers/mtd/spi/spi-nor-core.c | 35 +++
>> include/linux/mtd/spi-nor.h| 2 ++
>> 2 files changed, 37 insertions(+)
>>
>> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
>> index 1acff745d1a2..bade7d8a9f79 100644
>> --- a/drivers/mtd/spi/spi-nor-core.c
>> +++ b/drivers/mtd/spi/spi-nor-core.c
>> @@ -1417,6 +1417,7 @@ struct sfdp_parameter_header {
>>
>> #define SFDP_BFPT_ID0xff00 /* Basic Flash Parameter Table
>> */
>> #define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
>> +#define SFDP_MICROCHIP_ID 0x01bf /* Manufacturer specific Table */
>>
> Is this ID unique enough such that no other vendor will use the same? I
> recall that MSB byte should be assigned to Vendor and 0x01 does not seem
> to be Microchip specific? Or did I miss something?
>
It is unique.
Quoting form JESD216 rev D, section "6.3.3 Definition of Parameter ID Field":
"The original JESD216 specification used only a one byte ID field to identify
the parameter table owner.
JESD216 revision A expanded the ID field to two bytes, MSB and LSB, because a
single byte is
insufficient to uniquely identify all manufacturers ( vendors). The original
single byte parameter ID is
now referred to as the parameter ID LSB."
In the Microchip's case, 01h is the Parameter ID MSB (respects the 01h-7fh
interval) and bfh is the Parameter ID LSB (has odd parity, which is correct).
Now I'm looking in the JEP106AZ standard (Standard Manufacturer’s
Identification Code): 01h MSB indicates the bank number (one), and bfh LSB
indicates the Manufacturer Identification code (which is bfh for SST).
Cheers,
ta
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[U-Boot] [PATCH 4/4] configs: sama5d27_wlsom1_ek: mmc: Enable SPI NOR ethaddr retrieval
From: Tudor Ambarus Enable the SPI NOR SFDP support and the Microchip QSPI driver. CONFIG_SPI_FLASH_SFDP_SUPPORT enables the SFDP Vendor parser, and for the Microchip case, the retrieval of the ethaddr from the SPI NOR flash. While touching the SPI NOR logic, sync with the sama5d27_wlsom1_ek_qspiflash_defconfig and enable CONFIG_SPI_FLASH_SPANSION. Signed-off-by: Tudor Ambarus --- configs/sama5d27_wlsom1_ek_mmc_defconfig | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 50a8a8e83ccb..0b2b480e338a 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -17,6 +17,7 @@ CONFIG_DEBUG_UART_CLOCK=8200 CONFIG_SPL_FS_FAT=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y +CONFIG_SPL_TEXT_BASE=0x20 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" @@ -26,7 +27,6 @@ CONFIG_USE_BOOTARGS=y CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y -CONFIG_SPL_TEXT_BASE=0x20 CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set @@ -67,8 +67,12 @@ CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_ATMEL=y CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_BUS=2 +CONFIG_SF_DEFAULT_SPEED=5000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_PHY_MICREL=y @@ -83,6 +87,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 3/4] configs: sama5d27_wlsom1_ek: qspiflash: Enable SPI NOR ethaddr retrieval
From: Tudor Ambarus CONFIG_SPI_FLASH_SFDP_SUPPORT enables the SFDP Vendor parser, and for the Microchip case, the retrieval of the ethaddr from the SPI NOR flash. Signed-off-by: Tudor Ambarus --- configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index 82568e286d81..e7a9cc302d3e 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -31,8 +31,8 @@ CONFIG_SPL_SEPARATE_BSS=y CONFIG_SPL_DISPLAY_PRINT=y # CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR is not set CONFIG_SPL_SPI_LOAD=y -CONFIG_SPL_AT91_MCK_BYPASS=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x4 +CONFIG_SPL_AT91_MCK_BYPASS=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_FLASH is not set @@ -80,6 +80,7 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=2 CONFIG_SF_DEFAULT_SPEED=5000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_SPANSION=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 2/4] board: atmel: sama5d27_wlsom1_ek: Set ethaddr from spi-nor flash
From: Tudor Ambarus
The SST26VF064BEUI spi-nor flash is programmed at the factory with a
globally unique address stored in the SFDP vendor parameter table and
it is permanently writeprotected. Retrieve the EUI-48 address and set it
as ethaddr env.
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/include/mach/at91_common.h | 1 +
board/atmel/common/Makefile| 1 +
board/atmel/common/mac-spi-nor.c | 127 +
.../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 3 +
4 files changed, 132 insertions(+)
create mode 100644 board/atmel/common/mac-spi-nor.c
diff --git a/arch/arm/mach-at91/include/mach/at91_common.h
b/arch/arm/mach-at91/include/mach/at91_common.h
index e929b5e1d207..01e00c508a8a 100644
--- a/arch/arm/mach-at91/include/mach/at91_common.h
+++ b/arch/arm/mach-at91/include/mach/at91_common.h
@@ -40,6 +40,7 @@ void configure_ddrcfg_input_buffers(bool open);
#endif
int at91_set_ethaddr(int offset);
+void at91_spi_nor_set_ethaddr(void);
int at91_video_show_board_info(void);
#endif /* AT91_COMMON_H */
diff --git a/board/atmel/common/Makefile b/board/atmel/common/Makefile
index 4de0912f22e6..6bc8cabb8d6d 100644
--- a/board/atmel/common/Makefile
+++ b/board/atmel/common/Makefile
@@ -5,4 +5,5 @@
obj-y += board.o
obj-$(CONFIG_I2C_EEPROM) += mac_eeprom.o
+obj-$(CONFIG_SPI_FLASH_SFDP_SUPPORT) += mac-spi-nor.o
obj-$(CONFIG_DM_VIDEO) += video_display.o
diff --git a/board/atmel/common/mac-spi-nor.c b/board/atmel/common/mac-spi-nor.c
new file mode 100644
index ..96343678e0b6
--- /dev/null
+++ b/board/atmel/common/mac-spi-nor.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Tudor Ambarus
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#define ETH_ADDR_SIZE 6
+
+#ifdef CONFIG_SPI_FLASH_SST
+#define SFDP_MICROCHIP_MANUF_ID0xbf
+#define SFDP_MICROCHIP_MEM_TYPE0x26
+#define SFDP_MICROCHIP_DEV_ID 0x43
+
+#define SFDP_MICROCHIP_EUI_OFFSET 0x60
+#define SFDP_MICROCHIP_EUI48 0x30
+
+struct sst26vf064beui {
+ u8 manufacturer_id;
+ u8 memory_type;
+ u8 device_id;
+ u8 reserved;
+};
+
+/**
+ * sst26vf064beui_check() - Check the validity of the EUI-48 information from
+ * the sst26vf064beui SPI NOR Microchip SFDP table.
+ * @manufacturer_sfdp: pointer to the Microchip manufacturer specific SFDP
+ * table.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int sst26vf064beui_check(const u8 *manufacturer_sfdp)
+{
+ struct sst26vf064beui *sst26vf064beui =
+ (struct sst26vf064beui *)manufacturer_sfdp;
+
+ if (sst26vf064beui->manufacturer_id != SFDP_MICROCHIP_MANUF_ID)
+ return -EINVAL;
+
+ if (sst26vf064beui->memory_type != SFDP_MICROCHIP_MEM_TYPE)
+ return -EINVAL;
+
+ if (sst26vf064beui->device_id != SFDP_MICROCHIP_DEV_ID)
+ return -EINVAL;
+
+ /*
+* Check if the EUI-48 MAC address is programmed in the next six address
+* locations.
+*/
+ if (manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET] !=
+ SFDP_MICROCHIP_EUI48)
+ return -EINVAL;
+
+ return 0;
+}
+
+/**
+ * sst26vf064beui_get_ethaddr() - Get the ethernet address from the
+ * sst26vf064beui SPI NOR Microchip SFDP table.
+ * @manufacturer_sfdp: pointer to the Microchip manufacturer specific SFDP
+ * table.
+ * @ethaddr: pointer where to fill the ethernet address
+ * @size: size of the ethernet address.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int sst26vf064beui_get_ethaddr(const u8 *manufacturer_sfdp,
+ u8 *ethaddr, size_t size)
+{
+ u64 eui_table[2];
+ u64 *p = (u64 *)&manufacturer_sfdp[SFDP_MICROCHIP_EUI_OFFSET];
+ int i, ret;
+
+ ret = sst26vf064beui_check(manufacturer_sfdp);
+ if (ret)
+ return ret;
+
+ for (i = 0; i < 2; i++)
+ eui_table[i] = le64_to_cpu(p[i]);
+
+ /* Ethaddr starts at offset one. */
+ memcpy(ethaddr, &((u8 *)eui_table)[1], size);
+
+ return 0;
+}
+#endif
+
+/**
+ * at91_spi_nor_set_ethaddr() - Retrieve and set the ethernet address from the
+ * SPI NOR manufacturer specific SFDP table.
+ */
+void at91_spi_nor_set_ethaddr(void)
+{
+ struct udevice *dev;
+ struct spi_nor *nor;
+ const char *ethaddr_name = "ethaddr";
+ u8 ethaddr[ETH_ADDR_SIZE] = {0};
+
+ if (env_get(ethaddr_name))
+ return;
+
+ if (uclass_first_device_err(UCLASS_SPI_FLASH, &dev))
+ return;
+
+ nor = dev_get_uclass_priv(dev);
+ if (!nor)
+ return;
+
+ if (!nor->manufacturer_sfdp)
+ return;
+
+#ifdef CONFIG_SPI_FLASH_SST
+
[U-Boot] [PATCH 1/4] mtd: spi: spi-nor-core: Add Microchip SFDP parser
From: Tudor Ambarus
JESD216 allow vendors to define their own SFDP tables.
Add Microchip SFDP parser. The vendor table is allocated using
resource-managed kmalloc - the table will be freed on driver detach.
It will be accessible by getting the UCLASS_SPI_FLASH's private data.
The Michrochip's SFDP table is particularly of interest because contains
pre-programmed globally unique EUI-48 and EUI-64 identifiers.
Signed-off-by: Tudor Ambarus
---
drivers/mtd/spi/spi-nor-core.c | 35 +++
include/linux/mtd/spi-nor.h| 2 ++
2 files changed, 37 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1acff745d1a2..bade7d8a9f79 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1417,6 +1417,7 @@ struct sfdp_parameter_header {
#define SFDP_BFPT_ID 0xff00 /* Basic Flash Parameter Table */
#define SFDP_SECTOR_MAP_ID 0xff81 /* Sector Map Table */
+#define SFDP_MICROCHIP_ID 0x01bf /* Manufacturer specific Table */
#define SFDP_SIGNATURE 0x50444653U
#define SFDP_JESD216_MAJOR 1
@@ -1797,6 +1798,34 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
}
/**
+ * spi_nor_parse_microchip_sfdp() - parse the Microchip manufacturer specific
+ * SFDP table.
+ * @nor: pointer to a 'struct spi_nor'.
+ * @param_header: pointer to the SFDP parameter header.
+ *
+ * Return: 0 on success, -errno otherwise.
+ */
+static int
+spi_nor_parse_microchip_sfdp(struct spi_nor *nor,
+const struct sfdp_parameter_header *param_header)
+{
+ size_t size;
+ u32 addr;
+ int ret;
+
+ size = param_header->length * sizeof(u32);
+ addr = SFDP_PARAM_HEADER_PTP(param_header);
+
+ nor->manufacturer_sfdp = devm_kmalloc(nor->dev, size, GFP_KERNEL);
+ if (!nor->manufacturer_sfdp)
+ return -ENOMEM;
+
+ ret = spi_nor_read_sfdp(nor, addr, size, nor->manufacturer_sfdp);
+
+ return ret;
+}
+
+/**
* spi_nor_parse_sfdp() - parse the Serial Flash Discoverable Parameters.
* @nor: pointer to a 'struct spi_nor'
* @params:pointer to the 'struct spi_nor_flash_parameter' to be
@@ -1892,6 +1921,12 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
dev_info(dev, "non-uniform erase sector maps are not
supported yet.\n");
break;
+ case SFDP_MICROCHIP_ID:
+ err = spi_nor_parse_microchip_sfdp(nor, param_header);
+ if (err)
+ goto exit;
+ break;
+
default:
break;
}
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 88e80af57941..836a50178925 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -251,6 +251,7 @@ struct flash_info;
* @lock: the lock for the read/write/erase/lock/unlock operations
* @dev: point to a spi device, or a spi nor controller device.
* @info: spi-nor part JDEC MFR id and other info
+ * @manufacturer_sfdp: manufacturer specific SFDP table
* @page_size: the page size of the SPI NOR
* @addr_width:number of address bytes
* @erase_opcode: the opcode for erasing a sector
@@ -289,6 +290,7 @@ struct spi_nor {
struct udevice *dev;
struct spi_slave*spi;
const struct flash_info *info;
+ u8 *manufacturer_sfdp;
u32 page_size;
u8 addr_width;
u8 erase_opcode;
--
2.9.5
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[U-Boot] [PATCH 0/4] mtd: spi: spi-nor-core: Add Microchip SFDP parser
From: Tudor Ambarus Parse manufacturer specific SFDP table. The Microchip SFDP table contains pre-programmed globally unique MAC addresses. Retrieve the MAC address from the SPI NOR flash and set it in ethaddr in env. This can go through Eugen's tree if no obiections. Otherwise Eugen should take care to apply the Microchip specific code after Jagan's/Vignesh's tree gets merged. Tudor Ambarus (4): mtd: spi: spi-nor-core: Add Microchip SFDP parser board: atmel: sama5d27_wlsom1_ek: Set ethaddr from spi-nor flash configs: sama5d27_wlsom1_ek: qspiflash: Enable SPI NOR ethaddr retrieval configs: sama5d27_wlsom1_ek: mmc: Enable SPI NOR ethaddr retrieval arch/arm/mach-at91/include/mach/at91_common.h | 1 + board/atmel/common/Makefile| 1 + board/atmel/common/mac-spi-nor.c | 127 + .../atmel/sama5d27_wlsom1_ek/sama5d27_wlsom1_ek.c | 3 + configs/sama5d27_wlsom1_ek_mmc_defconfig | 7 +- configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 3 +- drivers/mtd/spi/spi-nor-core.c | 35 ++ include/linux/mtd/spi-nor.h| 2 + 8 files changed, 177 insertions(+), 2 deletions(-) create mode 100644 board/atmel/common/mac-spi-nor.c -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v2 3/3] spi-nor: spi-nor-ids: Add USE_FSR flag for mt25qu512a entry
On 09/27/2019 07:43 AM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
> mt25qu512a flash has Flag status register that indicates various errors
> that may be encountered during erase/write operations. Therefore add
> USE_FSR flag to the entry
>
n25q256 & 512 support flag status register command. Would you add the flag for
them too? mtq256 probably too.
> Signed-off-by: Vignesh Raghavendra
anyway, looks good:
Reviewed-by: Tudor Ambarus
> ---
> drivers/mtd/spi/spi-nor-ids.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index c7b6cf002c54..2e0aebbc44aa 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -166,7 +166,8 @@ const struct flash_info spi_nor_ids[] = {
> { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_QUAD_READ) },
> { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
> - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES |
> + USE_FSR) },
> { INFO("n25q512a",0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ) },
> { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ) },
>
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Re: [U-Boot] [PATCH RFT v2 2/3] spi-nor: spi-nor-ids: Add entries for mt25q variants
On 09/27/2019 07:43 AM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
> Newer variants of mt25q* flashes support 4 Byte addressing opcodes. Add
nit: "drop newer variants of"
> entries for the same. These flashes have bit 6 set in 5th byte of READ ID
> response.
>
> Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
I'm thinking out loud. If just the 6th bit of the 5th byte of the device ID is
the differentiator between the n25q and the mt25q flavors, maybe in future we
should introduce a mask to INFO6. But it's ok for now.
> ---
> drivers/mtd/spi/spi-nor-ids.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index bb67661b40d2..c7b6cf002c54 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -161,11 +161,14 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("n25q064a",0x20bb17, 0, 64 * 1024, 128, SECT_4K |
> SPI_NOR_QUAD_READ) },
> { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> + { INFO6("mt25ql256a",0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("n25q256a",0x20ba19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_QUAD_READ) },
> { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
>SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("n25q512a",0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ) },
> + { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K |
> USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ) },
> { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>
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Re: [U-Boot] [PATCH RFT v2 1/3] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*
On 09/27/2019 07:43 AM, Vignesh Raghavendra wrote:
> External E-Mail
>
>
> Older variants of n25q256* and n25q512* do not support 4 Byte stateless
nit: drop "older variants of". Looks like the latest datasheet still require
ENTER and EXIT 4-byte address mode commands.
> addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these
> entries.
>
> Signed-off-by: Vignesh Raghavendra
Reviewed-by: Tudor Ambarus
> ---
> drivers/mtd/spi/spi-nor-ids.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
> index df0643ed1d47..bb67661b40d2 100644
> --- a/drivers/mtd/spi/spi-nor-ids.c
> +++ b/drivers/mtd/spi/spi-nor-ids.c
> @@ -161,12 +161,12 @@ const struct flash_info spi_nor_ids[] = {
> { INFO("n25q064a",0x20bb17, 0, 64 * 1024, 128, SECT_4K |
> SPI_NOR_QUAD_READ) },
> { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K |
> SPI_NOR_QUAD_READ) },
> - { INFO("n25q256a",0x20ba19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> - { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> + { INFO("n25q256a",0x20ba19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
> + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K |
> SPI_NOR_QUAD_READ) },
> { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024,
>SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> - { INFO("n25q512a",0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> - { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
> + { INFO("n25q512a",0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ) },
> + { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ) },
> { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
> { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR |
> SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
>
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[U-Boot] [U-boot][PATCH v3 12/14] configs: sam9x60ek: Add QSPI_BOOT defines
From: Tudor Ambarus Cope with the offsets defined at: https://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections/demo_nandflash_map_lnx4sam6x.png The environment starts at 0x14 and it's of size 0x2. The device tree starts at 0x18 and it's of size 0x8. The zImage starts at 0x20 and it's of size 0x60. Signed-off-by: Tudor Ambarus --- include/configs/sam9x60ek.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index dbcbce3a2b80..5f89ae4a511a 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -78,6 +78,13 @@ "0x2200 0x20 0x60; " \ "nand read 0x2100 0x18 0x2; " \ "bootz 0x2200 - 0x2100" + +#elif defined(CONFIG_QSPI_BOOT) +/* bootstrap + u-boot + env + linux in SPI NOR flash */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x2100 0x18 0x8; " \ + "sf read 0x2200 0x20 0x60; " \ + "bootz 0x2200 - 0x2100" #endif /* -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [U-boot][PATCH v3 13/14] ARM: dts: at91: sam9x60ek: Enable qspi node
From: Tudor Ambarus
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.
Enable the qspi node together with the SST26VF064B qspi nor flash
memory. Booting from the QSPI NOR flash is now possible.
Signed-off-by: Tudor Ambarus
---
arch/arm/dts/sam9x60.dtsi | 29 +
arch/arm/dts/sam9x60ek-u-boot.dtsi | 28
arch/arm/dts/sam9x60ek.dts | 31 +++
3 files changed, 88 insertions(+)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index a66d0a278a87..9c16ba1e6a87 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -22,6 +22,7 @@
serial0 = &dbgu;
gpio0 = &pioA;
gpio1 = &pioB;
+ spi0 = &qspi;
};
clocks {
@@ -60,6 +61,17 @@
#size-cells = <1>;
ranges;
+ qspi: spi@f0014000 {
+ compatible = "microchip,sam9x60-qspi";
+ reg = <0xf0014000 0x100>, <0x7000
0x1000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ clocks = <&qspi_clk>, <&qspick>;
+ clock-names = "pclk", "qspick";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
macb0: ethernet@f802c000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
@@ -172,6 +184,18 @@
atmel,clk-divisors = <1 2 4 6>;
};
+ system: systemck {
+ compatible =
"atmel,at91rm9200-clk-system";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qspick: qspick {
+ #clock-cells = <0>;
+ reg = <19>;
+ clocks = <&mck>;
+ };
+ };
+
periph: periphck {
compatible =
"microchip,sam9x60-clk-peripheral";
#address-cells = <1>;
@@ -202,6 +226,11 @@
#clock-cells = <0>;
reg = <24>;
};
+
+ qspi_clk: qspi_clk {
+ #clock-cells = <0>;
+ reg = <35>;
+ };
};
generic: gck {
diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi
b/arch/arm/dts/sam9x60ek-u-boot.dtsi
index 68e220926e5e..93cf1262f6fc 100644
--- a/arch/arm/dts/sam9x60ek-u-boot.dtsi
+++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi
@@ -31,6 +31,10 @@
u-boot,dm-pre-reloc;
};
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
&pinctrl_dbgu {
u-boot,dm-pre-reloc;
};
@@ -39,10 +43,18 @@
u-boot,dm-pre-reloc;
};
+&pinctrl_qspi {
+ u-boot,dm-pre-reloc;
+};
+
&pioA {
u-boot,dm-pre-reloc;
};
+&pioB {
+ u-boot,dm-pre-reloc;
+};
+
&pmc {
u-boot,dm-pre-reloc;
};
@@ -59,6 +71,14 @@
u-boot,dm-pre-reloc;
};
+&system {
+ u-boot,dm-pre-reloc;
+};
+
+&qspick {
+ u-boot,dm-pre-reloc;
+};
+
&periph {
u-boot,dm-pre-reloc;
};
@@ -67,6 +87,10 @@
u-boot,dm-pre-reloc;
};
+&pioB_clk {
+ u-boot,dm-pre-reloc;
+};
+
&sdhci0_clk {
u-boot,dm-pre-reloc;
};
@@ -75,6 +99,10 @@
u-boot,dm-pre-reloc;
};
+&qspi_clk {
+ u-boot,dm-pre-reloc;
+};
+
&generic {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 6fe9f19f0bc7..63904272f08f 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -16,6 +16,37 @@
chosen {
stdout-path = &dbgu;
};
+
+ ahb {
+ apb {
+ qspi: spi@f0014000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ nor_flash: sst26vf064@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+
[U-Boot] [U-boot][PATCH v3 04/14] ARM: dts: Add dts files for sam9x60ek
From: Sandeep Sheriker Mallikarjun
add device tree files for sam9x60ek board with below changes.
- Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit)
- Add the reg property for the pinctrl node.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
are used by the board_init_f stage.
Signed-off-by: Sandeep Sheriker Mallikarjun
[prasanthi.chellaku...@microchip.com: fix style/whitespace issues]
Signed-off-by: Prasanthi Chellakumar
[nicolas.fe...@microchip.com:
- fix gclk,
- fix pio/pinctrl controller definition and allow to have more
than only PIOA for this SoC,
- removing pinctrl address]
Signed-off-by: Nicolas Ferre
[claudiu.bez...@microchip.com:
- use SAM9X60's compatible for pinctrl
- add drive strength and slew rate options for SDMMC0 pins.]
Signed-off-by: Claudiu Beznea
[tudor.amba...@microchip.com:
- u-boot,dm-pre-reloc property in dedicated file,
- fix pit len, starts from 0xFE40 and it is of len 0x10]
Signed-off-by: Tudor Ambarus
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sam9x60.dtsi | 225 +
arch/arm/dts/sam9x60ek-u-boot.dtsi | 104 +
arch/arm/dts/sam9x60ek.dts | 19
4 files changed, 350 insertions(+)
create mode 100644 arch/arm/dts/sam9x60.dtsi
create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi
create mode 100644 arch/arm/dts/sam9x60ek.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 250b9ba505aa..52027786ef50 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -690,6 +690,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
+dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb
+
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
new file mode 100644
index ..e880dc0068df
--- /dev/null
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M
+ */
+
+#include "skeleton.dtsi"
+#include
+#include
+#include
+#include
+#include
+
+/{
+ model = "Microchip SAM9X60 SoC";
+ compatible = "microchip,sam9x60";
+
+ aliases {
+ serial0 = &dbgu;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sdhci0: sdhci-host@8000 {
+ compatible = "microchip,sam9x60-sdhci";
+ reg = <0x8000 0x300>;
+ clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
+ clock-names = "hclock", "multclk", "baseclk";
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0>;
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dbgu: serial@f200 {
+ compatible = "atmel,at91sam9260-dbgu",
"atmel,at91sam9260-usart";
+ reg = <0xf200 0x200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&dbgu_clk>;
+ clock-names = "usart";
+ };
+
+ pinctrl {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "microchip,sam9x60-pinctrl",
"simple-bus";
+ ranges = <0xf400 0xf400 0x800>;
+ reg = <0xf400 0x200 /* pioA */
+ 0xf600 0x200 /* pioB */
+ 0xf800 0x200 /* pioC */
+ 0xfa00 0x200>; /* pioD */
+
+ /* shared pinctrl settings */
+ dbgu {
+
[U-Boot] [U-boot][PATCH v3 11/14] configs: Add sam9x60ek_nandflash_defconfig
From: Tudor Ambarus Boot from nand flash. Signed-off-by: Tudor Ambarus --- board/atmel/sam9x60ek/MAINTAINERS | 1 + configs/sam9x60ek_nandflash_defconfig | 53 +++ 2 files changed, 54 insertions(+) create mode 100644 configs/sam9x60ek_nandflash_defconfig diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS index e8c1346863a3..ec5bed7479ba 100644 --- a/board/atmel/sam9x60ek/MAINTAINERS +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -5,3 +5,4 @@ S: Maintained F: board/atmel/sam9x60ek/ F: include/configs/sam9x60ek.h F: configs/sam9x60ek_mmc_defconfig +F: configs/sam9x60ek_nandflash_defconfig diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig new file mode 100644 index ..948d7c7a7227 --- /dev/null +++ b/configs/sam9x60ek_nandflash_defconfig @@ -0,0 +1,53 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf200 +CONFIG_DEBUG_UART_CLOCK=2 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [U-boot][PATCH v3 14/14] configs: Add sam9x60ek_qspiflash_defconfig
From: Tudor Ambarus Boot from QSPI nor flash. The at91bootstrap, u-boot, u-boot env redundant, u-boot env, device tree and kernel will reside in the QSPI nor flash. The rootfs will reside in the NAND flash. Signed-off-by: Tudor Ambarus --- board/atmel/sam9x60ek/MAINTAINERS | 1 + configs/sam9x60ek_qspiflash_defconfig | 75 +++ 2 files changed, 76 insertions(+) create mode 100644 configs/sam9x60ek_qspiflash_defconfig diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS index ec5bed7479ba..d209249c2eff 100644 --- a/board/atmel/sam9x60ek/MAINTAINERS +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -6,3 +6,4 @@ F: board/atmel/sam9x60ek/ F: include/configs/sam9x60ek.h F: configs/sam9x60ek_mmc_defconfig F: configs/sam9x60ek_nandflash_defconfig +F: configs/sam9x60ek_qspiflash_defconfig diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig new file mode 100644 index ..0d0932bba3f8 --- /dev/null +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -0,0 +1,75 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf200 +CONFIG_DEBUG_UART_CLOCK=2 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=5000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [U-boot][PATCH v3 05/14] ARM: dts: at91: sam9x60: Add macb0 Ethernet controller
From: Nicolas Ferre
Add Ethernet controller to dtsi file and enable it on sam9x60ek
platform connected with rmii.
Signed-off-by: Nicolas Ferre
---
arch/arm/dts/sam9x60.dtsi | 31 +++
arch/arm/dts/sam9x60ek.dts | 5 +
2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index e880dc0068df..a66d0a278a87 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -60,6 +60,16 @@
#size-cells = <1>;
ranges;
+ macb0: ethernet@f802c000 {
+ compatible = "cdns,sam9x60-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ clock-names = "hclk", "pclk";
+ clocks = <&macb0_clk>, <&macb0_clk>;
+ status = "disabled";
+ };
+
dbgu: serial@f200 {
compatible = "atmel,at91sam9260-dbgu",
"atmel,at91sam9260-usart";
reg = <0xf200 0x200>;
@@ -88,6 +98,22 @@
};
};
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ ; /* PB10 periph A */
+ };
+ };
+
sdhci0 {
pinctrl_sdhci0: sdhci0 {
atmel,pins =
@@ -171,6 +197,11 @@
#clock-cells = <0>;
reg = <47>;
};
+
+ macb0_clk: macb0_clk {
+ #clock-cells = <0>;
+ reg = <24>;
+ };
};
generic: gck {
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index e64566ec8e58..6fe9f19f0bc7 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -17,3 +17,8 @@
stdout-path = &dbgu;
};
};
+
+&macb0 {
+ phy-mode = "rmii";
+ status = "okay";
+};
--
2.9.5
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[U-Boot] [U-boot][PATCH v3 08/14] ARM: at91: Rename sama5_sfr.h to at91_sfr.h
From: Tudor Ambarus
The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/armv7/sama5d4_devices.c | 2 +-
arch/arm/mach-at91/atmel_sfr.c | 2 +-
arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} | 4 ++--
board/laird/wb50n/wb50n.c | 2 +-
drivers/clk/at91/clk-utmi.c | 2 +-
5 files changed, 6 insertions(+), 6 deletions(-)
rename arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} (97%)
diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c
b/arch/arm/mach-at91/armv7/sama5d4_devices.c
index 5c693df2ecf0..e68ae9940788 100644
--- a/arch/arm/mach-at91/armv7/sama5d4_devices.c
+++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
@@ -8,7 +8,7 @@
#include
#include
#include
-#include
+#include
#include
char *get_cpu_name()
diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c
index 13cfba0ba0c0..b14222460f3a 100644
--- a/arch/arm/mach-at91/atmel_sfr.c
+++ b/arch/arm/mach-at91/atmel_sfr.c
@@ -7,7 +7,7 @@
#include
#include
#include
-#include
+#include
#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4)
void redirect_int_from_saic_to_aic(void)
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h
b/arch/arm/mach-at91/include/mach/at91_sfr.h
similarity index 97%
rename from arch/arm/mach-at91/include/mach/sama5_sfr.h
rename to arch/arm/mach-at91/include/mach/at91_sfr.h
index f9c412f9989a..dc259055cff6 100644
--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
+++ b/arch/arm/mach-at91/include/mach/at91_sfr.h
@@ -6,8 +6,8 @@
* Bo Shen
*/
-#ifndef __SAMA5_SFR_H
-#define __SAMA5_SFR_H
+#ifndef __AT91_SFR_H
+#define __AT91_SFR_H
struct atmel_sfr {
u32 reserved1; /* 0x00 */
diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c
index ab1dbcd879ae..13563abb49ef 100644
--- a/board/laird/wb50n/wb50n.c
+++ b/board/laird/wb50n/wb50n.c
@@ -4,7 +4,7 @@
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
index e8506099fd32..18af0bfeaad1 100644
--- a/drivers/clk/at91/clk-utmi.c
+++ b/drivers/clk/at91/clk-utmi.c
@@ -10,7 +10,7 @@
#include
#include
#include
-#include
+#include
#include "pmc.h"
/*
--
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[U-Boot] [U-boot][PATCH v3 10/14] board: sam9x60ek: Add NAND flash support
From: Tudor Ambarus
- EBI Chip Select Register is now in SFR,
- the pins are set to default values,
- timings are matching MT29F4G08BABWP's nand flash requirements.
Signed-off-by: Tudor Ambarus
---
board/atmel/sam9x60ek/sam9x60ek.c | 61 +++
include/configs/sam9x60ek.h | 28 ++
2 files changed, 89 insertions(+)
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c
b/board/atmel/sam9x60ek/sam9x60ek.c
index 62938741ddd6..e352afc67ed3 100644
--- a/board/atmel/sam9x60ek/sam9x60ek.c
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -7,8 +7,10 @@
#include
#include
+#include
#include
#include
+#include
#include
#include
#include
@@ -18,6 +20,62 @@ DECLARE_GLOBAL_DATA_PTR;
void at91_prepare_cpu_var(void);
+#ifdef CONFIG_CMD_NAND
+static void sam9x60ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+ unsigned int csa;
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
+
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+ /* Enable CS3 */
+ csa = readl(&sfr->ebicsa);
+ csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
+
+ /* Configure IO drive */
+ csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
+
+ writel(csa, &sfr->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
+ AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
+ &smc->cs[3].mode);
+}
+#endif
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
@@ -48,6 +106,9 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_CMD_NAND
+ sam9x60ek_nand_hw_init();
+#endif
return 0;
}
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index b778bd8e83eb..dbcbce3a2b80 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -42,6 +42,26 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x4000
+#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_MTD_DEVICE
+#endif
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP 8
+#define CONFIG_PMECC_SECTOR_SIZE 512
+
#define CONFIG_SYS_LOAD_ADDR 0x2200 /* load address */
#ifdef CONFIG_SD_BOOT
@@ -50,6 +70,14 @@
"fatload mmc 0:1 0x2100 at91-sam9x60ek.dtb;" \
"fatload mmc 0:1 0x2200 zImage;" \
"bootz 0x2200 - 0x2100"
+
+#elif defined(CONFIG_NAND_BOOT)
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET_REDUND 0x10
+#define CONFIG_BOOTCOMMAND "nand read " \
+ "0x2200 0x20 0x60; " \
+ "nand read 0x2100 0x18 0x2; " \
+ "bootz 0x2200 - 0x2100"
#endif
/*
--
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[U-Boot] [U-boot][PATCH v3 01/14] net: macb: Add sam9x60-macb compatibility string
From: Nicolas Ferre
Add this new compatibility string for matching sam9x60 product
macb.
Signed-off-by: Nicolas Ferre
---
drivers/net/macb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/net/macb.c b/drivers/net/macb.c
index c99cf663a416..e0f7b2350b20 100644
--- a/drivers/net/macb.c
+++ b/drivers/net/macb.c
@@ -1319,6 +1319,7 @@ static const struct macb_config sifive_config = {
static const struct udevice_id macb_eth_ids[] = {
{ .compatible = "cdns,macb" },
{ .compatible = "cdns,at91sam9260-macb" },
+ { .compatible = "cdns,sam9x60-macb" },
{ .compatible = "atmel,sama5d2-gem" },
{ .compatible = "atmel,sama5d3-gem" },
{ .compatible = "atmel,sama5d4-gem", .data = (ulong)&sama5d4_config },
--
2.9.5
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[U-Boot] [U-boot][PATCH v3 03/14] ARM: at91: Add sam9x60 soc
From: Sandeep Sheriker Mallikarjun
Add new Microchip sam9x60 SoC based on an ARM926.
Signed-off-by: Sandeep Sheriker Mallikarjun
[tudor.amba...@microchip.com: fix SFR definition]
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/Kconfig | 4 +
arch/arm/mach-at91/arm926ejs/Makefile | 1 +
arch/arm/mach-at91/arm926ejs/sam9x60_devices.c | 125 ++
arch/arm/mach-at91/include/mach/hardware.h | 2 +
arch/arm/mach-at91/include/mach/sam9x60.h | 169 +
5 files changed, 301 insertions(+)
create mode 100644 arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
create mode 100644 arch/arm/mach-at91/include/mach/sam9x60.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 14343280793b..3cf13042b7b4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -43,6 +43,10 @@ config AT91SAM9X5
bool
select CPU_ARM926EJS
+config SAM9X60
+ bool
+ select CPU_ARM926EJS
+
config SAMA5D2
bool
select CPU_V7A
diff --git a/arch/arm/mach-at91/arm926ejs/Makefile
b/arch/arm/mach-at91/arm926ejs/Makefile
index 6b0b28957af5..8de6a2f9661e 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
+obj-$(CONFIG_SAM9X60) += sam9x60_devices.o
obj-$(CONFIG_AT91_EFLASH) += eflash.o
obj-$(CONFIG_AT91_LED) += led.o
obj-y += clock.o
diff --git a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
new file mode 100644
index ..d463bbc78863
--- /dev/null
+++ b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+unsigned int get_chip_id(void)
+{
+ /* The 0x40 is the offset of cidr in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+ /* The 0x44 is the offset of exid in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x44);
+}
+
+unsigned int has_emac1(void)
+{
+ return cpu_is_sam9x60();
+}
+
+unsigned int has_emac0(void)
+{
+ return cpu_is_sam9x60();
+}
+
+unsigned int has_lcdc(void)
+{
+ return cpu_is_sam9x60();
+}
+
+char *get_cpu_name(void)
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sam9x60()) {
+ switch (extension_id) {
+ case ARCH_EXID_SAM9X60:
+ return "SAM9X60";
+ default:
+ return "Unknown CPU type";
+ }
+ } else {
+ return "Unknown CPU type";
+ }
+}
+
+void at91_seriald_hw_init(void)
+{
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 1); /* DRXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
+
+ at91_periph_clk_enable(ATMEL_ID_DBGU);
+}
+
+void at91_mci_hw_init(void)
+{
+ /* Initialize the SDMMC0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 1); /* CLK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 1); /* CMD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 1); /* DAT0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 1); /* DAT1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 1); /* DAT2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 1); /* DAT3 */
+
+ at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+}
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+ if (has_emac0()) {
+ /* Enable EMAC0 clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC0);
+ /* EMAC0 pins setup */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
+ }
+
+ if (has_emac1()) {
+ /* Enable EMAC1 clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC1);
+ /* EMAC1 pins setup */
+ at91_pio3_set_b_periph(AT91_PIO_POR
[U-Boot] [U-boot][PATCH v3 09/14] ARM: at91: Add SFR definitions
From: Tudor Ambarus
sama5's SFR has at offset 0x04 the DDR Configuration Register,
while sam9x60's SFR contains the EBI Chip Select Register. Add
a union to reconcile both boards.
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/include/mach/at91_sfr.h | 48 --
1 file changed, 45 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_sfr.h
b/arch/arm/mach-at91/include/mach/at91_sfr.h
index dc259055cff6..0300c336dd81 100644
--- a/arch/arm/mach-at91/include/mach/at91_sfr.h
+++ b/arch/arm/mach-at91/include/mach/at91_sfr.h
@@ -11,7 +11,10 @@
struct atmel_sfr {
u32 reserved1; /* 0x00 */
- u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ union {
+ u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ u32 ebicsa; /* 0x04: EBI Chip Select Register */
+ };
u32 reserved2; /* 0x08 */
u32 reserved3; /* 0x0c */
u32 ohciicr;/* 0x10: OHCI Interrupt Configuration Register */
@@ -28,7 +31,16 @@ struct atmel_sfr {
};
/* Register Mapping*/
+#define AT91_SFR_DDRCFG0x04/* DDR Configuration Register */
+#define AT91_SFR_CCFG_EBICSA 0x04/* EBI Chip Select Register */
+/* 0x08 ~ 0x0c: Reserved */
+#define AT91_SFR_OHCIICR 0x10/* OHCI INT Configuration Register */
+#define AT91_SFR_OHCIISR 0x14/* OHCI INT Status Register */
#define AT91_SFR_UTMICKTRIM0x30/* UTMI Clock Trimming Register */
+#define AT91_SFR_UTMISWAP 0x3c/* UTMI DP/DM Pin Swapping Register */
+#define AT91_SFR_LS0x7c/* Light Sleep Register */
+#define AT91_SFR_I2SCLKSEL 0x90/* I2SC Register */
+#define AT91_SFR_WPMR 0xe4/* Write Protection Mode Register */
/* Bit field in DDRCFG */
#define ATMEL_SFR_DDRCFG_FDQIEN0x0001
@@ -58,9 +70,39 @@ struct atmel_sfr {
#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)
#define AT91_SFR_EBICFG_SCH1_ON(0x1 << 12)
-#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
-
/* Bit field in AICREDIR */
#define ATMEL_SFR_AICREDIR_NSAIC 0x0001
+/* Bit field in DDRCFG */
+#define ATMEL_SFR_DDRCFG_FDQIEN0x0001
+#define ATMEL_SFR_DDRCFG_FDQSIEN 0x0002
+
+#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs))
+#define AT91_SFR_CCFG_EBI_DBPUCBIT(8)
+#define AT91_SFR_CCFG_EBI_DBPDCBIT(9)
+#define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60BIT(16)
+#define AT91_SFR_CCFG_EBI_DRIVEBIT(17)
+#define AT91_SFR_CCFG_DQIEN_F BIT(20)
+#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24)
+#define AT91_SFR_CCFG_DDR_MP_ENBIT(25)
+
+#define AT91_SFR_OHCIICR_RES(x)BIT(x)
+#define AT91_SFR_OHCIICR_ARIE BIT(4)
+#define AT91_SFR_OHCIICR_APPSTART BIT(5)
+#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x))
+#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23)
+#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8)
+
+#define AT91_SFR_OHCIISR_RIS(x)BIT(x)
+
+#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
+
+#define AT91_SFR_UTMISWAP_PORT(x) BIT(x)
+
+#define AT91_SFR_LS_VALUE(x) BIT(x)
+#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16)
+
+#define AT91_SFR_WPMR_WPEN BIT(0)
+#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)
+
#endif
--
2.9.5
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[U-Boot] [U-boot][PATCH v3 07/14] configs: Add sam9x60ek_mmc_defconfig
From: Sandeep Sheriker Mallikarjun add sam9x60ek_mmc_defconfig and for now only supports booting from sdcard. Signed-off-by: Sandeep Sheriker Mallikarjun Signed-off-by: Nicolas Ferre [nicolas.fe...@microchip.com: split patch, add Ethernet controller, phy and tools] [claudiu.bez...@microchip.com: add CONFIG_OF_LIBFDT_OVERLAY] Signed-off-by: Claudiu Beznea [tudor.amba...@microchip.com: Fix number of DRAM banks: One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks] Signed-off-by: Tudor Ambarus --- configs/sam9x60ek_mmc_defconfig | 52 + 1 file changed, 52 insertions(+) create mode 100644 configs/sam9x60ek_mmc_defconfig diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig new file mode 100644 index ..6cdc819a6793 --- /dev/null +++ b/configs/sam9x60ek_mmc_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf200 +CONFIG_DEBUG_UART_CLOCK=2 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [U-boot][PATCH v3 02/14] mmc: atmel_sdhci: Add sam9x60-sdhci compatibility string
From: Sandeep Sheriker Mallikarjun
Add new compatibility string for matching sam9x60 product.
Signed-off-by: Sandeep Sheriker Mallikarjun
---
drivers/mmc/atmel_sdhci.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/atmel_sdhci.c b/drivers/mmc/atmel_sdhci.c
index d930ed8da0e2..2b797c9bd400 100644
--- a/drivers/mmc/atmel_sdhci.c
+++ b/drivers/mmc/atmel_sdhci.c
@@ -112,6 +112,7 @@ static int atmel_sdhci_bind(struct udevice *dev)
static const struct udevice_id atmel_sdhci_ids[] = {
{ .compatible = "atmel,sama5d2-sdhci" },
+ { .compatible = "microchip,sam9x60-sdhci" },
{ }
};
--
2.9.5
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[U-Boot] [U-boot][PATCH v3 06/14] board: atmel: Add sam9x60ek board
From: Sandeep Sheriker Mallikarjun
Add new board SAM9X60-EK using the ARM926 SAM9X60 SoC.
Signed-off-by: Sandeep Sheriker Mallikarjun
[tudor.amba...@microchip.com:
- fix number of DRAM banks:
One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks]
- drop SPL related macros
- drop memtest macros
- drop CONFIG_SPI_BOOT, CONFIG_SYS_USE_DATAFLASH related macros
- drop inclusion of asm/arch/at91sam9_smc.h]
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/Kconfig| 7 +
board/atmel/sam9x60ek/Kconfig | 12
board/atmel/sam9x60ek/MAINTAINERS | 7 +
board/atmel/sam9x60ek/Makefile| 7 +
board/atmel/sam9x60ek/sam9x60ek.c | 59 ++
include/configs/sam9x60ek.h | 60 +++
6 files changed, 152 insertions(+)
create mode 100644 board/atmel/sam9x60ek/Kconfig
create mode 100644 board/atmel/sam9x60ek/MAINTAINERS
create mode 100644 board/atmel/sam9x60ek/Makefile
create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c
create mode 100644 include/configs/sam9x60ek.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 3cf13042b7b4..85524004f9e4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -160,6 +160,12 @@ config TARGET_GARDENA_SMART_GATEWAY_AT91SAM
select BOARD_LATE_INIT
select SUPPORT_SPL
+config TARGET_SAM9X60EK
+ bool "SAM9X60-EK board"
+ select SAM9X60
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+
config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
select BOARD_EARLY_INIT_F
@@ -316,6 +322,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sam9x60ek/Kconfig"
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
diff --git a/board/atmel/sam9x60ek/Kconfig b/board/atmel/sam9x60ek/Kconfig
new file mode 100644
index ..32fae2108e6e
--- /dev/null
+++ b/board/atmel/sam9x60ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAM9X60EK
+
+config SYS_BOARD
+ default "sam9x60ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_CONFIG_NAME
+ default "sam9x60ek"
+
+endif
diff --git a/board/atmel/sam9x60ek/MAINTAINERS
b/board/atmel/sam9x60ek/MAINTAINERS
new file mode 100644
index ..e8c1346863a3
--- /dev/null
+++ b/board/atmel/sam9x60ek/MAINTAINERS
@@ -0,0 +1,7 @@
+SAM9X60EK BOARD
+M: Sandeep Sheriker M
+M: Eugen Hristev
+S: Maintained
+F: board/atmel/sam9x60ek/
+F: include/configs/sam9x60ek.h
+F: configs/sam9x60ek_mmc_defconfig
diff --git a/board/atmel/sam9x60ek/Makefile b/board/atmel/sam9x60ek/Makefile
new file mode 100644
index ..12a406a3bb5c
--- /dev/null
+++ b/board/atmel/sam9x60ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Sandeep Sheriker M
+
+obj-y += sam9x60ek.o
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c
b/board/atmel/sam9x60ek/sam9x60ek.c
new file mode 100644
index ..62938741ddd6
--- /dev/null
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void at91_prepare_cpu_var(void);
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ at91_prepare_cpu_var();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
new file mode 100644
index ..b778bd8e83eb
--- /dev/null
+++ b/include/configs/sam9x60ek.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the SAM9X60EK board.
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 2400/* 24 MHz crystal */
[U-Boot] [U-boot][PATCH v3 00/14] Add support for sam9x60ek
From: Tudor Ambarus
Add support for sam9x60 SOC, sam9x60ek board, dts, NAND and QSPI.
Add defconfigs for MMC, NAND and QSPI.
v3:
- Enable MII utility commands and phy in qspi & nand defconfigs
- Add sam9x60-sdhci and sam9x60-macb compatibility strings
- nandflash_defconfig: Fix rootfs partition
v2: add maintainers for qspi & nand defconfigs
Nicolas Ferre (2):
net: macb: Add sam9x60-macb compatibility string
ARM: dts: at91: sam9x60: Add macb0 Ethernet controller
Sandeep Sheriker Mallikarjun (5):
mmc: atmel_sdhci: Add sam9x60-sdhci compatibility string
ARM: at91: Add sam9x60 soc
ARM: dts: Add dts files for sam9x60ek
board: atmel: Add sam9x60ek board
configs: Add sam9x60ek_mmc_defconfig
Tudor Ambarus (7):
ARM: at91: Rename sama5_sfr.h to at91_sfr.h
ARM: at91: Add SFR definitions
board: sam9x60ek: Add NAND flash support
configs: Add sam9x60ek_nandflash_defconfig
configs: sam9x60ek: Add QSPI_BOOT defines
ARM: dts: at91: sam9x60ek: Enable qspi node
configs: Add sam9x60ek_qspiflash_defconfig
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sam9x60.dtsi | 285 +
arch/arm/dts/sam9x60ek-u-boot.dtsi | 132 ++
arch/arm/dts/sam9x60ek.dts | 55
arch/arm/mach-at91/Kconfig | 11 +
arch/arm/mach-at91/arm926ejs/Makefile | 1 +
arch/arm/mach-at91/arm926ejs/sam9x60_devices.c | 125 +
arch/arm/mach-at91/armv7/sama5d4_devices.c | 2 +-
arch/arm/mach-at91/atmel_sfr.c | 2 +-
.../include/mach/{sama5_sfr.h => at91_sfr.h} | 52 +++-
arch/arm/mach-at91/include/mach/hardware.h | 2 +
arch/arm/mach-at91/include/mach/sam9x60.h | 169
board/atmel/sam9x60ek/Kconfig | 12 +
board/atmel/sam9x60ek/MAINTAINERS | 9 +
board/atmel/sam9x60ek/Makefile | 7 +
board/atmel/sam9x60ek/sam9x60ek.c | 120 +
board/laird/wb50n/wb50n.c | 2 +-
configs/sam9x60ek_mmc_defconfig| 52
configs/sam9x60ek_nandflash_defconfig | 53
configs/sam9x60ek_qspiflash_defconfig | 75 ++
drivers/clk/at91/clk-utmi.c| 2 +-
drivers/mmc/atmel_sdhci.c | 1 +
drivers/net/macb.c | 1 +
include/configs/sam9x60ek.h| 95 +++
24 files changed, 1258 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/dts/sam9x60.dtsi
create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi
create mode 100644 arch/arm/dts/sam9x60ek.dts
create mode 100644 arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
rename arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} (53%)
create mode 100644 arch/arm/mach-at91/include/mach/sam9x60.h
create mode 100644 board/atmel/sam9x60ek/Kconfig
create mode 100644 board/atmel/sam9x60ek/MAINTAINERS
create mode 100644 board/atmel/sam9x60ek/Makefile
create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c
create mode 100644 configs/sam9x60ek_mmc_defconfig
create mode 100644 configs/sam9x60ek_nandflash_defconfig
create mode 100644 configs/sam9x60ek_qspiflash_defconfig
create mode 100644 include/configs/sam9x60ek.h
--
2.9.5
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Re: [U-Boot] [PATCH RFT 3/3] spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and n25q512*
Hi, Simon,
On 09/24/2019 02:47 PM, Simon Goldschmidt wrote:
> External E-Mail
>
>
> On Tue, Sep 24, 2019 at 7:55 AM Vignesh Raghavendra wrote:
>>
>> Newer variants of n25q256* and n25q512* flashes support 4 Byte
>> addressing opcodes. Add entries for the same. These flashes Bit 6 set in
>> 5th byte of READ ID response.
>>
>> Signed-off-by: Vignesh Raghavendra
>> ---
>> drivers/mtd/spi/spi-nor-ids.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c
>> index 967537eafb55..0074073b123a 100644
>> --- a/drivers/mtd/spi/spi-nor-ids.c
>> +++ b/drivers/mtd/spi/spi-nor-ids.c
>> @@ -161,11 +161,14 @@ const struct flash_info spi_nor_ids[] = {
>> { INFO("n25q064a",0x20bb17, 0, 64 * 1024, 128, SECT_4K |
>> SPI_NOR_QUAD_READ) },
>> { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K |
>> SPI_NOR_QUAD_READ) },
>> { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K |
>> SPI_NOR_QUAD_READ) },
>> + { INFO6("n25q256a",0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K
>> | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) },
>
> From the discussion in the other thread, this should probably be named
> "mt25-something"? Seems like the 0x44 in the 5th byte wouldn't be found in the
> n25q256a?
>
Probably yes, but the ultimate test would be to dump all the JEDEC ID bytes from
the n25q256a flash, with code similar to that from below. It's not the first
time that we see manufacturers messing with the JEDEC IDs or with the SFDP
tables. It would be really helpful if you can dump the JEDEC ID bytes on a
n25q256a.
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1acff745d1a2..0be3496c5367 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -885,13 +885,16 @@ static const struct flash_info *spi_nor_read_id(struct
spi_nor *nor)
info = spi_nor_ids;
for (; info->name; info++) {
if (info->id_len) {
- if (!memcmp(info->id, id, info->id_len))
+ if (!memcmp(info->id, id, info->id_len)) {
+ dev_err(nor->dev, "JEDEC id bytes: %*ph\n",
+ SPI_NOR_MAX_ID_LEN, id);
return info;
+ }
}
}
- dev_err(nor->dev, "unrecognized JEDEC id bytes: %02x, %02x, %02x\n",
- id[0], id[1], id[2]);
+dev_err(nor->dev, "unrecognized JEDEC id bytes: %*ph\n",
+SPI_NOR_MAX_ID_LEN, id);
return ERR_PTR(-ENODEV);
}
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Re: [U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*
Hi, Simon, On 09/23/2019 12:30 PM, Simon Goldschmidt wrote: cut >>> > Subject: [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable >>> > SPI_NOR_4B_OPCODES for n25q512* and n25q256* >>> > >>> > Caution: EXT Email >>> > >>> > Not all variants of n25q256* and n25q512* support 4 Byte stateless >>> > addressing opcodes and there is no easy way to discover at runtime >>> whether >>> > the flash supports this feature or not. >>> > Therefore don't set SPI_NOR_4B_OPCODES for these flashes. >>> Hi Vignesh, >>> >>> I think it will be good to keep it here and disable this for boards >>> by using not set flag in config >>> Like >>> # SPI_NOR_4B_OPCODES is not set >>> >> >> SPI_NOR_4B_OPCODES is not a config option. Are you suggesting to add >> one? config options don't scale well especially when same defconfig is >> used for multiple boards that potentially have different flashes >> >>> >>> I'd prefer to take this patch, as this is what Linux does. >> >> No, this is not what Linux does. There is no opt-in or opt-out option. >> Decision to use 4 byte opcode is done at runtime based on flash that's >> detected. Either based on info->flags for that part or by parsing SFDP >> table. There is no config option of DT option to force 4 byte addressing >> >>> I think it's better to have an opt-in option. That way, all chips work with >>> the >>> default settings (even if that means some chips don't use 4 baste >>> opcodes even if they could). >>> >> >> One solution would be to look at SFDP tables of two variants of flash >> and see if there are any differences that can be used as a clue. >> >> Simon, >> Could you provide dump of SFDP tables and all the 6 bytes READ ID of the >> flash that you have? > > I have a n251256a with JEDEC ID 20, ba, 19, 10, 44, 00. Is this a n25q256a or a MT25QL256ABA? We want to check if there are n25q256a flashes that have the 6th bit of the Extended Device Id set to one or not. According to n25q256a datasheet the bit 6 is reserved (which probably translates to being zero), while on MT25QL256ABA is set to one. Cheers, ta ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH RFT 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q256 and n25q512*
Hi, Simon,
On 09/24/2019 10:02 AM, Simon Goldschmidt wrote:
> External E-Mail
>
>
> Hi Vignesh,
>
> On Tue, Sep 24, 2019 at 7:55 AM Vignesh Raghavendra wrote:
>>
>> This series removes SPI_NOR_4B_OPCODES flags from legacy variants of
>> n25q256* and n25q512* and adds entries for newer variants of those
>> flashes that support 4 Byte opcodes.
>>
>> I don't have the flash devices. So its only compile tested.
>>
>> Ashish, Simon,
>>
>> I would greatly appreciate if you could test these patches and make sure
>> 4 Byte opcodes are being used. (Probably by enabling/adding prints to
>> cmd->opcode in spi_mem_exec_op() in drivers/spi/spi-mem.c
>
> As written in my last mail, I currently cannot get SFDP to work on my board:
> I keep getting 0xffdddfdf instead of 0x50444653 (SFDP_SIGNATURE).
>
> Any idea for a reason of that? That device I have here seems to be equipped
> with an MT25QL256ABA, but that should not be an issue, I think.
Can you please check what's written on the chip itself? Usually manufacturers
write the chip name, and then the week and the year in the form week||year. Ex
4214, where week is 42 and the year 2014.
MT25QL256ABA datasheet says that: "Beginning
week 42 (2014), Micron's MT25Q production parts will include SFDP data that
aligns
with revision 1.6."
So maybe earlier versions don't have sfdp support?
Also, can you try this kind of patch? Let's dump the sfdp header.
SPI_FLASH_SFDP_SUPPORT has to be selected.
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 1acff745d1a2..7e93be90fc09 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -1815,14 +1815,22 @@ static int spi_nor_parse_sfdp(struct spi_nor *nor,
{
const struct sfdp_parameter_header *param_header, *bfpt_header;
struct sfdp_parameter_header *param_headers = NULL;
- struct sfdp_header header;
+ struct sfdp_header header = {};
+ u32 *sfdp_table = (u32 *)&header;
size_t psize;
int i, err;
/* Get the SFDP header. */
err = spi_nor_read_sfdp(nor, 0, sizeof(header), &header);
- if (err < 0)
+ if (err < 0) {
+ dev_err(nor->dev, "spi_nor_read_sfdp err = %d\n", err);
return err;
+ }
+
+ for (i = 0; i < sizeof(header) / sizeof(u32); i++) {
+ sfdp_table[i] = le32_to_cpu(sfdp_table[i]);
+ dev_err(nor->dev, "sfdp_table[%d] = %08x\n", i, sfdp_table[i]);
+ }
>
> Regards,
> Simon
>
>>
>> Euginey,
>>
>> Could you test this series on top of latest u-boot master and confirm
>> that your test cases still work?
>>
>> Regards
>> Vignesh
>>
>> Vignesh Raghavendra (3):
>> spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and
>> n25q256*
>> spi-nor: spi-nor-ids: Rename mt25qu512a entry
>> spi-nor: spi-nor-ids: Add entries for newer variants of n25q256* and
>> n25q512*
>>
>> drivers/mtd/spi/spi-nor-ids.c | 13 -
>> 1 file changed, 8 insertions(+), 5 deletions(-)
>>
>> --
>> 2.23.0
>>
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Re: [U-Boot] [EXT] [PATCH 2/2] spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256*
Hi, Simon, On 09/23/2019 12:30 PM, Simon Goldschmidt wrote: > How would I dump the SFDP tables? this should do it. Make sure SPI_FLASH_SFDP_SUPPORT is selected in menuconfig. Cheers, ta diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 1acff745d1a2..7062f31226bf 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -1680,6 +1680,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, for (i = 0; i < BFPT_DWORD_MAX; i++) bfpt.dwords[i] = le32_to_cpu(bfpt.dwords[i]); + for (i = 0; i < BFPT_DWORD_MAX; i++) + dev_err(nor->dev, "bfpt.dwords[%d] = %08x\n", i, + bfpt.dwords[i]); + ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 04/12] board: atmel: Add sam9x60ek board
From: Sandeep Sheriker Mallikarjun
Add new board SAM9X60-EK using the ARM926 SAM9X60 SoC.
Signed-off-by: Sandeep Sheriker Mallikarjun
[tudor.amba...@microchip.com:
- fix number of DRAM banks:
One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks]
- drop SPL related macros
- drop memtest macros
- drop CONFIG_SPI_BOOT, CONFIG_SYS_USE_DATAFLASH related macros
- drop inclusion of asm/arch/at91sam9_smc.h]
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/Kconfig| 7 +
board/atmel/sam9x60ek/Kconfig | 12
board/atmel/sam9x60ek/MAINTAINERS | 7 +
board/atmel/sam9x60ek/Makefile| 7 +
board/atmel/sam9x60ek/sam9x60ek.c | 59 ++
include/configs/sam9x60ek.h | 60 +++
6 files changed, 152 insertions(+)
create mode 100644 board/atmel/sam9x60ek/Kconfig
create mode 100644 board/atmel/sam9x60ek/MAINTAINERS
create mode 100644 board/atmel/sam9x60ek/Makefile
create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c
create mode 100644 include/configs/sam9x60ek.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 3cf13042b7b4..85524004f9e4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -160,6 +160,12 @@ config TARGET_GARDENA_SMART_GATEWAY_AT91SAM
select BOARD_LATE_INIT
select SUPPORT_SPL
+config TARGET_SAM9X60EK
+ bool "SAM9X60-EK board"
+ select SAM9X60
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+
config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
select BOARD_EARLY_INIT_F
@@ -316,6 +322,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sam9x60ek/Kconfig"
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
diff --git a/board/atmel/sam9x60ek/Kconfig b/board/atmel/sam9x60ek/Kconfig
new file mode 100644
index ..32fae2108e6e
--- /dev/null
+++ b/board/atmel/sam9x60ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAM9X60EK
+
+config SYS_BOARD
+ default "sam9x60ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_CONFIG_NAME
+ default "sam9x60ek"
+
+endif
diff --git a/board/atmel/sam9x60ek/MAINTAINERS
b/board/atmel/sam9x60ek/MAINTAINERS
new file mode 100644
index ..e8c1346863a3
--- /dev/null
+++ b/board/atmel/sam9x60ek/MAINTAINERS
@@ -0,0 +1,7 @@
+SAM9X60EK BOARD
+M: Sandeep Sheriker M
+M: Eugen Hristev
+S: Maintained
+F: board/atmel/sam9x60ek/
+F: include/configs/sam9x60ek.h
+F: configs/sam9x60ek_mmc_defconfig
diff --git a/board/atmel/sam9x60ek/Makefile b/board/atmel/sam9x60ek/Makefile
new file mode 100644
index ..12a406a3bb5c
--- /dev/null
+++ b/board/atmel/sam9x60ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Sandeep Sheriker M
+
+obj-y += sam9x60ek.o
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c
b/board/atmel/sam9x60ek/sam9x60ek.c
new file mode 100644
index ..62938741ddd6
--- /dev/null
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void at91_prepare_cpu_var(void);
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ at91_prepare_cpu_var();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
new file mode 100644
index ..b778bd8e83eb
--- /dev/null
+++ b/include/configs/sam9x60ek.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the SAM9X60EK board.
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 2400/* 24 MHz crystal */
[U-Boot] [PATCH v2 09/12] configs: Add sam9x60ek_nandflash_defconfig
From: Tudor Ambarus Boot from nand flash. Signed-off-by: Tudor Ambarus --- board/atmel/sam9x60ek/MAINTAINERS | 1 + configs/sam9x60ek_nandflash_defconfig | 51 +++ 2 files changed, 52 insertions(+) create mode 100644 configs/sam9x60ek_nandflash_defconfig diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS index e8c1346863a3..ec5bed7479ba 100644 --- a/board/atmel/sam9x60ek/MAINTAINERS +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -5,3 +5,4 @@ S: Maintained F: board/atmel/sam9x60ek/ F: include/configs/sam9x60ek.h F: configs/sam9x60ek_mmc_defconfig +F: configs/sam9x60ek_nandflash_defconfig diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig new file mode 100644 index ..4858539edeec --- /dev/null +++ b/configs/sam9x60ek_nandflash_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf200 +CONFIG_DEBUG_UART_CLOCK=2 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 11/12] ARM: dts: at91: sam9x60ek: Enable qspi node
From: Tudor Ambarus
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.
Enable the qspi node together with the SST26VF064B qspi nor flash
memory. Booting from the QSPI NOR flash is now possible.
Signed-off-by: Tudor Ambarus
---
arch/arm/dts/sam9x60.dtsi | 29 +
arch/arm/dts/sam9x60ek-u-boot.dtsi | 28
arch/arm/dts/sam9x60ek.dts | 31 +++
3 files changed, 88 insertions(+)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index a66d0a278a87..9c16ba1e6a87 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -22,6 +22,7 @@
serial0 = &dbgu;
gpio0 = &pioA;
gpio1 = &pioB;
+ spi0 = &qspi;
};
clocks {
@@ -60,6 +61,17 @@
#size-cells = <1>;
ranges;
+ qspi: spi@f0014000 {
+ compatible = "microchip,sam9x60-qspi";
+ reg = <0xf0014000 0x100>, <0x7000
0x1000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ clocks = <&qspi_clk>, <&qspick>;
+ clock-names = "pclk", "qspick";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
macb0: ethernet@f802c000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
@@ -172,6 +184,18 @@
atmel,clk-divisors = <1 2 4 6>;
};
+ system: systemck {
+ compatible =
"atmel,at91rm9200-clk-system";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qspick: qspick {
+ #clock-cells = <0>;
+ reg = <19>;
+ clocks = <&mck>;
+ };
+ };
+
periph: periphck {
compatible =
"microchip,sam9x60-clk-peripheral";
#address-cells = <1>;
@@ -202,6 +226,11 @@
#clock-cells = <0>;
reg = <24>;
};
+
+ qspi_clk: qspi_clk {
+ #clock-cells = <0>;
+ reg = <35>;
+ };
};
generic: gck {
diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi
b/arch/arm/dts/sam9x60ek-u-boot.dtsi
index 68e220926e5e..93cf1262f6fc 100644
--- a/arch/arm/dts/sam9x60ek-u-boot.dtsi
+++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi
@@ -31,6 +31,10 @@
u-boot,dm-pre-reloc;
};
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
&pinctrl_dbgu {
u-boot,dm-pre-reloc;
};
@@ -39,10 +43,18 @@
u-boot,dm-pre-reloc;
};
+&pinctrl_qspi {
+ u-boot,dm-pre-reloc;
+};
+
&pioA {
u-boot,dm-pre-reloc;
};
+&pioB {
+ u-boot,dm-pre-reloc;
+};
+
&pmc {
u-boot,dm-pre-reloc;
};
@@ -59,6 +71,14 @@
u-boot,dm-pre-reloc;
};
+&system {
+ u-boot,dm-pre-reloc;
+};
+
+&qspick {
+ u-boot,dm-pre-reloc;
+};
+
&periph {
u-boot,dm-pre-reloc;
};
@@ -67,6 +87,10 @@
u-boot,dm-pre-reloc;
};
+&pioB_clk {
+ u-boot,dm-pre-reloc;
+};
+
&sdhci0_clk {
u-boot,dm-pre-reloc;
};
@@ -75,6 +99,10 @@
u-boot,dm-pre-reloc;
};
+&qspi_clk {
+ u-boot,dm-pre-reloc;
+};
+
&generic {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 6fe9f19f0bc7..63904272f08f 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -16,6 +16,37 @@
chosen {
stdout-path = &dbgu;
};
+
+ ahb {
+ apb {
+ qspi: spi@f0014000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ nor_flash: sst26vf064@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+
[U-Boot] [PATCH v2 05/12] configs: Add sam9x60ek_mmc_defconfig
From: Sandeep Sheriker Mallikarjun add sam9x60ek_mmc_defconfig and for now only supports booting from sdcard. Signed-off-by: Sandeep Sheriker Mallikarjun Signed-off-by: Nicolas Ferre [nicolas.fe...@microchip.com: split patch, add Ethernet controller, phy and tools] [claudiu.bez...@microchip.com: add CONFIG_OF_LIBFDT_OVERLAY] Signed-off-by: Claudiu Beznea [tudor.amba...@microchip.com: Fix number of DRAM banks: One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks] Signed-off-by: Tudor Ambarus --- configs/sam9x60ek_mmc_defconfig | 52 + 1 file changed, 52 insertions(+) create mode 100644 configs/sam9x60ek_mmc_defconfig diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig new file mode 100644 index ..6cdc819a6793 --- /dev/null +++ b/configs/sam9x60ek_mmc_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf200 +CONFIG_DEBUG_UART_CLOCK=2 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 06/12] ARM: at91: Rename sama5_sfr.h to at91_sfr.h
From: Tudor Ambarus
The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/armv7/sama5d4_devices.c | 2 +-
arch/arm/mach-at91/atmel_sfr.c | 2 +-
arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} | 4 ++--
board/laird/wb50n/wb50n.c | 2 +-
drivers/clk/at91/clk-utmi.c | 2 +-
5 files changed, 6 insertions(+), 6 deletions(-)
rename arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} (97%)
diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c
b/arch/arm/mach-at91/armv7/sama5d4_devices.c
index 5c693df2ecf0..e68ae9940788 100644
--- a/arch/arm/mach-at91/armv7/sama5d4_devices.c
+++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
@@ -8,7 +8,7 @@
#include
#include
#include
-#include
+#include
#include
char *get_cpu_name()
diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c
index 13cfba0ba0c0..b14222460f3a 100644
--- a/arch/arm/mach-at91/atmel_sfr.c
+++ b/arch/arm/mach-at91/atmel_sfr.c
@@ -7,7 +7,7 @@
#include
#include
#include
-#include
+#include
#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4)
void redirect_int_from_saic_to_aic(void)
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h
b/arch/arm/mach-at91/include/mach/at91_sfr.h
similarity index 97%
rename from arch/arm/mach-at91/include/mach/sama5_sfr.h
rename to arch/arm/mach-at91/include/mach/at91_sfr.h
index f9c412f9989a..dc259055cff6 100644
--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
+++ b/arch/arm/mach-at91/include/mach/at91_sfr.h
@@ -6,8 +6,8 @@
* Bo Shen
*/
-#ifndef __SAMA5_SFR_H
-#define __SAMA5_SFR_H
+#ifndef __AT91_SFR_H
+#define __AT91_SFR_H
struct atmel_sfr {
u32 reserved1; /* 0x00 */
diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c
index ab1dbcd879ae..13563abb49ef 100644
--- a/board/laird/wb50n/wb50n.c
+++ b/board/laird/wb50n/wb50n.c
@@ -4,7 +4,7 @@
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
index e8506099fd32..18af0bfeaad1 100644
--- a/drivers/clk/at91/clk-utmi.c
+++ b/drivers/clk/at91/clk-utmi.c
@@ -10,7 +10,7 @@
#include
#include
#include
-#include
+#include
#include "pmc.h"
/*
--
2.9.5
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[U-Boot] [PATCH v2 08/12] board: sam9x60ek: Add NAND flash support
From: Tudor Ambarus
- EBI Chip Select Register is now in SFR,
- the pins are set to default values,
- timings are matching MT29F4G08BABWP's nand flash requirements.
Signed-off-by: Tudor Ambarus
---
board/atmel/sam9x60ek/sam9x60ek.c | 61 +++
include/configs/sam9x60ek.h | 28 ++
2 files changed, 89 insertions(+)
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c
b/board/atmel/sam9x60ek/sam9x60ek.c
index 62938741ddd6..e352afc67ed3 100644
--- a/board/atmel/sam9x60ek/sam9x60ek.c
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -7,8 +7,10 @@
#include
#include
+#include
#include
#include
+#include
#include
#include
#include
@@ -18,6 +20,62 @@ DECLARE_GLOBAL_DATA_PTR;
void at91_prepare_cpu_var(void);
+#ifdef CONFIG_CMD_NAND
+static void sam9x60ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+ unsigned int csa;
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
+
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+ /* Enable CS3 */
+ csa = readl(&sfr->ebicsa);
+ csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
+
+ /* Configure IO drive */
+ csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
+
+ writel(csa, &sfr->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
+ AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
+ &smc->cs[3].mode);
+}
+#endif
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
@@ -48,6 +106,9 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_CMD_NAND
+ sam9x60ek_nand_hw_init();
+#endif
return 0;
}
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index b778bd8e83eb..dbcbce3a2b80 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -42,6 +42,26 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x4000
+#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_MTD_DEVICE
+#endif
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP 8
+#define CONFIG_PMECC_SECTOR_SIZE 512
+
#define CONFIG_SYS_LOAD_ADDR 0x2200 /* load address */
#ifdef CONFIG_SD_BOOT
@@ -50,6 +70,14 @@
"fatload mmc 0:1 0x2100 at91-sam9x60ek.dtb;" \
"fatload mmc 0:1 0x2200 zImage;" \
"bootz 0x2200 - 0x2100"
+
+#elif defined(CONFIG_NAND_BOOT)
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET_REDUND 0x10
+#define CONFIG_BOOTCOMMAND "nand read " \
+ "0x2200 0x20 0x60; " \
+ "nand read 0x2100 0x18 0x2; " \
+ "bootz 0x2200 - 0x2100"
#endif
/*
--
2.9.5
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[U-Boot] [PATCH v2 10/12] configs: sam9x60ek: Add QSPI_BOOT defines
From: Tudor Ambarus Cope with the offsets defined at: https://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections/demo_nandflash_map_lnx4sam6x.png The environment starts at 0x14 and it's of size 0x2. The device tree starts at 0x18 and it's of size 0x8. The zImage starts at 0x20 and it's of size 0x60. Signed-off-by: Tudor Ambarus --- include/configs/sam9x60ek.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index dbcbce3a2b80..5f89ae4a511a 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -78,6 +78,13 @@ "0x2200 0x20 0x60; " \ "nand read 0x2100 0x18 0x2; " \ "bootz 0x2200 - 0x2100" + +#elif defined(CONFIG_QSPI_BOOT) +/* bootstrap + u-boot + env + linux in SPI NOR flash */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x2100 0x18 0x8; " \ + "sf read 0x2200 0x20 0x60; " \ + "bootz 0x2200 - 0x2100" #endif /* -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 02/12] ARM: dts: Add dts files for sam9x60ek
From: Sandeep Sheriker Mallikarjun
add device tree files for sam9x60ek board with below changes.
- Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit)
- Add the reg property for the pinctrl node.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
are used by the board_init_f stage.
Signed-off-by: Sandeep Sheriker Mallikarjun
[prasanthi.chellaku...@microchip.com: fix style/whitespace issues]
Signed-off-by: Prasanthi Chellakumar
[nicolas.fe...@microchip.com:
- fix gclk,
- fix pio/pinctrl controller definition and allow to have more
than only PIOA for this SoC,
- removing pinctrl address]
Signed-off-by: Nicolas Ferre
[claudiu.bez...@microchip.com:
- use SAM9X60's compatible for pinctrl
- add drive strength and slew rate options for SDMMC0 pins.]
Signed-off-by: Claudiu Beznea
[tudor.amba...@microchip.com:
- u-boot,dm-pre-reloc property in dedicated file,
- fix pit len, starts from 0xFE40 and it is of len 0x10]
Signed-off-by: Tudor Ambarus
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sam9x60.dtsi | 225 +
arch/arm/dts/sam9x60ek-u-boot.dtsi | 104 +
arch/arm/dts/sam9x60ek.dts | 19
4 files changed, 350 insertions(+)
create mode 100644 arch/arm/dts/sam9x60.dtsi
create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi
create mode 100644 arch/arm/dts/sam9x60ek.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 250b9ba505aa..52027786ef50 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -690,6 +690,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
+dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb
+
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
new file mode 100644
index ..e880dc0068df
--- /dev/null
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M
+ */
+
+#include "skeleton.dtsi"
+#include
+#include
+#include
+#include
+#include
+
+/{
+ model = "Microchip SAM9X60 SoC";
+ compatible = "microchip,sam9x60";
+
+ aliases {
+ serial0 = &dbgu;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sdhci0: sdhci-host@8000 {
+ compatible = "microchip,sam9x60-sdhci";
+ reg = <0x8000 0x300>;
+ clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
+ clock-names = "hclock", "multclk", "baseclk";
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0>;
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dbgu: serial@f200 {
+ compatible = "atmel,at91sam9260-dbgu",
"atmel,at91sam9260-usart";
+ reg = <0xf200 0x200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&dbgu_clk>;
+ clock-names = "usart";
+ };
+
+ pinctrl {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "microchip,sam9x60-pinctrl",
"simple-bus";
+ ranges = <0xf400 0xf400 0x800>;
+ reg = <0xf400 0x200 /* pioA */
+ 0xf600 0x200 /* pioB */
+ 0xf800 0x200 /* pioC */
+ 0xfa00 0x200>; /* pioD */
+
+ /* shared pinctrl settings */
+ dbgu {
+
[U-Boot] [PATCH v2 12/12] configs: Add sam9x60ek_qspiflash_defconfig
From: Tudor Ambarus Boot from QSPI nor flash. The at91bootstrap, u-boot, u-boot env redundant, u-boot env, device tree and kernel will reside in the QSPI nor flash. The rootfs will reside in the NAND flash. Signed-off-by: Tudor Ambarus --- board/atmel/sam9x60ek/MAINTAINERS | 1 + configs/sam9x60ek_qspiflash_defconfig | 73 +++ 2 files changed, 74 insertions(+) create mode 100644 configs/sam9x60ek_qspiflash_defconfig diff --git a/board/atmel/sam9x60ek/MAINTAINERS b/board/atmel/sam9x60ek/MAINTAINERS index ec5bed7479ba..d209249c2eff 100644 --- a/board/atmel/sam9x60ek/MAINTAINERS +++ b/board/atmel/sam9x60ek/MAINTAINERS @@ -6,3 +6,4 @@ F: board/atmel/sam9x60ek/ F: include/configs/sam9x60ek.h F: configs/sam9x60ek_mmc_defconfig F: configs/sam9x60ek_nandflash_defconfig +F: configs/sam9x60ek_qspiflash_defconfig diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig new file mode 100644 index ..8e3bf5e4ede6 --- /dev/null +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf200 +CONFIG_DEBUG_UART_CLOCK=2 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=5000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 07/12] ARM: at91: Add SFR definitions
From: Tudor Ambarus
sama5's SFR has at offset 0x04 the DDR Configuration Register,
while sam9x60's SFR contains the EBI Chip Select Register. Add
a union to reconcile both boards.
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/include/mach/at91_sfr.h | 48 --
1 file changed, 45 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_sfr.h
b/arch/arm/mach-at91/include/mach/at91_sfr.h
index dc259055cff6..0300c336dd81 100644
--- a/arch/arm/mach-at91/include/mach/at91_sfr.h
+++ b/arch/arm/mach-at91/include/mach/at91_sfr.h
@@ -11,7 +11,10 @@
struct atmel_sfr {
u32 reserved1; /* 0x00 */
- u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ union {
+ u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ u32 ebicsa; /* 0x04: EBI Chip Select Register */
+ };
u32 reserved2; /* 0x08 */
u32 reserved3; /* 0x0c */
u32 ohciicr;/* 0x10: OHCI Interrupt Configuration Register */
@@ -28,7 +31,16 @@ struct atmel_sfr {
};
/* Register Mapping*/
+#define AT91_SFR_DDRCFG0x04/* DDR Configuration Register */
+#define AT91_SFR_CCFG_EBICSA 0x04/* EBI Chip Select Register */
+/* 0x08 ~ 0x0c: Reserved */
+#define AT91_SFR_OHCIICR 0x10/* OHCI INT Configuration Register */
+#define AT91_SFR_OHCIISR 0x14/* OHCI INT Status Register */
#define AT91_SFR_UTMICKTRIM0x30/* UTMI Clock Trimming Register */
+#define AT91_SFR_UTMISWAP 0x3c/* UTMI DP/DM Pin Swapping Register */
+#define AT91_SFR_LS0x7c/* Light Sleep Register */
+#define AT91_SFR_I2SCLKSEL 0x90/* I2SC Register */
+#define AT91_SFR_WPMR 0xe4/* Write Protection Mode Register */
/* Bit field in DDRCFG */
#define ATMEL_SFR_DDRCFG_FDQIEN0x0001
@@ -58,9 +70,39 @@ struct atmel_sfr {
#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)
#define AT91_SFR_EBICFG_SCH1_ON(0x1 << 12)
-#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
-
/* Bit field in AICREDIR */
#define ATMEL_SFR_AICREDIR_NSAIC 0x0001
+/* Bit field in DDRCFG */
+#define ATMEL_SFR_DDRCFG_FDQIEN0x0001
+#define ATMEL_SFR_DDRCFG_FDQSIEN 0x0002
+
+#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs))
+#define AT91_SFR_CCFG_EBI_DBPUCBIT(8)
+#define AT91_SFR_CCFG_EBI_DBPDCBIT(9)
+#define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60BIT(16)
+#define AT91_SFR_CCFG_EBI_DRIVEBIT(17)
+#define AT91_SFR_CCFG_DQIEN_F BIT(20)
+#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24)
+#define AT91_SFR_CCFG_DDR_MP_ENBIT(25)
+
+#define AT91_SFR_OHCIICR_RES(x)BIT(x)
+#define AT91_SFR_OHCIICR_ARIE BIT(4)
+#define AT91_SFR_OHCIICR_APPSTART BIT(5)
+#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x))
+#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23)
+#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8)
+
+#define AT91_SFR_OHCIISR_RIS(x)BIT(x)
+
+#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
+
+#define AT91_SFR_UTMISWAP_PORT(x) BIT(x)
+
+#define AT91_SFR_LS_VALUE(x) BIT(x)
+#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16)
+
+#define AT91_SFR_WPMR_WPEN BIT(0)
+#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)
+
#endif
--
2.9.5
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[U-Boot] [PATCH v2 03/12] ARM: dts: at91: sam9x60: Add macb0 Ethernet controller
From: Nicolas Ferre
Add Ethernet controller to dtsi file and enable it on sam9x60ek
platform connected with rmii.
Signed-off-by: Nicolas Ferre
---
arch/arm/dts/sam9x60.dtsi | 31 +++
arch/arm/dts/sam9x60ek.dts | 5 +
2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index e880dc0068df..a66d0a278a87 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -60,6 +60,16 @@
#size-cells = <1>;
ranges;
+ macb0: ethernet@f802c000 {
+ compatible = "cdns,sam9x60-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ clock-names = "hclk", "pclk";
+ clocks = <&macb0_clk>, <&macb0_clk>;
+ status = "disabled";
+ };
+
dbgu: serial@f200 {
compatible = "atmel,at91sam9260-dbgu",
"atmel,at91sam9260-usart";
reg = <0xf200 0x200>;
@@ -88,6 +98,22 @@
};
};
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ ; /* PB10 periph A */
+ };
+ };
+
sdhci0 {
pinctrl_sdhci0: sdhci0 {
atmel,pins =
@@ -171,6 +197,11 @@
#clock-cells = <0>;
reg = <47>;
};
+
+ macb0_clk: macb0_clk {
+ #clock-cells = <0>;
+ reg = <24>;
+ };
};
generic: gck {
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index e64566ec8e58..6fe9f19f0bc7 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -17,3 +17,8 @@
stdout-path = &dbgu;
};
};
+
+&macb0 {
+ phy-mode = "rmii";
+ status = "okay";
+};
--
2.9.5
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[U-Boot] [PATCH v2 01/12] ARM: at91: Add sam9x60 soc
From: Sandeep Sheriker Mallikarjun
Add new Microchip sam9x60 SoC based on an ARM926.
Signed-off-by: Sandeep Sheriker Mallikarjun
[tudor.amba...@microchip.com: fix SFR definition]
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/Kconfig | 4 +
arch/arm/mach-at91/arm926ejs/Makefile | 1 +
arch/arm/mach-at91/arm926ejs/sam9x60_devices.c | 125 ++
arch/arm/mach-at91/include/mach/hardware.h | 2 +
arch/arm/mach-at91/include/mach/sam9x60.h | 169 +
5 files changed, 301 insertions(+)
create mode 100644 arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
create mode 100644 arch/arm/mach-at91/include/mach/sam9x60.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 14343280793b..3cf13042b7b4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -43,6 +43,10 @@ config AT91SAM9X5
bool
select CPU_ARM926EJS
+config SAM9X60
+ bool
+ select CPU_ARM926EJS
+
config SAMA5D2
bool
select CPU_V7A
diff --git a/arch/arm/mach-at91/arm926ejs/Makefile
b/arch/arm/mach-at91/arm926ejs/Makefile
index 6b0b28957af5..8de6a2f9661e 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
+obj-$(CONFIG_SAM9X60) += sam9x60_devices.o
obj-$(CONFIG_AT91_EFLASH) += eflash.o
obj-$(CONFIG_AT91_LED) += led.o
obj-y += clock.o
diff --git a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
new file mode 100644
index ..d463bbc78863
--- /dev/null
+++ b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+unsigned int get_chip_id(void)
+{
+ /* The 0x40 is the offset of cidr in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+ /* The 0x44 is the offset of exid in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x44);
+}
+
+unsigned int has_emac1(void)
+{
+ return cpu_is_sam9x60();
+}
+
+unsigned int has_emac0(void)
+{
+ return cpu_is_sam9x60();
+}
+
+unsigned int has_lcdc(void)
+{
+ return cpu_is_sam9x60();
+}
+
+char *get_cpu_name(void)
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sam9x60()) {
+ switch (extension_id) {
+ case ARCH_EXID_SAM9X60:
+ return "SAM9X60";
+ default:
+ return "Unknown CPU type";
+ }
+ } else {
+ return "Unknown CPU type";
+ }
+}
+
+void at91_seriald_hw_init(void)
+{
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 1); /* DRXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
+
+ at91_periph_clk_enable(ATMEL_ID_DBGU);
+}
+
+void at91_mci_hw_init(void)
+{
+ /* Initialize the SDMMC0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 1); /* CLK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 1); /* CMD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 1); /* DAT0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 1); /* DAT1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 1); /* DAT2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 1); /* DAT3 */
+
+ at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+}
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+ if (has_emac0()) {
+ /* Enable EMAC0 clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC0);
+ /* EMAC0 pins setup */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
+ }
+
+ if (has_emac1()) {
+ /* Enable EMAC1 clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC1);
+ /* EMAC1 pins setup */
+ at91_pio3_set_b_periph(AT91_PIO_POR
[U-Boot] [PATCH v2 00/12] Add support for sam9x60ek board
From: Tudor Ambarus
Add support for sam9x60 SOC, sam9x60ek board, dts, NAND and QSPI.
Add defconfigs for MMC, NAND and QSPI.
v2: add maintainers for qspi & nand defconfigs
Nicolas Ferre (1):
ARM: dts: at91: sam9x60: Add macb0 Ethernet controller
Sandeep Sheriker Mallikarjun (4):
ARM: at91: Add sam9x60 soc
ARM: dts: Add dts files for sam9x60ek
board: atmel: Add sam9x60ek board
configs: Add sam9x60ek_mmc_defconfig
Tudor Ambarus (7):
ARM: at91: Rename sama5_sfr.h to at91_sfr.h
ARM: at91: Add SFR definitions
board: sam9x60ek: Add NAND flash support
configs: Add sam9x60ek_nandflash_defconfig
configs: sam9x60ek: Add QSPI_BOOT defines
ARM: dts: at91: sam9x60ek: Enable qspi node
configs: Add sam9x60ek_qspiflash_defconfig
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sam9x60.dtsi | 285 +
arch/arm/dts/sam9x60ek-u-boot.dtsi | 132 ++
arch/arm/dts/sam9x60ek.dts | 55
arch/arm/mach-at91/Kconfig | 11 +
arch/arm/mach-at91/arm926ejs/Makefile | 1 +
arch/arm/mach-at91/arm926ejs/sam9x60_devices.c | 125 +
arch/arm/mach-at91/armv7/sama5d4_devices.c | 2 +-
arch/arm/mach-at91/atmel_sfr.c | 2 +-
.../include/mach/{sama5_sfr.h => at91_sfr.h} | 52 +++-
arch/arm/mach-at91/include/mach/hardware.h | 2 +
arch/arm/mach-at91/include/mach/sam9x60.h | 169
board/atmel/sam9x60ek/Kconfig | 12 +
board/atmel/sam9x60ek/MAINTAINERS | 9 +
board/atmel/sam9x60ek/Makefile | 7 +
board/atmel/sam9x60ek/sam9x60ek.c | 120 +
board/laird/wb50n/wb50n.c | 2 +-
configs/sam9x60ek_mmc_defconfig| 52
configs/sam9x60ek_nandflash_defconfig | 51
configs/sam9x60ek_qspiflash_defconfig | 73 ++
drivers/clk/at91/clk-utmi.c| 2 +-
include/configs/sam9x60ek.h| 95 +++
22 files changed, 1252 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/dts/sam9x60.dtsi
create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi
create mode 100644 arch/arm/dts/sam9x60ek.dts
create mode 100644 arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
rename arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} (53%)
create mode 100644 arch/arm/mach-at91/include/mach/sam9x60.h
create mode 100644 board/atmel/sam9x60ek/Kconfig
create mode 100644 board/atmel/sam9x60ek/MAINTAINERS
create mode 100644 board/atmel/sam9x60ek/Makefile
create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c
create mode 100644 configs/sam9x60ek_mmc_defconfig
create mode 100644 configs/sam9x60ek_nandflash_defconfig
create mode 100644 configs/sam9x60ek_qspiflash_defconfig
create mode 100644 include/configs/sam9x60ek.h
--
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[U-Boot] [PATCH 11/12] ARM: dts: at91: sam9x60ek: Enable qspi node
From: Tudor Ambarus
The sam9x60 qspi controller uses 2 clocks, one for the peripheral register
access, the other for the qspi core and phy. Both are mandatory.
Enable the qspi node together with the SST26VF064B qspi nor flash
memory. Booting from the QSPI NOR flash is now possible.
Signed-off-by: Tudor Ambarus
---
arch/arm/dts/sam9x60.dtsi | 29 +
arch/arm/dts/sam9x60ek-u-boot.dtsi | 28
arch/arm/dts/sam9x60ek.dts | 31 +++
3 files changed, 88 insertions(+)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index a66d0a278a87..9c16ba1e6a87 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -22,6 +22,7 @@
serial0 = &dbgu;
gpio0 = &pioA;
gpio1 = &pioB;
+ spi0 = &qspi;
};
clocks {
@@ -60,6 +61,17 @@
#size-cells = <1>;
ranges;
+ qspi: spi@f0014000 {
+ compatible = "microchip,sam9x60-qspi";
+ reg = <0xf0014000 0x100>, <0x7000
0x1000>;
+ reg-names = "qspi_base", "qspi_mmap";
+ clocks = <&qspi_clk>, <&qspick>;
+ clock-names = "pclk", "qspick";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
macb0: ethernet@f802c000 {
compatible = "cdns,sam9x60-macb", "cdns,macb";
reg = <0xf802c000 0x100>;
@@ -172,6 +184,18 @@
atmel,clk-divisors = <1 2 4 6>;
};
+ system: systemck {
+ compatible =
"atmel,at91rm9200-clk-system";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ qspick: qspick {
+ #clock-cells = <0>;
+ reg = <19>;
+ clocks = <&mck>;
+ };
+ };
+
periph: periphck {
compatible =
"microchip,sam9x60-clk-peripheral";
#address-cells = <1>;
@@ -202,6 +226,11 @@
#clock-cells = <0>;
reg = <24>;
};
+
+ qspi_clk: qspi_clk {
+ #clock-cells = <0>;
+ reg = <35>;
+ };
};
generic: gck {
diff --git a/arch/arm/dts/sam9x60ek-u-boot.dtsi
b/arch/arm/dts/sam9x60ek-u-boot.dtsi
index 68e220926e5e..93cf1262f6fc 100644
--- a/arch/arm/dts/sam9x60ek-u-boot.dtsi
+++ b/arch/arm/dts/sam9x60ek-u-boot.dtsi
@@ -31,6 +31,10 @@
u-boot,dm-pre-reloc;
};
+&qspi {
+ u-boot,dm-pre-reloc;
+};
+
&pinctrl_dbgu {
u-boot,dm-pre-reloc;
};
@@ -39,10 +43,18 @@
u-boot,dm-pre-reloc;
};
+&pinctrl_qspi {
+ u-boot,dm-pre-reloc;
+};
+
&pioA {
u-boot,dm-pre-reloc;
};
+&pioB {
+ u-boot,dm-pre-reloc;
+};
+
&pmc {
u-boot,dm-pre-reloc;
};
@@ -59,6 +71,14 @@
u-boot,dm-pre-reloc;
};
+&system {
+ u-boot,dm-pre-reloc;
+};
+
+&qspick {
+ u-boot,dm-pre-reloc;
+};
+
&periph {
u-boot,dm-pre-reloc;
};
@@ -67,6 +87,10 @@
u-boot,dm-pre-reloc;
};
+&pioB_clk {
+ u-boot,dm-pre-reloc;
+};
+
&sdhci0_clk {
u-boot,dm-pre-reloc;
};
@@ -75,6 +99,10 @@
u-boot,dm-pre-reloc;
};
+&qspi_clk {
+ u-boot,dm-pre-reloc;
+};
+
&generic {
u-boot,dm-pre-reloc;
};
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index 6fe9f19f0bc7..63904272f08f 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -16,6 +16,37 @@
chosen {
stdout-path = &dbgu;
};
+
+ ahb {
+ apb {
+ qspi: spi@f0014000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi>;
+ status = "okay";
+
+ nor_flash: sst26vf064@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+
[U-Boot] [PATCH 10/12] configs: sam9x60ek: Add QSPI_BOOT defines
From: Tudor Ambarus Cope with the offsets defined at: https://www.at91.com/linux4sam/pub/Linux4SAM/SambaSubsections/demo_nandflash_map_lnx4sam6x.png The environment starts at 0x14 and it's of size 0x2. The device tree starts at 0x18 and it's of size 0x8. The zImage starts at 0x20 and it's of size 0x60. Signed-off-by: Tudor Ambarus --- include/configs/sam9x60ek.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index dbcbce3a2b80..5f89ae4a511a 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -78,6 +78,13 @@ "0x2200 0x20 0x60; " \ "nand read 0x2100 0x18 0x2; " \ "bootz 0x2200 - 0x2100" + +#elif defined(CONFIG_QSPI_BOOT) +/* bootstrap + u-boot + env + linux in SPI NOR flash */ +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x2100 0x18 0x8; " \ + "sf read 0x2200 0x20 0x60; " \ + "bootz 0x2200 - 0x2100" #endif /* -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 08/12] board: sam9x60ek: Add NAND flash support
From: Tudor Ambarus
- EBI Chip Select Register is now in SFR,
- the pins are set to default values,
- timings are matching MT29F4G08BABWP's nand flash requirements.
Signed-off-by: Tudor Ambarus
---
board/atmel/sam9x60ek/sam9x60ek.c | 61 +++
include/configs/sam9x60ek.h | 28 ++
2 files changed, 89 insertions(+)
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c
b/board/atmel/sam9x60ek/sam9x60ek.c
index 62938741ddd6..e352afc67ed3 100644
--- a/board/atmel/sam9x60ek/sam9x60ek.c
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -7,8 +7,10 @@
#include
#include
+#include
#include
#include
+#include
#include
#include
#include
@@ -18,6 +20,62 @@ DECLARE_GLOBAL_DATA_PTR;
void at91_prepare_cpu_var(void);
+#ifdef CONFIG_CMD_NAND
+static void sam9x60ek_nand_hw_init(void)
+{
+ struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
+ struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
+ unsigned int csa;
+
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
+ /* Enable NandFlash */
+ at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
+ /* Configure RDY/BSY */
+ at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
+ at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
+
+ at91_periph_clk_enable(ATMEL_ID_PIOD);
+
+ /* Enable CS3 */
+ csa = readl(&sfr->ebicsa);
+ csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
+
+ /* Configure IO drive */
+ csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
+
+ writel(csa, &sfr->ebicsa);
+
+ /* Configure SMC CS3 for NAND/SmartMedia */
+ writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
+
+ writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
+ AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
+ &smc->cs[3].pulse);
+
+ writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
+ &smc->cs[3].cycle);
+
+ writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
+#ifdef CONFIG_SYS_NAND_DBW_16
+ AT91_SMC_MODE_DBW_16 |
+#else /* CONFIG_SYS_NAND_DBW_8 */
+ AT91_SMC_MODE_DBW_8 |
+#endif
+ AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
+ &smc->cs[3].mode);
+}
+#endif
+
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
@@ -48,6 +106,9 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+#ifdef CONFIG_CMD_NAND
+ sam9x60ek_nand_hw_init();
+#endif
return 0;
}
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
index b778bd8e83eb..dbcbce3a2b80 100644
--- a/include/configs/sam9x60ek.h
+++ b/include/configs/sam9x60ek.h
@@ -42,6 +42,26 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
+/* NAND flash */
+#ifdef CONFIG_CMD_NAND
+#define CONFIG_NAND_ATMEL
+#define CONFIG_SYS_MAX_NAND_DEVICE 1
+#define CONFIG_SYS_NAND_BASE 0x4000
+#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
+#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
+#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
+#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+#define CONFIG_MTD_DEVICE
+#endif
+
+/* PMECC & PMERRLOC */
+#define CONFIG_ATMEL_NAND_HWECC
+#define CONFIG_ATMEL_NAND_HW_PMECC
+#define CONFIG_PMECC_CAP 8
+#define CONFIG_PMECC_SECTOR_SIZE 512
+
#define CONFIG_SYS_LOAD_ADDR 0x2200 /* load address */
#ifdef CONFIG_SD_BOOT
@@ -50,6 +70,14 @@
"fatload mmc 0:1 0x2100 at91-sam9x60ek.dtb;" \
"fatload mmc 0:1 0x2200 zImage;" \
"bootz 0x2200 - 0x2100"
+
+#elif defined(CONFIG_NAND_BOOT)
+/* bootstrap + u-boot + env + linux in nandflash */
+#define CONFIG_ENV_OFFSET_REDUND 0x10
+#define CONFIG_BOOTCOMMAND "nand read " \
+ "0x2200 0x20 0x60; " \
+ "nand read 0x2100 0x18 0x2; " \
+ "bootz 0x2200 - 0x2100"
#endif
/*
--
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[U-Boot] [PATCH 05/12] configs: Add sam9x60ek_mmc_defconfig
From: Sandeep Sheriker Mallikarjun add sam9x60ek_mmc_defconfig and for now only supports booting from sdcard. Signed-off-by: Sandeep Sheriker Mallikarjun Signed-off-by: Nicolas Ferre [nicolas.fe...@microchip.com: split patch, add Ethernet controller, phy and tools] [claudiu.bez...@microchip.com: add CONFIG_OF_LIBFDT_OVERLAY] Signed-off-by: Claudiu Beznea [tudor.amba...@microchip.com: Fix number of DRAM banks: One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks] Signed-off-by: Tudor Ambarus --- configs/sam9x60ek_mmc_defconfig | 52 + 1 file changed, 52 insertions(+) create mode 100644 configs/sam9x60ek_mmc_defconfig diff --git a/configs/sam9x60ek_mmc_defconfig b/configs/sam9x60ek_mmc_defconfig new file mode 100644 index ..6cdc819a6793 --- /dev/null +++ b/configs/sam9x60ek_mmc_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_ENV_SIZE=0x4000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf200 +CONFIG_DEBUG_UART_CLOCK=2 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="mem=256M console=ttyS0,115200 root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_FAT=y +CONFIG_ENV_FAT_DEVICE_AND_PART="0:1" +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_PHY_MICREL=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 07/12] ARM: at91: Add SFR definitions
From: Tudor Ambarus
sama5's SFR has at offset 0x04 the DDR Configuration Register,
while sam9x60's SFR contains the EBI Chip Select Register. Add
a union to reconcile both boards.
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/include/mach/at91_sfr.h | 48 --
1 file changed, 45 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-at91/include/mach/at91_sfr.h
b/arch/arm/mach-at91/include/mach/at91_sfr.h
index dc259055cff6..0300c336dd81 100644
--- a/arch/arm/mach-at91/include/mach/at91_sfr.h
+++ b/arch/arm/mach-at91/include/mach/at91_sfr.h
@@ -11,7 +11,10 @@
struct atmel_sfr {
u32 reserved1; /* 0x00 */
- u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ union {
+ u32 ddrcfg; /* 0x04: DDR Configuration Register */
+ u32 ebicsa; /* 0x04: EBI Chip Select Register */
+ };
u32 reserved2; /* 0x08 */
u32 reserved3; /* 0x0c */
u32 ohciicr;/* 0x10: OHCI Interrupt Configuration Register */
@@ -28,7 +31,16 @@ struct atmel_sfr {
};
/* Register Mapping*/
+#define AT91_SFR_DDRCFG0x04/* DDR Configuration Register */
+#define AT91_SFR_CCFG_EBICSA 0x04/* EBI Chip Select Register */
+/* 0x08 ~ 0x0c: Reserved */
+#define AT91_SFR_OHCIICR 0x10/* OHCI INT Configuration Register */
+#define AT91_SFR_OHCIISR 0x14/* OHCI INT Status Register */
#define AT91_SFR_UTMICKTRIM0x30/* UTMI Clock Trimming Register */
+#define AT91_SFR_UTMISWAP 0x3c/* UTMI DP/DM Pin Swapping Register */
+#define AT91_SFR_LS0x7c/* Light Sleep Register */
+#define AT91_SFR_I2SCLKSEL 0x90/* I2SC Register */
+#define AT91_SFR_WPMR 0xe4/* Write Protection Mode Register */
/* Bit field in DDRCFG */
#define ATMEL_SFR_DDRCFG_FDQIEN0x0001
@@ -58,9 +70,39 @@ struct atmel_sfr {
#define AT91_SFR_EBICFG_SCH1_OFF (0x0 << 12)
#define AT91_SFR_EBICFG_SCH1_ON(0x1 << 12)
-#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
-
/* Bit field in AICREDIR */
#define ATMEL_SFR_AICREDIR_NSAIC 0x0001
+/* Bit field in DDRCFG */
+#define ATMEL_SFR_DDRCFG_FDQIEN0x0001
+#define ATMEL_SFR_DDRCFG_FDQSIEN 0x0002
+
+#define AT91_SFR_CCFG_EBI_CSA(cs, val) ((val) << (cs))
+#define AT91_SFR_CCFG_EBI_DBPUCBIT(8)
+#define AT91_SFR_CCFG_EBI_DBPDCBIT(9)
+#define AT91_SFR_CCFG_EBI_DRIVE_SAM9X60BIT(16)
+#define AT91_SFR_CCFG_EBI_DRIVEBIT(17)
+#define AT91_SFR_CCFG_DQIEN_F BIT(20)
+#define AT91_SFR_CCFG_NFD0_ON_D16 BIT(24)
+#define AT91_SFR_CCFG_DDR_MP_ENBIT(25)
+
+#define AT91_SFR_OHCIICR_RES(x)BIT(x)
+#define AT91_SFR_OHCIICR_ARIE BIT(4)
+#define AT91_SFR_OHCIICR_APPSTART BIT(5)
+#define AT91_SFR_OHCIICR_USB_SUSP(x) BIT(8 + (x))
+#define AT91_SFR_OHCIICR_UDPPUDIS BIT(23)
+#define AT91_OHCIICR_USB_SUSPEND GENMASK(10, 8)
+
+#define AT91_SFR_OHCIISR_RIS(x)BIT(x)
+
+#define AT91_UTMICKTRIM_FREQ GENMASK(1, 0)
+
+#define AT91_SFR_UTMISWAP_PORT(x) BIT(x)
+
+#define AT91_SFR_LS_VALUE(x) BIT(x)
+#define AT91_SFR_LS_MEM_POWER_GATING_ULP1_EN BIT(16)
+
+#define AT91_SFR_WPMR_WPEN BIT(0)
+#define AT91_SFR_WPMR_WPKEY_MASK GENMASK(31, 8)
+
#endif
--
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[U-Boot] [PATCH 12/12] configs: Add sam9x60ek_qspiflash_defconfig
From: Tudor Ambarus Boot from QSPI nor flash. The at91bootstrap, u-boot, u-boot env redundant, u-boot env, device tree and kernel will reside in the QSPI nor flash. The rootfs will reside in the NAND flash. Signed-off-by: Tudor Ambarus --- configs/sam9x60ek_qspiflash_defconfig | 73 +++ 1 file changed, 73 insertions(+) create mode 100644 configs/sam9x60ek_qspiflash_defconfig diff --git a/configs/sam9x60ek_qspiflash_defconfig b/configs/sam9x60ek_qspiflash_defconfig new file mode 100644 index ..8e3bf5e4ede6 --- /dev/null +++ b/configs/sam9x60ek_qspiflash_defconfig @@ -0,0 +1,73 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf200 +CONFIG_DEBUG_UART_CLOCK=2 +CONFIG_ENV_SECT_SIZE=0x1000 +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=12 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SF=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_USE_ENV_SPI_BUS=y +CONFIG_ENV_SPI_BUS=0 +CONFIG_USE_ENV_SPI_CS=y +CONFIG_ENV_SPI_CS=0 +CONFIG_USE_ENV_SPI_MAX_HZ=y +CONFIG_ENV_SPI_MAX_HZ=5000 +CONFIG_USE_ENV_SPI_MODE=y +CONFIG_ENV_SPI_MODE=0x0 +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_MTD=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 09/12] configs: Add sam9x60ek_nandflash_defconfig
From: Tudor Ambarus Boot from nand flash. Signed-off-by: Tudor Ambarus --- configs/sam9x60ek_nandflash_defconfig | 51 +++ 1 file changed, 51 insertions(+) create mode 100644 configs/sam9x60ek_nandflash_defconfig diff --git a/configs/sam9x60ek_nandflash_defconfig b/configs/sam9x60ek_nandflash_defconfig new file mode 100644 index ..4858539edeec --- /dev/null +++ b/configs/sam9x60ek_nandflash_defconfig @@ -0,0 +1,51 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAM9X60EK=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=8 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf200 +CONFIG_DEBUG_UART_CLOCK=2 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk mtdparts=atmel_nand:256k(bootstrap)ro,768k(uboot)ro,256k(env_redundant),256k(env),512k(dtb),6M(kernel)ro,-(rootfs) rootfstype=ubifs ubi.mtd=6 root=ubi0:rootfs rw" +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="U-Boot> " +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_FAT=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="sam9x60ek" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_DM=y +CONFIG_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_AT91_GPIO=y +CONFIG_DM_MMC=y +CONFIG_GENERIC_ATMEL_MCI=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_AT91=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH 06/12] ARM: at91: Rename sama5_sfr.h to at91_sfr.h
From: Tudor Ambarus
The Special Function Registers (SFR) are present in sam9x5 and
sam9x60 too, rename sama5_sfr to at91_sfr.h.
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/armv7/sama5d4_devices.c | 2 +-
arch/arm/mach-at91/atmel_sfr.c | 2 +-
arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} | 4 ++--
board/laird/wb50n/wb50n.c | 2 +-
drivers/clk/at91/clk-utmi.c | 2 +-
5 files changed, 6 insertions(+), 6 deletions(-)
rename arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} (97%)
diff --git a/arch/arm/mach-at91/armv7/sama5d4_devices.c
b/arch/arm/mach-at91/armv7/sama5d4_devices.c
index 5c693df2ecf0..e68ae9940788 100644
--- a/arch/arm/mach-at91/armv7/sama5d4_devices.c
+++ b/arch/arm/mach-at91/armv7/sama5d4_devices.c
@@ -8,7 +8,7 @@
#include
#include
#include
-#include
+#include
#include
char *get_cpu_name()
diff --git a/arch/arm/mach-at91/atmel_sfr.c b/arch/arm/mach-at91/atmel_sfr.c
index 13cfba0ba0c0..b14222460f3a 100644
--- a/arch/arm/mach-at91/atmel_sfr.c
+++ b/arch/arm/mach-at91/atmel_sfr.c
@@ -7,7 +7,7 @@
#include
#include
#include
-#include
+#include
#if defined(CONFIG_SAMA5D2) || defined(CONFIG_SAMA5D4)
void redirect_int_from_saic_to_aic(void)
diff --git a/arch/arm/mach-at91/include/mach/sama5_sfr.h
b/arch/arm/mach-at91/include/mach/at91_sfr.h
similarity index 97%
rename from arch/arm/mach-at91/include/mach/sama5_sfr.h
rename to arch/arm/mach-at91/include/mach/at91_sfr.h
index f9c412f9989a..dc259055cff6 100644
--- a/arch/arm/mach-at91/include/mach/sama5_sfr.h
+++ b/arch/arm/mach-at91/include/mach/at91_sfr.h
@@ -6,8 +6,8 @@
* Bo Shen
*/
-#ifndef __SAMA5_SFR_H
-#define __SAMA5_SFR_H
+#ifndef __AT91_SFR_H
+#define __AT91_SFR_H
struct atmel_sfr {
u32 reserved1; /* 0x00 */
diff --git a/board/laird/wb50n/wb50n.c b/board/laird/wb50n/wb50n.c
index ab1dbcd879ae..13563abb49ef 100644
--- a/board/laird/wb50n/wb50n.c
+++ b/board/laird/wb50n/wb50n.c
@@ -4,7 +4,7 @@
#include
#include
-#include
+#include
#include
#include
#include
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
index e8506099fd32..18af0bfeaad1 100644
--- a/drivers/clk/at91/clk-utmi.c
+++ b/drivers/clk/at91/clk-utmi.c
@@ -10,7 +10,7 @@
#include
#include
#include
-#include
+#include
#include "pmc.h"
/*
--
2.9.5
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[U-Boot] [PATCH 03/12] ARM: dts: at91: sam9x60: Add macb0 Ethernet controller
From: Nicolas Ferre
Add Ethernet controller to dtsi file and enable it on sam9x60ek
platform connected with rmii.
Signed-off-by: Nicolas Ferre
---
arch/arm/dts/sam9x60.dtsi | 31 +++
arch/arm/dts/sam9x60ek.dts | 5 +
2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
index e880dc0068df..a66d0a278a87 100644
--- a/arch/arm/dts/sam9x60.dtsi
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -60,6 +60,16 @@
#size-cells = <1>;
ranges;
+ macb0: ethernet@f802c000 {
+ compatible = "cdns,sam9x60-macb", "cdns,macb";
+ reg = <0xf802c000 0x100>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_rmii>;
+ clock-names = "hclk", "pclk";
+ clocks = <&macb0_clk>, <&macb0_clk>;
+ status = "disabled";
+ };
+
dbgu: serial@f200 {
compatible = "atmel,at91sam9260-dbgu",
"atmel,at91sam9260-usart";
reg = <0xf200 0x200>;
@@ -88,6 +98,22 @@
};
};
+ macb0 {
+ pinctrl_macb0_rmii: macb0_rmii-0 {
+ atmel,pins =
+ ; /* PB10 periph A */
+ };
+ };
+
sdhci0 {
pinctrl_sdhci0: sdhci0 {
atmel,pins =
@@ -171,6 +197,11 @@
#clock-cells = <0>;
reg = <47>;
};
+
+ macb0_clk: macb0_clk {
+ #clock-cells = <0>;
+ reg = <24>;
+ };
};
generic: gck {
diff --git a/arch/arm/dts/sam9x60ek.dts b/arch/arm/dts/sam9x60ek.dts
index e64566ec8e58..6fe9f19f0bc7 100644
--- a/arch/arm/dts/sam9x60ek.dts
+++ b/arch/arm/dts/sam9x60ek.dts
@@ -17,3 +17,8 @@
stdout-path = &dbgu;
};
};
+
+&macb0 {
+ phy-mode = "rmii";
+ status = "okay";
+};
--
2.9.5
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[U-Boot] [PATCH 04/12] board: atmel: Add sam9x60ek board
From: Sandeep Sheriker Mallikarjun
Add new board SAM9X60-EK using the ARM926 SAM9X60 SoC.
Signed-off-by: Sandeep Sheriker Mallikarjun
[tudor.amba...@microchip.com:
- fix number of DRAM banks:
One DDR2-SDRAM (W972GG6KB 2 Gbit = 16 Mbit x 16 x 8 banks]
- drop SPL related macros
- drop memtest macros
- drop CONFIG_SPI_BOOT, CONFIG_SYS_USE_DATAFLASH related macros
- drop inclusion of asm/arch/at91sam9_smc.h]
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/Kconfig| 7 +
board/atmel/sam9x60ek/Kconfig | 12
board/atmel/sam9x60ek/MAINTAINERS | 6
board/atmel/sam9x60ek/Makefile| 7 +
board/atmel/sam9x60ek/sam9x60ek.c | 59 ++
include/configs/sam9x60ek.h | 60 +++
6 files changed, 151 insertions(+)
create mode 100644 board/atmel/sam9x60ek/Kconfig
create mode 100644 board/atmel/sam9x60ek/MAINTAINERS
create mode 100644 board/atmel/sam9x60ek/Makefile
create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c
create mode 100644 include/configs/sam9x60ek.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 3cf13042b7b4..85524004f9e4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -160,6 +160,12 @@ config TARGET_GARDENA_SMART_GATEWAY_AT91SAM
select BOARD_LATE_INIT
select SUPPORT_SPL
+config TARGET_SAM9X60EK
+ bool "SAM9X60-EK board"
+ select SAM9X60
+ select BOARD_EARLY_INIT_F
+ select BOARD_LATE_INIT
+
config TARGET_SAMA5D2_PTC_EK
bool "SAMA5D2 PTC EK board"
select BOARD_EARLY_INIT_F
@@ -316,6 +322,7 @@ source "board/atmel/at91sam9m10g45ek/Kconfig"
source "board/atmel/at91sam9n12ek/Kconfig"
source "board/atmel/at91sam9rlek/Kconfig"
source "board/atmel/at91sam9x5ek/Kconfig"
+source "board/atmel/sam9x60ek/Kconfig"
source "board/atmel/sama5d2_ptc_ek/Kconfig"
source "board/atmel/sama5d2_xplained/Kconfig"
source "board/atmel/sama5d27_som1_ek/Kconfig"
diff --git a/board/atmel/sam9x60ek/Kconfig b/board/atmel/sam9x60ek/Kconfig
new file mode 100644
index ..32fae2108e6e
--- /dev/null
+++ b/board/atmel/sam9x60ek/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_SAM9X60EK
+
+config SYS_BOARD
+ default "sam9x60ek"
+
+config SYS_VENDOR
+ default "atmel"
+
+config SYS_CONFIG_NAME
+ default "sam9x60ek"
+
+endif
diff --git a/board/atmel/sam9x60ek/MAINTAINERS
b/board/atmel/sam9x60ek/MAINTAINERS
new file mode 100644
index ..93ed5d9f1509
--- /dev/null
+++ b/board/atmel/sam9x60ek/MAINTAINERS
@@ -0,0 +1,6 @@
+SAM9X60EK BOARD
+M: Sandeep Sheriker M
+S: Maintained
+F: board/atmel/sam9x60ek/
+F: include/configs/sam9x60ek.h
+F: configs/sam9x60ek_mmc_defconfig
diff --git a/board/atmel/sam9x60ek/Makefile b/board/atmel/sam9x60ek/Makefile
new file mode 100644
index ..12a406a3bb5c
--- /dev/null
+++ b/board/atmel/sam9x60ek/Makefile
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+#
+# Author: Sandeep Sheriker M
+
+obj-y += sam9x60ek.o
diff --git a/board/atmel/sam9x60ek/sam9x60ek.c
b/board/atmel/sam9x60ek/sam9x60ek.c
new file mode 100644
index ..62938741ddd6
--- /dev/null
+++ b/board/atmel/sam9x60ek/sam9x60ek.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void at91_prepare_cpu_var(void);
+
+#ifdef CONFIG_BOARD_LATE_INIT
+int board_late_init(void)
+{
+ at91_prepare_cpu_var();
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_DEBUG_UART_BOARD_INIT
+void board_debug_uart_init(void)
+{
+ at91_seriald_hw_init();
+}
+#endif
+
+#ifdef CONFIG_BOARD_EARLY_INIT_F
+int board_early_init_f(void)
+{
+#ifdef CONFIG_DEBUG_UART
+ debug_uart_init();
+#endif
+ return 0;
+}
+#endif
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h
new file mode 100644
index ..b778bd8e83eb
--- /dev/null
+++ b/include/configs/sam9x60ek.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuation settings for the SAM9X60EK board.
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+/* ARM asynchronous clock */
+#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
+#define CONFIG_SYS_AT91_MAIN_CLOCK 2400/* 24 MHz crystal */
+
+#define CONFIG_CMDLIN
[U-Boot] [PATCH 02/12] ARM: dts: Add dts files for sam9x60ek
From: Sandeep Sheriker Mallikarjun
add device tree files for sam9x60ek board with below changes.
- Add initial device nodes (pmc, pinctrl, sdhc, dbgu & pit)
- Add the reg property for the pinctrl node.
- Add the "u-boot,dm-pre-reloc" property to determine which nodes
are used by the board_init_f stage.
Signed-off-by: Sandeep Sheriker Mallikarjun
[prasanthi.chellaku...@microchip.com: fix style/whitespace issues]
Signed-off-by: Prasanthi Chellakumar
[nicolas.fe...@microchip.com:
- fix gclk,
- fix pio/pinctrl controller definition and allow to have more
than only PIOA for this SoC,
- removing pinctrl address]
Signed-off-by: Nicolas Ferre
[claudiu.bez...@microchip.com:
- use SAM9X60's compatible for pinctrl
- add drive strength and slew rate options for SDMMC0 pins.]
Signed-off-by: Claudiu Beznea
[tudor.amba...@microchip.com:
- u-boot,dm-pre-reloc property in dedicated file,
- fix pit len, starts from 0xFE40 and it is of len 0x10]
Signed-off-by: Tudor Ambarus
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sam9x60.dtsi | 225 +
arch/arm/dts/sam9x60ek-u-boot.dtsi | 104 +
arch/arm/dts/sam9x60ek.dts | 19
4 files changed, 350 insertions(+)
create mode 100644 arch/arm/dts/sam9x60.dtsi
create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi
create mode 100644 arch/arm/dts/sam9x60ek.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 250b9ba505aa..52027786ef50 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -690,6 +690,8 @@ dtb-$(CONFIG_TARGET_AT91SAM9X5EK) += \
at91sam9x25ek.dtb \
at91sam9x35ek.dtb
+dtb-$(CONFIG_TARGET_SAM9X60EK) += sam9x60ek.dtb
+
dtb-$(CONFIG_TARGET_AT91SAM9N12EK) += at91sam9n12ek.dtb
dtb-$(CONFIG_TARGET_GARDENA_SMART_GATEWAY_AT91SAM) += \
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/dts/sam9x60.dtsi
new file mode 100644
index ..e880dc0068df
--- /dev/null
+++ b/arch/arm/dts/sam9x60.dtsi
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * sam9x60.dtsi - Device Tree Include file for SAM9X60 SoC.
+ *
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ *
+ * Author: Sandeep Sheriker M
+ */
+
+#include "skeleton.dtsi"
+#include
+#include
+#include
+#include
+#include
+
+/{
+ model = "Microchip SAM9X60 SoC";
+ compatible = "microchip,sam9x60";
+
+ aliases {
+ serial0 = &dbgu;
+ gpio0 = &pioA;
+ gpio1 = &pioB;
+ };
+
+ clocks {
+ slow_xtal: slow_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ main_xtal: main_xtal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ ahb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sdhci0: sdhci-host@8000 {
+ compatible = "microchip,sam9x60-sdhci";
+ reg = <0x8000 0x300>;
+ clocks = <&sdhci0_clk>, <&sdhci0_gclk>, <&main>;
+ clock-names = "hclock", "multclk", "baseclk";
+ bus-width = <4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdhci0>;
+ };
+
+ apb {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ dbgu: serial@f200 {
+ compatible = "atmel,at91sam9260-dbgu",
"atmel,at91sam9260-usart";
+ reg = <0xf200 0x200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_dbgu>;
+ clocks = <&dbgu_clk>;
+ clock-names = "usart";
+ };
+
+ pinctrl {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "microchip,sam9x60-pinctrl",
"simple-bus";
+ ranges = <0xf400 0xf400 0x800>;
+ reg = <0xf400 0x200 /* pioA */
+ 0xf600 0x200 /* pioB */
+ 0xf800 0x200 /* pioC */
+ 0xfa00 0x200>; /* pioD */
+
+ /* shared pinctrl settings */
+ dbgu {
+
[U-Boot] [PATCH 01/12] ARM: at91: Add sam9x60 soc
From: Sandeep Sheriker Mallikarjun
Add new Microchip sam9x60 SoC based on an ARM926.
Signed-off-by: Sandeep Sheriker Mallikarjun
[tudor.amba...@microchip.com: fix SFR definition]
Signed-off-by: Tudor Ambarus
---
arch/arm/mach-at91/Kconfig | 4 +
arch/arm/mach-at91/arm926ejs/Makefile | 1 +
arch/arm/mach-at91/arm926ejs/sam9x60_devices.c | 125 ++
arch/arm/mach-at91/include/mach/hardware.h | 2 +
arch/arm/mach-at91/include/mach/sam9x60.h | 169 +
5 files changed, 301 insertions(+)
create mode 100644 arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
create mode 100644 arch/arm/mach-at91/include/mach/sam9x60.h
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 14343280793b..3cf13042b7b4 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -43,6 +43,10 @@ config AT91SAM9X5
bool
select CPU_ARM926EJS
+config SAM9X60
+ bool
+ select CPU_ARM926EJS
+
config SAMA5D2
bool
select CPU_V7A
diff --git a/arch/arm/mach-at91/arm926ejs/Makefile
b/arch/arm/mach-at91/arm926ejs/Makefile
index 6b0b28957af5..8de6a2f9661e 100644
--- a/arch/arm/mach-at91/arm926ejs/Makefile
+++ b/arch/arm/mach-at91/arm926ejs/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_AT91SAM9M10G45) += at91sam9m10g45_devices.o
obj-$(CONFIG_AT91SAM9G45) += at91sam9m10g45_devices.o
obj-$(CONFIG_AT91SAM9N12) += at91sam9n12_devices.o
obj-$(CONFIG_AT91SAM9X5) += at91sam9x5_devices.o
+obj-$(CONFIG_SAM9X60) += sam9x60_devices.o
obj-$(CONFIG_AT91_EFLASH) += eflash.o
obj-$(CONFIG_AT91_LED) += led.o
obj-y += clock.o
diff --git a/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
new file mode 100644
index ..d463bbc78863
--- /dev/null
+++ b/arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 Microchip Technology Inc. and its subsidiaries
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+unsigned int get_chip_id(void)
+{
+ /* The 0x40 is the offset of cidr in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x40) & ~ARCH_ID_VERSION_MASK;
+}
+
+unsigned int get_extension_chip_id(void)
+{
+ /* The 0x44 is the offset of exid in DBGU */
+ return readl(ATMEL_BASE_DBGU + 0x44);
+}
+
+unsigned int has_emac1(void)
+{
+ return cpu_is_sam9x60();
+}
+
+unsigned int has_emac0(void)
+{
+ return cpu_is_sam9x60();
+}
+
+unsigned int has_lcdc(void)
+{
+ return cpu_is_sam9x60();
+}
+
+char *get_cpu_name(void)
+{
+ unsigned int extension_id = get_extension_chip_id();
+
+ if (cpu_is_sam9x60()) {
+ switch (extension_id) {
+ case ARCH_EXID_SAM9X60:
+ return "SAM9X60";
+ default:
+ return "Unknown CPU type";
+ }
+ } else {
+ return "Unknown CPU type";
+ }
+}
+
+void at91_seriald_hw_init(void)
+{
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 9, 1); /* DRXD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
+
+ at91_periph_clk_enable(ATMEL_ID_DBGU);
+}
+
+void at91_mci_hw_init(void)
+{
+ /* Initialize the SDMMC0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 17, 1); /* CLK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 16, 1); /* CMD */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 15, 1); /* DAT0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 18, 1); /* DAT1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 19, 1); /* DAT2 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTA, 20, 1); /* DAT3 */
+
+ at91_periph_clk_enable(ATMEL_ID_SDMMC0);
+}
+
+#ifdef CONFIG_MACB
+void at91_macb_hw_init(void)
+{
+ if (has_emac0()) {
+ /* Enable EMAC0 clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC0);
+ /* EMAC0 pins setup */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 4, 0); /* ETXCK */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 3, 0); /* ERXDV */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 0, 0); /* ERX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 1, 0); /* ERX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 2, 0); /* ERXER */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 7, 0); /* ETXEN */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 9, 0); /* ETX0 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 10, 0); /* ETX1 */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 5, 0); /* EMDIO */
+ at91_pio3_set_a_periph(AT91_PIO_PORTB, 6, 0); /* EMDC */
+ }
+
+ if (has_emac1()) {
+ /* Enable EMAC1 clock */
+ at91_periph_clk_enable(ATMEL_ID_EMAC1);
+ /* EMAC1 pins setup */
+ at91_pio3_set_b_periph(AT91_PIO_POR
[U-Boot] [PATCH 00/12] add support for sam9x60ek
From: Tudor Ambarus
Add support for sam9x60 SOC, sam9x60ek board, dts, NAND and QSPI.
Add defconfigs for MMC, NAND and QSPI.
Nicolas Ferre (1):
ARM: dts: at91: sam9x60: Add macb0 Ethernet controller
Sandeep Sheriker Mallikarjun (4):
ARM: at91: Add sam9x60 soc
ARM: dts: Add dts files for sam9x60ek
board: atmel: Add sam9x60ek board
configs: Add sam9x60ek_mmc_defconfig
Tudor Ambarus (7):
ARM: at91: Rename sama5_sfr.h to at91_sfr.h
ARM: at91: Add SFR definitions
board: sam9x60ek: Add NAND flash support
configs: Add sam9x60ek_nandflash_defconfig
configs: sam9x60ek: Add QSPI_BOOT defines
ARM: dts: at91: sam9x60ek: Enable qspi node
configs: Add sam9x60ek_qspiflash_defconfig
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sam9x60.dtsi | 285 +
arch/arm/dts/sam9x60ek-u-boot.dtsi | 132 ++
arch/arm/dts/sam9x60ek.dts | 55
arch/arm/mach-at91/Kconfig | 11 +
arch/arm/mach-at91/arm926ejs/Makefile | 1 +
arch/arm/mach-at91/arm926ejs/sam9x60_devices.c | 125 +
arch/arm/mach-at91/armv7/sama5d4_devices.c | 2 +-
arch/arm/mach-at91/atmel_sfr.c | 2 +-
.../include/mach/{sama5_sfr.h => at91_sfr.h} | 52 +++-
arch/arm/mach-at91/include/mach/hardware.h | 2 +
arch/arm/mach-at91/include/mach/sam9x60.h | 169
board/atmel/sam9x60ek/Kconfig | 12 +
board/atmel/sam9x60ek/MAINTAINERS | 6 +
board/atmel/sam9x60ek/Makefile | 7 +
board/atmel/sam9x60ek/sam9x60ek.c | 120 +
board/laird/wb50n/wb50n.c | 2 +-
configs/sam9x60ek_mmc_defconfig| 52
configs/sam9x60ek_nandflash_defconfig | 51
configs/sam9x60ek_qspiflash_defconfig | 73 ++
drivers/clk/at91/clk-utmi.c| 2 +-
include/configs/sam9x60ek.h| 95 +++
22 files changed, 1249 insertions(+), 9 deletions(-)
create mode 100644 arch/arm/dts/sam9x60.dtsi
create mode 100644 arch/arm/dts/sam9x60ek-u-boot.dtsi
create mode 100644 arch/arm/dts/sam9x60ek.dts
create mode 100644 arch/arm/mach-at91/arm926ejs/sam9x60_devices.c
rename arch/arm/mach-at91/include/mach/{sama5_sfr.h => at91_sfr.h} (53%)
create mode 100644 arch/arm/mach-at91/include/mach/sam9x60.h
create mode 100644 board/atmel/sam9x60ek/Kconfig
create mode 100644 board/atmel/sam9x60ek/MAINTAINERS
create mode 100644 board/atmel/sam9x60ek/Makefile
create mode 100644 board/atmel/sam9x60ek/sam9x60ek.c
create mode 100644 configs/sam9x60ek_mmc_defconfig
create mode 100644 configs/sam9x60ek_nandflash_defconfig
create mode 100644 configs/sam9x60ek_qspiflash_defconfig
create mode 100644 include/configs/sam9x60ek.h
--
2.9.5
___
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[U-Boot] [PATCH] at91: configs: Drop duplication of defconfig macros
From: Tudor Ambarus
'commit a9221f3ebd6d ("at91, omap2plus: configs: migrate CONFIG_ENV_ to
defconfigs")'
migrated CONFIG_ENV_ macros to defconfigs but did not remove the
identical redefinition of these macros in include/configs/.
Since the duplicated macros have the same value as the ones in defconfigs,
no "redefined" warnings were raised. Remove duplicated macros for all
sama5 and sam9x5ek boards.
While verifying that the removal of the macros from include/configs did
not change the same macros in defconfigs, overwrite the old defconfig by
saving them with the output from "make arch=ARM savedefconfig". This
resulted in the movement of some macros in the defconfig files.
Signed-off-by: Tudor Ambarus
---
configs/sama5d27_som1_ek_mmc1_defconfig | 2 +-
configs/sama5d27_som1_ek_mmc_defconfig | 2 +-
configs/sama5d27_som1_ek_qspiflash_defconfig | 2 +-
configs/sama5d2_ptc_ek_mmc_defconfig | 1 -
configs/sama5d2_ptc_ek_nandflash_defconfig | 1 -
configs/sama5d2_xplained_emmc_defconfig | 2 +-
configs/sama5d2_xplained_mmc_defconfig | 2 +-
configs/sama5d2_xplained_qspiflash_defconfig | 2 +-
configs/sama5d2_xplained_spiflash_defconfig | 2 +-
configs/sama5d3_xplained_mmc_defconfig | 2 +-
configs/sama5d3xek_mmc_defconfig | 2 +-
configs/sama5d3xek_spiflash_defconfig| 2 +-
configs/sama5d4_xplained_mmc_defconfig | 2 +-
configs/sama5d4_xplained_spiflash_defconfig | 2 +-
configs/sama5d4ek_mmc_defconfig | 2 +-
configs/sama5d4ek_spiflash_defconfig | 2 +-
include/configs/at91-sama5_common.h | 8
include/configs/at91sam9x5ek.h | 11 ---
include/configs/sama5d27_som1_ek.h | 2 --
include/configs/sama5d2_icp.h| 1 -
20 files changed, 14 insertions(+), 38 deletions(-)
diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig
b/configs/sama5d27_som1_ek_mmc1_defconfig
index 29d364ce1778..3d877f77d8fd 100644
--- a/configs/sama5d27_som1_ek_mmc1_defconfig
+++ b/configs/sama5d27_som1_ek_mmc1_defconfig
@@ -18,6 +18,7 @@ CONFIG_DEBUG_UART_CLOCK=8200
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x20
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
@@ -27,7 +28,6 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk1p2 rw
rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x20
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d27_som1_ek_mmc_defconfig
b/configs/sama5d27_som1_ek_mmc_defconfig
index bb74c639939b..cadaa93355a4 100644
--- a/configs/sama5d27_som1_ek_mmc_defconfig
+++ b/configs/sama5d27_som1_ek_mmc_defconfig
@@ -19,6 +19,7 @@ CONFIG_DEBUG_UART_CLOCK=8200
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x20
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
@@ -28,7 +29,6 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw
rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x20
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig
b/configs/sama5d27_som1_ek_qspiflash_defconfig
index 50b7983850dc..97f1efc626ef 100644
--- a/configs/sama5d27_som1_ek_qspiflash_defconfig
+++ b/configs/sama5d27_som1_ek_qspiflash_defconfig
@@ -19,6 +19,7 @@ CONFIG_ENV_SECT_SIZE=0x1000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_DEBUG_UART=y
+CONFIG_SPL_TEXT_BASE=0x20
CONFIG_ENV_VARS_UBOOT_CONFIG=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2"
@@ -28,7 +29,6 @@ CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw
rootwait"
CONFIG_MISC_INIT_R=y
# CONFIG_DISPLAY_BOARDINFO is not set
-CONFIG_SPL_TEXT_BASE=0x20
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_BOOTZ=y
diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig
b/configs/sama5d2_ptc_ek_mmc_defconfig
index 17699dec52f9..e1ff84f3b4c9 100644
--- a/configs/sama5d2_ptc_ek_mmc_defconfig
+++ b/configs/sama5d2_ptc_ek_mmc_defconfig
@@ -36,7 +36,6 @@ CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig
b/configs/sama5d2_ptc_ek_nandflash_defconfig
index 0b18bd41fc2c..4210a52a1319 100644
--- a/configs/sama5d2_ptc_ek_nandflash_defconfig
+++ b/configs/sama5d2_ptc_ek_nandflash_defconfig
@@ -35,7 +35,6 @@ CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_ptc_ek"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
-CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_CLK=y
CONFIG_CLK_AT91=y
CONFIG_AT91_UTMI=y
diff
[U-Boot] [PATCH v5 10/10] configs: sama5d2_xplained: add support QSPI flash boot
From: Eugen Hristev The spi-nor flash resides on spi bus 1. Update the CONFIG_ENV_SPI_CS and CONFIG_BOOTCOMMAND accordingly. Based on original work by Wenyou Yang. Signed-off-by: Eugen Hristev [tudor.amba...@microchip.com: amend the commit message.] Signed-off-by: Tudor Ambarus --- v5: no change v4: no change v3: no change v2: new patch include/configs/sama5d2_xplained.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index e522740e0c5b..3dea3591275f 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -46,6 +46,17 @@ #endif +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_ENV_SPI_BUS +#undef CONFIG_BOOTCOMMAND +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_BOOTCOMMAND "sf probe 1:0; "\ + "sf read 0x2100 0x18 0x8; " \ + "sf read 0x2200 0x20 0x60; "\ + "bootz 0x2200 - 0x2100" + +#endif + /* SPL */ #define CONFIG_SPL_MAX_SIZE0x1 #define CONFIG_SPL_BSS_START_ADDR 0x2000 -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 06/10] ARM: at91: sama5: add common environment for QSPI
From: Cyrille Pitchen Use the same memory layout as we use for the NAND boot on the other boards. QSPI flashes are present on the following boards: sama5d2_xplained RevB: 32 Mbyte flash (mx25l3273fm2i-08g) sama5d2_xplained RevC: 8 Mbyte flash (sst26vf064b-104i/sn) sama5d27_som1_ek:8 Mbyte flash (sst26vf064b-104i/sn) sama5d2_ptc_ek: 8 Mbyte flash (sst26vf064b-104i/sn) The 8 Mbyte limit is enough to cope with the memory layout used in the NAND boot. rootfs exceeds the 8 Mbyte limit and will stay in eMMC in the sama5d2_xplained case. The final scope is to use a single memory layout for all boot medias. Signed-off-by: Cyrille Pitchen [tudor.amba...@microchip.com: change memory layout, add commit message] Signed-off-by: Tudor Ambarus --- v5: no change v4: no change v3: no change v2: new patch include/configs/at91-sama5_common.h | 8 1 file changed, 8 insertions(+) diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 30c6cd47cac2..fc46540a10ab 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -72,6 +72,14 @@ "sf read 0x2100 0x6 0xc000; " \ "sf read 0x2200 0x6c000 0x394000; " \ "bootz 0x2200 - 0x2100" +#elif CONFIG_QSPI_BOOT +#define CONFIG_ENV_OFFSET 0x14 +#define CONFIG_ENV_SIZE0x2 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x2100 0x18 0x8; " \ + "sf read 0x2200 0x20 0x60; "\ + "bootz 0x2200 - 0x2100" #endif #endif -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 04/10] configs: sama5d27_som1_ek: enable qspi controller and flashes
From: Tudor Ambarus We use a sst spi-nor flash memory on sama5d27_som1_ek. Select the others for testing purposes. Signed-off-by: Tudor Ambarus --- v5: no change v4: no change v3: no change v2: new patch configs/sama5d27_som1_ek_mmc1_defconfig | 2 ++ configs/sama5d27_som1_ek_mmc_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 205a4399410f..9b2b78110357 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=6600 CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y @@ -80,6 +81,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 0a0780066cd8..e5c551e205d0 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=6600 CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y @@ -80,6 +81,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 08/10] configs: sama5d27_som1_ek: add qspiflash_defconfig
From: Tudor Ambarus Add the default config file of QSPI media. The config is based on sama5d27_som1_ek_mmc_defconfig. Signed-off-by: Tudor Ambarus --- v5: no change v4: no change v3: fix the following: ./tools/genboardscfg.py WARNING: no status info for 'sama5d27_som1_ek_qspiflash' WARNING: no maintainers for 'sama5d27_som1_ek_qspiflash' v2: new patch board/atmel/sama5d27_som1_ek/MAINTAINERS | 1 + configs/sama5d27_som1_ek_qspiflash_defconfig | 101 +++ 2 files changed, 102 insertions(+) create mode 100644 configs/sama5d27_som1_ek_qspiflash_defconfig diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS index 74434e93e952..f2d2f49db304 100644 --- a/board/atmel/sama5d27_som1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -5,3 +5,4 @@ F: board/atmel/sama5d27_som1_ek/ F: include/configs/sama5d27_som1_ek.h F: configs/sama5d27_som1_ek_mmc_defconfig F: configs/sama5d27_som1_ek_mmc1_defconfig +F: configs/sama5d27_som1_ek_qspiflash_defconfig diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig new file mode 100644 index ..128b6645f6d9 --- /dev/null +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAMA5D27_SOM1_EK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf802 +CONFIG_DEBUG_UART_CLOCK=8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_TEXT_BASE=0x20 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=6600 +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_ATMEL_USBA=y +CONFIG_DM_VIDEO=y +CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 05/10] ARM: dts: at91: sama5d2_xplained: fix QSPI0 node
From: Cyrille Pitchen
Fix the following:
- use "jedec,spi-nor" binding, we use jedec compatible flashes
- set bus width to 4, we use quad capable flashes
- differentiate bewteen data and clk and cs pins
- drop partions as we don't use them in u-boot.
Signed-off-by: Cyrille Pitchen
[tudor.amba...@microchip.com: use "jedec,spi-nor", edit commit message]
Signed-off-by: Tudor Ambarus
---
v5: no change
v4: no change
v3: no change
v2: new patch
arch/arm/dts/at91-sama5d2_xplained.dts | 36 --
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts
b/arch/arm/dts/at91-sama5d2_xplained.dts
index c0708feeb7b2..7f0d1696ba3e 100644
--- a/arch/arm/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/dts/at91-sama5d2_xplained.dts
@@ -79,26 +79,18 @@
};
qspi0: spi@f002 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0_sck_cs_default
&pinctrl_qspi0_dat_default>;
status = "okay";
+ u-boot,dm-pre-reloc;
flash@0 {
- compatible = "atmel,sama5d2-qspi-flash";
+ compatible = "jedec,spi-nor";
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi0_default>;
spi-max-frequency = <8300>;
-
- partition@ {
- label = "boot";
- reg = <0x 0x00c0>;
- };
-
- partition@00c0 {
- label = "rootfs";
- reg = <0x00c0 0x>;
- };
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
};
};
@@ -208,14 +200,20 @@
bias-disable;
};
- pinctrl_qspi0_default: qspi0_default {
+ pinctrl_qspi0_sck_cs_default:
qspi0_sck_cs_default {
pinmux = ,
-,
-,
+;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_qspi0_dat_default:
qspi0_dat_default {
+ pinmux = ,
,
,
;
- bias-disable;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
};
pinctrl_sdmmc0_cmd_dat_default:
sdmmc0_cmd_dat_default {
--
2.9.5
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[U-Boot] [PATCH v5 03/10] configs: sama5d2_xplained: enable qspi controller and flashes
From: Tudor Ambarus We have a macronix spi-nor flash on sama5d2_xplained RevB and a sst spi-nor flash on RevC. Select the rest for testing purposes. Signed-off-by: Tudor Ambarus --- v5: no change v4: no change v3: no change v2: new patch configs/sama5d2_xplained_emmc_defconfig | 5 + configs/sama5d2_xplained_mmc_defconfig | 5 + configs/sama5d2_xplained_spiflash_defconfig | 5 + 3 files changed, 15 insertions(+) diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index f643b5a62f39..f244777121b1 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -65,6 +65,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y @@ -76,6 +80,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index c25d67bfebb1..633f6c5ad00c 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -67,6 +67,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y @@ -78,6 +82,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index ac5ae5133c3d..39da86530429 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -64,6 +64,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y @@ -75,6 +79,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 09/10] configs: sama5d27_som1_ek: qspi: use common memory layout
From: Tudor Ambarus Use the qspi memory layout defined in at91-sama5_common - it aligns with the 8 Mbyte flash (sst26vf064b-104i/sn) available in sama5d27_som1_ek. Signed-off-by: Tudor Ambarus --- v5: no change v4: no change v3: no change v2: new patch include/configs/sama5d27_som1_ek.h | 7 --- 1 file changed, 7 deletions(-) diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 5f6979cd77a5..90846c4bfd44 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -43,13 +43,6 @@ #endif #ifdef CONFIG_QSPI_BOOT -#define CONFIG_ENV_OFFSET 0xb -#define CONFIG_ENV_SIZE0x1 -#define CONFIG_ENV_SECT_SIZE 0x1 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x2100 0xc 0x2; " \ - "sf read 0x2200 0xe 0x40; " \ - "bootz 0x2200 - 0x2100" #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 07/10] configs: sama5d2_xplained: add qspiflash_defconfig
From: Tudor Ambarus Add the default config file of QSPI media. The config is based on sama5d2_xplained_mmc_defconfig. Signed-off-by: Tudor Ambarus --- v5: no change v4: no change v3: fix the following: ./tools/genboardscfg.py WARNING: no status info for 'sama5d2_xplained_qspiflash' WARNING: no maintainers for 'sama5d2_xplained_qspiflash' v2: new patch board/atmel/sama5d2_xplained/MAINTAINERS | 1 + configs/sama5d2_xplained_qspiflash_defconfig | 101 +++ 2 files changed, 102 insertions(+) create mode 100644 configs/sama5d2_xplained_qspiflash_defconfig diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS index 08de5bb6a076..88e327f81cd8 100644 --- a/board/atmel/sama5d2_xplained/MAINTAINERS +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -6,3 +6,4 @@ F: include/configs/sama5d2_xplained.h F: configs/sama5d2_xplained_mmc_defconfig F: configs/sama5d2_xplained_spiflash_defconfig F: configs/sama5d2_xplained_emmc_defconfig +F: configs/sama5d2_xplained_qspiflash_defconfig diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig new file mode 100644 index ..1bf04936f748 --- /dev/null +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x26f0 +CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf802 +CONFIG_DEBUG_UART_CLOCK=8300 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_TEXT_BASE=0x20 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=3000 +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_ATMEL_USBA=y +CONFIG_DM_VIDEO=y +CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v5 02/10] spi: Add Atmel QuadSPI driver
From: Tudor Ambarus Backport the driver from linux v5.1-rc5 and adapt it for u-boot. Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash. Signed-off-by: Tudor Ambarus --- v5: drop struct platform_device *pdev; linux leftover, 2 new blank lines v4: update Kconfig description v3: no change v2: no change drivers/spi/Kconfig | 8 + drivers/spi/Makefile| 1 + drivers/spi/atmel-quadspi.c | 536 3 files changed, 545 insertions(+) create mode 100644 drivers/spi/atmel-quadspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 04ddb32a8f31..a9c080c4fe9c 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -49,6 +49,14 @@ config ATH79_SPI uses driver model and requires a device tree binding to operate. please refer to doc/device-tree-bindings/spi/spi-ath79.txt. +config ATMEL_QSPI + bool "Atmel Quad SPI Controller" + depends on ARCH_AT91 + help + Enable the Atmel Quad SPI controller in master mode. This driver + does not support generic SPI. The implementation supports only the + spi-mem interface. + config ATMEL_SPI bool "Atmel SPI driver" default y if ARCH_AT91 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3f9f2fab2b9f..64c407e2eddf 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -18,6 +18,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o +obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c new file mode 100644 index ..7d9a54011dda --- /dev/null +++ b/drivers/spi/atmel-quadspi.c @@ -0,0 +1,536 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Atmel QSPI Controller + * + * Copyright (C) 2015 Atmel Corporation + * Copyright (C) 2018 Cryptera A/S + * + * Author: Cyrille Pitchen + * Author: Piotr Bugalski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* QSPI register offsets */ +#define QSPI_CR 0x /* Control Register */ +#define QSPI_MR 0x0004 /* Mode Register */ +#define QSPI_RD 0x0008 /* Receive Data Register */ +#define QSPI_TD 0x000c /* Transmit Data Register */ +#define QSPI_SR 0x0010 /* Status Register */ +#define QSPI_IER 0x0014 /* Interrupt Enable Register */ +#define QSPI_IDR 0x0018 /* Interrupt Disable Register */ +#define QSPI_IMR 0x001c /* Interrupt Mask Register */ +#define QSPI_SCR 0x0020 /* Serial Clock Register */ + +#define QSPI_IAR 0x0030 /* Instruction Address Register */ +#define QSPI_ICR 0x0034 /* Instruction Code Register */ +#define QSPI_WICR0x0034 /* Write Instruction Code Register */ +#define QSPI_IFR 0x0038 /* Instruction Frame Register */ +#define QSPI_RICR0x003C /* Read Instruction Code Register */ + +#define QSPI_SMR 0x0040 /* Scrambling Mode Register */ +#define QSPI_SKR 0x0044 /* Scrambling Key Register */ + +#define QSPI_WPMR0x00E4 /* Write Protection Mode Register */ +#define QSPI_WPSR0x00E8 /* Write Protection Status Register */ + +#define QSPI_VERSION 0x00FC /* Version Register */ + +/* Bitfields in QSPI_CR (Control Register) */ +#define QSPI_CR_QSPIEN BIT(0) +#define QSPI_CR_QSPIDIS BIT(1) +#define QSPI_CR_SWRST BIT(7) +#define QSPI_CR_LASTXFERBIT(24) + +/* Bitfields in QSPI_MR (Mode Register) */ +#define QSPI_MR_SMM BIT(0) +#define QSPI_MR_LLB BIT(1) +#define QSPI_MR_WDRBT BIT(2) +#define QSPI_MR_SMRMBIT(3) +#define QSPI_MR_CSMODE_MASK GENMASK(5, 4) +#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4) +#define QSPI_MR_CSMODE_LASTXFER (1 << 4) +#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4) +#define QSPI_MR_NBBITS_MASK GENMASK(11, 8) +#define QSPI_MR_NBBITS(n) n) - 8) << 8) & QSPI_MR_NBBITS_MASK) +#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16) +#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK) +#define QSPI_MR_DLYCS_MASK GENMASK(31, 24) +#define QSPI_MR_DLYCS(n)(((n) << 24) & QSPI_MR_DLYCS_MASK) + +/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */ +#define QSPI_SR_RDRFBIT(0) +#define QSPI_SR_TDREBIT(1) +#define QSPI_SR_TXEMPTY BIT(2) +#define QSPI_SR_OVRES BIT(3) +#define QSPI_SR_CSR BIT(8) +#define QSPI_SR_CSS BIT(9) +#define QSPI_SR_INSTRE BIT(10) +#define QSPI_SR_QSPIENS BIT(24) + +#define QSPI_SR_CMD_COMPLETED
[U-Boot] [PATCH v5 01/10] dt-bindings: spi: add bindings for Atmel QSPI driver
From: Tudor Ambarus
Describe the DT bindings for the driver of the Atmel QSPI
controller. Taken form linux v5.1-rc5.
Signed-off-by: Tudor Ambarus
---
v5: no change
v4: no change
v3: no change
v2: no change
doc/device-tree-bindings/spi/atmel-quadspi.txt | 37 ++
1 file changed, 37 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/atmel-quadspi.txt
diff --git a/doc/device-tree-bindings/spi/atmel-quadspi.txt
b/doc/device-tree-bindings/spi/atmel-quadspi.txt
new file mode 100644
index ..7c40ea694352
--- /dev/null
+++ b/doc/device-tree-bindings/spi/atmel-quadspi.txt
@@ -0,0 +1,37 @@
+* Atmel Quad Serial Peripheral Interface (QSPI)
+
+Required properties:
+- compatible: Should be one of the following:
+ - "atmel,sama5d2-qspi"
+ - "microchip,sam9x60-qspi"
+- reg:Should contain the locations and lengths of the base
registers
+ and the mapped memory.
+- reg-names: Should contain the resource reg names:
+ - qspi_base: configuration register address space
+ - qspi_mmap: memory mapped address space
+- interrupts: Should contain the interrupt for the device.
+- clocks: Should reference the peripheral clock and the QSPI system
+ clock if available.
+- clock-names:Should contain "pclk" for the peripheral clock and "qspick"
+ for the system clock when available.
+- #address-cells: Should be <1>.
+- #size-cells:Should be <0>.
+
+Example:
+
+spi@f002 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0xf002 0x100>, <0xd000 0x800>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+
+ m25p80@0 {
+ ...
+ };
+};
--
2.9.5
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[U-Boot] [PATCH v5 00/10] spi: Add Atmel QuadSPI driver
From: Tudor Ambarus Backport the driver from linux v5.1-rc5 and adapt it for u-boot. Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash, and on sama5d27_som1_ek with sst26vf064b spi-nor flash. V5: drop struct platform_device *pdev; linux leftover, add 2 new blank lines v4: Update Kconfig description v3: fix following config warnings reported by travis: ./tools/genboardscfg.py WARNING: no status info for 'sama5d2_xplained_qspiflash' WARNING: no maintainers for 'sama5d2_xplained_qspiflash' WARNING: no status info for 'sama5d27_som1_ek_qspiflash' WARNING: no maintainers for 'sama5d27_som1_ek_qspiflash' v2: update/add configs and update sama5d2_xplained dts Cyrille Pitchen (2): ARM: dts: at91: sama5d2_xplained: fix QSPI0 node ARM: at91: sama5: add common environment for QSPI Eugen Hristev (1): configs: sama5d2_xplained: add support QSPI flash boot Tudor Ambarus (7): dt-bindings: spi: add bindings for Atmel QSPI driver spi: Add Atmel QuadSPI driver configs: sama5d2_xplained: enable qspi controller and flashes configs: sama5d27_som1_ek: enable qspi controller and flashes configs: sama5d2_xplained: add qspiflash_defconfig configs: sama5d27_som1_ek: add qspiflash_defconfig configs: sama5d27_som1_ek: qspi: use common memory layout arch/arm/dts/at91-sama5d2_xplained.dts | 36 +- board/atmel/sama5d27_som1_ek/MAINTAINERS | 1 + board/atmel/sama5d2_xplained/MAINTAINERS | 1 + configs/sama5d27_som1_ek_mmc1_defconfig| 2 + configs/sama5d27_som1_ek_mmc_defconfig | 2 + configs/sama5d27_som1_ek_qspiflash_defconfig | 101 + configs/sama5d2_xplained_emmc_defconfig| 5 + configs/sama5d2_xplained_mmc_defconfig | 5 + configs/sama5d2_xplained_qspiflash_defconfig | 101 + configs/sama5d2_xplained_spiflash_defconfig| 5 + doc/device-tree-bindings/spi/atmel-quadspi.txt | 37 ++ drivers/spi/Kconfig| 8 + drivers/spi/Makefile | 1 + drivers/spi/atmel-quadspi.c| 536 + include/configs/at91-sama5_common.h| 8 + include/configs/sama5d27_som1_ek.h | 7 - include/configs/sama5d2_xplained.h | 11 + 17 files changed, 841 insertions(+), 26 deletions(-) create mode 100644 configs/sama5d27_som1_ek_qspiflash_defconfig create mode 100644 configs/sama5d2_xplained_qspiflash_defconfig create mode 100644 doc/device-tree-bindings/spi/atmel-quadspi.txt create mode 100644 drivers/spi/atmel-quadspi.c -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
Re: [U-Boot] [PATCH v4 02/10] spi: Add Atmel QuadSPI driver
Hi, Jagan,
On 06/12/2019 11:02 AM, Jagan Teki wrote:
> External E-Mail
>
>
> On Wed, May 15, 2019 at 12:33 PM wrote:
>>
>> From: Tudor Ambarus
>>
>> Backport the driver from linux v5.1-rc5 and adapt it for u-boot.
>> Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash.
>>
>> Signed-off-by: Tudor Ambarus
>> ---
>> v4: update Kconfig description
>> v3: no change
>> v2: no change
>>
>> drivers/spi/Kconfig | 8 +
>> drivers/spi/Makefile| 1 +
>> drivers/spi/atmel-quadspi.c | 535
>>
>> 3 files changed, 544 insertions(+)
>> create mode 100644 drivers/spi/atmel-quadspi.c
>>
cut
>> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
>> new file mode 100644
>> index ..c54fbe6bc6cf
>> --- /dev/null
>> +++ b/drivers/spi/atmel-quadspi.c
>> @@ -0,0 +1,535 @@
cut
>> +struct atmel_qspi {
>> + void __iomem *regs;
>> + void __iomem *mem;
>> + struct platform_device *pdev;
>
> Linux copy, please drop this.
>
will do
>> +static int atmel_qspi_probe(struct udevice *dev)
>> +{
>> + struct atmel_qspi *aq = dev_get_priv(dev);
>> + struct resource res;
>> + int ret;
>> +
>> + aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
>> + if (!aq->caps) {
>> + dev_err(dev, "Could not retrieve QSPI caps\n");
>> + return -EINVAL;
>> + };
>> +
>> + /* Map the registers */
>> + ret = dev_read_resource_byname(dev, "qspi_base", &res);
>> + if (ret) {
>> + dev_err(dev, "missing registers\n");
>> + return ret;
>> + }
>
> space
ok
>
>> + aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
>> + if (IS_ERR(aq->regs))
>> + return PTR_ERR(aq->regs);
>> +
>> + /* Map the AHB memory */
>> + ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
>> + if (ret) {
>> + dev_err(dev, "missing AHB memory\n");
>> + return ret;
>> + }
>
> space
ok
>
>> + aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
>> + if (IS_ERR(aq->mem))
>> + return PTR_ERR(aq->mem);
>> +
>> + ret = atmel_qspi_enable_clk(dev);
>> + if (ret)
>> + return ret;
>> +
>> + atmel_qspi_init(aq);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
>> + .supports_op = atmel_qspi_supports_op,
>> + .exec_op = atmel_qspi_exec_op,
>> +};
>> +
>> +static const struct dm_spi_ops atmel_qspi_ops = {
>> + .set_speed = atmel_qspi_set_speed,
>> + .set_mode = atmel_qspi_set_mode,
>> + .mem_ops = &atmel_qspi_mem_ops,
>> +};
>> +
>> +static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
>> +
>> +static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
>> + .has_qspick = true,
>> + .has_ricr = true,
>> +};
>> +
>> +static const struct udevice_id atmel_qspi_ids[] = {
>> + {
>> + .compatible = "atmel,sama5d2-qspi",
>> + .data = (ulong)&atmel_sama5d2_qspi_caps,
>
> Better assign NULL
I deliberately added a zeroed caps instance to the sama5d2 entry to not allow
aq->caps to be NULL. This way I avoid redundant checks like:
+ if (aq->caps && aq->caps->has_qspick) {
and
+ if (aq->caps && aq->caps->has_ricr) {
Since this patch is just a backport from the linux driver and does not modify
the code logic, can we keep it as it is, and modify it later on if you have a
strong opinion on this?
Cheers,
ta
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[U-Boot] [PATCH] configs: sama5d2_ptc_ek: fix NAND PMECC_CAP
From: Tudor Ambarus
CONFIG_PMECC_CAP has a higher priority than its ONFI detected
parameter and will overwrite it when defined. As per commit
49ad40298cc5, CONFIG_PMECC_CAP has a default value of 2 if not
otherwise stated. This results in the overwriting of the ONFI ECC
bits value. The following errors are seen when booting the kernel
from the nand flash:
Loading Environment from NAND... PMECC: Too many errors
NAND read from offset 14 failed -74
*** Warning - some problems detected reading environment; recovered successfully
*** Warning - bad CRC, using default environment
In:serial
Out: serial
Err: serial
Net: eth0: ethernet@f8008000
Hit any key to stop autoboot: 0
NAND read: device 0 offset 0x18, size 0x8
PMECC: Too many errors
NAND read from offset 18 failed -74
0 bytes read: ERROR
NAND read: device 0 offset 0x20, size 0x60
PMECC: Too many errors
NAND read from offset 20 failed -74
0 bytes read: ERROR
Bad Linux ARM zImage magic!
Fix it by setting the right value for ECC bits.
Fixes: 49ad40298cc5 ("ARM: at91: Convert SPL_GENERATE_ATMEL_PMECC_HEADER to
Kconfig")
Signed-off-by: Tudor Ambarus
---
configs/sama5d2_ptc_ek_mmc_defconfig | 1 +
configs/sama5d2_ptc_ek_nandflash_defconfig | 1 +
2 files changed, 2 insertions(+)
diff --git a/configs/sama5d2_ptc_ek_mmc_defconfig
b/configs/sama5d2_ptc_ek_mmc_defconfig
index bf2b5584df17..25b3aaf623ed 100644
--- a/configs/sama5d2_ptc_ek_mmc_defconfig
+++ b/configs/sama5d2_ptc_ek_mmc_defconfig
@@ -51,6 +51,7 @@ CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_NAND=y
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=4
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
diff --git a/configs/sama5d2_ptc_ek_nandflash_defconfig
b/configs/sama5d2_ptc_ek_nandflash_defconfig
index 9608ecd0b33f..3f7e6270d0ca 100644
--- a/configs/sama5d2_ptc_ek_nandflash_defconfig
+++ b/configs/sama5d2_ptc_ek_nandflash_defconfig
@@ -50,6 +50,7 @@ CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ATMEL=y
CONFIG_NAND_ATMEL=y
CONFIG_ATMEL_NAND_HW_PMECC=y
+CONFIG_PMECC_CAP=4
CONFIG_DM_ETH=y
CONFIG_MACB=y
CONFIG_PINCTRL=y
--
2.9.5
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[U-Boot] [PATCH v4 02/10] spi: Add Atmel QuadSPI driver
From: Tudor Ambarus Backport the driver from linux v5.1-rc5 and adapt it for u-boot. Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash. Signed-off-by: Tudor Ambarus --- v4: update Kconfig description v3: no change v2: no change drivers/spi/Kconfig | 8 + drivers/spi/Makefile| 1 + drivers/spi/atmel-quadspi.c | 535 3 files changed, 544 insertions(+) create mode 100644 drivers/spi/atmel-quadspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index dc3e23f353aa..0b87c155b87a 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -49,6 +49,14 @@ config ATH79_SPI uses driver model and requires a device tree binding to operate. please refer to doc/device-tree-bindings/spi/spi-ath79.txt. +config ATMEL_QSPI + bool "Atmel Quad SPI Controller" + depends on ARCH_AT91 + help + Enable the Atmel Quad SPI controller in master mode. This driver + does not support generic SPI. The implementation supports only the + spi-mem interface. + config ATMEL_SPI bool "Atmel SPI driver" default y if ARCH_AT91 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8be9a4baa244..32b42d18b1af 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -18,6 +18,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o +obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c new file mode 100644 index ..c54fbe6bc6cf --- /dev/null +++ b/drivers/spi/atmel-quadspi.c @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Atmel QSPI Controller + * + * Copyright (C) 2015 Atmel Corporation + * Copyright (C) 2018 Cryptera A/S + * + * Author: Cyrille Pitchen + * Author: Piotr Bugalski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* QSPI register offsets */ +#define QSPI_CR 0x /* Control Register */ +#define QSPI_MR 0x0004 /* Mode Register */ +#define QSPI_RD 0x0008 /* Receive Data Register */ +#define QSPI_TD 0x000c /* Transmit Data Register */ +#define QSPI_SR 0x0010 /* Status Register */ +#define QSPI_IER 0x0014 /* Interrupt Enable Register */ +#define QSPI_IDR 0x0018 /* Interrupt Disable Register */ +#define QSPI_IMR 0x001c /* Interrupt Mask Register */ +#define QSPI_SCR 0x0020 /* Serial Clock Register */ + +#define QSPI_IAR 0x0030 /* Instruction Address Register */ +#define QSPI_ICR 0x0034 /* Instruction Code Register */ +#define QSPI_WICR0x0034 /* Write Instruction Code Register */ +#define QSPI_IFR 0x0038 /* Instruction Frame Register */ +#define QSPI_RICR0x003C /* Read Instruction Code Register */ + +#define QSPI_SMR 0x0040 /* Scrambling Mode Register */ +#define QSPI_SKR 0x0044 /* Scrambling Key Register */ + +#define QSPI_WPMR0x00E4 /* Write Protection Mode Register */ +#define QSPI_WPSR0x00E8 /* Write Protection Status Register */ + +#define QSPI_VERSION 0x00FC /* Version Register */ + +/* Bitfields in QSPI_CR (Control Register) */ +#define QSPI_CR_QSPIEN BIT(0) +#define QSPI_CR_QSPIDIS BIT(1) +#define QSPI_CR_SWRST BIT(7) +#define QSPI_CR_LASTXFERBIT(24) + +/* Bitfields in QSPI_MR (Mode Register) */ +#define QSPI_MR_SMM BIT(0) +#define QSPI_MR_LLB BIT(1) +#define QSPI_MR_WDRBT BIT(2) +#define QSPI_MR_SMRMBIT(3) +#define QSPI_MR_CSMODE_MASK GENMASK(5, 4) +#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4) +#define QSPI_MR_CSMODE_LASTXFER (1 << 4) +#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4) +#define QSPI_MR_NBBITS_MASK GENMASK(11, 8) +#define QSPI_MR_NBBITS(n) n) - 8) << 8) & QSPI_MR_NBBITS_MASK) +#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16) +#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK) +#define QSPI_MR_DLYCS_MASK GENMASK(31, 24) +#define QSPI_MR_DLYCS(n)(((n) << 24) & QSPI_MR_DLYCS_MASK) + +/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */ +#define QSPI_SR_RDRFBIT(0) +#define QSPI_SR_TDREBIT(1) +#define QSPI_SR_TXEMPTY BIT(2) +#define QSPI_SR_OVRES BIT(3) +#define QSPI_SR_CSR BIT(8) +#define QSPI_SR_CSS BIT(9) +#define QSPI_SR_INSTRE BIT(10) +#define QSPI_SR_QSPIENS BIT(24) + +#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR) + +/* Bitfields in QSPI_SCR (Serial Clock
Re: [U-Boot] [PATCH v3 02/10] spi: Add Atmel QuadSPI driver
On 05/14/2019 01:26 PM, Tudor Ambarus - M18064 wrote: > From: Tudor Ambarus > > Backport the driver from linux v5.1-rc5 and adapt it for u-boot. > Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash. > > Signed-off-by: Tudor Ambarus > --- > v3: no change > v2: no change > > drivers/spi/Kconfig | 7 + > drivers/spi/Makefile| 1 + > drivers/spi/atmel-quadspi.c | 535 > > 3 files changed, 543 insertions(+) > create mode 100644 drivers/spi/atmel-quadspi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index dc3e23f353aa..69c2f92c7826 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -49,6 +49,13 @@ config ATH79_SPI > uses driver model and requires a device tree binding to operate. > please refer to doc/device-tree-bindings/spi/spi-ath79.txt. > > +config ATMEL_QSPI > + bool "Atmel QSPI driver" "Atmel Quad SPI Controller" > + depends on ARCH_AT91 > + help > + Enable the Ateml Quad-SPI (QSPI) driver. This driver can only be > + used to access SPI NOR flashes. The description is wrong, I'll submit a new version if everything else looks ok. This should have been: This enables support for the Quad SPI controller in master mode. This driver does not support generic SPI. The implementation only supports spi-mem interface. ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 08/10] configs: sama5d27_som1_ek: add qspiflash_defconfig
From: Tudor Ambarus Add the default config file of QSPI media. The config is based on sama5d27_som1_ek_mmc_defconfig. Signed-off-by: Tudor Ambarus --- v3: fix the following: ./tools/genboardscfg.py WARNING: no status info for 'sama5d27_som1_ek_qspiflash' WARNING: no maintainers for 'sama5d27_som1_ek_qspiflash' v2: new patch board/atmel/sama5d27_som1_ek/MAINTAINERS | 1 + configs/sama5d27_som1_ek_qspiflash_defconfig | 101 +++ 2 files changed, 102 insertions(+) create mode 100644 configs/sama5d27_som1_ek_qspiflash_defconfig diff --git a/board/atmel/sama5d27_som1_ek/MAINTAINERS b/board/atmel/sama5d27_som1_ek/MAINTAINERS index 74434e93e952..f2d2f49db304 100644 --- a/board/atmel/sama5d27_som1_ek/MAINTAINERS +++ b/board/atmel/sama5d27_som1_ek/MAINTAINERS @@ -5,3 +5,4 @@ F: board/atmel/sama5d27_som1_ek/ F: include/configs/sama5d27_som1_ek.h F: configs/sama5d27_som1_ek_mmc_defconfig F: configs/sama5d27_som1_ek_mmc1_defconfig +F: configs/sama5d27_som1_ek_qspiflash_defconfig diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig new file mode 100644 index ..128b6645f6d9 --- /dev/null +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x23f0 +CONFIG_TARGET_SAMA5D27_SOM1_EK=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf802 +CONFIG_DEBUG_UART_CLOCK=8200 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_TEXT_BASE=0x20 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d27_som1_ek" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=6600 +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_ATMEL_USBA=y +CONFIG_DM_VIDEO=y +CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 10/10] configs: sama5d2_xplained: add support QSPI flash boot
From: Eugen Hristev The spi-nor flash resides on spi bus 1. Update the CONFIG_ENV_SPI_CS and CONFIG_BOOTCOMMAND accordingly. Based on original work by Wenyou Yang. Signed-off-by: Eugen Hristev [tudor.amba...@microchip.com: amend the commit message.] Signed-off-by: Tudor Ambarus --- v3: no change v2: new patch include/configs/sama5d2_xplained.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index e522740e0c5b..3dea3591275f 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -46,6 +46,17 @@ #endif +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_ENV_SPI_BUS +#undef CONFIG_BOOTCOMMAND +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_BOOTCOMMAND "sf probe 1:0; "\ + "sf read 0x2100 0x18 0x8; " \ + "sf read 0x2200 0x20 0x60; "\ + "bootz 0x2200 - 0x2100" + +#endif + /* SPL */ #define CONFIG_SPL_MAX_SIZE0x1 #define CONFIG_SPL_BSS_START_ADDR 0x2000 -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 09/10] configs: sama5d27_som1_ek: qspi: use common memory layout
From: Tudor Ambarus Use the qspi memory layout defined in at91-sama5_common - it aligns with the 8 Mbyte flash (sst26vf064b-104i/sn) available in sama5d27_som1_ek. Signed-off-by: Tudor Ambarus --- v3: no change v2: new patch include/configs/sama5d27_som1_ek.h | 7 --- 1 file changed, 7 deletions(-) diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 5f6979cd77a5..90846c4bfd44 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -43,13 +43,6 @@ #endif #ifdef CONFIG_QSPI_BOOT -#define CONFIG_ENV_OFFSET 0xb -#define CONFIG_ENV_SIZE0x1 -#define CONFIG_ENV_SECT_SIZE 0x1 -#define CONFIG_BOOTCOMMAND "sf probe 0; " \ - "sf read 0x2100 0xc 0x2; " \ - "sf read 0x2200 0xe 0x40; " \ - "bootz 0x2200 - 0x2100" #undef CONFIG_BOOTARGS #define CONFIG_BOOTARGS \ "console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait" -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 03/10] configs: sama5d2_xplained: enable qspi controller and flashes
From: Tudor Ambarus We have a macronix spi-nor flash on sama5d2_xplained RevB and a sst spi-nor flash on RevC. Select the rest for testing purposes. Signed-off-by: Tudor Ambarus --- v3: no change v2: new patch configs/sama5d2_xplained_emmc_defconfig | 5 + configs/sama5d2_xplained_mmc_defconfig | 5 + configs/sama5d2_xplained_spiflash_defconfig | 5 + 3 files changed, 15 insertions(+) diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index f643b5a62f39..f244777121b1 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -65,6 +65,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y @@ -76,6 +80,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index c25d67bfebb1..633f6c5ad00c 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -67,6 +67,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y @@ -78,6 +82,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index ac5ae5133c3d..39da86530429 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -64,6 +64,10 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=3000 CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y CONFIG_MACB=y CONFIG_PINCTRL=y @@ -75,6 +79,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 07/10] configs: sama5d2_xplained: add qspiflash_defconfig
From: Tudor Ambarus Add the default config file of QSPI media. The config is based on sama5d2_xplained_mmc_defconfig. Signed-off-by: Tudor Ambarus --- v3: fix the following: ./tools/genboardscfg.py WARNING: no status info for 'sama5d2_xplained_qspiflash' WARNING: no maintainers for 'sama5d2_xplained_qspiflash' v2: new patch board/atmel/sama5d2_xplained/MAINTAINERS | 1 + configs/sama5d2_xplained_qspiflash_defconfig | 101 +++ 2 files changed, 102 insertions(+) create mode 100644 configs/sama5d2_xplained_qspiflash_defconfig diff --git a/board/atmel/sama5d2_xplained/MAINTAINERS b/board/atmel/sama5d2_xplained/MAINTAINERS index 08de5bb6a076..88e327f81cd8 100644 --- a/board/atmel/sama5d2_xplained/MAINTAINERS +++ b/board/atmel/sama5d2_xplained/MAINTAINERS @@ -6,3 +6,4 @@ F: include/configs/sama5d2_xplained.h F: configs/sama5d2_xplained_mmc_defconfig F: configs/sama5d2_xplained_spiflash_defconfig F: configs/sama5d2_xplained_emmc_defconfig +F: configs/sama5d2_xplained_qspiflash_defconfig diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig new file mode 100644 index ..1bf04936f748 --- /dev/null +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -0,0 +1,101 @@ +CONFIG_ARM=y +CONFIG_ARCH_AT91=y +CONFIG_SYS_TEXT_BASE=0x26f0 +CONFIG_TARGET_SAMA5D2_XPLAINED=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_MMC_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_DEBUG_UART_BASE=0xf802 +CONFIG_DEBUG_UART_CLOCK=8300 +CONFIG_SPL_FS_FAT=y +CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_DEBUG_UART=y +CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="SAMA5D2,SYS_USE_MMC" +CONFIG_QSPI_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk root=/dev/mmcblk0p1 rw rootwait" +CONFIG_MISC_INIT_R=y +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SPL_TEXT_BASE=0x20 +CONFIG_SPL_SEPARATE_BSS=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_BOOTZ=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="at91-sama5d2_xplained" +CONFIG_OF_SPL_REMOVE_PROPS="interrupts interrupt-parent dmas dma-names" +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_CLK_AT91=y +CONFIG_AT91_UTMI=y +CONFIG_AT91_H32MX=y +CONFIG_AT91_GENERIC_CLK=y +CONFIG_DM_GPIO=y +CONFIG_ATMEL_PIO4=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_AT91=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ATMEL=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=3000 +CONFIG_SPI_FLASH_ATMEL=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_SST=y +CONFIG_DM_ETH=y +CONFIG_MACB=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_AT91PIO4=y +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ATMEL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_ATMEL_USART=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y +CONFIG_TIMER=y +CONFIG_SPL_TIMER=y +CONFIG_ATMEL_PIT_TIMER=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_STORAGE=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_ATMEL_USBA=y +CONFIG_DM_VIDEO=y +CONFIG_ATMEL_HLCD=y +CONFIG_W1=y +CONFIG_W1_GPIO=y +CONFIG_W1_EEPROM=y +CONFIG_W1_EEPROM_DS24XXX=y +CONFIG_FAT_WRITE=y +CONFIG_OF_LIBFDT_OVERLAY=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 05/10] ARM: dts: at91: sama5d2_xplained: fix QSPI0 node
From: Cyrille Pitchen
Fix the following:
- use "jedec,spi-nor" binding, we use jedec compatible flashes
- set bus width to 4, we use quad capable flashes
- differentiate bewteen data and clk and cs pins
- drop partions as we don't use them in u-boot.
Signed-off-by: Cyrille Pitchen
[tudor.amba...@microchip.com: use "jedec,spi-nor", edit commit message]
Signed-off-by: Tudor Ambarus
---
v3: no change
v2: new patch
arch/arm/dts/at91-sama5d2_xplained.dts | 36 --
1 file changed, 17 insertions(+), 19 deletions(-)
diff --git a/arch/arm/dts/at91-sama5d2_xplained.dts
b/arch/arm/dts/at91-sama5d2_xplained.dts
index c0708feeb7b2..7f0d1696ba3e 100644
--- a/arch/arm/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/dts/at91-sama5d2_xplained.dts
@@ -79,26 +79,18 @@
};
qspi0: spi@f002 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0_sck_cs_default
&pinctrl_qspi0_dat_default>;
status = "okay";
+ u-boot,dm-pre-reloc;
flash@0 {
- compatible = "atmel,sama5d2-qspi-flash";
+ compatible = "jedec,spi-nor";
reg = <0>;
- #address-cells = <1>;
- #size-cells = <1>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_qspi0_default>;
spi-max-frequency = <8300>;
-
- partition@ {
- label = "boot";
- reg = <0x 0x00c0>;
- };
-
- partition@00c0 {
- label = "rootfs";
- reg = <0x00c0 0x>;
- };
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+ u-boot,dm-pre-reloc;
};
};
@@ -208,14 +200,20 @@
bias-disable;
};
- pinctrl_qspi0_default: qspi0_default {
+ pinctrl_qspi0_sck_cs_default:
qspi0_sck_cs_default {
pinmux = ,
-,
-,
+;
+ bias-disable;
+ u-boot,dm-pre-reloc;
+ };
+
+ pinctrl_qspi0_dat_default:
qspi0_dat_default {
+ pinmux = ,
,
,
;
- bias-disable;
+ bias-pull-up;
+ u-boot,dm-pre-reloc;
};
pinctrl_sdmmc0_cmd_dat_default:
sdmmc0_cmd_dat_default {
--
2.9.5
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[U-Boot] [PATCH v3 04/10] configs: sama5d27_som1_ek: enable qspi controller and flashes
From: Tudor Ambarus We use a sst spi-nor flash memory on sama5d27_som1_ek. Select the others for testing purposes. Signed-off-by: Tudor Ambarus --- v3: no change v2: new patch configs/sama5d27_som1_ek_mmc1_defconfig | 2 ++ configs/sama5d27_som1_ek_mmc_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 205a4399410f..9b2b78110357 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=6600 CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y @@ -80,6 +81,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 0a0780066cd8..e5c551e205d0 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=6600 CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y @@ -80,6 +81,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 06/10] ARM: at91: sama5: add common environment for QSPI
From: Cyrille Pitchen Use the same memory layout as we use for the NAND boot on the other boards. QSPI flashes are present on the following boards: sama5d2_xplained RevB: 32 Mbyte flash (mx25l3273fm2i-08g) sama5d2_xplained RevC: 8 Mbyte flash (sst26vf064b-104i/sn) sama5d27_som1_ek:8 Mbyte flash (sst26vf064b-104i/sn) sama5d2_ptc_ek: 8 Mbyte flash (sst26vf064b-104i/sn) The 8 Mbyte limit is enough to cope with the memory layout used in the NAND boot. rootfs exceeds the 8 Mbyte limit and will stay in eMMC in the sama5d2_xplained case. The final scope is to use a single memory layout for all boot medias. Signed-off-by: Cyrille Pitchen [tudor.amba...@microchip.com: change memory layout, add commit message] Signed-off-by: Tudor Ambarus --- v3: no change v2: new patch include/configs/at91-sama5_common.h | 8 1 file changed, 8 insertions(+) diff --git a/include/configs/at91-sama5_common.h b/include/configs/at91-sama5_common.h index 30c6cd47cac2..fc46540a10ab 100644 --- a/include/configs/at91-sama5_common.h +++ b/include/configs/at91-sama5_common.h @@ -72,6 +72,14 @@ "sf read 0x2100 0x6 0xc000; " \ "sf read 0x2200 0x6c000 0x394000; " \ "bootz 0x2200 - 0x2100" +#elif CONFIG_QSPI_BOOT +#define CONFIG_ENV_OFFSET 0x14 +#define CONFIG_ENV_SIZE0x2 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_BOOTCOMMAND "sf probe 0; " \ + "sf read 0x2100 0x18 0x8; " \ + "sf read 0x2200 0x20 0x60; "\ + "bootz 0x2200 - 0x2100" #endif #endif -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v3 02/10] spi: Add Atmel QuadSPI driver
From: Tudor Ambarus Backport the driver from linux v5.1-rc5 and adapt it for u-boot. Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash. Signed-off-by: Tudor Ambarus --- v3: no change v2: no change drivers/spi/Kconfig | 7 + drivers/spi/Makefile| 1 + drivers/spi/atmel-quadspi.c | 535 3 files changed, 543 insertions(+) create mode 100644 drivers/spi/atmel-quadspi.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index dc3e23f353aa..69c2f92c7826 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -49,6 +49,13 @@ config ATH79_SPI uses driver model and requires a device tree binding to operate. please refer to doc/device-tree-bindings/spi/spi-ath79.txt. +config ATMEL_QSPI + bool "Atmel QSPI driver" + depends on ARCH_AT91 + help + Enable the Ateml Quad-SPI (QSPI) driver. This driver can only be + used to access SPI NOR flashes. + config ATMEL_SPI bool "Atmel SPI driver" default y if ARCH_AT91 diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 8be9a4baa244..32b42d18b1af 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -18,6 +18,7 @@ endif obj-$(CONFIG_ALTERA_SPI) += altera_spi.o obj-$(CONFIG_ATH79_SPI) += ath79_spi.o +obj-$(CONFIG_ATMEL_QSPI) += atmel-quadspi.o obj-$(CONFIG_ATMEL_SPI) += atmel_spi.o obj-$(CONFIG_BCM63XX_HSSPI) += bcm63xx_hsspi.o obj-$(CONFIG_BCM63XX_SPI) += bcm63xx_spi.o diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c new file mode 100644 index ..c54fbe6bc6cf --- /dev/null +++ b/drivers/spi/atmel-quadspi.c @@ -0,0 +1,535 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Atmel QSPI Controller + * + * Copyright (C) 2015 Atmel Corporation + * Copyright (C) 2018 Cryptera A/S + * + * Author: Cyrille Pitchen + * Author: Piotr Bugalski + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* QSPI register offsets */ +#define QSPI_CR 0x /* Control Register */ +#define QSPI_MR 0x0004 /* Mode Register */ +#define QSPI_RD 0x0008 /* Receive Data Register */ +#define QSPI_TD 0x000c /* Transmit Data Register */ +#define QSPI_SR 0x0010 /* Status Register */ +#define QSPI_IER 0x0014 /* Interrupt Enable Register */ +#define QSPI_IDR 0x0018 /* Interrupt Disable Register */ +#define QSPI_IMR 0x001c /* Interrupt Mask Register */ +#define QSPI_SCR 0x0020 /* Serial Clock Register */ + +#define QSPI_IAR 0x0030 /* Instruction Address Register */ +#define QSPI_ICR 0x0034 /* Instruction Code Register */ +#define QSPI_WICR0x0034 /* Write Instruction Code Register */ +#define QSPI_IFR 0x0038 /* Instruction Frame Register */ +#define QSPI_RICR0x003C /* Read Instruction Code Register */ + +#define QSPI_SMR 0x0040 /* Scrambling Mode Register */ +#define QSPI_SKR 0x0044 /* Scrambling Key Register */ + +#define QSPI_WPMR0x00E4 /* Write Protection Mode Register */ +#define QSPI_WPSR0x00E8 /* Write Protection Status Register */ + +#define QSPI_VERSION 0x00FC /* Version Register */ + +/* Bitfields in QSPI_CR (Control Register) */ +#define QSPI_CR_QSPIEN BIT(0) +#define QSPI_CR_QSPIDIS BIT(1) +#define QSPI_CR_SWRST BIT(7) +#define QSPI_CR_LASTXFERBIT(24) + +/* Bitfields in QSPI_MR (Mode Register) */ +#define QSPI_MR_SMM BIT(0) +#define QSPI_MR_LLB BIT(1) +#define QSPI_MR_WDRBT BIT(2) +#define QSPI_MR_SMRMBIT(3) +#define QSPI_MR_CSMODE_MASK GENMASK(5, 4) +#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4) +#define QSPI_MR_CSMODE_LASTXFER (1 << 4) +#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4) +#define QSPI_MR_NBBITS_MASK GENMASK(11, 8) +#define QSPI_MR_NBBITS(n) n) - 8) << 8) & QSPI_MR_NBBITS_MASK) +#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16) +#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK) +#define QSPI_MR_DLYCS_MASK GENMASK(31, 24) +#define QSPI_MR_DLYCS(n)(((n) << 24) & QSPI_MR_DLYCS_MASK) + +/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */ +#define QSPI_SR_RDRFBIT(0) +#define QSPI_SR_TDREBIT(1) +#define QSPI_SR_TXEMPTY BIT(2) +#define QSPI_SR_OVRES BIT(3) +#define QSPI_SR_CSR BIT(8) +#define QSPI_SR_CSS BIT(9) +#define QSPI_SR_INSTRE BIT(10) +#define QSPI_SR_QSPIENS BIT(24) + +#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR) + +/* Bitfields in QSPI_SCR (Serial Clock Register) */ +#define QSPI_SCR_CPOL BIT(0) +#define QSPI_SCR_CPHA B
[U-Boot] [PATCH v3 01/10] dt-bindings: spi: add bindings for Atmel QSPI driver
From: Tudor Ambarus
Describe the DT bindings for the driver of the Atmel QSPI
controller. Taken form linux v5.1-rc5.
Signed-off-by: Tudor Ambarus
---
v3: no change
v2: no change
doc/device-tree-bindings/spi/atmel-quadspi.txt | 37 ++
1 file changed, 37 insertions(+)
create mode 100644 doc/device-tree-bindings/spi/atmel-quadspi.txt
diff --git a/doc/device-tree-bindings/spi/atmel-quadspi.txt
b/doc/device-tree-bindings/spi/atmel-quadspi.txt
new file mode 100644
index ..7c40ea694352
--- /dev/null
+++ b/doc/device-tree-bindings/spi/atmel-quadspi.txt
@@ -0,0 +1,37 @@
+* Atmel Quad Serial Peripheral Interface (QSPI)
+
+Required properties:
+- compatible: Should be one of the following:
+ - "atmel,sama5d2-qspi"
+ - "microchip,sam9x60-qspi"
+- reg:Should contain the locations and lengths of the base
registers
+ and the mapped memory.
+- reg-names: Should contain the resource reg names:
+ - qspi_base: configuration register address space
+ - qspi_mmap: memory mapped address space
+- interrupts: Should contain the interrupt for the device.
+- clocks: Should reference the peripheral clock and the QSPI system
+ clock if available.
+- clock-names:Should contain "pclk" for the peripheral clock and "qspick"
+ for the system clock when available.
+- #address-cells: Should be <1>.
+- #size-cells:Should be <0>.
+
+Example:
+
+spi@f002 {
+ compatible = "atmel,sama5d2-qspi";
+ reg = <0xf002 0x100>, <0xd000 0x800>;
+ reg-names = "qspi_base", "qspi_mmap";
+ interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
+ clock-names = "pclk";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+
+ m25p80@0 {
+ ...
+ };
+};
--
2.9.5
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[U-Boot] [PATCH v3 00/10] spi: Add Atmel QuadSPI driver
From: Tudor Ambarus Backport the driver from linux v5.1-rc5 and adapt it for u-boot. Tested on sama5d2_xplained Rev B with mx25l25635e spi-nor flash, and on sama5d27_som1_ek with sst26vf064b spi-nor flash. v3: fix following config warnings reported by travis: ./tools/genboardscfg.py WARNING: no status info for 'sama5d2_xplained_qspiflash' WARNING: no maintainers for 'sama5d2_xplained_qspiflash' WARNING: no status info for 'sama5d27_som1_ek_qspiflash' WARNING: no maintainers for 'sama5d27_som1_ek_qspiflash' v2: update/add configs and update sama5d2_xplained dts Cyrille Pitchen (2): ARM: dts: at91: sama5d2_xplained: fix QSPI0 node ARM: at91: sama5: add common environment for QSPI Eugen Hristev (1): configs: sama5d2_xplained: add support QSPI flash boot Tudor Ambarus (7): dt-bindings: spi: add bindings for Atmel QSPI driver spi: Add Atmel QuadSPI driver configs: sama5d2_xplained: enable qspi controller and flashes configs: sama5d27_som1_ek: enable qspi controller and flashes configs: sama5d2_xplained: add qspiflash_defconfig configs: sama5d27_som1_ek: add qspiflash_defconfig configs: sama5d27_som1_ek: qspi: use common memory layout arch/arm/dts/at91-sama5d2_xplained.dts | 36 +- board/atmel/sama5d27_som1_ek/MAINTAINERS | 1 + board/atmel/sama5d2_xplained/MAINTAINERS | 1 + configs/sama5d27_som1_ek_mmc1_defconfig| 2 + configs/sama5d27_som1_ek_mmc_defconfig | 2 + configs/sama5d27_som1_ek_qspiflash_defconfig | 101 + configs/sama5d2_xplained_emmc_defconfig| 5 + configs/sama5d2_xplained_mmc_defconfig | 5 + configs/sama5d2_xplained_qspiflash_defconfig | 101 + configs/sama5d2_xplained_spiflash_defconfig| 5 + doc/device-tree-bindings/spi/atmel-quadspi.txt | 37 ++ drivers/spi/Kconfig| 7 + drivers/spi/Makefile | 1 + drivers/spi/atmel-quadspi.c| 535 + include/configs/at91-sama5_common.h| 8 + include/configs/sama5d27_som1_ek.h | 7 - include/configs/sama5d2_xplained.h | 11 + 17 files changed, 839 insertions(+), 26 deletions(-) create mode 100644 configs/sama5d27_som1_ek_qspiflash_defconfig create mode 100644 configs/sama5d2_xplained_qspiflash_defconfig create mode 100644 doc/device-tree-bindings/spi/atmel-quadspi.txt create mode 100644 drivers/spi/atmel-quadspi.c -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 10/10] configs: sama5d2_xplained: add support QSPI flash boot
From: Eugen Hristev The spi-nor flash resides on spi bus 1. Update the CONFIG_ENV_SPI_CS and CONFIG_BOOTCOMMAND accordingly. Based on original work by Wenyou Yang. Signed-off-by: Eugen Hristev [tudor.amba...@microchip.com: amend the commit message.] Signed-off-by: Tudor Ambarus --- v2: new patch include/configs/sama5d2_xplained.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index e522740e0c5b..3dea3591275f 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -46,6 +46,17 @@ #endif +#ifdef CONFIG_QSPI_BOOT +#undef CONFIG_ENV_SPI_BUS +#undef CONFIG_BOOTCOMMAND +#define CONFIG_ENV_SPI_BUS 1 +#define CONFIG_BOOTCOMMAND "sf probe 1:0; "\ + "sf read 0x2100 0x18 0x8; " \ + "sf read 0x2200 0x20 0x60; "\ + "bootz 0x2200 - 0x2100" + +#endif + /* SPL */ #define CONFIG_SPL_MAX_SIZE0x1 #define CONFIG_SPL_BSS_START_ADDR 0x2000 -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
[U-Boot] [PATCH v2 04/10] configs: sama5d27_som1_ek: enable qspi controller and flashes
From: Tudor Ambarus We use a sst spi-nor flash memory on sama5d27_som1_ek. Select the others for testing purposes. Signed-off-by: Tudor Ambarus --- v2: new patch configs/sama5d27_som1_ek_mmc1_defconfig | 2 ++ configs/sama5d27_som1_ek_mmc_defconfig | 2 ++ 2 files changed, 4 insertions(+) diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 205a4399410f..9b2b78110357 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=6600 CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y @@ -80,6 +81,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 0a0780066cd8..e5c551e205d0 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -67,6 +67,7 @@ CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=6600 CONFIG_SPI_FLASH_ATMEL=y CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_SST=y CONFIG_DM_ETH=y @@ -80,6 +81,7 @@ CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ATMEL_USART=y CONFIG_SPI=y CONFIG_DM_SPI=y +CONFIG_ATMEL_QSPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y CONFIG_ATMEL_PIT_TIMER=y -- 2.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
