[U-Boot] [PATCH v3 4/4] SMDK55250: Enable SATA
This patch adds required macros for enabling SATA. Signed-off-by: Vasanth Ananthan --- include/configs/smdk5250.h | 15 --- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index e412da8..67cdbe2 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -68,7 +68,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) /* select serial console configuration */ -#define CONFIG_SERIAL3 /* use SERIAL 3 */ +#define CONFIG_SERIAL2 /* use SERIAL 2 */ #define CONFIG_BAUDRATE115200 #define EXYNOS5_DEFAULT_UART_OFFSET0x01 @@ -97,6 +97,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_NET +#define CONFIG_CMD_SATA #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK @@ -192,8 +193,6 @@ #define EXYNOS_COPY_SPI_FNPTR_ADDR 0x02020058 #define SPI_FLASH_UBOOT_POS(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE) -#define CONFIG_DOS_PARTITION - #define CONFIG_IRAM_STACK 0x0205 #define CONFIG_SYS_INIT_SP_ADDR(CONFIG_SYS_LOAD_ADDR - 0x100) @@ -259,4 +258,14 @@ /* Enable devicetree support */ #define CONFIG_OF_LIBFDT +/* Enable SATA */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR EXYNOS5_SATA_BASE + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + #endif /* __CONFIG_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 3/4] Drivers: block: Support for SATA in Exynos5
This patch provides support for SATA in Exynos5250
Signed-off-by: Vasanth Ananthan
---
drivers/block/dwc_ahsata.c | 397 ++--
1 file changed, 387 insertions(+), 10 deletions(-)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index c9b71f7..58537d3 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -35,6 +35,64 @@
#include
#include "dwc_ahsata.h"
+#ifdef SATA_DEBUG
+#define debug(fmt, args...)printf(fmt, ##args)
+#else
+#define debug(fmt, args...)
+#endif /* MKIMAGE_DEBUG */
+
+#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
+#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
+
+#define writel_with_flush(a, b)do { writel(a, b); readl(b); } while (0)
+
+#define EXYNOS5_SATA_PHY_CONTROL (0x1004 + 0x724)
+#define S5P_PMU_SATA_PHY_CONTROL_EN0x1
+
+#define SATA_TIME_LIMIT1
+#define SATA_PHY_I2C_SLAVE_ADDRS 0x70
+
+#define SATA_RESET 0x4
+#define RESET_CMN_RST_N(1 << 1)
+#define LINK_RESET 0xFF
+
+#define SATA_MODE0 0x10
+
+#define SATA_CTRL0 0x14
+#define CTRL0_P0_PHY_CALIBRATED_SEL(1 << 9)
+#define CTRL0_P0_PHY_CALIBRATED(1 << 8)
+
+#define SATA_PHSATA_CTRLM 0xE0
+#define PHCTRLM_REF_RATE (1 << 1)
+#define PHCTRLM_HIGH_SPEED (1 << 0)
+
+#define SATA_PHSATA_STATM 0xF0
+#define PHSTATM_PLL_LOCKED (1 << 0)
+
+#define SATA_I2C_CON 0x00
+#define SATA_I2C_STAT 0x04
+#define SATA_I2C_ADDR 0x08
+#define SATA_I2C_DS0x0C
+#define SATA_I2C_LC0x10
+
+/* I2CCON reg */
+#define CON_ACKEN (1 << 7)
+#define CON_CLK512 (1 << 6)
+#define CON_CLK16 (~CON_CLK512)
+#define CON_INTEN (1 << 5)
+#define CON_INTPND (1 << 4)
+#define CON_TXCLK_PS (0xF)
+
+/* I2CSTAT reg */
+#define STAT_MSTT (0x3 << 6)
+#define STAT_BSYST (1 << 5)
+#define STAT_RTEN (1 << 4)
+#define STAT_LAST (1 << 0)
+
+#define LC_FLTR_EN (1 << 2)
+
+#define SATA_PHY_CON_RESET 0xF003F
+
struct sata_port_regs {
u32 clb;
u32 clbu;
@@ -88,10 +146,243 @@ struct sata_host_regs {
u32 idr;
};
-#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
-#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
+void * const phy_ctrl = (void *)EXYNOS5_SATA_PHY_BASE;
+void * const phy_i2c_base = (void *)EXYNOS5_SATA_PHY_I2C;
-#define writel_with_flush(a, b)do { writel(a, b); readl(b); } while (0)
+enum {
+ SATA_GENERATION1,
+ SATA_GENERATION2,
+ SATA_GENERATION3,
+};
+
+static u8 sata_is_reg(void *base, u32 reg, u32 checkbit, u32 status)
+{
+ if ((readl(base + reg) & checkbit) == status)
+ return 1;
+ else
+ return 0;
+}
+
+static u8 wait_for_reg_status(void *base, u32 reg, u32 checkbit,
+ u32 status)
+{
+ u32 time_limit_cnt = 0;
+ while (!sata_is_reg(base, reg, checkbit, status)) {
+ if (time_limit_cnt == SATA_TIME_LIMIT)
+ return 0;
+ udelay(1000);
+ time_limit_cnt++;
+ }
+ return 1;
+}
+
+static void sata_set_gen(u8 gen)
+{
+ writel(gen, phy_ctrl + SATA_MODE0);
+}
+
+/* Address :I2C Address */
+static void sata_i2c_write_addrs(u8 data)
+{
+ writeb((data & 0xFE), phy_i2c_base + SATA_I2C_DS);
+}
+
+static void sata_i2c_write_data(u8 data)
+{
+ writeb((data), phy_i2c_base + SATA_I2C_DS);
+}
+
+static void sata_i2c_start(void)
+{
+ u32 val;
+ val = readl(phy_i2c_base + SATA_I2C_STAT);
+ val |= STAT_BSYST;
+ writel(val, phy_i2c_base + SATA_I2C_STAT);
+}
+
+static void sata_i2c_stop(void)
+{
+ u32 val;
+ val = readl(phy_i2c_base + SATA_I2C_STAT);
+ val &= ~STAT_BSYST;
+ writel(val, phy_i2c_base + SATA_I2C_STAT);
+}
+
+static u8 sata_i2c_get_int_status(void)
+{
+ if ((readl(phy_i2c_base + SATA_I2C_CON)) & CON_INTPND)
+ return 1;
+ else
+ return 0;
+}
+
+static u8 sata_i2c_is_tx_ack(void)
+{
+ if ((readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_LAST)
+ return 0;
+ else
+ return 1;
+}
+
+static u8 sata_i2c_is_bus_ready(void)
+{
+ if ((readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_BSYST)
+ return 0;
+ else
+ return 1;
+}
+
+static u8 sata_i2c_wait_for_busready(u32 time_out)
+{
+ while (--time_out) {
+
[U-Boot] [PATCH v3 2/4] Exynos5: Add base addresses for SATA
This patch adds the macro definition of SATA controller and PHY controller
base addresses.
Signed-off-by: Vasanth Ananthan
---
arch/arm/include/asm/arch-exynos/cpu.h|3 +++
arch/arm/include/asm/arch-exynos/periph.h |1 +
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index d1b2ea8..6ea1230 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -80,8 +80,11 @@
#define EXYNOS5_USB_HOST_EHCI_BASE 0x1211
#define EXYNOS5_USBPHY_BASE0x1213
#define EXYNOS5_USBOTG_BASE0x1214
+#define EXYNOS5_SATA_PHY_BASE 0x1217
+#define EXYNOS5_SATA_PHY_I2C0x121D
#define EXYNOS5_MMC_BASE 0x1220
#define EXYNOS5_SROMC_BASE 0x1225
+#define EXYNOS5_SATA_BASE 0x122F
#define EXYNOS5_UART_BASE 0x12C0
#define EXYNOS5_I2C_BASE 0x12C6
#define EXYNOS5_SPI_BASE 0x12D2
diff --git a/arch/arm/include/asm/arch-exynos/periph.h
b/arch/arm/include/asm/arch-exynos/periph.h
index 13abd2d..58dc675 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -54,6 +54,7 @@ enum periph_id {
PERIPH_ID_UART1,
PERIPH_ID_UART2,
PERIPH_ID_UART3,
+ PERIPH_ID_SATA,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
--
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[U-Boot] [PATCH v3 1/4] Exynos5: Add clock support for SATA
This patch adds clock support for SATA
Signed-off-by: Vasanth Ananthan
---
arch/arm/cpu/armv7/exynos/clock.c | 64
arch/arm/include/asm/arch-exynos/clk.h |3 +-
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index fe61f88..db68ef0 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
/* Epll Clock division values to achive different frequency output */
static struct set_epll_con_val exynos5_epll_div[] = {
@@ -326,6 +327,53 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
return uclk;
}
+/* Sets clocks related to SATA */
+static int exynos5_set_sata_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ u32 tmp;
+
+ /* Setting src as MPLL_USER */
+ tmp = readl(&clk->src_fsys);
+ tmp &= ~(1 << 24);
+ writel(tmp, &clk->src_fsys);
+
+ /* Unmasking SATA clk */
+ tmp = readl(&clk->src_mask_fsys);
+ tmp |= (1 << 24);
+ writel(tmp, &clk->src_mask_fsys);
+
+ /* Set divider value for getting sclk as 66 MHz */
+ tmp = readl(&clk->div_fsys0);
+ tmp |= (0xB << 20);
+
+ return 0;
+}
+
+/* Returns the clock frequency in Hz */
+static unsigned long exynos5_get_sata_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+ unsigned long uclk, sclk;
+ u32 ratio, tmp;
+
+ tmp = readl(&clk->src_fsys);
+
+ if ((tmp & (1 << 24)) == 0)
+ sclk = get_pll_clk(MPLL);
+ else
+ sclk = get_pll_clk(BPLL);
+
+ ratio = readl(&clk->div_fsys0);
+ ratio = (ratio >> 20) & 0xf;
+
+ uclk = sclk / (ratio + 1);
+
+ return uclk;
+}
+
/* exynos5: return uart clock frequency */
static unsigned long exynos5_get_uart_clk(int dev_index)
{
@@ -963,6 +1011,22 @@ unsigned long get_uart_clk(int dev_index)
return exynos4_get_uart_clk(dev_index);
}
+unsigned long get_sata_clk(void)
+{
+ if (cpu_is_exynos5())
+ return exynos5_get_sata_clk();
+
+ return -ENOSYS;
+}
+
+void set_sata_clk(void)
+{
+ if (cpu_is_exynos5())
+ return exynos5_set_sata_clk();
+
+ return -ENOSYS;
+}
+
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index cd12323..10f28cc 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -42,5 +42,6 @@ void set_i2s_clk_source(void);
int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
int set_epll_clk(unsigned long rate);
int set_spi_clk(int periph_id, unsigned int rate);
-
+unsigned long get_sata_clk(void);
+void set_sata_clk(void);
#endif
--
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[U-Boot] [PATCH v2 4/4] SMDK55250: Enable SATA
This patch adds required macros for enabling SATA. Signed-off-by: Vasanth Ananthan --- include/configs/smdk5250.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index e412da8..123fcc3 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -97,6 +97,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_NET +#define CONFIG_CMD_SATA #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK @@ -259,4 +260,14 @@ /* Enable devicetree support */ #define CONFIG_OF_LIBFDT +/* Enable SATA */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR EXYNOS5_SATA_BASE + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + #endif /* __CONFIG_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 3/4] Drivers: block: Support for SATA in Exynos5
This patch provides support for SATA in Exynos5250
Signed-off-by: Vasanth Ananthan
---
drivers/block/dwc_ahsata.c | 394 +++-
1 file changed, 387 insertions(+), 7 deletions(-)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index c9b71f7..5125134 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -35,6 +35,69 @@
#include
#include "dwc_ahsata.h"
+
+#define bool unsigned char
+#define false 0
+#define true 1
+
+#ifdef SATA_DEBUG
+#define debug(fmt, args...)printf(fmt, ##args)
+#else
+#define debug(fmt, args...)
+#endif /* MKIMAGE_DEBUG */
+
+#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
+#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
+
+#define writel_with_flush(a, b)do { writel(a, b); readl(b); } while (0)
+
+#define EXYNOS5_SATA_PHY_CONTROL (0x1004 + 0x724)
+#define S5P_PMU_SATA_PHY_CONTROL_EN0x1
+
+#define SATA_TIME_LIMIT1
+#define SATA_PHY_I2C_SLAVE_ADDRS 0x70
+
+#define SATA_RESET 0x4
+#define RESET_CMN_RST_N(1 << 1)
+#define LINK_RESET 0xF
+
+#define SATA_MODE0 0x10
+
+#define SATA_CTRL0 0x14
+#define CTRL0_P0_PHY_CALIBRATED_SEL(1 << 9)
+#define CTRL0_P0_PHY_CALIBRATED(1 << 8)
+
+#define SATA_PHSATA_CTRLM 0xE0
+#define PHCTRLM_REF_RATE (1 << 1)
+#define PHCTRLM_HIGH_SPEED (1 << 0)
+
+#define SATA_PHSATA_STATM 0xF0
+#define PHSTATM_PLL_LOCKED (1 << 0)
+
+#define SATA_I2C_CON 0x00
+#define SATA_I2C_STAT 0x04
+#define SATA_I2C_ADDR 0x08
+#define SATA_I2C_DS0x0C
+#define SATA_I2C_LC0x10
+
+/* I2CCON reg */
+#define CON_ACKEN (1 << 7)
+#define CON_CLK512 (1 << 6)
+#define CON_CLK16 (~CON_CLK512)
+#define CON_INTEN (1 << 5)
+#define CON_INTPND (1 << 4)
+#define CON_TXCLK_PS (0xF)
+
+/* I2CSTAT reg */
+#define STAT_MSTT (0x3 << 6)
+#define STAT_BSYST (1 << 5)
+#define STAT_RTEN (1 << 4)
+#define STAT_LAST (1 << 0)
+
+#define LC_FLTR_EN (1 << 2)
+
+#define SATA_PHY_CON_RESET 0xF003F
+
struct sata_port_regs {
u32 clb;
u32 clbu;
@@ -88,10 +151,244 @@ struct sata_host_regs {
u32 idr;
};
-#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
-#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
+void * const phy_ctrl = (void *)EXYNOS5_SATA_PHY_BASE;
+void * const phy_i2c_base = (void *)EXYNOS5_SATA_PHY_I2C;
-#define writel_with_flush(a, b)do { writel(a, b); readl(b); } while (0)
+enum {
+ SATA_GENERATION1,
+ SATA_GENERATION2,
+ SATA_GENERATION3,
+};
+
+static bool sata_is_reg(void *base, u32 reg, u32 checkbit, u32 status)
+{
+ if ((readl(base + reg) & checkbit) == status)
+ return true;
+ else
+ return false;
+}
+
+static bool wait_for_reg_status(void *base, u32 reg, u32 checkbit,
+ u32 status)
+{
+ u32 time_limit_cnt = 0;
+ while (!sata_is_reg(base, reg, checkbit, status)) {
+ if (time_limit_cnt == SATA_TIME_LIMIT)
+ return false;
+ udelay(1000);
+ time_limit_cnt++;
+ }
+ return true;
+}
+
+static void sata_set_gen(u8 gen)
+{
+ writel(gen, phy_ctrl + SATA_MODE0);
+}
+
+/* Address :I2C Address */
+static void sata_i2c_write_addrs(u8 data)
+{
+ writeb((data & 0xFE), phy_i2c_base + SATA_I2C_DS);
+}
+
+static void sata_i2c_write_data(u8 data)
+{
+ writeb((data), phy_i2c_base + SATA_I2C_DS);
+}
+
+static void sata_i2c_start(void)
+{
+ u32 val;
+ val = readl(phy_i2c_base + SATA_I2C_STAT);
+ val |= STAT_BSYST;
+ writel(val, phy_i2c_base + SATA_I2C_STAT);
+}
+
+static void sata_i2c_stop(void)
+{
+ u32 val;
+ val = readl(phy_i2c_base + SATA_I2C_STAT);
+ val &= ~STAT_BSYST;
+ writel(val, phy_i2c_base + SATA_I2C_STAT);
+}
+
+static bool sata_i2c_get_int_status(void)
+{
+ if ((readl(phy_i2c_base + SATA_I2C_CON)) & CON_INTPND)
+ return true;
+ else
+ return false;
+}
+
+static bool sata_i2c_is_tx_ack(void)
+{
+ if ((readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_LAST)
+ return false;
+ else
+ return true;
+}
+
+static bool sata_i2c_is_bus_ready(void)
+{
+ if ((readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_BSYST)
+ return false;
+ else
+
[U-Boot] [PATCH v2 2/4] Exynos5: Add base addresses for SATA
This patch adds the macro definition of SATA controller and PHY controller
base addresses.
Signed-off-by: Vasanth Ananthan
---
arch/arm/include/asm/arch-exynos/cpu.h|3 +++
arch/arm/include/asm/arch-exynos/periph.h |1 +
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index d1b2ea8..6ea1230 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -80,8 +80,11 @@
#define EXYNOS5_USB_HOST_EHCI_BASE 0x1211
#define EXYNOS5_USBPHY_BASE0x1213
#define EXYNOS5_USBOTG_BASE0x1214
+#define EXYNOS5_SATA_PHY_BASE 0x1217
+#define EXYNOS5_SATA_PHY_I2C0x121D
#define EXYNOS5_MMC_BASE 0x1220
#define EXYNOS5_SROMC_BASE 0x1225
+#define EXYNOS5_SATA_BASE 0x122F
#define EXYNOS5_UART_BASE 0x12C0
#define EXYNOS5_I2C_BASE 0x12C6
#define EXYNOS5_SPI_BASE 0x12D2
diff --git a/arch/arm/include/asm/arch-exynos/periph.h
b/arch/arm/include/asm/arch-exynos/periph.h
index 13abd2d..58dc675 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -54,6 +54,7 @@ enum periph_id {
PERIPH_ID_UART1,
PERIPH_ID_UART2,
PERIPH_ID_UART3,
+ PERIPH_ID_SATA,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
--
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[U-Boot] [PATCH v2 1/4] Exynos5: Add clock support for SATA
This patch adds clock support for SATA
Signed-off-by: Vasanth Ananthan
---
arch/arm/cpu/armv7/exynos/clock.c | 22 ++
arch/arm/include/asm/arch-exynos/clk.h |1 +
2 files changed, 23 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index fe61f88..22b327b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
/* Epll Clock division values to achive different frequency output */
static struct set_epll_con_val exynos5_epll_div[] = {
@@ -326,6 +327,19 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
return uclk;
}
+static unsigned long exynos5_get_sata_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ /*
+ * This clock is used as a input for 1ms timer, so return
+ * the clock equivalent to 1 MHz
+ */
+
+ return CONFIG_SYS_CLK_FREQ / 10;
+}
+
/* exynos5: return uart clock frequency */
static unsigned long exynos5_get_uart_clk(int dev_index)
{
@@ -963,6 +977,14 @@ unsigned long get_uart_clk(int dev_index)
return exynos4_get_uart_clk(dev_index);
}
+unsigned long get_sata_clock(void)
+{
+ if (cpu_is_exynos5())
+ return exynos5_get_sata_clk();
+
+ return -ENOSYS;
+}
+
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index cd12323..182ed95 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -42,5 +42,6 @@ void set_i2s_clk_source(void);
int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
int set_epll_clk(unsigned long rate);
int set_spi_clk(int periph_id, unsigned int rate);
+unsigned long get_sata_clk(void);
#endif
--
1.7.9.5
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[U-Boot] [PATCH v2 0/4] Support for SATA on EXYNOS5
This patch set adds support for SATA on Exynos5250 Vasanth Ananthan (4): Exynos5: Add clock support for SATA Exynos5: Add base addresses for SATA Drivers: block: Support for SATA in Exynos5 SMDK55250: Enable SATA arch/arm/cpu/armv7/exynos/clock.c | 22 ++ arch/arm/include/asm/arch-exynos/clk.h|1 + arch/arm/include/asm/arch-exynos/cpu.h|3 + arch/arm/include/asm/arch-exynos/periph.h |1 + drivers/block/dwc_ahsata.c| 394 - include/configs/smdk5250.h| 11 + 6 files changed, 425 insertions(+), 7 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/4] Drivers: block: Support for SATA in Exynos5
This patch provides support for SATA in Exynos5250
Signed-off-by: Vasanth Ananthan
---
drivers/block/dwc_ahsata.c | 394 +++-
1 file changed, 387 insertions(+), 7 deletions(-)
diff --git a/drivers/block/dwc_ahsata.c b/drivers/block/dwc_ahsata.c
index c9b71f7..5125134 100644
--- a/drivers/block/dwc_ahsata.c
+++ b/drivers/block/dwc_ahsata.c
@@ -35,6 +35,69 @@
#include
#include "dwc_ahsata.h"
+
+#define bool unsigned char
+#define false 0
+#define true 1
+
+#ifdef SATA_DEBUG
+#define debug(fmt, args...)printf(fmt, ##args)
+#else
+#define debug(fmt, args...)
+#endif /* MKIMAGE_DEBUG */
+
+#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
+#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
+
+#define writel_with_flush(a, b)do { writel(a, b); readl(b); } while (0)
+
+#define EXYNOS5_SATA_PHY_CONTROL (0x1004 + 0x724)
+#define S5P_PMU_SATA_PHY_CONTROL_EN0x1
+
+#define SATA_TIME_LIMIT1
+#define SATA_PHY_I2C_SLAVE_ADDRS 0x70
+
+#define SATA_RESET 0x4
+#define RESET_CMN_RST_N(1 << 1)
+#define LINK_RESET 0xF
+
+#define SATA_MODE0 0x10
+
+#define SATA_CTRL0 0x14
+#define CTRL0_P0_PHY_CALIBRATED_SEL(1 << 9)
+#define CTRL0_P0_PHY_CALIBRATED(1 << 8)
+
+#define SATA_PHSATA_CTRLM 0xE0
+#define PHCTRLM_REF_RATE (1 << 1)
+#define PHCTRLM_HIGH_SPEED (1 << 0)
+
+#define SATA_PHSATA_STATM 0xF0
+#define PHSTATM_PLL_LOCKED (1 << 0)
+
+#define SATA_I2C_CON 0x00
+#define SATA_I2C_STAT 0x04
+#define SATA_I2C_ADDR 0x08
+#define SATA_I2C_DS0x0C
+#define SATA_I2C_LC0x10
+
+/* I2CCON reg */
+#define CON_ACKEN (1 << 7)
+#define CON_CLK512 (1 << 6)
+#define CON_CLK16 (~CON_CLK512)
+#define CON_INTEN (1 << 5)
+#define CON_INTPND (1 << 4)
+#define CON_TXCLK_PS (0xF)
+
+/* I2CSTAT reg */
+#define STAT_MSTT (0x3 << 6)
+#define STAT_BSYST (1 << 5)
+#define STAT_RTEN (1 << 4)
+#define STAT_LAST (1 << 0)
+
+#define LC_FLTR_EN (1 << 2)
+
+#define SATA_PHY_CON_RESET 0xF003F
+
struct sata_port_regs {
u32 clb;
u32 clbu;
@@ -88,10 +151,244 @@ struct sata_host_regs {
u32 idr;
};
-#define MAX_DATA_BYTES_PER_SG (4 * 1024 * 1024)
-#define MAX_BYTES_PER_TRANS (AHCI_MAX_SG * MAX_DATA_BYTES_PER_SG)
+void * const phy_ctrl = (void *)EXYNOS5_SATA_PHY_BASE;
+void * const phy_i2c_base = (void *)EXYNOS5_SATA_PHY_I2C;
-#define writel_with_flush(a, b)do { writel(a, b); readl(b); } while (0)
+enum {
+ SATA_GENERATION1,
+ SATA_GENERATION2,
+ SATA_GENERATION3,
+};
+
+static bool sata_is_reg(void *base, u32 reg, u32 checkbit, u32 status)
+{
+ if ((readl(base + reg) & checkbit) == status)
+ return true;
+ else
+ return false;
+}
+
+static bool wait_for_reg_status(void *base, u32 reg, u32 checkbit,
+ u32 status)
+{
+ u32 time_limit_cnt = 0;
+ while (!sata_is_reg(base, reg, checkbit, status)) {
+ if (time_limit_cnt == SATA_TIME_LIMIT)
+ return false;
+ udelay(1000);
+ time_limit_cnt++;
+ }
+ return true;
+}
+
+static void sata_set_gen(u8 gen)
+{
+ writel(gen, phy_ctrl + SATA_MODE0);
+}
+
+/* Address :I2C Address */
+static void sata_i2c_write_addrs(u8 data)
+{
+ writeb((data & 0xFE), phy_i2c_base + SATA_I2C_DS);
+}
+
+static void sata_i2c_write_data(u8 data)
+{
+ writeb((data), phy_i2c_base + SATA_I2C_DS);
+}
+
+static void sata_i2c_start(void)
+{
+ u32 val;
+ val = readl(phy_i2c_base + SATA_I2C_STAT);
+ val |= STAT_BSYST;
+ writel(val, phy_i2c_base + SATA_I2C_STAT);
+}
+
+static void sata_i2c_stop(void)
+{
+ u32 val;
+ val = readl(phy_i2c_base + SATA_I2C_STAT);
+ val &= ~STAT_BSYST;
+ writel(val, phy_i2c_base + SATA_I2C_STAT);
+}
+
+static bool sata_i2c_get_int_status(void)
+{
+ if ((readl(phy_i2c_base + SATA_I2C_CON)) & CON_INTPND)
+ return true;
+ else
+ return false;
+}
+
+static bool sata_i2c_is_tx_ack(void)
+{
+ if ((readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_LAST)
+ return false;
+ else
+ return true;
+}
+
+static bool sata_i2c_is_bus_ready(void)
+{
+ if ((readl(phy_i2c_base + SATA_I2C_STAT)) & STAT_BSYST)
+ return false;
+ else
+
[U-Boot] [PATCH 1/4] Exynos5: Add clock support for SATA
This patch adds clock support for SATA
Signed-off-by: Vasanth Ananthan
---
arch/arm/cpu/armv7/exynos/clock.c | 22 ++
arch/arm/include/asm/arch-exynos/clk.h |1 +
2 files changed, 23 insertions(+)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index fe61f88..22b327b 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -26,6 +26,7 @@
#include
#include
#include
+#include
/* Epll Clock division values to achive different frequency output */
static struct set_epll_con_val exynos5_epll_div[] = {
@@ -326,6 +327,19 @@ static unsigned long exynos4_get_uart_clk(int dev_index)
return uclk;
}
+static unsigned long exynos5_get_sata_clk(void)
+{
+ struct exynos5_clock *clk =
+ (struct exynos5_clock *)samsung_get_base_clock();
+
+ /*
+ * This clock is used as a input for 1ms timer, so return
+ * the clock equivalent to 1 MHz
+ */
+
+ return CONFIG_SYS_CLK_FREQ / 10;
+}
+
/* exynos5: return uart clock frequency */
static unsigned long exynos5_get_uart_clk(int dev_index)
{
@@ -963,6 +977,14 @@ unsigned long get_uart_clk(int dev_index)
return exynos4_get_uart_clk(dev_index);
}
+unsigned long get_sata_clock(void)
+{
+ if (cpu_is_exynos5())
+ return exynos5_get_sata_clk();
+
+ return -ENOSYS;
+}
+
void set_mmc_clk(int dev_index, unsigned int div)
{
if (cpu_is_exynos5())
diff --git a/arch/arm/include/asm/arch-exynos/clk.h
b/arch/arm/include/asm/arch-exynos/clk.h
index cd12323..182ed95 100644
--- a/arch/arm/include/asm/arch-exynos/clk.h
+++ b/arch/arm/include/asm/arch-exynos/clk.h
@@ -42,5 +42,6 @@ void set_i2s_clk_source(void);
int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq);
int set_epll_clk(unsigned long rate);
int set_spi_clk(int periph_id, unsigned int rate);
+unsigned long get_sata_clk(void);
#endif
--
1.7.9.5
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[U-Boot] [PATCH 2/4] Exynos5: Add base addresses for SATA
This patch adds the macro definition of SATA controller and PHY controller
base addresses.
Signed-off-by: Vasanth Ananthan
---
arch/arm/include/asm/arch-exynos/cpu.h|3 +++
arch/arm/include/asm/arch-exynos/periph.h |1 +
2 files changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index d1b2ea8..11265ea 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -91,6 +91,9 @@
#define EXYNOS5_GPIO_PART2_BASE0x1340
#define EXYNOS5_FIMD_BASE 0x1440
#define EXYNOS5_DP_BASE0x145B
+#define EXYNOS5_SATA_BASE 0x122F
+#define EXYNOS5_SATA_PHY_BASE 0x1217
+#define EXYNOS5_SATA_PHY_I2C 0x121D
#define EXYNOS5_ADC_BASE DEVICE_NOT_AVAILABLE
#define EXYNOS5_MODEM_BASE DEVICE_NOT_AVAILABLE
diff --git a/arch/arm/include/asm/arch-exynos/periph.h
b/arch/arm/include/asm/arch-exynos/periph.h
index 13abd2d..58dc675 100644
--- a/arch/arm/include/asm/arch-exynos/periph.h
+++ b/arch/arm/include/asm/arch-exynos/periph.h
@@ -54,6 +54,7 @@ enum periph_id {
PERIPH_ID_UART1,
PERIPH_ID_UART2,
PERIPH_ID_UART3,
+ PERIPH_ID_SATA,
PERIPH_ID_COUNT,
PERIPH_ID_NONE = -1,
--
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[U-Boot] [PATCH 4/4] SMDK55250: Enable SATA
This patch adds required macros for enabling SATA. Signed-off-by: Vasanth Ananthan --- include/configs/smdk5250.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index e412da8..123fcc3 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -97,6 +97,7 @@ #define CONFIG_CMD_EXT2 #define CONFIG_CMD_FAT #define CONFIG_CMD_NET +#define CONFIG_CMD_SATA #define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK @@ -259,4 +260,14 @@ /* Enable devicetree support */ #define CONFIG_OF_LIBFDT +/* Enable SATA */ +#ifdef CONFIG_CMD_SATA + #define CONFIG_DWC_AHSATA + #define CONFIG_SYS_SATA_MAX_DEVICE 1 + #define CONFIG_DWC_AHSATA_PORT_ID 0 + #define CONFIG_DWC_AHSATA_BASE_ADDR EXYNOS5_SATA_BASE + #define CONFIG_LBA48 + #define CONFIG_LIBATA +#endif + #endif /* __CONFIG_H */ -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 0/4] Support for SATA on EXYNOS5
This patch set adds support for SATA on Exynos5250 Vasanth Ananthan (4): Exynos5: Add clock support for SATA Exynos5: Add base addresses for SATA Drivers: block: Support for SATA in Exynos5 SMDK55250: Enable SATA arch/arm/cpu/armv7/exynos/clock.c | 22 ++ arch/arm/include/asm/arch-exynos/clk.h|1 + arch/arm/include/asm/arch-exynos/cpu.h|3 + arch/arm/include/asm/arch-exynos/periph.h |1 + drivers/block/dwc_ahsata.c| 394 - include/configs/smdk5250.h| 11 + 6 files changed, 425 insertions(+), 7 deletions(-) -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
