from:"Yannick FERTRE"

[PATCH] video: stm32: stm32_ltdc: support several hardware versions

2022-04-06 Thread Yannick Fertre

Register mapping & pixel formats depend on version of ltdc
display controller.

Signed-off-by: Yannick Fertre 
---

 drivers/video/stm32/stm32_ltdc.c | 245 +++
 1 file changed, 216 insertions(+), 29 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index e741e74739..60bfd2390d 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -25,8 +25,114 @@ struct stm32_ltdc_priv {
void __iomem *regs;
enum video_log2_bpp l2bpp;
u32 bg_col_argb;
+   const u32 *layer_regs;
+   const u32 *pix_fmt_hw;
u32 crop_x, crop_y, crop_w, crop_h;
u32 alpha;
+   u32 hw_version;
+};
+
+/* Layer register offsets */
+static const u32 layer_regs_a0[] = {
+   0x80,   /* L1 configuration 0 */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x84,   /* L1 control register */
+   0x88,   /* L1 window horizontal position configuration */
+   0x8c,   /* L1 window vertical position configuration */
+   0x90,   /* L1 color keying configuration */
+   0x94,   /* L1 pixel format configuration */
+   0x98,   /* L1 constant alpha configuration */
+   0x9c,   /* L1 default color configuration */
+   0xa0,   /* L1 blending factors configuration */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0xac,   /* L1 color frame buffer address */
+   0xb0,   /* L1 color frame buffer length */
+   0xb4,   /* L1 color frame buffer line number */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0xc4,   /* L1 CLUT write */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00/* not available */
+};
+
+static const u32 layer_regs_a1[] = {
+   0x80,   /* L1 configuration 0 */
+   0x84,   /* L1 configuration 1 */
+   0x00,   /* L1 reload control */
+   0x88,   /* L1 control register */
+   0x8c,   /* L1 window horizontal position configuration */
+   0x90,   /* L1 window vertical position configuration */
+   0x94,   /* L1 color keying configuration */
+   0x98,   /* L1 pixel format configuration */
+   0x9c,   /* L1 constant alpha configuration */
+   0xa0,   /* L1 default color configuration */
+   0xa4,   /* L1 blending factors configuration */
+   0xa8,   /* L1 burst length configuration */
+   0x00,   /* not available */
+   0xac,   /* L1 color frame buffer address */
+   0xb0,   /* L1 color frame buffer length */
+   0xb4,   /* L1 color frame buffer line number */
+   0xb8,   /* L1 auxiliary frame buffer address 0 */
+   0xbc,   /* L1 auxiliary frame buffer address 1 */
+   0xc0,   /* L1 auxiliary frame buffer length */
+   0xc4,   /* L1 auxiliary frame buffer line number */
+   0xc8,   /* L1 CLUT write */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00,   /* not available */
+   0x00/* not available */
+};
+
+static const u32 layer_regs_a2[] = {
+   0x100,  /* L1 configuration 0 */
+   0x104,  /* L1 configuration 1 */
+   0x108,  /* L1 reload control */
+   0x10c,  /* L1 control register */
+   0x110,  /* L1 window horizontal position configuration */
+   0x114,  /* L1 window vertical position configuration */
+   0x118,  /* L1 color keying configuration */
+   0x11c,  /* L1 pixel format configuration */
+   0x120,  /* L1 constant alpha configuration */
+   0x124,  /* L1 default color configuration */
+   0x128,  /* L1 blending factors configuration */
+   0x12c,  /* L1 burst length configuration */
+   0x130,  /* L1 planar configuration */
+   0x134,  /* L1 color frame buffer address */
+   0x138,  /* L1 color frame buffer length */
+   0x13c,  /* L1 color frame buffer line number */
+   0x140,  /* L1 auxiliary frame buffer address 0 */
+   0x144,  /* L1 auxiliary frame buffer address 1 */
+   0x148,  /* L1 auxiliary frame buffer length */
+   0x14c,  /* L1 auxiliary frame buffer line number */
+   0x150,  /* L1 CLUT write */
+   0x154,  /* not available */
+   0x158,  /* not available */
+   0x15c,  /* not available */
+   0x160,  /* not available */
+   0x164,  /* not available */
+   0x168,  /* not available */
+   0x16c,  /* L1 Conversion YCbCr R

[PATCH] video: stm32: stm32_ltdc: fix data enable polarity

2022-04-06 Thread Yannick FERTRE

Wrong DISPLAY_FLAGS used to set the data enable polarity.

Signed-off-by: Yannick FERTRE 
---

 drivers/video/stm32/stm32_ltdc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index e741e74739..9269d4bfb4 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -255,7 +255,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv,
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= GCR_VSPOL;
-   if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_DE_LOW)
val |= GCR_DEPOL;
if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
val |= GCR_PCPOL;
-- 
2.25.1

Re: [PATCH 2/2] video: dw_mipi_dsi: update log of dphy_enable

2021-03-04 Thread yannick Fertre


Acked-by: Yannick Fertre 


On 3/4/21 1:14 PM, Patrick Delaunay wrote:

From: Yannick Fertre 

The DSI phy can be turned on from the DSI digital interface in
the dphy_enable() function or from a dedicated DSI phy "wrapper"
in phy_ops->init() function. If the STM32MP1 case, the wrapper
is used then the dphy_enable() "warning" traces are not relevant.

This patch moves these "warning" traces to "debug" traces so
they are still available for DSI phy based on the digital
interface in debug logging mode, but not there in normal mode
for both cases.
Note: The related Linux kernel driver uses a "debug"
message too.

Signed-off-by: Yannick Fertre 
Signed-off-by: Patrick Delaunay 
---

  drivers/video/dw_mipi_dsi.c | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index a5beed3514..9ae09eec12 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -721,15 +721,15 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi 
*dsi)
ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
 val & PHY_LOCK, PHY_STATUS_TIMEOUT_US);
if (ret)
-   dev_warn(dsi->dsi_host.dev,
-"failed to wait phy lock state\n");
+   dev_dbg(dsi->dsi_host.dev,
+   "failed to wait phy lock state\n");
  
  	ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,

 val, val & PHY_STOP_STATE_CLK_LANE,
 PHY_STATUS_TIMEOUT_US);
if (ret)
-   dev_warn(dsi->dsi_host.dev,
-"failed to wait phy clk lane stop state\n");
+   dev_dbg(dsi->dsi_host.dev,
+   "failed to wait phy clk lane stop state\n");
  }
  
  static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)

Re: [PATCH 1/2] video: dw_mipi_dsi: missing device to log debug

2021-03-04 Thread yannick Fertre


Acked-by: Yannick Fertre 


On 3/4/21 1:14 PM, Patrick Delaunay wrote:

From: Yannick Fertre 

Missing udevice to struct dw_mipi_dsi to log trace.

Signed-off-by: Yannick Fertre 
Signed-off-by: Patrick Delaunay 
---

  drivers/video/dw_mipi_dsi.c | 1 +
  1 file changed, 1 insertion(+)

diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index 4dde648814..a5beed3514 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -797,6 +797,7 @@ static int dw_mipi_dsi_init(struct udevice *dev,
dsi->phy_ops = phy_ops;
dsi->max_data_lanes = max_data_lanes;
dsi->device = device;
+   dsi->dsi_host.dev = (struct device *)dev;
dsi->dsi_host.ops = &dw_mipi_dsi_host_ops;
device->host = &dsi->dsi_host;

Re: [PATCH 2/2] video: stm32_dsi: Convert to use APIs which support live DT

2020-09-10 Thread Yannick FERTRE

Reviewed-by: Yannick Fertré 


On 9/9/20 5:44 PM, Patrick Delaunay wrote:
> Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
> driver can support live DT.
> 
> Signed-off-by: Patrick Delaunay 
> ---
> 
>   drivers/video/stm32/stm32_dsi.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
> index 283151398b..9d5abacc2b 100644
> --- a/drivers/video/stm32/stm32_dsi.c
> +++ b/drivers/video/stm32/stm32_dsi.c
> @@ -359,8 +359,7 @@ static int stm32_dsi_attach(struct udevice *dev)
>   
>   ret = panel_get_display_timing(priv->panel, &timings);
>   if (ret) {
> - ret = fdtdec_decode_display_timing(gd->fdt_blob,
> -dev_of_offset(priv->panel),
> + ret = ofnode_decode_display_timing(dev_ofnode(priv->panel),
>  0, &timings);
>   if (ret) {
>   dev_err(dev, "decode display timing error %d\n", ret);
>

Re: [PATCH 1/2] video: stm32_ltdc: Convert to use APIs which support live DT

2020-09-10 Thread Yannick FERTRE

Reviewed-by: Yannick Fertré 


On 9/9/20 5:44 PM, Patrick Delaunay wrote:
> Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the
> driver can support live DT.
> 
> Signed-off-by: Patrick Delaunay 
> ---
> 
>   drivers/video/stm32/stm32_ltdc.c | 3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/video/stm32/stm32_ltdc.c 
> b/drivers/video/stm32/stm32_ltdc.c
> index 2f3427a32e..7fff735930 100644
> --- a/drivers/video/stm32/stm32_ltdc.c
> +++ b/drivers/video/stm32/stm32_ltdc.c
> @@ -366,8 +366,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
>   
>   ret = panel_get_display_timing(panel, &timings);
>   if (ret) {
> - ret = fdtdec_decode_display_timing(gd->fdt_blob,
> -dev_of_offset(panel),
> + ret = ofnode_decode_display_timing(dev_ofnode(panel),
>  0, &timings);
>   if (ret) {
>   dev_err(dev, "decode display timing error %d\n", ret);
>

[PATCH v1 2/4] video: stm32: stm32_dsi: copy DSI fields

2020-06-24 Thread Yannick Fertre

Copy the DSI data link characteristics from panel
platform data to mipi DSI device.

Signed-off-by: Yannick Fertre 
---
 drivers/video/stm32/stm32_dsi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
index 04796435f1..c9b1633cf7 100644
--- a/drivers/video/stm32/stm32_dsi.c
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -354,6 +354,9 @@ static int stm32_dsi_attach(struct udevice *dev)
 
mplat = dev_get_platdata(priv->panel);
mplat->device = &priv->device;
+   device->lanes = mplat->lanes;
+   device->format = mplat->format;
+   device->mode_flags = mplat->mode_flags;
 
ret = panel_get_display_timing(priv->panel, &timings);
if (ret) {
-- 
2.17.1

[PATCH v1 1/4] video: mipi update panel platform data

2020-06-24 Thread Yannick Fertre

Add new fields "lanes, format & mode_flags" to structure
mipi_dsi_panel_plat.

Signed-off-by: Yannick Fertre 
---
 include/mipi_dsi.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/include/mipi_dsi.h b/include/mipi_dsi.h
index 83c5163cf8..c8a7d3daef 100644
--- a/include/mipi_dsi.h
+++ b/include/mipi_dsi.h
@@ -221,9 +221,15 @@ static inline int mipi_dsi_pixel_format_to_bpp(enum 
mipi_dsi_pixel_format fmt)
 /**
  * struct mipi_dsi_panel_plat - DSI panel platform data
  * @device: DSI peripheral device
+ * @lanes: number of active data lanes
+ * @format: pixel format for video mode
+ * @mode_flags: DSI operation mode related flags
  */
 struct mipi_dsi_panel_plat {
struct mipi_dsi_device *device;
+   unsigned int lanes;
+   enum mipi_dsi_pixel_format format;
+   unsigned long mode_flags;
 };
 
 /**
-- 
2.17.1

[PATCH v1 0/4] rework DSI characteristics

2020-06-24 Thread Yannick Fertre

Fill characteristics of DSI data link to platform data instead of
mipi device to avoid memory corruption.

Yannick Fertre (4):
  video: mipi update panel platform data
  video: stm32: stm32_dsi: copy DSI fields
  video: raydium_rm68200: fill characteristics of DSI data link
  video: orisetech_otm8009a: fill characteristics of DSI data link

 drivers/video/orisetech_otm8009a.c | 20 +---
 drivers/video/raydium-rm68200.c| 20 +---
 drivers/video/stm32/stm32_dsi.c|  3 +++
 include/mipi_dsi.h |  6 ++
 4 files changed, 19 insertions(+), 30 deletions(-)

-- 
2.17.1

[PATCH v1 4/4] video: orisetech_otm8009a: fill characteristics of DSI data link

2020-06-24 Thread Yannick Fertre

Fill characteristics of DSI data link to platform data instead of
mipi device to avoid memory corruption.

Signed-off-by: Yannick Fertre 
---
 drivers/video/orisetech_otm8009a.c | 20 +---
 1 file changed, 5 insertions(+), 15 deletions(-)

diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
index b1f2dd403e..362bf6a6fe 100644
--- a/drivers/video/orisetech_otm8009a.c
+++ b/drivers/video/orisetech_otm8009a.c
@@ -62,9 +62,6 @@
 struct otm8009a_panel_priv {
struct udevice *reg;
struct gpio_desc reset;
-   unsigned int lanes;
-   enum mipi_dsi_pixel_format format;
-   unsigned long mode_flags;
 };
 
 static const struct display_timing default_timing = {
@@ -293,17 +290,8 @@ static int otm8009a_panel_enable_backlight(struct udevice 
*dev)
 static int otm8009a_panel_get_display_timing(struct udevice *dev,
 struct display_timing *timings)
 {
-   struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
-   struct mipi_dsi_device *device = plat->device;
-   struct otm8009a_panel_priv *priv = dev_get_priv(dev);
-
memcpy(timings, &default_timing, sizeof(*timings));
 
-   /* fill characteristics of DSI data link */
-   device->lanes = priv->lanes;
-   device->format = priv->format;
-   device->mode_flags = priv->mode_flags;
-
return 0;
 }
 
@@ -335,6 +323,7 @@ static int otm8009a_panel_ofdata_to_platdata(struct udevice 
*dev)
 static int otm8009a_panel_probe(struct udevice *dev)
 {
struct otm8009a_panel_priv *priv = dev_get_priv(dev);
+   struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
int ret;
 
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
@@ -350,9 +339,10 @@ static int otm8009a_panel_probe(struct udevice *dev)
dm_gpio_set_value(&priv->reset, false);
mdelay(10); /* >5ms */
 
-   priv->lanes = 2;
-   priv->format = MIPI_DSI_FMT_RGB888;
-   priv->mode_flags = MIPI_DSI_MODE_VIDEO |
+   /* fill characteristics of DSI data link */
+   plat->lanes = 2;
+   plat->format = MIPI_DSI_FMT_RGB888;
+   plat->mode_flags = MIPI_DSI_MODE_VIDEO |
   MIPI_DSI_MODE_VIDEO_BURST |
   MIPI_DSI_MODE_LPM;
 
-- 
2.17.1

[PATCH v1 3/4] video: raydium_rm68200: fill characteristics of DSI data link

2020-06-24 Thread Yannick Fertre

Fill characteristics of DSI data link to platform data instead of
mipi device to avoid memory corruption.

Signed-off-by: Yannick Fertre 
---
 drivers/video/raydium-rm68200.c | 20 +---
 1 file changed, 5 insertions(+), 15 deletions(-)

diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c
index 9169280fb8..353894503b 100644
--- a/drivers/video/raydium-rm68200.c
+++ b/drivers/video/raydium-rm68200.c
@@ -75,9 +75,6 @@ struct rm68200_panel_priv {
struct udevice *reg;
struct udevice *backlight;
struct gpio_desc reset;
-   unsigned int lanes;
-   enum mipi_dsi_pixel_format format;
-   unsigned long mode_flags;
 };
 
 static const struct display_timing default_timing = {
@@ -259,17 +256,8 @@ static int rm68200_panel_enable_backlight(struct udevice 
*dev)
 static int rm68200_panel_get_display_timing(struct udevice *dev,
struct display_timing *timings)
 {
-   struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
-   struct mipi_dsi_device *device = plat->device;
-   struct rm68200_panel_priv *priv = dev_get_priv(dev);
-
memcpy(timings, &default_timing, sizeof(*timings));
 
-   /* fill characteristics of DSI data link */
-   device->lanes = priv->lanes;
-   device->format = priv->format;
-   device->mode_flags = priv->mode_flags;
-
return 0;
 }
 
@@ -308,6 +296,7 @@ static int rm68200_panel_ofdata_to_platdata(struct udevice 
*dev)
 static int rm68200_panel_probe(struct udevice *dev)
 {
struct rm68200_panel_priv *priv = dev_get_priv(dev);
+   struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
int ret;
 
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
@@ -322,9 +311,10 @@ static int rm68200_panel_probe(struct udevice *dev)
dm_gpio_set_value(&priv->reset, false);
mdelay(10);
 
-   priv->lanes = 2;
-   priv->format = MIPI_DSI_FMT_RGB888;
-   priv->mode_flags = MIPI_DSI_MODE_VIDEO |
+   /* fill characteristics of DSI data link */
+   plat->lanes = 2;
+   plat->format = MIPI_DSI_FMT_RGB888;
+   plat->mode_flags = MIPI_DSI_MODE_VIDEO |
   MIPI_DSI_MODE_VIDEO_BURST |
   MIPI_DSI_MODE_LPM;
 
-- 
2.17.1

[PATCH] video: check hardware version of DSI

2020-06-24 Thread Yannick Fertre

Check the hardware version of DSI. Versions 1.30 & 1.31 are only
supported.

Signed-off-by: Yannick Fertre 
---
 drivers/video/stm32/stm32_dsi.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
index 04796435f1..31ab8ebec7 100644
--- a/drivers/video/stm32/stm32_dsi.c
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -271,7 +271,6 @@ static int dsi_get_lane_mbps(void *priv_data, struct 
display_timing *timings,
u32 val;
 
/* Update lane capabilities according to hw version */
-   dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
dsi->lane_min_kbps = LANE_MIN_KBPS;
dsi->lane_max_kbps = LANE_MAX_KBPS;
if (dsi->hw_version == HWVER_131) {
@@ -475,6 +474,15 @@ static int stm32_dsi_probe(struct udevice *dev)
/* Reset */
reset_deassert(&rst);
 
+   /* check hardware version */
+   priv->hw_version = dsi_read(priv, DSI_VERSION) & VERSION;
+   if (priv->hw_version != HWVER_130 &&
+   priv->hw_version != HWVER_131) {
+   dev_err(dev, "DSI version 0x%x not supported\n", 
priv->hw_version);
+   ret = -ENODEV;
+   goto err_clk;
+   }
+
return 0;
 err_clk:
clk_disable(&clk);
-- 
2.17.1

Re: [U-Boot] [PATCH v5 01/15] video: bmp: check resolutions of panel/bitmap

2019-10-25 Thread Yannick FERTRE

Hello Heinrich,

Sorry for the delay.

This match is not superfluous. On the STM32F746 board, a bitmap larger 
than the panel resolution is embedded.

Without this patch, the board does not boot.

I propose to send an additional patch that checks the coordinates.

Best regards

-- 
Yannick Fertré Microcontrollers and Digital ICs Group | 
Microcontrolleurs Division


On 10/24/19 10:43 PM, Heinrich Schuchardt wrote:
> On 10/24/19 4:05 PM, Patrice CHOTARD wrote:
>> Hi Heinrich, all
>>
>> On 10/7/19 7:34 PM, Heinrich Schuchardt wrote:
>>> On 10/7/19 3:29 PM, Yannick Fertré wrote:
 If the size of the bitmap is bigger than the size of
 the panel then errors appear when calculating axis alignment
 and the copy of bitmap is done outside of framebuffer.

 Signed-off-by: Yannick Fertré 
 ---
    drivers/video/video_bmp.c | 7 +++
    1 file changed, 7 insertions(+)

 diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
 index 193f37d..4af1fb4 100644
 --- a/drivers/video/video_bmp.c
 +++ b/drivers/video/video_bmp.c
 @@ -249,6 +249,13 @@ int video_bmp_display(struct udevice *dev, 
 ulong bmp_image, int x, int y,

    padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width);

 +    /* check if picture size exceeds panel size */
 +    if ((pwidth < width) || (priv->ysize < height)) {
 +    printf("Error: BMP size %d x %d is bigger than panel size 
 %d x %d\n",
 +   (int)width, (int)height, priv->xsize, priv->ysize);
 +    return -EINVAL;
 +    }
 +
    if (align) {
    video_splash_align_axis(&x, priv->xsize, width);
    video_splash_align_axis(&y, priv->ysize, height);
>>>
>>> This is followed by:
>>>
>>>  if ((x + width) > pwidth)
>>>  width = pwidth - x;
>>>  if ((y + height) > priv->ysize)
>>>  height = priv->ysize - y;
>>>
>>> These lines will clip a bitmap that given the left upper corner x, y
>>> does not fit onto the screen.
>>>
>>> So isn't this patch superfluous?
>>>
>>> What is missing are checks for x and y.
>>>
>>> For testing I have used qemu_x86 and added
>>>
>>>  #define CONFIG_BMP_24BPP y
>>>
>>> to the top of drivers/video/video_bmp.c and loaded a 24bit bitmap.
>>>
>>> Clipping works as expected. But passing a value of x exceeding the
>>> screen width lead to a crash.
>>>
>>> What I really dislike in the existing coding is that CONFIG_BMP_*BPP is
>>> defined in includes instead of using Kconfig but that is a different 
>>> story.
>>>
>>> Best regards
>>>
>>> Heinrich
>>
>> For information all this series patches have been applied on 
>> u-boot/master excepts  this one.
>>
>> Unfortunately, without this patch, stm32f746-discovery board doesn't 
>> boot anymore.
>
> I still do not understand why this patch is needed.
>
> Could you, please, try to analyze why the board does not boot.
>
> What is wrong with the existing code for clipping?
> Or is the non-booting just coincidence but the bug is somewhere else?
>
> What are the values of the parameters passed to video_bmp_display()?
> Which bitmap file are you using?
> What is the size of the display?
>
> Best regards
>
> Heinrich
>
>>
>> Heinrich, could this patch be merged, waiting for a clean patch from 
>> Yannick ?
>>
>> Regards
>>
>> Patrice
>>
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Re: [U-Boot] [PATCH v4 01/15] video: bmp: check resolutions of panel/bitmap

2019-09-24 Thread Yannick FERTRE

Hello Heinrich,

Thank for your review.

You're right my patch does not allow to properly protect the framebuffer.

I will push a new patch which check the bitmap size and exit in case of 
size error.

Yannick Fertré


On 9/17/19 11:12 PM, Heinrich Schuchardt wrote:
> On 9/13/19 11:47 AM, Yannick Fertré wrote:
>> If the size of the bitmap is bigger than the size of
>> the panel then errors appear when calculating axis alignment
>> and the copy of bitmap is done outside of framebuffer.
>>
>> Signed-off-by: Yannick Fertré 
>> ---
>>   drivers/video/video_bmp.c | 14 ++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/drivers/video/video_bmp.c b/drivers/video/video_bmp.c
>> index 193f37d..544bd5f 100644
>> --- a/drivers/video/video_bmp.c
>> +++ b/drivers/video/video_bmp.c
>> @@ -54,6 +54,13 @@ static void video_display_rle8_bitmap(struct 
>> udevice *dev,
>>   height = get_unaligned_le32(&bmp->header.height);
>>   bmap = (uchar *)bmp + 
>> get_unaligned_le32(&bmp->header.data_offset);
>>
>> +    /* check if picture size exceed panel size */
>
> %s/exceed/exceeds/
>
>> +    if (priv->xsize < width)
>> +    width = priv->xsize;
>
> In case of BMP_RLE8_DELTA width is not checked before writing to the
> frame buffer. So this modification of width will lead to unexpected 
> effects.
>
> In the 'default' case width is checked and this may lead to decoding 
> errors.
>
>> +
>> +    if (priv->ysize < height)
>> +    height = priv->ysize;
>> +
>>   x = 0;
>>   y = height - 1;
>>
>> @@ -249,6 +256,13 @@ int video_bmp_display(struct udevice *dev, ulong 
>> bmp_image, int x, int y,
>>
>>   padded_width = (width & 0x3 ? (width & ~0x3) + 4 : width);
>>
>> +    /* check if picture size exceed panel size */
>> +    if (pwidth < width)
>> +    width = pwidth;
>> +
>> +    if (priv->ysize < height)
>> +    height = priv->ysize;
>> +
>
> You forgot to consider the position (x,y) of the picture.
>
> Best regards
>
> Heinrich
>
>>   if (align) {
>>   video_splash_align_axis(&x, priv->xsize, width);
>>   video_splash_align_axis(&y, priv->ysize, height);
>>
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Re: [U-Boot] [PATCH v3 03/10] video: add support of MIPI DSI interface

2018-08-22 Thread Yannick FERTRE

Hi,

Ok, I 'll rework driver with a new uclass & driver model.

Best regards


On 08/21/2018 07:31 PM, Simon Glass wrote:
> Hi,
>
> On 17 August 2018 at 08:38, Yannick Fertré  wrote:
>> Mipi_display.c contains a set of dsi helpers.
>> This file is a copy of file drm_mipi_dsi.c (linux kernel).
>>
>> Signed-off-by: Yannick Fertré 
>> ---
>>   drivers/video/Kconfig|   8 +
>>   drivers/video/Makefile   |   1 +
>>   drivers/video/mipi_dsi.c | 828 
>> +++
>>   include/mipi_dsi.h   | 451 ++
>>   4 files changed, 1288 insertions(+)
>>   create mode 100644 drivers/video/mipi_dsi.c
>>   create mode 100644 include/mipi_dsi.h
> Yes I think you need a uclass. However it is probably not applicable
> for this file, but for the other one, where you have the transfer()
> method. You should set up a uclass for that.
>
> Regards,
> Simon
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[U-Boot] [PATCH v3 00/10] splash screen on the stm32f769 disco board

2018-03-13 Thread yannick fertre

Version 3:
- Replace some pr_error, pr_warn or pr_info by dev_error, dev_warn & dev_info.
- Refresh stm32f769-disco_defconfig with last modification done on v2018.3-rc4.
- rework include files ordering.

Version 2:
- Replace debug log by pr_error, pr_warn or pr_info.
- Rework bridge between ltdc & dsi panel
- Rework backligh management (with or witout gpio)
- Rework panel otm8009a
- Add new panel raydium rm68200

Version 1:
- Initial commit

This serie contains all patchsets needed for displaying a splash screen 
on the stm32f769 disco board.
A new config has been created configs/stm32f769-disco_defconfig.
This is necessary due to the difference of panels between stm32f769-disco &
stm32f746-disco boards.
This serie depends on:
  http://patchwork.ozlabs.org/patch/870938/
  http://patchwork.ozlabs.org/cover/880576/
yannick fertre (10):
  video: stm32: stm32_ltdc: add bridge to display controller
  video: stm32: stm32_ltdc: update debug log
  video: add support of MIPI DSI interface
  video: add support of panel OTM8009A
  video: add MIPI DSI host controller bridge
  video: add support of STM32 MIPI DSI controller driver
  video: add support of panel rm68200
  arm: dts: stm32: add dsi for STM32F746
  arm: dts: stm32: add display for STM32F769 disco board
  board: Add STM32F769 SoC, discovery board support

 arch/arm/dts/stm32f746.dtsi|  12 +
 arch/arm/dts/stm32f769-disco.dts   |  71 
 configs/stm32f769-disco_defconfig  |  65 +++
 drivers/video/Kconfig  |  32 ++
 drivers/video/Makefile |   4 +
 drivers/video/dw_mipi_dsi.c| 822 +
 drivers/video/mipi_display.c   | 807 
 drivers/video/orisetech_otm8009a.c | 327 +++
 drivers/video/raydium-rm68200.c| 326 +++
 drivers/video/stm32/Kconfig|  10 +
 drivers/video/stm32/Makefile   |   1 +
 drivers/video/stm32/stm32_dsi.c| 426 +++
 drivers/video/stm32/stm32_ltdc.c   | 144 ---
 include/dw_mipi_dsi.h  |  34 ++
 include/mipi_display.h | 257 +++-
 15 files changed, 3279 insertions(+), 59 deletions(-)
 create mode 100644 configs/stm32f769-disco_defconfig
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 drivers/video/mipi_display.c
 create mode 100644 drivers/video/orisetech_otm8009a.c
 create mode 100644 drivers/video/raydium-rm68200.c
 create mode 100644 drivers/video/stm32/stm32_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

-- 
1.9.1

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[U-Boot] [PATCH v3 04/10] otm

2018-03-13 Thread yannick fertre

---
 drivers/video/orisetech_otm8009a.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
index 81b11d7..aa8139a 100644
--- a/drivers/video/orisetech_otm8009a.c
+++ b/drivers/video/orisetech_otm8009a.c
@@ -289,9 +289,11 @@ static int otm8009a_panel_probe(struct udevice *dev)
struct otm8009a_panel_priv *priv = dev_get_priv(dev);
int ret;
 
-   /* reset panel must be done before probe */
+   /* reset panel */
dm_gpio_set_value(&priv->reset, true);
 
+   mdelay(1);
+
if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
dev_err(dev, "enable regulator '%s'\n", priv->reg->name);
ret = regulator_set_enable(priv->reg, true);
-- 
1.9.1

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[U-Boot] [PATCH v3 10/10] board: Add STM32F769 SoC, discovery board support

2018-03-13 Thread yannick fertre

Signed-off-by: yannick fertre 
---
 configs/stm32f769-disco_defconfig | 65 +++
 1 file changed, 65 insertions(+)
 create mode 100644 configs/stm32f769-disco_defconfig

diff --git a/configs/stm32f769-disco_defconfig 
b/configs/stm32f769-disco_defconfig
new file mode 100644
index 000..01b3b51
--- /dev/null
+++ b/configs/stm32f769-disco_defconfig
@@ -0,0 +1,65 @@
+CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_SYS_TEXT_BASE=0x08008000
+CONFIG_SYS_MALLOC_F_LEN=0xC00
+CONFIG_STM32F7=y
+CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 
ignore_loglevel"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+# CONFIG_SPL_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
-- 
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[U-Boot] [PATCH v3 02/10] video: stm32: stm32_ltdc: update debug log

2018-03-13 Thread yannick fertre

Replace  macro debug by pr_error, pr_warn or pr_info.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 67 ++--
 1 file changed, 30 insertions(+), 37 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index bd9c0de..3e12c71 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -5,7 +5,6 @@
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
-
 #include 
 #include 
 #include 
@@ -13,12 +12,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
@@ -176,13 +173,13 @@ static u32 stm32_ltdc_get_pixel_format(enum 
video_log2_bpp l2bpp)
case VIDEO_BPP2:
case VIDEO_BPP4:
default:
-   debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
- __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
+   pr_warn("warning %dbpp not supported yet, %dbpp instead\n",
+   VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
pf = PF_RGB565;
break;
}
 
-   debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
+   pr_info("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
 
return (u32)pf;
 }
@@ -249,7 +246,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv,
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   dev_info(dev, "timing->flags 0x%08x\n", timings->flags);
if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
@@ -343,26 +340,25 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
-   debug("%s: ltdc dt register address error\n", __func__);
+   dev_err(dev, "ltdc dt register address error\n");
return -EINVAL;
}
 
ret = clk_get_by_index(dev, 0, &pclk);
if (ret) {
-   debug("%s: peripheral clock get error %d\n", __func__, ret);
+   dev_err(dev, "peripheral clock get error %d\n", ret);
return ret;
}
 
ret = clk_enable(&pclk);
if (ret) {
-   debug("%s: peripheral clock enable error %d\n",
- __func__, ret);
+   dev_err(dev, "peripheral clock enable error %d\n", ret);
return ret;
}
 
ret = reset_get_by_index(dev, 0, &rst);
if (ret) {
-   debug("%s: missing ltdc hardware reset\n", __func__);
+   dev_err(dev, "missing ltdc hardware reset\n");
return -ENODEV;
}
 
@@ -371,42 +367,39 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
 #ifdef CONFIG_VIDEO_BRIDGE
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
-   if (ret) {
-   debug("%s: No video bridge, or no backlight on bridge\n",
- __func__);
-   }
+   if (ret)
+   dev_info(dev, "No video bridge, or no backlight on bridge\n");
 
if (bridge) {
ret = video_bridge_attach(bridge);
if (ret) {
-   debug("%s: fail to attach bridge\n", __func__);
+   dev_err(dev, "fail to attach bridge\n");
return ret;
}
}
 #endif
ret = uclass_first_device(UCLASS_PANEL, &panel);
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
+   dev_err(dev, "panel device error %d\n", ret);
return ret;
}
 
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(panel),
   0, &timings);
if (ret) {
-   debug("%s: decode display timing error %d\n",
- __func__, ret);
+   dev_err(dev, "decode display timing error %d\n", ret);
return ret;
}
 
rate = clk_set_rate(&pclk, timings.pixelclock.typ);
if (rate < 0) {
-   debug("%s: fail to set pixel clock %d hz %d hz\n",
- __func__, timings.pixelclock.typ, rate);
+   dev_err(dev, "fail to set pixel clock %d hz %d hz\n",
+   timings.pixelclock.typ, rate);
return rate;
}
 
-   debug("%s: Set pixel clock req %d hz get %d hz\n",

[U-Boot] [PATCH v3 09/10] arm: dts: stm32: add display for STM32F769 disco board

2018-03-13 Thread yannick fertre

Enable the display controller, mipi dsi bridge & panel.
Set panel display timings.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f769-disco.dts | 71 
 1 file changed, 71 insertions(+)

diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index 59c9d31..82985b9 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -42,6 +42,7 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
+#include 
 #include 
 
 / {
@@ -264,3 +265,73 @@
bus-width = <4>;
max-frequency = <2500>;
 };
+
+<dc {
+   status = "okay";
+
+   port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ltdc_out_dsi: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <&dsi_in>;
+   };
+   };
+};
+
+&dsi {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dsi_in: endpoint {
+   remote-endpoint = <<dc_out_dsi>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dsi_out: endpoint {
+   remote-endpoint = <&dsi_panel_in>;
+   };
+   };
+   };
+
+   panel-dsi@0 {
+   compatible = "orisetech,otm8009a";
+   reg = <0>; /* dsi virtual channel (0..3) */
+   reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>;
+   status = "okay";
+
+   port {
+   dsi_panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+
+   display-timings {
+   timing@0 {
+   clock-frequency = <32729000>;
+   hactive = <480>;
+   hfront-porch = <120>;
+   hback-porch = <63>;
+   hsync-len = <120>;
+   vactive = <800>;
+   vfront-porch = <12>;
+   vback-porch = <12>;
+   vsync-len = <12>;
+   hsync-active = <0>;
+   vsync-active = <0>;
+   de-active = <0>;
+   pixelclk-active = <1>;
+   };
+   };
+   };
+};
-- 
1.9.1

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[U-Boot] [PATCH v3 08/10] arm: dts: stm32: add dsi for STM32F746

2018-03-13 Thread yannick fertre

Add mipi dsi bridge node in device-tree.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f746.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 8581df9..3b8af67 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -339,6 +339,18 @@
u-boot,dm-pre-reloc;
status = "disabled";
};
+
+   dsi: dsi@40016c00 {
+   compatible = "st,stm32-dsi";
+   reg = <0x40016C00 0x800>;
+   resets = <&rcc STM32F7_APB2_RESET(DSI)>;
+   clocks =  <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
+ <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
+ <&clk_hse>;
+   clock-names = "pclk", "px_clk", "ref";
+   u-boot,dm-pre-reloc;
+   status = "disabled";
+   };
};
 };
 
-- 
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[U-Boot] [PATCH v3 06/10] video: add support of STM32 MIPI DSI controller driver

2018-03-13 Thread yannick fertre

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/Kconfig |  10 +
 drivers/video/stm32/Makefile|   1 +
 drivers/video/stm32/stm32_dsi.c | 426 
 3 files changed, 437 insertions(+)
 create mode 100644 drivers/video/stm32/stm32_dsi.c

diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 113a2bb..2ea6f18 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
  DSI. This option enables these supports which can be used on
  devices which have RGB TFT or DSI display connected.
 
+config VIDEO_STM32_DSI
+   bool "Enable STM32 DSI video support"
+   depends on VIDEO_STM32
+   select VIDEO_MIPI_DSI
+   select VIDEO_BRIDGE
+   select VIDEO_DW_MIPI_DSI
+   help
+ This option enables support DSI internal bridge which can be used on
+ devices which have DSI display connected.
+
 config VIDEO_STM32_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_STM32
diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
index 372a2e1..f8c3ff7 100644
--- a/drivers/video/stm32/Makefile
+++ b/drivers/video/stm32/Makefile
@@ -8,3 +8,4 @@
 #
 
 obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000..949db4f
--- /dev/null
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,426 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * This driver is based on the mipi dsi driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US 20
+
+struct stm32_dsi_priv {
+   struct mipi_dsi_device device;
+   void __iomem *base;
+   struct udevice *panel;
+   u32 pllref_clk;
+   u32 hw_version;
+   int lane_min_kbps;
+   int lane_max_kbps;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+   writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+   return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(struct stm32_dsi_priv *dsi, u32 reg, u32 mask)
+

[U-Boot] [PATCH v3 07/10] video: add support of panel rm68200

2018-03-13 Thread yannick fertre

Support for Raydium rm68200 720p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig   |   8 +
 drivers/video/Makefile  |   1 +
 drivers/video/raydium-rm68200.c | 326 
 3 files changed, 335 insertions(+)
 create mode 100644 drivers/video/raydium-rm68200.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0f641d7..2561c59 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -328,6 +328,14 @@ config VIDEO_LCD_ORISETECH_OTM8009A
---help---
Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
 
+config VIDEO_LCD_RAYDIUM_RM68200
+   bool "RM68200 DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Raydium rm68200 720x1280 dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 50be569..1a6c8d3 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
+obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c
new file mode 100644
index 000..49b22af
--- /dev/null
+++ b/drivers/video/raydium-rm68200.c
@@ -0,0 +1,326 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre  for STMicroelectronics.
+ *   Philippe Cornu  for STMicroelectronics.
+ *
+ * This rm68200 panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-raydium-rm68200.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "raydium_rm68200"
+
+/*** Manufacturer Command Set ***/
+#define MCS_CMD_MODE_SW0xFE /* CMD Mode Switch */
+#define MCS_CMD1_UCS   0x00 /* User Command Set (UCS = CMD1) */
+#define MCS_CMD2_P00x01 /* Manufacture Command Set Page0 (CMD2 P0) */
+#define MCS_CMD2_P10x02 /* Manufacture Command Set Page1 (CMD2 P1) */
+#define MCS_CMD2_P20x03 /* Manufacture Command Set Page2 (CMD2 P2) */
+#define MCS_CMD2_P30x04 /* Manufacture Command Set Page3 (CMD2 P3) */
+
+/* CMD2 P0 commands (Display Options and Power) */
+#define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
+#define MCS_SGOPCTR0x16 /* Source Bias Current */
+#define MCS_SDCTR  0x1A /* Source Output Delay Time */
+#define MCS_INVCTR 0x1B /* Inversion Type */
+#define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
+#define MCS_SETAVDD0x27 /* PFM Control for AVDD Output */
+#define MCS_SETAVEE0x29 /* PFM Control for AVEE Output */
+#define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
+#define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
+#define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
+#define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
+#define MCS_SETVGN 0x52 /* VG M/S N Control */
+#define MCS_SETVGP 0x54 /* VG M/S P Control */
+#define MCS_SW_CTRL0x5F /* Interface Control for PFM and MIPI */
+
+/* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
+#define GOA_VSTV1  0x00
+#define GOA_VSTV2  0x07
+#define GOA_VCLK1  0x0E
+#define GOA_VCLK2  0x17
+#define GOA_VCLK_OPT1  0x20
+#define GOA_BICLK1 0x2A
+#define GOA_BICLK2 0x37
+#define GOA_BICLK3 0x44
+#define GOA_BICLK4 0x4F
+#define GOA_BICLK_OPT1 0x5B
+#define GOA_BICLK_OPT2 0x60
+#define MCS_GOA_GPO1   0x6D
+#define MCS_GOA_GPO2   0x71
+#define MCS_GOA_EQ 0x74
+#define MCS_GOA_CLK_GALLON 0x7C
+#define MCS_GOA_FS_SEL00x7E
+#define MCS_GOA_FS_SEL10x87
+#define MCS_GOA_FS_SEL20x91
+#define MCS_GOA_FS_SEL30x9B
+#define MCS_GOA_BS_SEL00xAC
+#define MCS_GOA_BS_SEL10xB5
+#define MCS_GOA_BS_SEL20xBF
+#define MCS_GOA_BS_SEL30xC9
+#define MCS_GOA_BS_SEL40xD3
+
+/* CMD2 P3 commands (Gamma) */
+#define MCS_GAMMA_VP   0x60 /* Gamma VP1~VP16 */
+#define MCS_GAMMA_VN   0x70 /* Gamma VN1~VN16 */
+
+struct rm68200_panel_priv {
+   struct udevice *reg;
+   struct udevice *backlight;
+   struct gpio_desc reset;
+};
+
+static void rm68200_dcs_write_buf(struct

[U-Boot] [PATCH v3 04/10] video: add support of panel OTM8009A

2018-03-13 Thread yannick fertre

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig  |   8 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 327 +
 3 files changed, 336 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..b5fc535 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6f42cca..65002af 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..aa8139a
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,327 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre  for STMicroelectronics.
+ *   Philippe Cornu  for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+struct otm8009a_panel_priv {
+   struct udevice *reg;
+   struct gpio_desc reset;
+};
+
+static void otm8009a_dcs_write_b

[U-Boot] [PATCH v3 05/10] video: add MIPI DSI host controller bridge

2018-03-13 Thread yannick fertre

Add a Synopsys Designware MIPI DSI host bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig   |   9 +
 drivers/video/Makefile  |   1 +
 drivers/video/dw_mipi_dsi.c | 822 
 include/dw_mipi_dsi.h   |  34 ++
 4 files changed, 866 insertions(+)
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index b5fc535..0f641d7 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -657,6 +657,15 @@ config VIDEO_DW_HDMI
  rather requires a SoC-specific glue driver to call it), it
  can not be enabled from the configuration menu.
 
+config VIDEO_DW_MIPI_DSI
+   bool
+   help
+ Enables the common driver code for the Designware MIPI DSI
+ block found in SoCs from various vendors.
+ As this does not provide any functionality by itself (but
+ rather requires a SoC-specific glue driver to call it), it
+ can not be enabled from the configuration menu.
+
 config VIDEO_SIMPLE
bool "Simple display driver for preconfigured display"
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 65002af..50be569 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o
 obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
new file mode 100644
index 000..d7bd92d
--- /dev/null
+++ b/drivers/video/dw_mipi_dsi.c
@@ -0,0 +1,822 @@
+/*
+ * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * Modified by Yannick Fertre 
+ * This generic Synopsys DesignWare MIPI DSI host driver is based on the
+ * bridge synopsys from drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c (kernel
+ * linux).
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_CLKMGR_CFG 0x08
+#define TO_CLK_DIVISION(div)   (((div) & 0xff) << 8)
+#define TX_ESC_CLK_DIVISION(div)   ((div) & 0xff)
+
+#define DSI_DPI_VCID   0x0c
+#define DPI_VCID(vcid) ((vcid) & 0x3)
+
+#define DSI_DPI_COLOR_CODING   0x10
+#define LOOSELY18_EN   BIT(8)
+#define DPI_COLOR_CODING_16BIT_1   0x0
+#define DPI_COLOR_CODING_16BIT_2   0x1
+#define DPI_COLOR_CODING_16BIT_3   0x2
+#define DPI_COLOR_CODING_18BIT_1   0x3
+#define DPI_COLOR_CODING_18BIT_2   0x4
+#define DPI_COLOR_CODING_24BIT 0x5
+
+#define DSI_DPI_CFG_POL0x14
+#define COLORM_ACTIVE_LOW  BIT(4)
+#define SHUTD_ACTIVE_LOW   BIT(3)
+#define HSYNC_ACTIVE_LOW   BIT(2)
+#define VSYNC_ACTIVE_LOW   BIT(1)
+#define DATAEN_ACTIVE_LOW  BIT(0)
+
+#define DSI_DPI_LP_CMD_TIM 0x18
+#define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
+#define INVACT_LPCMD_TIME(p)   ((p) & 0xff)
+
+#define DSI_DBI_VCID   0x1c
+#define DSI_DBI_CFG0x20
+#define DSI_DBI_PARTITIONING_EN0x24
+#define DSI_DBI_CMDSIZE0x28
+
+#define DSI_PCKHDL_CFG 0x2c
+#define CRC_RX_EN  BIT(4)
+#define ECC_RX_EN  BIT(3)
+#define BTA_EN BIT(2)
+#define EOTP_RX_EN BIT(1)
+#define EOTP_TX_EN BIT(0)
+
+#define DSI_GEN_VCID   0x30
+
+#define DSI_MODE_CFG   0x34
+#define ENABLE_VIDEO_MODE  0
+#define ENABLE_CMD_MODEBIT(0)
+
+#define DSI_VID_MODE_CFG   0x38
+#define ENABLE_LOW_POWER   (0x3f << 8)
+#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
+#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
+#define VID_MODE_TYPE_BURST0x2
+#de

[U-Boot] [PATCH v3 03/10] video: add support of panel OTM8009A

2018-03-13 Thread yannick fertre

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig  |   8 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 325 +
 3 files changed, 334 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..b5fc535 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6f42cca..65002af 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..81b11d7
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,325 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre  for STMicroelectronics.
+ *   Philippe Cornu  for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+struct otm8009a_panel_priv {
+   struct udevice *reg;
+   struct gpio_desc reset;
+};
+
+static void otm8009a_dcs_write_b

[U-Boot] [PATCH v3 03/10] video: add support of MIPI DSI interface

2018-03-13 Thread yannick fertre

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/mipi_display.c | 807 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..6f42cca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..d90ff5d
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,807 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)
+{
+   switch (type) {
+   case MIPI_DSI_V_SYNC_START:
+   case MIPI_DSI_V_SYNC_END:
+   case MIP

[U-Boot] [PATCH v3 02/10] video: add support of MIPI DSI interface

2018-03-13 Thread yannick fertre

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/mipi_display.c | 807 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..6f42cca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..d90ff5d
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,807 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)
+{
+   switch (type) {
+   case MIPI_DSI_V_SYNC_START:
+   case MIPI_DSI_V_SYNC_END:
+   case MIP

[U-Boot] [PATCH v3 01/10] video: stm32: stm32_ltdc: update debug log

2018-03-13 Thread yannick fertre

Replace  macro debug by pr_error, pr_warn or pr_info.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 67 ++--
 1 file changed, 30 insertions(+), 37 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index bd9c0de..3e12c71 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -5,7 +5,6 @@
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
-
 #include 
 #include 
 #include 
@@ -13,12 +12,10 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
-#include 
-
-DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
@@ -176,13 +173,13 @@ static u32 stm32_ltdc_get_pixel_format(enum 
video_log2_bpp l2bpp)
case VIDEO_BPP2:
case VIDEO_BPP4:
default:
-   debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
- __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
+   pr_warn("warning %dbpp not supported yet, %dbpp instead\n",
+   VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
pf = PF_RGB565;
break;
}
 
-   debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
+   pr_info("%d bpp -> ltdc pf %d\n", VNBITS(l2bpp), pf);
 
return (u32)pf;
 }
@@ -249,7 +246,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv,
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   dev_info(dev, "timing->flags 0x%08x\n", timings->flags);
if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
@@ -343,26 +340,25 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
-   debug("%s: ltdc dt register address error\n", __func__);
+   dev_err(dev, "ltdc dt register address error\n");
return -EINVAL;
}
 
ret = clk_get_by_index(dev, 0, &pclk);
if (ret) {
-   debug("%s: peripheral clock get error %d\n", __func__, ret);
+   dev_err(dev, "peripheral clock get error %d\n", ret);
return ret;
}
 
ret = clk_enable(&pclk);
if (ret) {
-   debug("%s: peripheral clock enable error %d\n",
- __func__, ret);
+   dev_err(dev, "peripheral clock enable error %d\n", ret);
return ret;
}
 
ret = reset_get_by_index(dev, 0, &rst);
if (ret) {
-   debug("%s: missing ltdc hardware reset\n", __func__);
+   dev_err(dev, "missing ltdc hardware reset\n");
return -ENODEV;
}
 
@@ -371,42 +367,39 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
 #ifdef CONFIG_VIDEO_BRIDGE
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
-   if (ret) {
-   debug("%s: No video bridge, or no backlight on bridge\n",
- __func__);
-   }
+   if (ret)
+   dev_info(dev, "No video bridge, or no backlight on bridge\n");
 
if (bridge) {
ret = video_bridge_attach(bridge);
if (ret) {
-   debug("%s: fail to attach bridge\n", __func__);
+   dev_err(dev, "fail to attach bridge\n");
return ret;
}
}
 #endif
ret = uclass_first_device(UCLASS_PANEL, &panel);
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
+   dev_err(dev, "panel device error %d\n", ret);
return ret;
}
 
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(panel),
   0, &timings);
if (ret) {
-   debug("%s: decode display timing error %d\n",
- __func__, ret);
+   dev_err(dev, "decode display timing error %d\n", ret);
return ret;
}
 
rate = clk_set_rate(&pclk, timings.pixelclock.typ);
if (rate < 0) {
-   debug("%s: fail to set pixel clock %d hz %d hz\n",
- __func__, timings.pixelclock.typ, rate);
+   dev_err(dev, "fail to set pixel clock %d hz %d hz\n",
+   timings.pixelclock.typ, rate);
return rate;
}
 
-   debug("%s: Set pixel clock req %d hz get %d hz\n",

[U-Boot] [PATCH v3 01/10] video: stm32: stm32_ltdc: add bridge to display controller

2018-03-13 Thread yannick fertre

Manage a bridge insert between the display controller & a panel.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 107 ++-
 1 file changed, 71 insertions(+), 36 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index e160c77..bd9c0de 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -15,12 +16,12 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
-   struct display_timing timing;
enum video_log2_bpp l2bpp;
u32 bg_col_argb;
u32 crop_x, crop_y, crop_w, crop_h;
@@ -210,23 +211,23 @@ static void stm32_ltdc_enable(struct stm32_ltdc_priv 
*priv)
setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
 }
 
-static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
+static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
+   struct display_timing *timings)
 {
void __iomem *regs = priv->regs;
-   struct display_timing *timing = &priv->timing;
u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
u32 total_w, total_h;
u32 val;
 
/* Convert video timings to ltdc timings */
-   hsync = timing->hsync_len.typ - 1;
-   vsync = timing->vsync_len.typ - 1;
-   acc_hbp = hsync + timing->hback_porch.typ;
-   acc_vbp = vsync + timing->vback_porch.typ;
-   acc_act_w = acc_hbp + timing->hactive.typ;
-   acc_act_h = acc_vbp + timing->vactive.typ;
-   total_w = acc_act_w + timing->hfront_porch.typ;
-   total_h = acc_act_h + timing->vfront_porch.typ;
+   hsync = timings->hsync_len.typ - 1;
+   vsync = timings->vsync_len.typ - 1;
+   acc_hbp = hsync + timings->hback_porch.typ;
+   acc_vbp = vsync + timings->vback_porch.typ;
+   acc_act_w = acc_hbp + timings->hactive.typ;
+   acc_act_h = acc_vbp + timings->vactive.typ;
+   total_w = acc_act_w + timings->hfront_porch.typ;
+   total_h = acc_act_h + timings->vfront_porch.typ;
 
/* Synchronization sizes */
val = (hsync << 16) | vsync;
@@ -248,14 +249,14 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv)
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
-   if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
-   if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= GCR_VSPOL;
-   if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
val |= GCR_DEPOL;
-   if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+   if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
val |= GCR_PCPOL;
clrsetbits_le32(regs + LTDC_GCR,
GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
@@ -331,7 +332,11 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
-   struct udevice *panel;
+#ifdef CONFIG_VIDEO_BRIDGE
+   struct udevice *bridge = NULL;
+#endif
+   struct udevice *panel = NULL;
+   struct display_timing timings;
struct clk pclk;
struct reset_ctl rst;
int rate, ret;
@@ -364,63 +369,93 @@ static int stm32_ltdc_probe(struct udevice *dev)
/* Reset */
reset_deassert(&rst);
 
-   ret = uclass_first_device(UCLASS_PANEL, &panel);
+#ifdef CONFIG_VIDEO_BRIDGE
+   ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
-   return ret;
+   debug("%s: No video bridge, or no backlight on bridge\n",
+ __func__);
}
 
-   ret = panel_enable_backlight(panel);
+   if (bridge) {
+   ret = video_bridge_attach(bridge);
+   if (ret) {
+   debug("%s: fail to attach bridge\n", __func__);
+   return ret;
+   }
+   }
+#endif
+   ret = uclass_first_device(UCLASS_PANEL, &panel);
if (ret) {
-   debug("%s: panel %s enable backlight error %d\n",
- __func__, panel->name, ret);
+

Re: [U-Boot] [PATCH v3 04/10] otm

2018-03-13 Thread Yannick FERTRE

Hi,

Sorry, I send more than 10 patches.

I will remove this dummy patches tomorrow with next version.



On 03/13/2018 03:12 PM, Patrice CHOTARD wrote:
> Hi Yannick
>
> There is a problem with patch 4. I received two patches 04/10, this one
> and [PATCH v3 04/10] video: add support of panel OTM8009A.
>
> Patrice
>
> On 03/13/2018 02:50 PM, yannick fertre wrote:
>> ---
>>drivers/video/orisetech_otm8009a.c | 4 +++-
>>1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/video/orisetech_otm8009a.c 
>> b/drivers/video/orisetech_otm8009a.c
>> index 81b11d7..aa8139a 100644
>> --- a/drivers/video/orisetech_otm8009a.c
>> +++ b/drivers/video/orisetech_otm8009a.c
>> @@ -289,9 +289,11 @@ static int otm8009a_panel_probe(struct udevice *dev)
>>  struct otm8009a_panel_priv *priv = dev_get_priv(dev);
>>  int ret;
>>
>> -/* reset panel must be done before probe */
>> +/* reset panel */
>>  dm_gpio_set_value(&priv->reset, true);
>>
>> +mdelay(1);
>> +
>>  if (IS_ENABLED(CONFIG_DM_REGULATOR) && priv->reg) {
>>  dev_err(dev, "enable regulator '%s'\n", priv->reg->name);
>>  ret = regulator_set_enable(priv->reg, true);
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[U-Boot] [PATCH v2 05/10] video: add MIPI DSI host controller bridge

2018-03-02 Thread yannick fertre

Add a Synopsys Designware MIPI DSI host bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig   |   9 +
 drivers/video/Makefile  |   1 +
 drivers/video/dw_mipi_dsi.c | 822 
 include/dw_mipi_dsi.h   |  32 ++
 4 files changed, 864 insertions(+)
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index b5fc535..0f641d7 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -657,6 +657,15 @@ config VIDEO_DW_HDMI
  rather requires a SoC-specific glue driver to call it), it
  can not be enabled from the configuration menu.
 
+config VIDEO_DW_MIPI_DSI
+   bool
+   help
+ Enables the common driver code for the Designware MIPI DSI
+ block found in SoCs from various vendors.
+ As this does not provide any functionality by itself (but
+ rather requires a SoC-specific glue driver to call it), it
+ can not be enabled from the configuration menu.
+
 config VIDEO_SIMPLE
bool "Simple display driver for preconfigured display"
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 65002af..50be569 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o
 obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
new file mode 100644
index 000..d7bd92d
--- /dev/null
+++ b/drivers/video/dw_mipi_dsi.c
@@ -0,0 +1,822 @@
+/*
+ * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * Modified by Yannick Fertre 
+ * This generic Synopsys DesignWare MIPI DSI host driver is based on the
+ * bridge synopsys from drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c (kernel
+ * linux).
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_CLKMGR_CFG 0x08
+#define TO_CLK_DIVISION(div)   (((div) & 0xff) << 8)
+#define TX_ESC_CLK_DIVISION(div)   ((div) & 0xff)
+
+#define DSI_DPI_VCID   0x0c
+#define DPI_VCID(vcid) ((vcid) & 0x3)
+
+#define DSI_DPI_COLOR_CODING   0x10
+#define LOOSELY18_EN   BIT(8)
+#define DPI_COLOR_CODING_16BIT_1   0x0
+#define DPI_COLOR_CODING_16BIT_2   0x1
+#define DPI_COLOR_CODING_16BIT_3   0x2
+#define DPI_COLOR_CODING_18BIT_1   0x3
+#define DPI_COLOR_CODING_18BIT_2   0x4
+#define DPI_COLOR_CODING_24BIT 0x5
+
+#define DSI_DPI_CFG_POL0x14
+#define COLORM_ACTIVE_LOW  BIT(4)
+#define SHUTD_ACTIVE_LOW   BIT(3)
+#define HSYNC_ACTIVE_LOW   BIT(2)
+#define VSYNC_ACTIVE_LOW   BIT(1)
+#define DATAEN_ACTIVE_LOW  BIT(0)
+
+#define DSI_DPI_LP_CMD_TIM 0x18
+#define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
+#define INVACT_LPCMD_TIME(p)   ((p) & 0xff)
+
+#define DSI_DBI_VCID   0x1c
+#define DSI_DBI_CFG0x20
+#define DSI_DBI_PARTITIONING_EN0x24
+#define DSI_DBI_CMDSIZE0x28
+
+#define DSI_PCKHDL_CFG 0x2c
+#define CRC_RX_EN  BIT(4)
+#define ECC_RX_EN  BIT(3)
+#define BTA_EN BIT(2)
+#define EOTP_RX_EN BIT(1)
+#define EOTP_TX_EN BIT(0)
+
+#define DSI_GEN_VCID   0x30
+
+#define DSI_MODE_CFG   0x34
+#define ENABLE_VIDEO_MODE  0
+#define ENABLE_CMD_MODEBIT(0)
+
+#define DSI_VID_MODE_CFG   0x38
+#define ENABLE_LOW_POWER   (0x3f << 8)
+#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
+#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
+#define VID_MODE_TYPE_BURST0x2
+#de

[U-Boot] [PATCH v2 07/10] video: add support of panel rm68200

2018-03-02 Thread yannick fertre

Support for Raydium rm68200 720p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig   |   8 +
 drivers/video/Makefile  |   1 +
 drivers/video/raydium-rm68200.c | 329 
 3 files changed, 338 insertions(+)
 create mode 100644 drivers/video/raydium-rm68200.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 0f641d7..2561c59 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -328,6 +328,14 @@ config VIDEO_LCD_ORISETECH_OTM8009A
---help---
Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
 
+config VIDEO_LCD_RAYDIUM_RM68200
+   bool "RM68200 DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Raydium rm68200 720x1280 dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 50be569..1a6c8d3 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
 obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
+obj-$(CONFIG_VIDEO_LCD_RAYDIUM_RM68200) += raydium-rm68200.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/raydium-rm68200.c b/drivers/video/raydium-rm68200.c
new file mode 100644
index 000..46afb58
--- /dev/null
+++ b/drivers/video/raydium-rm68200.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre  for STMicroelectronics.
+ *   Philippe Cornu  for STMicroelectronics.
+ *
+ * This rm68200 panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-raydium-rm68200.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DRV_NAME "raydium_rm68200"
+
+/*** Manufacturer Command Set ***/
+#define MCS_CMD_MODE_SW0xFE /* CMD Mode Switch */
+#define MCS_CMD1_UCS   0x00 /* User Command Set (UCS = CMD1) */
+#define MCS_CMD2_P00x01 /* Manufacture Command Set Page0 (CMD2 P0) */
+#define MCS_CMD2_P10x02 /* Manufacture Command Set Page1 (CMD2 P1) */
+#define MCS_CMD2_P20x03 /* Manufacture Command Set Page2 (CMD2 P2) */
+#define MCS_CMD2_P30x04 /* Manufacture Command Set Page3 (CMD2 P3) */
+
+/* CMD2 P0 commands (Display Options and Power) */
+#define MCS_STBCTR 0x12 /* TE1 Output Setting Zig-Zag Connection */
+#define MCS_SGOPCTR0x16 /* Source Bias Current */
+#define MCS_SDCTR  0x1A /* Source Output Delay Time */
+#define MCS_INVCTR 0x1B /* Inversion Type */
+#define MCS_EXT_PWR_IC 0x24 /* External PWR IC Control */
+#define MCS_SETAVDD0x27 /* PFM Control for AVDD Output */
+#define MCS_SETAVEE0x29 /* PFM Control for AVEE Output */
+#define MCS_BT2CTR 0x2B /* DDVDL Charge Pump Control */
+#define MCS_BT3CTR 0x2F /* VGH Charge Pump Control */
+#define MCS_BT4CTR 0x34 /* VGL Charge Pump Control */
+#define MCS_VCMCTR 0x46 /* VCOM Output Level Control */
+#define MCS_SETVGN 0x52 /* VG M/S N Control */
+#define MCS_SETVGP 0x54 /* VG M/S P Control */
+#define MCS_SW_CTRL0x5F /* Interface Control for PFM and MIPI */
+
+/* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
+#define GOA_VSTV1  0x00
+#define GOA_VSTV2  0x07
+#define GOA_VCLK1  0x0E
+#define GOA_VCLK2  0x17
+#define GOA_VCLK_OPT1  0x20
+#define GOA_BICLK1 0x2A
+#define GOA_BICLK2 0x37
+#define GOA_BICLK3 0x44
+#define GOA_BICLK4 0x4F
+#define GOA_BICLK_OPT1 0x5B
+#define GOA_BICLK_OPT2 0x60
+#define MCS_GOA_GPO1   0x6D
+#define MCS_GOA_GPO2   0x71
+#define MCS_GOA_EQ 0x74
+#define MCS_GOA_CLK_GALLON 0x7C
+#define MCS_GOA_FS_SEL00x7E
+#define MCS_GOA_FS_SEL10x87
+#define MCS_GOA_FS_SEL20x91
+#define MCS_GOA_FS_SEL30x9B
+#define MCS_GOA_BS_SEL00xAC
+#define MCS_GOA_BS_SEL10xB5
+#define MCS_GOA_BS_SEL20xBF
+#define MCS_GOA_BS_SEL30xC9
+#define MCS_GOA_BS_SEL40xD3
+
+/* CMD2 P3 commands (Gamma) */
+#define MCS_GAMMA_VP   0x60 /* Gamma VP1~VP16 */
+#define MCS_GAMMA_VN   0x70 /* Gamma VN1~VN16 */
+
+struct rm68200_panel_priv {
+   struct udevice *reg;
+   struct udevice *backlight;
+   struct gpio_desc reset;
+};
+
+static void rm68200_dcs_write_buf(struct udevice *dev, const void *data,
+ size_t len)
+{
+   struct mipi_dsi_panel_plat *plat = dev_get_platdata(dev);
+   struct mipi_dsi

[U-Boot] [PATCH v2 02/10] video: stm32: stm32_ltdc: update debug log

2018-03-02 Thread yannick fertre

Replace  macro debug by pr_error, pr_warn or pr_info.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 62 
 1 file changed, 31 insertions(+), 31 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index bd9c0de..e95f35c 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -176,13 +176,13 @@ static u32 stm32_ltdc_get_pixel_format(enum 
video_log2_bpp l2bpp)
case VIDEO_BPP2:
case VIDEO_BPP4:
default:
-   debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
- __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
+   pr_warn("%s: warning %dbpp not supported yet, %dbpp instead\n",
+   __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
pf = PF_RGB565;
break;
}
 
-   debug("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
+   pr_info("%s: %d bpp -> ltdc pf %d\n", __func__, VNBITS(l2bpp), pf);
 
return (u32)pf;
 }
@@ -249,7 +249,7 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv,
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   pr_info("%s: timing->flags 0x%08x\n", __func__, timings->flags);
if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
@@ -343,26 +343,26 @@ static int stm32_ltdc_probe(struct udevice *dev)
 
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
-   debug("%s: ltdc dt register address error\n", __func__);
+   pr_err("%s: ltdc dt register address error\n", __func__);
return -EINVAL;
}
 
ret = clk_get_by_index(dev, 0, &pclk);
if (ret) {
-   debug("%s: peripheral clock get error %d\n", __func__, ret);
+   pr_err("%s: peripheral clock get error %d\n", __func__, ret);
return ret;
}
 
ret = clk_enable(&pclk);
if (ret) {
-   debug("%s: peripheral clock enable error %d\n",
- __func__, ret);
+   pr_err("%s: peripheral clock enable error %d\n",
+  __func__, ret);
return ret;
}
 
ret = reset_get_by_index(dev, 0, &rst);
if (ret) {
-   debug("%s: missing ltdc hardware reset\n", __func__);
+   pr_err("%s: missing ltdc hardware reset\n", __func__);
return -ENODEV;
}
 
@@ -372,41 +372,40 @@ static int stm32_ltdc_probe(struct udevice *dev)
 #ifdef CONFIG_VIDEO_BRIDGE
ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
if (ret) {
-   debug("%s: No video bridge, or no backlight on bridge\n",
- __func__);
+   pr_info("%s: No video bridge, or no backlight on bridge\n",
+   __func__);
}
 
if (bridge) {
ret = video_bridge_attach(bridge);
if (ret) {
-   debug("%s: fail to attach bridge\n", __func__);
+   pr_err("%s: fail to attach bridge\n", __func__);
return ret;
}
}
 #endif
ret = uclass_first_device(UCLASS_PANEL, &panel);
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
+   pr_err("%s: panel device error %d\n", __func__, ret);
return ret;
}
 
ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(panel),
   0, &timings);
if (ret) {
-   debug("%s: decode display timing error %d\n",
- __func__, ret);
+   pr_err("%s: decode display timing error %d\n", __func__, ret);
return ret;
}
 
rate = clk_set_rate(&pclk, timings.pixelclock.typ);
if (rate < 0) {
-   debug("%s: fail to set pixel clock %d hz %d hz\n",
- __func__, timings.pixelclock.typ, rate);
+   pr_err("%s: fail to set pixel clock %d hz %d hz\n",
+  __func__, timings.pixelclock.typ, rate);
return rate;
}
 
-   debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
- timings.pixelclock.typ, rate);
+   pr_info("%s: Set pixel clock req %d hz get %d hz\n", __func__,
+   timi

[U-Boot] [PATCH v2 09/10] arm: dts: stm32: add display for STM32F769 disco board

2018-03-02 Thread yannick fertre

Enable the display controller, mipi dsi bridge & panel.
Set panel display timings.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f769-disco.dts | 71 
 1 file changed, 71 insertions(+)

diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index 59c9d31..82985b9 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -42,6 +42,7 @@
 
 /dts-v1/;
 #include "stm32f746.dtsi"
+#include 
 #include 
 
 / {
@@ -264,3 +265,73 @@
bus-width = <4>;
max-frequency = <2500>;
 };
+
+<dc {
+   status = "okay";
+
+   port {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   ltdc_out_dsi: endpoint@0 {
+   reg = <0>;
+   remote-endpoint = <&dsi_in>;
+   };
+   };
+};
+
+&dsi {
+   #address-cells = <1>;
+   #size-cells = <0>;
+   status = "okay";
+
+   ports {
+   #address-cells = <1>;
+   #size-cells = <0>;
+
+   port@0 {
+   reg = <0>;
+   dsi_in: endpoint {
+   remote-endpoint = <<dc_out_dsi>;
+   };
+   };
+
+   port@1 {
+   reg = <1>;
+   dsi_out: endpoint {
+   remote-endpoint = <&dsi_panel_in>;
+   };
+   };
+   };
+
+   panel-dsi@0 {
+   compatible = "orisetech,otm8009a";
+   reg = <0>; /* dsi virtual channel (0..3) */
+   reset-gpios = <&gpioj 15 GPIO_ACTIVE_LOW>;
+   status = "okay";
+
+   port {
+   dsi_panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+
+   display-timings {
+   timing@0 {
+   clock-frequency = <32729000>;
+   hactive = <480>;
+   hfront-porch = <120>;
+   hback-porch = <63>;
+   hsync-len = <120>;
+   vactive = <800>;
+   vfront-porch = <12>;
+   vback-porch = <12>;
+   vsync-len = <12>;
+   hsync-active = <0>;
+   vsync-active = <0>;
+   de-active = <0>;
+   pixelclk-active = <1>;
+   };
+   };
+   };
+};
-- 
1.9.1

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[U-Boot] [PATCH v2 06/10] video: add support of STM32 MIPI DSI controller driver

2018-03-02 Thread yannick fertre

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/Kconfig |  10 +
 drivers/video/stm32/Makefile|   1 +
 drivers/video/stm32/stm32_dsi.c | 427 
 3 files changed, 438 insertions(+)
 create mode 100644 drivers/video/stm32/stm32_dsi.c

diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 113a2bb..2ea6f18 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
  DSI. This option enables these supports which can be used on
  devices which have RGB TFT or DSI display connected.
 
+config VIDEO_STM32_DSI
+   bool "Enable STM32 DSI video support"
+   depends on VIDEO_STM32
+   select VIDEO_MIPI_DSI
+   select VIDEO_BRIDGE
+   select VIDEO_DW_MIPI_DSI
+   help
+ This option enables support DSI internal bridge which can be used on
+ devices which have DSI display connected.
+
 config VIDEO_STM32_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_STM32
diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
index 372a2e1..f8c3ff7 100644
--- a/drivers/video/stm32/Makefile
+++ b/drivers/video/stm32/Makefile
@@ -8,3 +8,4 @@
 #
 
 obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000..3e26433
--- /dev/null
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * This driver is based on the mipi dsi driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+/*
+ * DSI wrapper registers & bit definitions
+ * Note: registers are named as in the Reference Manual
+ */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US 20
+
+struct stm32_dsi_priv {
+   struct mipi_dsi_device device;
+   void __iomem *base;
+   struct udevice *panel;
+   u32 pllref_clk;
+   u32 hw_version;
+   int lane_min_kbps;
+   int lane_max_kbps;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+   writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+   return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(str

[U-Boot] [PATCH v2 08/10] arm: dts: stm32: add dsi for STM32F746

2018-03-02 Thread yannick fertre

Add mipi dsi bridge node in device-tree.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f746.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index e4d32bf..4ec954d 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -332,6 +332,18 @@
u-boot,dm-pre-reloc;
status = "disabled";
};
+
+   dsi: dsi@40016c00 {
+   compatible = "st,stm32-dsi";
+   reg = <0x40016C00 0x800>;
+   resets = <&rcc STM32F7_APB2_RESET(DSI)>;
+   clocks =  <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
+ <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
+ <&clk_hse>;
+   clock-names = "pclk", "px_clk", "ref";
+   u-boot,dm-pre-reloc;
+   status = "disabled";
+   };
};
 };
 
-- 
1.9.1

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[U-Boot] [PATCH v2 10/10] board: Add STM32F769 SoC, discovery board support

2018-03-02 Thread yannick fertre

Signed-off-by: yannick fertre 
---
 configs/stm32f769-disco_defconfig | 63 +++
 1 file changed, 63 insertions(+)
 create mode 100644 configs/stm32f769-disco_defconfig

diff --git a/configs/stm32f769-disco_defconfig 
b/configs/stm32f769-disco_defconfig
new file mode 100644
index 000..ac34076
--- /dev/null
+++ b/configs/stm32f769-disco_defconfig
@@ -0,0 +1,63 @@
+CONFIG_ARM=y
+CONFIG_STM32=y
+CONFIG_SYS_MALLOC_F_LEN=0xC00
+CONFIG_STM32F7=y
+CONFIG_TARGET_STM32F746_DISCO=y
+CONFIG_DEFAULT_DEVICE_TREE="stm32f769-disco"
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="console=ttyS0,115200 earlyprintk consoleblank=0 
ignore_loglevel"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_BOARD_EARLY_INIT_F=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="U-Boot > "
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n"
+CONFIG_AUTOBOOT_STOP_STR=" "
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_FPGA is not set
+CONFIG_CMD_GPT=y
+# CONFIG_RANDOM_UUID is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_SNTP=y
+CONFIG_CMD_DNS=y
+CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_BMP=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_DOS_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_NETCONSOLE=y
+# CONFIG_BLK is not set
+CONFIG_DM_MMC=y
+# CONFIG_SPL_DM_MMC is not set
+CONFIG_ARM_PL180_MMCI=y
+CONFIG_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DM_ETH=y
+CONFIG_ETH_DESIGNWARE=y
+# CONFIG_PINCTRL_FULL is not set
+CONFIG_DM_SPI=y
+CONFIG_STM32_QSPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_LCD_ORISETECH_OTM8009A=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_DSI=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=800
+CONFIG_OF_LIBFDT_OVERLAY=y
+# CONFIG_EFI_LOADER is not set
-- 
1.9.1

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[U-Boot] [PATCH v2 04/10] video: add support of panel OTM8009A

2018-03-02 Thread yannick fertre

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig  |   8 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 329 +
 3 files changed, 338 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..b5fc535 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,14 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on DM_VIDEO
+   select VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 6f42cca..65002af 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -37,6 +37,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..79f2da8
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Yannick Fertre  for STMicroelectronics.
+ *   Philippe Cornu  for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+struct otm8009a_panel_priv {
+   struct udevice *reg;
+   struct gpio_desc reset;
+};
+
+static vo

[U-Boot] [PATCH v2 03/10] video: add support of MIPI DSI interface

2018-03-02 Thread yannick fertre

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   1 +
 drivers/video/mipi_display.c | 807 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1071 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..6f42cca 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -52,6 +52,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..d90ff5d
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,807 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)
+{
+   switch (type) {
+   case MIPI_DSI_V_SYNC_START:
+   case MIPI_DSI_V_SYNC_END:
+   case MIP

[U-Boot] [PATCH v2 01/10] video: stm32: stm32_ltdc: add bridge to display controller

2018-03-02 Thread yannick fertre

Manage a bridge insert between the display controller & a panel.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 107 ++-
 1 file changed, 71 insertions(+), 36 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index e160c77..bd9c0de 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -15,12 +16,12 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
-   struct display_timing timing;
enum video_log2_bpp l2bpp;
u32 bg_col_argb;
u32 crop_x, crop_y, crop_w, crop_h;
@@ -210,23 +211,23 @@ static void stm32_ltdc_enable(struct stm32_ltdc_priv 
*priv)
setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
 }
 
-static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
+static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
+   struct display_timing *timings)
 {
void __iomem *regs = priv->regs;
-   struct display_timing *timing = &priv->timing;
u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
u32 total_w, total_h;
u32 val;
 
/* Convert video timings to ltdc timings */
-   hsync = timing->hsync_len.typ - 1;
-   vsync = timing->vsync_len.typ - 1;
-   acc_hbp = hsync + timing->hback_porch.typ;
-   acc_vbp = vsync + timing->vback_porch.typ;
-   acc_act_w = acc_hbp + timing->hactive.typ;
-   acc_act_h = acc_vbp + timing->vactive.typ;
-   total_w = acc_act_w + timing->hfront_porch.typ;
-   total_h = acc_act_h + timing->vfront_porch.typ;
+   hsync = timings->hsync_len.typ - 1;
+   vsync = timings->vsync_len.typ - 1;
+   acc_hbp = hsync + timings->hback_porch.typ;
+   acc_vbp = vsync + timings->vback_porch.typ;
+   acc_act_w = acc_hbp + timings->hactive.typ;
+   acc_act_h = acc_vbp + timings->vactive.typ;
+   total_w = acc_act_w + timings->hfront_porch.typ;
+   total_h = acc_act_h + timings->vfront_porch.typ;
 
/* Synchronization sizes */
val = (hsync << 16) | vsync;
@@ -248,14 +249,14 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv)
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
-   if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
-   if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= GCR_VSPOL;
-   if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
val |= GCR_DEPOL;
-   if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+   if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
val |= GCR_PCPOL;
clrsetbits_le32(regs + LTDC_GCR,
GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
@@ -331,7 +332,11 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
-   struct udevice *panel;
+#ifdef CONFIG_VIDEO_BRIDGE
+   struct udevice *bridge = NULL;
+#endif
+   struct udevice *panel = NULL;
+   struct display_timing timings;
struct clk pclk;
struct reset_ctl rst;
int rate, ret;
@@ -364,63 +369,93 @@ static int stm32_ltdc_probe(struct udevice *dev)
/* Reset */
reset_deassert(&rst);
 
-   ret = uclass_first_device(UCLASS_PANEL, &panel);
+#ifdef CONFIG_VIDEO_BRIDGE
+   ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
-   return ret;
+   debug("%s: No video bridge, or no backlight on bridge\n",
+ __func__);
}
 
-   ret = panel_enable_backlight(panel);
+   if (bridge) {
+   ret = video_bridge_attach(bridge);
+   if (ret) {
+   debug("%s: fail to attach bridge\n", __func__);
+   return ret;
+   }
+   }
+#endif
+   ret = uclass_first_device(UCLASS_PANEL, &panel);
if (ret) {
-   debug("%s: panel %s enable backlight error %d\n",
- __func__, panel->name, ret);
+

[U-Boot] [PATCH v2 00/10] splash screen on the stm32f769 disco board

2018-03-02 Thread yannick fertre

Version 2:
- Replace debug log by pr_error, pr_warn or pr_info.
- Rework bridge between ltdc & dsi panel
- Rework backligh management (with or witout gpio)
- Rework panel otm8009a
- Add new panel raydium rm68200

Version 1:
- Initial commit

This serie contains all patchsets needed for displaying a splash screen 
on the stm32f769 disco board.

yannick fertre (10):
  video: stm32: stm32_ltdc: add bridge to display controller
  video: stm32: stm32_ltdc: update debug log
  video: add support of MIPI DSI interface
  video: add support of panel OTM8009A
  video: add MIPI DSI host controller bridge
  video: add support of STM32 MIPI DSI controller driver
  video: add support of panel rm68200
  arm: dts: stm32: add dsi for STM32F746
  arm: dts: stm32: add display for STM32F769 disco board
  board: Add STM32F769 SoC, discovery board support

 arch/arm/dts/stm32f746.dtsi|  12 +
 arch/arm/dts/stm32f769-disco.dts   |  71 
 configs/stm32f769-disco_defconfig  |  63 +++
 drivers/video/Kconfig  |  32 ++
 drivers/video/Makefile |   4 +
 drivers/video/dw_mipi_dsi.c| 822 +
 drivers/video/mipi_display.c   | 807 
 drivers/video/orisetech_otm8009a.c | 329 +++
 drivers/video/raydium-rm68200.c| 329 +++
 drivers/video/stm32/Kconfig|  10 +
 drivers/video/stm32/Makefile   |   1 +
 drivers/video/stm32/stm32_dsi.c| 427 +++
 drivers/video/stm32/stm32_ltdc.c   | 144 ---
 include/dw_mipi_dsi.h  |  32 ++
 include/mipi_display.h | 257 +++-
 15 files changed, 3285 insertions(+), 55 deletions(-)
 create mode 100644 configs/stm32f769-disco_defconfig
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 drivers/video/mipi_display.c
 create mode 100644 drivers/video/orisetech_otm8009a.c
 create mode 100644 drivers/video/raydium-rm68200.c
 create mode 100644 drivers/video/stm32/stm32_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

-- 
1.9.1

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[U-Boot] [PATCH v2 7/9] arm: dts: stm32: add display for STM32F746 disco board

2018-03-02 Thread yannick fertre

Enable the display controller , panel & backlight.
Set panel display timings & set the RGB data bus.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f746-disco.dts | 70 
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 9e8d2a0..e47f762 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -89,6 +89,37 @@
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
};
+
+   backlight: backlight {
+   compatible = "gpio-backlight";
+   gpios = <&gpiok 3 0>;
+   status = "okay";
+   };
+
+   panel-rgb@0 {
+   compatible = "simple-panel";
+   backlight = <&backlight>;
+   enable-gpios = <&gpioi 12 0>;
+   status = "okay";
+
+   display-timings {
+   timing@0 {
+   clock-frequency = <900>;
+   hactive = <480>;
+   vactive = <272>;
+   hfront-porch = <2>;
+   hback-porch = <2>;
+   hsync-len = <41>;
+   vfront-porch = <2>;
+   vback-porch = <2>;
+   vsync-len = <10>;
+   hsync-active = <0>;
+   vsync-active = <0>;
+   de-active = <0>;
+   pixelclk-active = <1>;
+   };
+   };
+   };
 };
 
 &clk_hse {
@@ -183,6 +214,40 @@
  slew-rate = <2>;
};
};
+
+   ltdc_pins: ltdc@0 {
+   pins {
+   pinmux = ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ;
+   slew-rate = <2>;
+   };
+   };
 };
 
 &usart1 {
@@ -250,3 +315,8 @@
bus-width = <4>;
max-frequency = <2500>;
 };
+
+<dc {
+   status = "okay";
+   pinctrl-0 = <<dc_pins>;
+};
-- 
1.9.1

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[U-Boot] [PATCH v2 6/9] arm: dts: stm32: add ltdc for STM32F746

2018-03-02 Thread yannick fertre

From: Philippe CORNU 

Add display controller node in device-tree.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f746.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 46d148e..e4d32bf 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -323,6 +323,15 @@
pinctrl-names = "default", "opendrain";
max-frequency = <4800>;
};
+
+   ltdc: display-controller@40016800 {
+   compatible = "st,stm32-ltdc";
+   reg = <0x40016800 0x200>;
+   resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+   clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+   u-boot,dm-pre-reloc;
+   status = "disabled";
+   };
};
 };
 
-- 
1.9.1

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[U-Boot] [PATCH v2 9/9] board: Add display to STM32F746 SoC discovery board

2018-03-02 Thread yannick fertre

Signed-off-by: yannick fertre 
---
 configs/stm32f746-disco_defconfig | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/configs/stm32f746-disco_defconfig 
b/configs/stm32f746-disco_defconfig
index f8fa198..0bc9c01 100644
--- a/configs/stm32f746-disco_defconfig
+++ b/configs/stm32f746-disco_defconfig
@@ -28,6 +28,7 @@ CONFIG_CMD_PING=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_DNS=y
 CONFIG_CMD_LINK_LOCAL=y
+CONFIG_CMD_BMP=y
 CONFIG_CMD_TIMER=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_EXT4=y
@@ -52,5 +53,10 @@ CONFIG_ETH_DESIGNWARE=y
 # CONFIG_PINCTRL_FULL is not set
 CONFIG_DM_SPI=y
 CONFIG_STM32_QSPI=y
+CONFIG_DM_VIDEO=y
+CONFIG_BACKLIGHT_GPIO=y
+CONFIG_VIDEO_STM32=y
+CONFIG_VIDEO_STM32_MAX_XRES=480
+CONFIG_VIDEO_STM32_MAX_YRES=640
 CONFIG_OF_LIBFDT_OVERLAY=y
 # CONFIG_EFI_LOADER is not set
-- 
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[U-Boot] [PATCH v2 5/9] video: stm32: stm32_ltdc: set the blending factor

2018-03-02 Thread yannick fertre

Set the blending factor regarding the pixel format

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 41 ++--
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 6c3557b..e160c77 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -138,7 +138,9 @@ struct stm32_ltdc_priv {
 #define LXCFBLNR_CFBLN GENMASK(10, 0)  /* Color Frame Buffer Line Number */
 
 #define BF1_PAXCA  0x600   /* Pixel Alpha x Constant Alpha */
+#define BF1_CA 0x400   /* Constant Alpha */
 #define BF2_1PAXCA 0x007   /* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA0x005   /* 1 - Constant Alpha */
 
 enum stm32_ltdc_pix_fmt {
PF_ARGB = 0,
@@ -161,11 +163,17 @@ static u32 stm32_ltdc_get_pixel_format(enum 
video_log2_bpp l2bpp)
pf = PF_RGB565;
break;
 
+   case VIDEO_BPP32:
+   pf = PF_ARGB;
+   break;
+
+   case VIDEO_BPP8:
+   pf = PF_L8;
+   break;
+
case VIDEO_BPP1:
case VIDEO_BPP2:
case VIDEO_BPP4:
-   case VIDEO_BPP8:
-   case VIDEO_BPP32:
default:
debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
  __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
@@ -178,6 +186,23 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp 
l2bpp)
return (u32)pf;
 }
 
+static bool has_alpha(u32 fmt)
+{
+   switch (fmt) {
+   case PF_ARGB:
+   case PF_ARGB1555:
+   case PF_ARGB:
+   case PF_AL44:
+   case PF_AL88:
+   return true;
+   case PF_RGB888:
+   case PF_RGB565:
+   case PF_L8:
+   default:
+   return false;
+   }
+}
+
 static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
 {
/* Reload configuration immediately & enable LTDC */
@@ -247,6 +272,7 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv 
*priv, ulong fb_addr)
u32 line_length;
u32 bus_width;
u32 val, tmp, bpp;
+   u32 format;
 
x0 = priv->crop_x;
x1 = priv->crop_x + priv->crop_w - 1;
@@ -277,15 +303,18 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv 
*priv, ulong fb_addr)
clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
 
/* Pixel format */
-   val = stm32_ltdc_get_pixel_format(priv->l2bpp);
-   clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
+   format = stm32_ltdc_get_pixel_format(priv->l2bpp);
+   clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
 
/* Constant alpha value */
clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
 
+   /* Specifies the blending factors : with or without pixel alpha */
+   /* Manage hw-specific capabilities */
+   val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
+
/* Blending factors */
-   clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
-   BF1_PAXCA | BF2_1PAXCA);
+   clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
 
/* Frame buffer line number */
clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
-- 
1.9.1

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[U-Boot] [PATCH v2 1/9] video: stm32: stm32_ltdc: add reset

2018-03-02 Thread yannick fertre

Add reset of LTDC display controller.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index b417ac2..d8784f1 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -302,6 +303,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
struct udevice *panel;
struct clk pclk, pxclk;
+   struct reset_ctl rst;
int ret;
 
priv->regs = (void *)dev_read_addr(dev);
@@ -316,6 +318,15 @@ static int stm32_ltdc_probe(struct udevice *dev)
return ret;
}
 
+   ret = reset_get_by_index(dev, 0, &rst);
+   if (ret) {
+   debug("%s: missing ltdc hardware reset\n", __func__);
+   return -ENODEV;
+   }
+
+   /* Reset */
+   reset_deassert(&rst);
+
ret = panel_enable_backlight(panel);
if (ret) {
debug("%s: panel %s enable backlight error %d\n",
-- 
1.9.1

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[U-Boot] [PATCH v2 4/9] video: stm32: stm32_ltdc: missing set of line interrupt position

2018-03-02 Thread yannick fertre

Set LIPCR (line interrupt position conf) register with line length.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 08e0afc..6c3557b 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -219,6 +219,8 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv)
val = (total_w << 16) | total_h;
clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 
+   setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
+
/* Signal polarities */
val = 0;
debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
-- 
1.9.1

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[U-Boot] [PATCH v2 0/9] splash screen on the stm32f746 disco board

2018-03-02 Thread yannick fertre

Version 2:
- Add patch to display bitmap stmicroelectronics_uboot_logo_8bit_rle
- Add patch to defconfig to add splash screen
- Rename panel in dts.

Version 1:
- Initial commit

This serie contains all patchsets needed for displaying a splash screen 
on the stm32f746 disco board & some display features (reset, blending & line
interrupt position).

Philippe CORNU (1):
  arm: dts: stm32: add ltdc for STM32F746

yannick fertre (8):
  video: stm32: stm32_ltdc: add reset
  video: stm32: stm32_ltdc: update file header & footer
  video: stm32: stm32_ltdc: set rate of the pixel clock
  video: stm32: stm32_ltdc: missing set of line interrupt position
  video: stm32: stm32_ltdc: set the blending factor
  arm: dts: stm32: add display for STM32F746 disco board
  stm32f7: board: add splash screen
  board: Add display to STM32F746 SoC discovery board

 arch/arm/dts/stm32f746-disco.dts   |   70 +
 arch/arm/dts/stm32f746.dtsi|9 +
 board/st/stm32f746-disco/stm32f746-disco.c |9 +
 configs/stm32f746-disco_defconfig  |6 +
 drivers/video/stm32/stm32_ltdc.c   |  117 +-
 include/configs/stm32f746-disco.h  |   10 +
 include/st_logo_data.h | 3267 
 7 files changed, 3453 insertions(+), 35 deletions(-)
 create mode 100644 include/st_logo_data.h

-- 
1.9.1

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[U-Boot] [PATCH v2 3/9] video: stm32: stm32_ltdc: set rate of the pixel clock

2018-03-02 Thread yannick fertre

pxclk is useless to set pixel clock.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 52 ++--
 1 file changed, 29 insertions(+), 23 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 8d89b58..08e0afc 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -301,9 +301,9 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
struct udevice *panel;
-   struct clk pclk, pxclk;
+   struct clk pclk;
struct reset_ctl rst;
-   int ret;
+   int rate, ret;
 
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
@@ -311,9 +311,16 @@ static int stm32_ltdc_probe(struct udevice *dev)
return -EINVAL;
}
 
-   ret = uclass_first_device(UCLASS_PANEL, &panel);
+   ret = clk_get_by_index(dev, 0, &pclk);
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
+   debug("%s: peripheral clock get error %d\n", __func__, ret);
+   return ret;
+   }
+
+   ret = clk_enable(&pclk);
+   if (ret) {
+   debug("%s: peripheral clock enable error %d\n",
+ __func__, ret);
return ret;
}
 
@@ -326,6 +333,12 @@ static int stm32_ltdc_probe(struct udevice *dev)
/* Reset */
reset_deassert(&rst);
 
+   ret = uclass_first_device(UCLASS_PANEL, &panel);
+   if (ret) {
+   debug("%s: panel device error %d\n", __func__, ret);
+   return ret;
+   }
+
ret = panel_enable_backlight(panel);
if (ret) {
debug("%s: panel %s enable backlight error %d\n",
@@ -333,31 +346,24 @@ static int stm32_ltdc_probe(struct udevice *dev)
return ret;
}
 
-   ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
-  0, &priv->timing);
+   ret = fdtdec_decode_display_timing(gd->fdt_blob,
+  dev_of_offset(dev), 0,
+  &priv->timing);
if (ret) {
-   debug("%s: decode display timing error %d\n", __func__, ret);
+   debug("%s: decode display timing error %d\n",
+ __func__, ret);
return -EINVAL;
}
 
-   ret = clk_get_by_name(dev, "pclk", &pclk);
-   if (ret) {
-   debug("%s: peripheral clock get error %d\n", __func__, ret);
-   return ret;
+   rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ);
+   if (rate < 0) {
+   debug("%s: fail to set pixel clock %d hz %d hz\n",
+ __func__, priv->timing.pixelclock.typ, rate);
+   return rate;
}
 
-   ret = clk_enable(&pclk);
-   if (ret) {
-   debug("%s: peripheral clock enable error %d\n", __func__, ret);
-   return ret;
-   }
-
-   /* Verify pixel clock value if any & inform user accordingly */
-   ret = clk_get_by_name(dev, "pxclk", &pxclk);
-   if (!ret) {
-   if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ)
-   printf("Warning: please adjust ltdc pixel clock\n");
-   }
+   debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
+ priv->timing.pixelclock.typ, rate);
 
/* TODO Below parameters are hard-coded for the moment... */
priv->l2bpp = VIDEO_BPP16;
-- 
1.9.1

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[U-Boot] [PATCH v2 2/9] video: stm32: stm32_ltdc: update file header & footer

2018-03-02 Thread yannick fertre

Modified copyright & driver name.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index d8784f1..8d89b58 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -1,8 +1,7 @@
 /*
- * Copyright (C) STMicroelectronics SA 2017
- *
- * Authors: Philippe Cornu 
- *  Yannick Fertre 
+ * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -408,10 +407,10 @@ static const struct udevice_id stm32_ltdc_ids[] = {
 };
 
 U_BOOT_DRIVER(stm32_ltdc) = {
-   .name   = "stm32_ltdc",
-   .id = UCLASS_VIDEO,
-   .of_match = stm32_ltdc_ids,
-   .probe  = stm32_ltdc_probe,
-   .bind   = stm32_ltdc_bind,
+   .name   = "stm32_display",
+   .id = UCLASS_VIDEO,
+   .of_match   = stm32_ltdc_ids,
+   .probe  = stm32_ltdc_probe,
+   .bind   = stm32_ltdc_bind,
.priv_auto_alloc_size   = sizeof(struct stm32_ltdc_priv),
 };
-- 
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[U-Boot] [PATCH v1 5/7] video: add support of STM32 MIPI DSI controller driver

2018-02-13 Thread yannick fertre

Add the STM32 DSI controller driver that uses the Synopsys DesignWare
MIPI DSI host controller bridge.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/Kconfig |  10 +
 drivers/video/stm32/Makefile|   1 +
 drivers/video/stm32/stm32_dsi.c | 429 
 3 files changed, 440 insertions(+)
 create mode 100644 drivers/video/stm32/stm32_dsi.c

diff --git a/drivers/video/stm32/Kconfig b/drivers/video/stm32/Kconfig
index 113a2bb..2ea6f18 100644
--- a/drivers/video/stm32/Kconfig
+++ b/drivers/video/stm32/Kconfig
@@ -15,6 +15,16 @@ menuconfig VIDEO_STM32
  DSI. This option enables these supports which can be used on
  devices which have RGB TFT or DSI display connected.
 
+config VIDEO_STM32_DSI
+   bool "Enable STM32 DSI video support"
+   depends on VIDEO_STM32
+   select VIDEO_MIPI_DSI
+   select VIDEO_BRIDGE
+   select VIDEO_DW_MIPI_DSI
+   help
+ This option enables support DSI internal bridge which can be used on
+ devices which have DSI display connected.
+
 config VIDEO_STM32_MAX_XRES
int "Maximum horizontal resolution (for memory allocation purposes)"
depends on VIDEO_STM32
diff --git a/drivers/video/stm32/Makefile b/drivers/video/stm32/Makefile
index 372a2e1..f8c3ff7 100644
--- a/drivers/video/stm32/Makefile
+++ b/drivers/video/stm32/Makefile
@@ -8,3 +8,4 @@
 #
 
 obj-${CONFIG_VIDEO_STM32} = stm32_ltdc.o
+obj-${CONFIG_VIDEO_STM32_DSI} += stm32_dsi.o
diff --git a/drivers/video/stm32/stm32_dsi.c b/drivers/video/stm32/stm32_dsi.c
new file mode 100644
index 000..af45ba4
--- /dev/null
+++ b/drivers/video/stm32/stm32_dsi.c
@@ -0,0 +1,429 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * This driver is based on the mipi dsi driver from
+ * drivers/gpu/drm/stm/dw_mipi_dsi-stm.c (kernel linux).
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define HWVER_130  0x31333000  /* IP version 1.30 */
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+/* DSI digital registers & bit definitions */
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+/* DSI wrapper registers & bit definitions */
+/* Note: registers are named as in the Reference Manual */
+#define DSI_WCFGR  0x0400  /* Wrapper ConFiGuration Reg */
+#define WCFGR_DSIM BIT(0)  /* DSI Mode */
+#define WCFGR_COLMUX   GENMASK(3, 1)   /* COLor MUltipleXing */
+
+#define DSI_WCR0x0404  /* Wrapper Control Reg */
+#define WCR_DSIEN  BIT(3)  /* DSI ENable */
+
+#define DSI_WISR   0x040C  /* Wrapper Interrupt and Status Reg */
+#define WISR_PLLLS BIT(8)  /* PLL Lock Status */
+#define WISR_RRS   BIT(12) /* Regulator Ready Status */
+
+#define DSI_WPCR0  0x0418  /* Wrapper Phy Conf Reg 0 */
+#define WPCR0_UIX4 GENMASK(5, 0)   /* Unit Interval X 4 */
+#define WPCR0_TDDL BIT(16) /* Turn Disable Data Lanes */
+
+#define DSI_WRPCR  0x0430  /* Wrapper Regulator & Pll Ctrl Reg */
+#define WRPCR_PLLENBIT(0)  /* PLL ENable */
+#define WRPCR_NDIV GENMASK(8, 2)   /* pll loop DIVision Factor */
+#define WRPCR_IDF  GENMASK(14, 11) /* pll Input Division Factor */
+#define WRPCR_ODF  GENMASK(17, 16) /* pll Output Division Factor */
+#define WRPCR_REGENBIT(24) /* REGulator ENable */
+#define WRPCR_BGRENBIT(28) /* BandGap Reference ENable */
+#define IDF_MIN1
+#define IDF_MAX7
+#define NDIV_MIN   10
+#define NDIV_MAX   125
+#define ODF_MIN1
+#define ODF_MAX8
+
+/* dsi color format coding according to the datasheet */
+enum dsi_color {
+   DSI_RGB565_CONF1,
+   DSI_RGB565_CONF2,
+   DSI_RGB565_CONF3,
+   DSI_RGB666_CONF1,
+   DSI_RGB666_CONF2,
+   DSI_RGB888,
+};
+
+#define LANE_MIN_KBPS  31250
+#define LANE_MAX_KBPS  50
+
+/* Timeout for regulator on/off, pll lock/unlock & fifo empty */
+#define TIMEOUT_US 20
+
+struct stm32_dsi_priv {
+   struct mipi_dsi_device device;
+   void __iomem *base;
+   struct udevice *panel;
+   u32 pllref_clk;
+   u32 hw_version;
+   int lane_min_kbps;
+   int lane_max_kbps;
+};
+
+static inline void dsi_write(struct stm32_dsi_priv *dsi, u32 reg, u32 val)
+{
+   writel(val, dsi->base + reg);
+}
+
+static inline u32 dsi_read(struct stm32_dsi_priv *dsi, u32 reg)
+{
+   return readl(dsi->base + reg);
+}
+
+static inline void dsi_set(str

[U-Boot] [PATCH v1 4/7] video: add MIPI DSI host controller bridge

2018-02-13 Thread yannick fertre

Add a Synopsys Designware MIPI DSI host bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig   |   9 +
 drivers/video/Makefile  |   1 +
 drivers/video/dw_mipi_dsi.c | 822 
 include/dw_mipi_dsi.h   |  32 ++
 4 files changed, 864 insertions(+)
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2ce49bc..fa248fc 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -656,6 +656,15 @@ config VIDEO_DW_HDMI
  rather requires a SoC-specific glue driver to call it), it
  can not be enabled from the configuration menu.
 
+config VIDEO_DW_MIPI_DSI
+   bool
+   help
+ Enables the common driver code for the Designware MIPI DSI
+ block found in SoCs from various vendors.
+ As this does not provide any functionality by itself (but
+ rather requires a SoC-specific glue driver to call it), it
+ can not be enabled from the configuration menu.
+
 config VIDEO_SIMPLE
bool "Simple display driver for preconfigured display"
help
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 0590759..b266dfd 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -54,6 +54,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-$(CONFIG_VIDEO_DW_MIPI_DSI) += dw_mipi_dsi.o
 obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
new file mode 100644
index 000..d316c1b
--- /dev/null
+++ b/drivers/video/dw_mipi_dsi.c
@@ -0,0 +1,822 @@
+/*
+ * Copyright (C) 2016, Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * Modified by Yannick Fertre 
+ * This generic Synopsys DesignWare MIPI DSI host driver is based on the
+ * bridge synopsys from drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c (kernel
+ * linux).
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define HWVER_131  0x31333100  /* IP version 1.31 */
+
+#define DSI_VERSION0x00
+#define VERSIONGENMASK(31, 8)
+
+#define DSI_PWR_UP 0x04
+#define RESET  0
+#define POWERUPBIT(0)
+
+#define DSI_CLKMGR_CFG 0x08
+#define TO_CLK_DIVISION(div)   (((div) & 0xff) << 8)
+#define TX_ESC_CLK_DIVISION(div)   ((div) & 0xff)
+
+#define DSI_DPI_VCID   0x0c
+#define DPI_VCID(vcid) ((vcid) & 0x3)
+
+#define DSI_DPI_COLOR_CODING   0x10
+#define LOOSELY18_EN   BIT(8)
+#define DPI_COLOR_CODING_16BIT_1   0x0
+#define DPI_COLOR_CODING_16BIT_2   0x1
+#define DPI_COLOR_CODING_16BIT_3   0x2
+#define DPI_COLOR_CODING_18BIT_1   0x3
+#define DPI_COLOR_CODING_18BIT_2   0x4
+#define DPI_COLOR_CODING_24BIT 0x5
+
+#define DSI_DPI_CFG_POL0x14
+#define COLORM_ACTIVE_LOW  BIT(4)
+#define SHUTD_ACTIVE_LOW   BIT(3)
+#define HSYNC_ACTIVE_LOW   BIT(2)
+#define VSYNC_ACTIVE_LOW   BIT(1)
+#define DATAEN_ACTIVE_LOW  BIT(0)
+
+#define DSI_DPI_LP_CMD_TIM 0x18
+#define OUTVACT_LPCMD_TIME(p)  (((p) & 0xff) << 16)
+#define INVACT_LPCMD_TIME(p)   ((p) & 0xff)
+
+#define DSI_DBI_VCID   0x1c
+#define DSI_DBI_CFG0x20
+#define DSI_DBI_PARTITIONING_EN0x24
+#define DSI_DBI_CMDSIZE0x28
+
+#define DSI_PCKHDL_CFG 0x2c
+#define CRC_RX_EN  BIT(4)
+#define ECC_RX_EN  BIT(3)
+#define BTA_EN BIT(2)
+#define EOTP_RX_EN BIT(1)
+#define EOTP_TX_EN BIT(0)
+
+#define DSI_GEN_VCID   0x30
+
+#define DSI_MODE_CFG   0x34
+#define ENABLE_VIDEO_MODE  0
+#define ENABLE_CMD_MODEBIT(0)
+
+#define DSI_VID_MODE_CFG   0x38
+#define ENABLE_LOW_POWER   (0x3f << 8)
+#define ENABLE_LOW_POWER_MASK  (0x3f << 8)
+#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES0x0
+#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS0x1
+#define VID_MODE_TYPE_BURST0x2
+#de

[U-Boot] [PATCH v1 4/7] video: stm32: stm32_ltdc: missing set of line interrupt position

2018-02-13 Thread yannick fertre

Set LIPCR (line interrupt position conf) register with line length.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 08e0afc..6c3557b 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -219,6 +219,8 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv)
val = (total_w << 16) | total_h;
clrsetbits_le32(regs + LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
 
+   setbits_le32(regs + LTDC_LIPCR, acc_act_h + 1);
+
/* Signal polarities */
val = 0;
debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
-- 
1.9.1

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[U-Boot] [PATCH v1 6/7] arm: dts: stm32: add dsi for STM32F746

2018-02-13 Thread yannick fertre

Add mipi dsi bridge node in device-tree.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f746.dtsi | 12 
 1 file changed, 12 insertions(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index e4d32bf..4ec954d 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -332,6 +332,18 @@
u-boot,dm-pre-reloc;
status = "disabled";
};
+
+   dsi: dsi@40016c00 {
+   compatible = "st,stm32-dsi";
+   reg = <0x40016C00 0x800>;
+   resets = <&rcc STM32F7_APB2_RESET(DSI)>;
+   clocks =  <&rcc 0 STM32F7_APB2_CLOCK(DSI)>,
+ <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>,
+ <&clk_hse>;
+   clock-names = "pclk", "px_clk", "ref";
+   u-boot,dm-pre-reloc;
+   status = "disabled";
+   };
};
 };
 
-- 
1.9.1

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[U-Boot] [PATCH v1 6/7] arm: dts: stm32: add ltdc for STM32F746

2018-02-13 Thread yannick fertre

From: Philippe CORNU 

Add display controller node in device-tree.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f746.dtsi | 9 +
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index 46d148e..e4d32bf 100644
--- a/arch/arm/dts/stm32f746.dtsi
+++ b/arch/arm/dts/stm32f746.dtsi
@@ -323,6 +323,15 @@
pinctrl-names = "default", "opendrain";
max-frequency = <4800>;
};
+
+   ltdc: display-controller@40016800 {
+   compatible = "st,stm32-ltdc";
+   reg = <0x40016800 0x200>;
+   resets = <&rcc STM32F7_APB2_RESET(LTDC)>;
+   clocks = <&rcc 0 STM32F7_APB2_CLOCK(LTDC)>;
+   u-boot,dm-pre-reloc;
+   status = "disabled";
+   };
};
 };
 
-- 
1.9.1

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[U-Boot] [PATCH v1 0/7] splash screen on the stm32f769 disco board

2018-02-13 Thread yannick fertre

This serie contains all patchsets needed for displaying a splash screen 
on the stm32f769 disco board.

yannick fertre (7):
  video: stm32: stm32_ltdc: add bridge to display controller
  video: add support of MIPI DSI interface
  video: add support of panel OTM8009A
  video: add MIPI DSI host controller bridge
  video: add support of STM32 MIPI DSI controller driver
  arm: dts: stm32: add dsi for STM32F746
  arm: dts: stm32: add display for STM32F769 disco board

 arch/arm/dts/stm32f746.dtsi|  12 +
 arch/arm/dts/stm32f769-disco.dts   |  59 +++
 drivers/video/Kconfig  |  23 ++
 drivers/video/Makefile |   4 +
 drivers/video/dw_mipi_dsi.c| 822 +
 drivers/video/mipi_display.c   | 809 
 drivers/video/orisetech_otm8009a.c | 316 ++
 drivers/video/stm32/Kconfig|  10 +
 drivers/video/stm32/Makefile   |   1 +
 drivers/video/stm32/stm32_dsi.c| 429 +++
 drivers/video/stm32/stm32_ltdc.c   | 107 +++--
 include/dw_mipi_dsi.h  |  32 ++
 include/mipi_display.h | 257 +++-
 13 files changed, 2844 insertions(+), 37 deletions(-)
 create mode 100644 drivers/video/dw_mipi_dsi.c
 create mode 100644 drivers/video/mipi_display.c
 create mode 100644 drivers/video/orisetech_otm8009a.c
 create mode 100644 drivers/video/stm32/stm32_dsi.c
 create mode 100644 include/dw_mipi_dsi.h

-- 
1.9.1
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[U-Boot] [PATCH v1 7/7] arm: dts: stm32: add display for STM32F769 disco board

2018-02-13 Thread yannick fertre

Enable the display controller, mipi dsi bridge & panel.
Set panel display timings.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f769-disco.dts | 59 
 1 file changed, 59 insertions(+)

diff --git a/arch/arm/dts/stm32f769-disco.dts b/arch/arm/dts/stm32f769-disco.dts
index 59c9d31..79c18e0 100644
--- a/arch/arm/dts/stm32f769-disco.dts
+++ b/arch/arm/dts/stm32f769-disco.dts
@@ -84,6 +84,36 @@
compatible = "st,button1";
button-gpio = <&gpioa 0 0>;
};
+
+   panel: panel {
+   compatible = "orisetech,otm8009a";
+   enable-gpios = <&gpioj 15 1>;
+   status = "okay";
+
+   port {
+   panel_in: endpoint {
+   remote-endpoint = <&dsi_out>;
+   };
+   };
+
+   display-timings {
+   timing@0 {
+   clock-frequency = <32729000>;
+   hactive = <480>;
+   hfront-porch = <120>;
+   hback-porch = <63>;
+   hsync-len = <120>;
+   vactive = <800>;
+   vfront-porch = <12>;
+   vback-porch = <12>;
+   vsync-len = <12>;
+   hsync-active = <0>;
+   vsync-active = <0>;
+   de-active = <0>;
+   pixelclk-active = <1>;
+   };
+   };
+   };
 };
 
 &clk_hse {
@@ -264,3 +294,32 @@
bus-width = <4>;
max-frequency = <2500>;
 };
+
+<dc {
+   status = "okay";
+
+   ports {
+   port@0 {
+   dp_out: endpoint {
+   remote-endpoint = <&dsi_in>;
+   };
+   };
+   };
+};
+
+&dsi {
+   status = "okay";
+
+   ports {
+   port@0 {
+   dsi_out: endpoint {
+   remote-endpoint = <&panel_in>;
+   };
+   };
+   port@1 {
+   dsi_in: endpoint {
+   remote-endpoint = <&dp_out>;
+   };
+   };
+   };
+};
-- 
1.9.1

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[U-Boot] [PATCH v1 2/7] video: add support of MIPI DSI interface

2018-02-13 Thread yannick fertre

Mipi_display.c contains a set of dsi helpers.
This file is a copy of file drm_mipi_dsi.c (linux kernel).

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig|   7 +
 drivers/video/Makefile   |   2 +
 drivers/video/mipi_display.c | 809 +++
 include/mipi_display.h   | 257 +-
 4 files changed, 1074 insertions(+), 1 deletion(-)
 create mode 100644 drivers/video/mipi_display.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 2fc0def..1981298 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -75,6 +75,13 @@ config VIDEO_ANSI
  Enable ANSI escape sequence decoding for a more fully functional
  console.
 
+config VIDEO_MIPI_DSI
+   bool "Support MIPI DSI interface"
+   depends on DM_VIDEO
+   default y if DM_VIDEO
+   help
+ Support MIPI DSI interface for driving a MIPI compatible LCD panel.
+
 config CONSOLE_NORMAL
bool "Support a simple text console"
depends on DM_VIDEO
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index dfafe08..a6f927f 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -1,3 +1,4 @@
+
 #
 # (C) Copyright 2000-2007
 # Wolfgang Denk, DENX Software Engineering, w...@denx.de.
@@ -52,6 +53,7 @@ obj-$(CONFIG_FORMIKE) += formike.o
 obj-$(CONFIG_LG4573) += lg4573.o
 obj-$(CONFIG_AM335X_LCD) += am335x-fb.o
 obj-$(CONFIG_VIDEO_DW_HDMI) += dw_hdmi.o
+obj-${CONFIG_VIDEO_MIPI_DSI} += mipi_display.o
 obj-$(CONFIG_VIDEO_SIMPLE) += simplefb.o
 obj-${CONFIG_VIDEO_TEGRA124} += tegra124/
 obj-${CONFIG_EXYNOS_FB} += exynos/
diff --git a/drivers/video/mipi_display.c b/drivers/video/mipi_display.c
new file mode 100644
index 000..ffd4bd7
--- /dev/null
+++ b/drivers/video/mipi_display.c
@@ -0,0 +1,809 @@
+/*
+ * MIPI DSI Bus
+ *
+ * Copyright (C) 2012-2013, Samsung Electronics, Co., Ltd.
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Andrzej Hajda 
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+ * DOC: dsi helpers
+ *
+ * These functions contain some common logic and helpers to deal with MIPI DSI
+ * peripherals.
+ *
+ * Helpers are provided for a number of standard MIPI DSI command as well as a
+ * subset of the MIPI DCS command set.
+ */
+
+/**
+ * mipi_dsi_attach - attach a DSI device to its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_attach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->attach)
+   return -ENOSYS;
+
+   return ops->attach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_attach);
+
+/**
+ * mipi_dsi_detach - detach a DSI device from its DSI host
+ * @dsi: DSI peripheral
+ */
+int mipi_dsi_detach(struct mipi_dsi_device *dsi)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->detach)
+   return -ENOSYS;
+
+   return ops->detach(dsi->host, dsi);
+}
+EXPORT_SYMBOL(mipi_dsi_detach);
+
+static ssize_t mipi_dsi_device_transfer(struct mipi_dsi_device *dsi,
+   struct mipi_dsi_msg *msg)
+{
+   const struct mipi_dsi_host_ops *ops = dsi->host->ops;
+
+   if (!ops || !ops->transfer)
+   return -ENOSYS;
+
+   if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
+   msg->flags |= MIPI_DSI_MSG_USE_LPM;
+
+   return ops->transfer(dsi->host, msg);
+}
+
+/**
+ * mipi_dsi_packet_format_is_short - check if a packet is of the short format
+ * @type: MIPI DSI data type of the packet
+ *
+ * Return: true if the packet for the given data type is a short packet, false
+ * otherwise.
+ */
+bool mipi_dsi_packet_format_is_short(u8 type)

[U-Boot] [PATCH v1 3/7] video: stm32: stm32_ltdc: set rate of the pixel clock

2018-02-13 Thread yannick fertre

pxclk is useless to set pixel clock.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 52 ++--
 1 file changed, 29 insertions(+), 23 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 8d89b58..08e0afc 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -301,9 +301,9 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
struct udevice *panel;
-   struct clk pclk, pxclk;
+   struct clk pclk;
struct reset_ctl rst;
-   int ret;
+   int rate, ret;
 
priv->regs = (void *)dev_read_addr(dev);
if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
@@ -311,9 +311,16 @@ static int stm32_ltdc_probe(struct udevice *dev)
return -EINVAL;
}
 
-   ret = uclass_first_device(UCLASS_PANEL, &panel);
+   ret = clk_get_by_index(dev, 0, &pclk);
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
+   debug("%s: peripheral clock get error %d\n", __func__, ret);
+   return ret;
+   }
+
+   ret = clk_enable(&pclk);
+   if (ret) {
+   debug("%s: peripheral clock enable error %d\n",
+ __func__, ret);
return ret;
}
 
@@ -326,6 +333,12 @@ static int stm32_ltdc_probe(struct udevice *dev)
/* Reset */
reset_deassert(&rst);
 
+   ret = uclass_first_device(UCLASS_PANEL, &panel);
+   if (ret) {
+   debug("%s: panel device error %d\n", __func__, ret);
+   return ret;
+   }
+
ret = panel_enable_backlight(panel);
if (ret) {
debug("%s: panel %s enable backlight error %d\n",
@@ -333,31 +346,24 @@ static int stm32_ltdc_probe(struct udevice *dev)
return ret;
}
 
-   ret = fdtdec_decode_display_timing(gd->fdt_blob, dev_of_offset(dev),
-  0, &priv->timing);
+   ret = fdtdec_decode_display_timing(gd->fdt_blob,
+  dev_of_offset(dev), 0,
+  &priv->timing);
if (ret) {
-   debug("%s: decode display timing error %d\n", __func__, ret);
+   debug("%s: decode display timing error %d\n",
+ __func__, ret);
return -EINVAL;
}
 
-   ret = clk_get_by_name(dev, "pclk", &pclk);
-   if (ret) {
-   debug("%s: peripheral clock get error %d\n", __func__, ret);
-   return ret;
+   rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ);
+   if (rate < 0) {
+   debug("%s: fail to set pixel clock %d hz %d hz\n",
+ __func__, priv->timing.pixelclock.typ, rate);
+   return rate;
}
 
-   ret = clk_enable(&pclk);
-   if (ret) {
-   debug("%s: peripheral clock enable error %d\n", __func__, ret);
-   return ret;
-   }
-
-   /* Verify pixel clock value if any & inform user accordingly */
-   ret = clk_get_by_name(dev, "pxclk", &pxclk);
-   if (!ret) {
-   if (clk_get_rate(&pxclk) != priv->timing.pixelclock.typ)
-   printf("Warning: please adjust ltdc pixel clock\n");
-   }
+   debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
+ priv->timing.pixelclock.typ, rate);
 
/* TODO Below parameters are hard-coded for the moment... */
priv->l2bpp = VIDEO_BPP16;
-- 
1.9.1

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[U-Boot] [PATCH v1 3/7] video: add support of panel OTM8009A

2018-02-13 Thread yannick fertre

Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.

Signed-off-by: yannick fertre 
---
 drivers/video/Kconfig  |   7 +
 drivers/video/Makefile |   1 +
 drivers/video/orisetech_otm8009a.c | 316 +
 3 files changed, 324 insertions(+)
 create mode 100644 drivers/video/orisetech_otm8009a.c

diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 1981298..2ce49bc 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -320,6 +320,13 @@ config VIDEO_LCD_ANX9804
from a parallel LCD interface and translate it on the fy into a DP
interface for driving eDP TFT displays. It uses I2C for configuration.
 
+config VIDEO_LCD_ORISETECH_OTM8009A
+   bool "OTM8009A DSI LCD panel support"
+   depends on VIDEO_MIPI_DSI
+   default n
+   ---help---
+   Support for Orise Tech otm8009a 480p dsi 2dl video mode panel.
+
 config VIDEO_LCD_SSD2828
bool "SSD2828 bridge chip"
default n
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index a6f927f..0590759 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -38,6 +38,7 @@ obj-$(CONFIG_VIDEO_COREBOOT) += coreboot.o
 obj-$(CONFIG_VIDEO_DA8XX) += da8xx-fb.o videomodes.o
 obj-$(CONFIG_VIDEO_LCD_ANX9804) += anx9804.o
 obj-$(CONFIG_VIDEO_LCD_HITACHI_TX18D42VM) += hitachi_tx18d42vm_lcd.o
+obj-$(CONFIG_VIDEO_LCD_ORISETECH_OTM8009A) += orisetech_otm8009a.o
 obj-$(CONFIG_VIDEO_LCD_SSD2828) += ssd2828.o
 obj-$(CONFIG_VIDEO_MB862xx) += mb862xx.o videomodes.o
 obj-$(CONFIG_VIDEO_MX3) += mx3fb.o videomodes.o
diff --git a/drivers/video/orisetech_otm8009a.c 
b/drivers/video/orisetech_otm8009a.c
new file mode 100644
index 000..b75e03f
--- /dev/null
+++ b/drivers/video/orisetech_otm8009a.c
@@ -0,0 +1,316 @@
+/*
+ * Copyright (C) 2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
+ *
+ * This otm8009a panel driver is based on the panel driver from
+ * drivers/gpu/drm/panel/panel-orisetech-otm8009a.c (kernel linux)
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define DRV_NAME "orisetech_otm8009a"
+
+#define OTM8009A_BACKLIGHT_DEFAULT 240
+#define OTM8009A_BACKLIGHT_MAX 255
+
+/* Manufacturer Command Set */
+#define MCS_ADRSFT 0x  /* Address Shift Function */
+#define MCS_PANSET 0xB3A6  /* Panel Type Setting */
+#define MCS_SD_CTRL0xC0A2  /* Source Driver Timing Setting */
+#define MCS_P_DRV_M0xC0B4  /* Panel Driving Mode */
+#define MCS_OSC_ADJ0xC181  /* Oscillator Adjustment for Idle/Normal mode */
+#define MCS_RGB_VID_SET0xC1A1  /* RGB Video Mode Setting */
+#define MCS_SD_PCH_CTRL0xC480  /* Source Driver Precharge Control */
+#define MCS_NO_DOC10xC48A  /* Command not documented */
+#define MCS_PWR_CTRL1  0xC580  /* Power Control Setting 1 */
+#define MCS_PWR_CTRL2  0xC590  /* Power Control Setting 2 for Normal Mode */
+#define MCS_PWR_CTRL4  0xC5B0  /* Power Control Setting 4 for DC Voltage */
+#define MCS_PANCTRLSET10xCB80  /* Panel Control Setting 1 */
+#define MCS_PANCTRLSET20xCB90  /* Panel Control Setting 2 */
+#define MCS_PANCTRLSET30xCBA0  /* Panel Control Setting 3 */
+#define MCS_PANCTRLSET40xCBB0  /* Panel Control Setting 4 */
+#define MCS_PANCTRLSET50xCBC0  /* Panel Control Setting 5 */
+#define MCS_PANCTRLSET60xCBD0  /* Panel Control Setting 6 */
+#define MCS_PANCTRLSET70xCBE0  /* Panel Control Setting 7 */
+#define MCS_PANCTRLSET80xCBF0  /* Panel Control Setting 8 */
+#define MCS_PANU2D10xCC80  /* Panel U2D Setting 1 */
+#define MCS_PANU2D20xCC90  /* Panel U2D Setting 2 */
+#define MCS_PANU2D30xCCA0  /* Panel U2D Setting 3 */
+#define MCS_PAND2U10xCCB0  /* Panel D2U Setting 1 */
+#define MCS_PAND2U20xCCC0  /* Panel D2U Setting 2 */
+#define MCS_PAND2U30xCCD0  /* Panel D2U Setting 3 */
+#define MCS_GOAVST 0xCE80  /* GOA VST Setting */
+#define MCS_GOACLKA1   0xCEA0  /* GOA CLKA1 Setting */
+#define MCS_GOACLKA3   0xCEB0  /* GOA CLKA3 Setting */
+#define MCS_GOAECLK0xCFC0  /* GOA ECLK Setting */
+#define MCS_NO_DOC20xCFD0  /* Command not documented */
+#define MCS_GVDDSET0xD800  /* GVDD/NGVDD */
+#define MCS_VCOMDC 0xD900  /* VCOM Voltage Setting */
+#define MCS_GMCT2_2P   0xE100  /* Gamma Correction 2.2+ Setting */
+#define MCS_GMCT2_2N   0xE200  /* Gamma Correction 2.2- Setting */
+#define MCS_NO_DOC30xF5B6  /* Command not documented */
+#define MCS_CMD2_ENA1  0xFF00  /* Enable Access Command2 "CMD2" */
+#define MCS_CMD2_ENA2  0xFF80  /* Enable Access Orise Command2 */
+
+static ssize_t otm8009a_dcs_write_buf(struct udevice *dev, const void *data,
+ size_t len)
+{

[U-Boot] [PATCH v1 7/7] arm: dts: stm32: add display for STM32F746 disco board

2018-02-13 Thread yannick fertre

Enable the display controller , panel & backlight.
Set panel display timings & set the RGB data bus.

Signed-off-by: yannick fertre 
---
 arch/arm/dts/stm32f746-disco.dts | 70 
 1 file changed, 70 insertions(+)

diff --git a/arch/arm/dts/stm32f746-disco.dts b/arch/arm/dts/stm32f746-disco.dts
index 9e8d2a0..bbde947 100644
--- a/arch/arm/dts/stm32f746-disco.dts
+++ b/arch/arm/dts/stm32f746-disco.dts
@@ -89,6 +89,37 @@
compatible = "st,button1";
button-gpio = <&gpioi 11 0>;
};
+
+   backlight: backlight {
+   compatible = "gpio-backlight";
+   gpios = <&gpiok 3 0>;
+   status = "okay";
+   };
+
+   panel: panel {
+   compatible = "simple-panel";
+   backlight = <&backlight>;
+   enable-gpios = <&gpioi 12 0>;
+   status = "okay";
+
+   display-timings {
+   timing@0 {
+   clock-frequency = <900>;
+   hactive = <480>;
+   vactive = <272>;
+   hfront-porch = <2>;
+   hback-porch = <2>;
+   hsync-len = <41>;
+   vfront-porch = <2>;
+   vback-porch = <2>;
+   vsync-len = <10>;
+   hsync-active = <0>;
+   vsync-active = <0>;
+   de-active = <0>;
+   pixelclk-active = <1>;
+   };
+   };
+   };
 };
 
 &clk_hse {
@@ -183,6 +214,40 @@
  slew-rate = <2>;
};
};
+
+   ltdc_pins: ltdc@0 {
+   pins {
+   pinmux = ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ,
+  ;
+   slew-rate = <2>;
+   };
+   };
 };
 
 &usart1 {
@@ -250,3 +315,8 @@
bus-width = <4>;
max-frequency = <2500>;
 };
+
+<dc {
+   status = "okay";
+   pinctrl-0 = <<dc_pins>;
+};
-- 
1.9.1

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[U-Boot] [PATCH v1 5/7] video: stm32: stm32_ltdc: set the blending factor

2018-02-13 Thread yannick fertre

Set the blending factor regarding the pixel format

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 41 ++--
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index 6c3557b..e160c77 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -138,7 +138,9 @@ struct stm32_ltdc_priv {
 #define LXCFBLNR_CFBLN GENMASK(10, 0)  /* Color Frame Buffer Line Number */
 
 #define BF1_PAXCA  0x600   /* Pixel Alpha x Constant Alpha */
+#define BF1_CA 0x400   /* Constant Alpha */
 #define BF2_1PAXCA 0x007   /* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA0x005   /* 1 - Constant Alpha */
 
 enum stm32_ltdc_pix_fmt {
PF_ARGB = 0,
@@ -161,11 +163,17 @@ static u32 stm32_ltdc_get_pixel_format(enum 
video_log2_bpp l2bpp)
pf = PF_RGB565;
break;
 
+   case VIDEO_BPP32:
+   pf = PF_ARGB;
+   break;
+
+   case VIDEO_BPP8:
+   pf = PF_L8;
+   break;
+
case VIDEO_BPP1:
case VIDEO_BPP2:
case VIDEO_BPP4:
-   case VIDEO_BPP8:
-   case VIDEO_BPP32:
default:
debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
  __func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
@@ -178,6 +186,23 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp 
l2bpp)
return (u32)pf;
 }
 
+static bool has_alpha(u32 fmt)
+{
+   switch (fmt) {
+   case PF_ARGB:
+   case PF_ARGB1555:
+   case PF_ARGB:
+   case PF_AL44:
+   case PF_AL88:
+   return true;
+   case PF_RGB888:
+   case PF_RGB565:
+   case PF_L8:
+   default:
+   return false;
+   }
+}
+
 static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
 {
/* Reload configuration immediately & enable LTDC */
@@ -247,6 +272,7 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv 
*priv, ulong fb_addr)
u32 line_length;
u32 bus_width;
u32 val, tmp, bpp;
+   u32 format;
 
x0 = priv->crop_x;
x1 = priv->crop_x + priv->crop_w - 1;
@@ -277,15 +303,18 @@ static void stm32_ltdc_set_layer1(struct stm32_ltdc_priv 
*priv, ulong fb_addr)
clrsetbits_le32(regs + LTDC_L1CFBLR, LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
 
/* Pixel format */
-   val = stm32_ltdc_get_pixel_format(priv->l2bpp);
-   clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, val);
+   format = stm32_ltdc_get_pixel_format(priv->l2bpp);
+   clrsetbits_le32(regs + LTDC_L1PFCR, LXPFCR_PF, format);
 
/* Constant alpha value */
clrsetbits_le32(regs + LTDC_L1CACR, LXCACR_CONSTA, priv->alpha);
 
+   /* Specifies the blending factors : with or without pixel alpha */
+   /* Manage hw-specific capabilities */
+   val = has_alpha(format) ? BF1_PAXCA | BF2_1PAXCA : BF1_CA | BF2_1CA;
+
/* Blending factors */
-   clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1,
-   BF1_PAXCA | BF2_1PAXCA);
+   clrsetbits_le32(regs + LTDC_L1BFCR, LXBFCR_BF2 | LXBFCR_BF1, val);
 
/* Frame buffer line number */
clrsetbits_le32(regs + LTDC_L1CFBLNR, LXCFBLNR_CFBLN, priv->crop_h);
-- 
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[U-Boot] [PATCH v1 1/7] video: stm32: stm32_ltdc: add bridge to display controller

2018-02-13 Thread yannick fertre

Manage a bridge insert between the display controller & a panel.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 107 ++-
 1 file changed, 71 insertions(+), 36 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index e160c77..bd9c0de 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -8,6 +8,7 @@
 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -15,12 +16,12 @@
 #include 
 #include 
 #include 
+#include 
 
 DECLARE_GLOBAL_DATA_PTR;
 
 struct stm32_ltdc_priv {
void __iomem *regs;
-   struct display_timing timing;
enum video_log2_bpp l2bpp;
u32 bg_col_argb;
u32 crop_x, crop_y, crop_w, crop_h;
@@ -210,23 +211,23 @@ static void stm32_ltdc_enable(struct stm32_ltdc_priv 
*priv)
setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
 }
 
-static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
+static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
+   struct display_timing *timings)
 {
void __iomem *regs = priv->regs;
-   struct display_timing *timing = &priv->timing;
u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
u32 total_w, total_h;
u32 val;
 
/* Convert video timings to ltdc timings */
-   hsync = timing->hsync_len.typ - 1;
-   vsync = timing->vsync_len.typ - 1;
-   acc_hbp = hsync + timing->hback_porch.typ;
-   acc_vbp = vsync + timing->vback_porch.typ;
-   acc_act_w = acc_hbp + timing->hactive.typ;
-   acc_act_h = acc_vbp + timing->vactive.typ;
-   total_w = acc_act_w + timing->hfront_porch.typ;
-   total_h = acc_act_h + timing->vfront_porch.typ;
+   hsync = timings->hsync_len.typ - 1;
+   vsync = timings->vsync_len.typ - 1;
+   acc_hbp = hsync + timings->hback_porch.typ;
+   acc_vbp = vsync + timings->vback_porch.typ;
+   acc_act_w = acc_hbp + timings->hactive.typ;
+   acc_act_h = acc_vbp + timings->vactive.typ;
+   total_w = acc_act_w + timings->hfront_porch.typ;
+   total_h = acc_act_h + timings->vfront_porch.typ;
 
/* Synchronization sizes */
val = (hsync << 16) | vsync;
@@ -248,14 +249,14 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv 
*priv)
 
/* Signal polarities */
val = 0;
-   debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
-   if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
+   debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
+   if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
val |= GCR_HSPOL;
-   if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
val |= GCR_VSPOL;
-   if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
val |= GCR_DEPOL;
-   if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+   if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
val |= GCR_PCPOL;
clrsetbits_le32(regs + LTDC_GCR,
GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
@@ -331,7 +332,11 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
-   struct udevice *panel;
+#ifdef CONFIG_VIDEO_BRIDGE
+   struct udevice *bridge = NULL;
+#endif
+   struct udevice *panel = NULL;
+   struct display_timing timings;
struct clk pclk;
struct reset_ctl rst;
int rate, ret;
@@ -364,63 +369,93 @@ static int stm32_ltdc_probe(struct udevice *dev)
/* Reset */
reset_deassert(&rst);
 
-   ret = uclass_first_device(UCLASS_PANEL, &panel);
+#ifdef CONFIG_VIDEO_BRIDGE
+   ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
if (ret) {
-   debug("%s: panel device error %d\n", __func__, ret);
-   return ret;
+   debug("%s: No video bridge, or no backlight on bridge\n",
+ __func__);
}
 
-   ret = panel_enable_backlight(panel);
+   if (bridge) {
+   ret = video_bridge_attach(bridge);
+   if (ret) {
+   debug("%s: fail to attach bridge\n", __func__);
+   return ret;
+   }
+   }
+#endif
+   ret = uclass_first_device(UCLASS_PANEL, &panel);
if (ret) {
-   debug("%s: panel %s enable backlight error %d\n",
- __func__, panel->name, ret);
+

[U-Boot] [PATCH v1 1/7] video: stm32: stm32_ltdc: add reset

2018-02-13 Thread yannick fertre

Add reset of LTDC display controller.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index b417ac2..d8784f1 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -11,6 +11,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -302,6 +303,7 @@ static int stm32_ltdc_probe(struct udevice *dev)
struct stm32_ltdc_priv *priv = dev_get_priv(dev);
struct udevice *panel;
struct clk pclk, pxclk;
+   struct reset_ctl rst;
int ret;
 
priv->regs = (void *)dev_read_addr(dev);
@@ -316,6 +318,15 @@ static int stm32_ltdc_probe(struct udevice *dev)
return ret;
}
 
+   ret = reset_get_by_index(dev, 0, &rst);
+   if (ret) {
+   debug("%s: missing ltdc hardware reset\n", __func__);
+   return -ENODEV;
+   }
+
+   /* Reset */
+   reset_deassert(&rst);
+
ret = panel_enable_backlight(panel);
if (ret) {
debug("%s: panel %s enable backlight error %d\n",
-- 
1.9.1

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[U-Boot] [PATCH v1 2/7] video: stm32: stm32_ltdc: update file header & footer

2018-02-13 Thread yannick fertre

Modified copyright & driver name.

Signed-off-by: yannick fertre 
---
 drivers/video/stm32/stm32_ltdc.c | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/drivers/video/stm32/stm32_ltdc.c b/drivers/video/stm32/stm32_ltdc.c
index d8784f1..8d89b58 100644
--- a/drivers/video/stm32/stm32_ltdc.c
+++ b/drivers/video/stm32/stm32_ltdc.c
@@ -1,8 +1,7 @@
 /*
- * Copyright (C) STMicroelectronics SA 2017
- *
- * Authors: Philippe Cornu 
- *  Yannick Fertre 
+ * Copyright (C) 2017-2018 STMicroelectronics - All Rights Reserved
+ * Author(s): Philippe Cornu  for STMicroelectronics.
+ *   Yannick Fertre  for STMicroelectronics.
  *
  * SPDX-License-Identifier: GPL-2.0+
  */
@@ -408,10 +407,10 @@ static const struct udevice_id stm32_ltdc_ids[] = {
 };
 
 U_BOOT_DRIVER(stm32_ltdc) = {
-   .name   = "stm32_ltdc",
-   .id = UCLASS_VIDEO,
-   .of_match = stm32_ltdc_ids,
-   .probe  = stm32_ltdc_probe,
-   .bind   = stm32_ltdc_bind,
+   .name   = "stm32_display",
+   .id = UCLASS_VIDEO,
+   .of_match   = stm32_ltdc_ids,
+   .probe  = stm32_ltdc_probe,
+   .bind   = stm32_ltdc_bind,
.priv_auto_alloc_size   = sizeof(struct stm32_ltdc_priv),
 };
-- 
1.9.1

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[U-Boot] [PATCH v1 0/7] splash screen on the stm32f746 disco board

2018-02-13 Thread yannick fertre

This serie contains all patchsets needed for displaying a splash screen 
on the stm32f746 disco board & some display features (reset, blending & line
interrupt position).

Philippe CORNU (1):
  arm: dts: stm32: add ltdc for STM32F746

yannick fertre (6):
  video: stm32: stm32_ltdc: add reset
  video: stm32: stm32_ltdc: update file header & footer
  video: stm32: stm32_ltdc: set rate of the pixel clock
  video: stm32: stm32_ltdc: missing set of line interrupt position
  video: stm32: stm32_ltdc: set the blending factor
  arm: dts: stm32: add display for STM32F746 disco board

 arch/arm/dts/stm32f746-disco.dts |  70 +++
 arch/arm/dts/stm32f746.dtsi  |   9 +++
 drivers/video/stm32/stm32_ltdc.c | 117 +++
 3 files changed, 161 insertions(+), 35 deletions(-)

-- 
1.9.1

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