Re: [U-Boot] [Patch 1/2] MIPS: fix a latent bug on initialize $gp
On Wed, Nov 28, 2012 at 02:33:10PM +0100, Daniel Schwierzeck wrote: 2012/11/26 Zhi-zhou Zhang zhizhou...@gmail.com: On Sun, Nov 25, 2012 at 09:30:54PM +0100, Daniel Schwierzeck wrote: 2012/11/24 Zhi-zhou Zhang zhizhou...@gmail.com: If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned. then the following ld insntrustion generates a Adel exception. So here make _gp be always aligned in 8 bytes. which toolchain do you use? Actually _gp is aligned to 16 bytes in the linker script. Thus the instruction ld gp, 0(ra) and the address loaded into gp is always aligned to 8 bytes. This works at least with ELDK-5.2.1 and a self-built gcc-4.7.2. Thanks for review. I have do a simple test by modify this snip as following: .align 3 //nop nop bal 1f nop .dword _gp 1: ld gp, 0(ra) Qemu give me a Adel exception: (qemu) info registers pc=0xbfc00688 HI=0x LO=0x ds 0098 0 GPR00: r0 at 109f v0 v1 GPR04: a0 a1 a2 a3 GPR08: t0 t1 t2 t3 GPR12: t4 0002 t5 t6 t7 GPR16: s0 s1 s2 s3 GPR20: s4 s5 s6 s7 GPR24: t8 t9 k0 k1 GPR28: gp sp s8 ra bfc00544 CP0 Status 0x10400082 Cause 0x0410 EPC0xbfc00550 Config0 0x80004482 Config1 0xfea3519b LLAddr 0x We can also see the arrange with objdump: bfc00538: nop bfc0053c: 04110004bal bfc00550 bfc00540: nop bfc00544: nop bfc00548: bfc36ed0cache 0x3,28368(s8) bfc0054c: sd ra,-1(ra) bfc00550: dffcld gp,0(ra) It shows that although _gp is aligned to 8 bytes. but it's not in the address of 0(ra). I did some experiments too and now I understand your problem. If you put additional instructions before bal 1f, the compiler puts a nop between bal and _gp to fill the gap in order to keep _gp aligned. But then the link address of bal that will be stored in the gp register points to the additional nop and not to _gp as it was intended. I can't reproduce this with MIPS32. Maybe this is a compiler bug. Dear Daniel, I'm sorry for my poor Engilsh. I didn't describe the problem exactly. I think tlink script only set the value of _gp. and .dword do decide where _gp be linked. Because the compiler always align dword to 8 bytes, the gap comes and was filled with zero. The MIPS's ISA set 4 bytes per instruction. so MIPS's link address is always aligned to 4 bytes. MIPS32 won't occur this problem. But if the link address is not aligned to 8 bytes, MIPS64 goes wrong. We have half chance encountering it. Thanks. I pushed a modified version of your patch to git://git.denx.de/u-boot-mips.git [1]. Could you check if this is okay for you? [1] http://git.denx.de/?p=u-boot/u-boot-mips.git;a=commitdiff;h=4bb639edce852c8ed2ae3219e436845495270453 -- Best regards, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch 1/2] MIPS: fix a latent bug on initialize $gp
On Sun, Nov 25, 2012 at 09:30:54PM +0100, Daniel Schwierzeck wrote: 2012/11/24 Zhi-zhou Zhang zhizhou...@gmail.com: If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned. then the following ld insntrustion generates a Adel exception. So here make _gp be always aligned in 8 bytes. which toolchain do you use? Actually _gp is aligned to 16 bytes in the linker script. Thus the instruction ld gp, 0(ra) and the address loaded into gp is always aligned to 8 bytes. This works at least with ELDK-5.2.1 and a self-built gcc-4.7.2. Thanks for review. I have do a simple test by modify this snip as following: .align 3 //nop nop bal 1f nop .dword _gp 1: ld gp, 0(ra) Qemu give me a Adel exception: (qemu) info registers pc=0xbfc00688 HI=0x LO=0x ds 0098 0 GPR00: r0 at 109f v0 v1 GPR04: a0 a1 a2 a3 GPR08: t0 t1 t2 t3 GPR12: t4 0002 t5 t6 t7 GPR16: s0 s1 s2 s3 GPR20: s4 s5 s6 s7 GPR24: t8 t9 k0 k1 GPR28: gp sp s8 ra bfc00544 CP0 Status 0x10400082 Cause 0x0410 EPC0xbfc00550 Config0 0x80004482 Config1 0xfea3519b LLAddr 0x We can also see the arrange with objdump: bfc00538: nop bfc0053c: 04110004bal bfc00550 bfc00540: nop bfc00544: nop bfc00548: bfc36ed0cache 0x3,28368(s8) bfc0054c: sd ra,-1(ra) bfc00550: dffcld gp,0(ra) It shows that although _gp is aligned to 8 bytes. but it's not in the address of 0(ra). Signed-off-by: Zhi-zhou Zhang zhizhou...@gmail.com --- arch/mips/cpu/mips64/start.S |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S index 4112de7..8e8cc33 100644 --- a/arch/mips/cpu/mips64/start.S +++ b/arch/mips/cpu/mips64/start.S @@ -108,7 +108,10 @@ reset: mtc0t0, CP0_CONFIG #endif - /* Initialize $gp */ + /* Initialize $gp, _gp must be 8 bytes algined. */ + .align 3 + nop + nop bal 1f nop .dword _gp -- 1.7.9.5 -- Best regards, Daniel ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 1/2] MIPS: fix a latent bug on initialize $gp
If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned. then the following ld insntrustion generates a Adel exception. So here make _gp be always aligned in 8 bytes. Signed-off-by: Zhi-zhou Zhang zhizhou...@gmail.com --- arch/mips/cpu/mips64/start.S |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S index 4112de7..8e8cc33 100644 --- a/arch/mips/cpu/mips64/start.S +++ b/arch/mips/cpu/mips64/start.S @@ -108,7 +108,10 @@ reset: mtc0t0, CP0_CONFIG #endif - /* Initialize $gp */ + /* Initialize $gp, _gp must be 8 bytes algined. */ + .align 3 + nop + nop bal 1f nop .dword _gp -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 2/2] MIPS: do not modify variable before relocate_code
Because timestamp is declared as `static', we needn't initialize
it by writing it a zero. If we do it before relocate_code, we
will write into a flash address(0xbfc0).
Signed-off-by: Zhi-zhou Zhang zhizhou...@gmail.com
---
arch/mips/cpu/mips32/time.c |1 -
arch/mips/cpu/mips64/time.c |1 -
2 files changed, 2 deletions(-)
diff --git a/arch/mips/cpu/mips32/time.c b/arch/mips/cpu/mips32/time.c
index 350896a..09fc842 100644
--- a/arch/mips/cpu/mips32/time.c
+++ b/arch/mips/cpu/mips32/time.c
@@ -36,7 +36,6 @@ static unsigned long timestamp;
int timer_init(void)
{
/* Set up the timer for the first expiration. */
- timestamp = 0;
write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
return 0;
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
index 5154280..720f7b7 100644
--- a/arch/mips/cpu/mips64/time.c
+++ b/arch/mips/cpu/mips64/time.c
@@ -37,7 +37,6 @@ static unsigned long timestamp;
int timer_init(void)
{
/* Set up the timer for the first expiration. */
- timestamp = 0;
write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
return 0;
--
1.7.9.5
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Re: [U-Boot] include: fix mips64 build warning
On Mon, Oct 1, 2012 at 7:06 PM, Daniel Schwierzeck daniel.schwierz...@gmail.com wrote: Hi Zhi-zhou, 2012/9/29 Zhi-zhou Zhang etou...@gmail.com: fix warnings when building mips64, we define CONFIG_MIPS64 in config file. And this macro decides size_t. hashtable.c: In function 'hexport_r': hashtable.c:495:2: warning: format '%zu' expects argument of type 'size_t', but argument 5 has type 'unsigned int' [-Wformat] hashtable.c:554:5: warning: format '%zu' expects argument of type 'size_t', but argument 2 has type 'unsigned int' [-Wformat] hashtable.c:554:5: warning: format '%zu' expects argument of type 'size_t', but argument 3 has type 'unsigned int' [-Wformat] hashtable.c: In function 'himport_r': hashtable.c:654:3: warning: format '%zu' expects argument of type 'size_t', but argument 2 has type 'unsigned int' [-Wformat] Signed-off-by: Zhi-zhou Zhang etou...@gmail.com thanks but I already fixed this in next branch of git://git.denx.de/u-boot-mips.git. I've replaced your check with #if _MIPS_SZLONG != 64 (gcc built-in). Linux MIPS does the same. --- include/linux/types.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/types.h b/include/linux/types.h index 1b0b4a4..33ee095 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -4,6 +4,7 @@ #ifdef __KERNEL__ #include linux/config.h #endif +#include config.h #include linux/posix_types.h #include asm/types.h -- 1.7.9.5 -- Best regards, Daniel That's fine, thanks. -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] include: fix mips64 build warning
fix warnings when building mips64, we define CONFIG_MIPS64 in config file. And this macro decides size_t. hashtable.c: In function 'hexport_r': hashtable.c:495:2: warning: format '%zu' expects argument of type 'size_t', but argument 5 has type 'unsigned int' [-Wformat] hashtable.c:554:5: warning: format '%zu' expects argument of type 'size_t', but argument 2 has type 'unsigned int' [-Wformat] hashtable.c:554:5: warning: format '%zu' expects argument of type 'size_t', but argument 3 has type 'unsigned int' [-Wformat] hashtable.c: In function 'himport_r': hashtable.c:654:3: warning: format '%zu' expects argument of type 'size_t', but argument 2 has type 'unsigned int' [-Wformat] Signed-off-by: Zhi-zhou Zhang etou...@gmail.com --- include/linux/types.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/types.h b/include/linux/types.h index 1b0b4a4..33ee095 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -4,6 +4,7 @@ #ifdef __KERNEL__ #include linux/config.h #endif +#include config.h #include linux/posix_types.h #include asm/types.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] include: fix mips64 build warning
fix warnings when building mips64, we define CONFIG_MIPS64 in config file. And this macro decides size_t. hashtable.c: In function 'hexport_r': hashtable.c:495:2: warning: format '%zu' expects argument of type 'size_t', but argument 5 has type 'unsigned int' [-Wformat] hashtable.c:554:5: warning: format '%zu' expects argument of type 'size_t', but argument 2 has type 'unsigned int' [-Wformat] hashtable.c:554:5: warning: format '%zu' expects argument of type 'size_t', but argument 3 has type 'unsigned int' [-Wformat] hashtable.c: In function 'himport_r': hashtable.c:654:3: warning: format '%zu' expects argument of type 'size_t', but argument 2 has type 'unsigned int' [-Wformat] Signed-off-by: Zhi-zhou Zhang etou...@gmail.com --- include/linux/types.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/types.h b/include/linux/types.h index 1b0b4a4..33ee095 100644 --- a/include/linux/types.h +++ b/include/linux/types.h @@ -4,6 +4,7 @@ #ifdef __KERNEL__ #include linux/config.h #endif +#include config.h #include linux/posix_types.h #include asm/types.h -- 1.7.9.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V5 2/4] MIPS: change address related header files
On Wed, Sep 5, 2012 at 6:25 AM, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
2012/9/4 Zhizhou Zhang etou...@gmail.com:
Prepare for upcoming mips64 support. This patch add mips64 address
space support.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/include/asm/addrspace.h |2 +-
arch/mips/include/asm/asm.h |2 +-
arch/mips/include/asm/io.h | 16
arch/mips/include/asm/posix_types.h |6 ++
4 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/arch/mips/include/asm/addrspace.h
b/arch/mips/include/asm/addrspace.h
index 3a1e6d6..b768bb5 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -136,7 +136,7 @@
cannot access physical memory directly from core */
#define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000)
#else /* !CONFIG_SOC_AU1X00 */
-#define UNCACHED_SDRAM(a) KSEG1ADDR(a)
+#define UNCACHED_SDRAM(a) CKSEG1ADDR(a)
#endif /* CONFIG_SOC_AU1X00 */
#endif /* __ASSEMBLY__ */
diff --git a/arch/mips/include/asm/asm.h b/arch/mips/include/asm/asm.h
index 608cfcf..933ccb1 100644
--- a/arch/mips/include/asm/asm.h
+++ b/arch/mips/include/asm/asm.h
@@ -401,7 +401,7 @@ symbol = value
#ifdef CONFIG_SGI_IP28
/* Inhibit speculative stores to volatile (e.g.DMA) or invalid
addresses. */
#include asm/cacheops.h
-#define R10KCBARRIER(addr) cache Cache_Barrier, addr;
+#define R10KCBARRIER(addr) cache CACHE_BARRIER, addr;
this change is unrelated to this patch. I guess this belongs to patch 1/4
I'm so careless! Then what should I do now? need I resend these once
again? I think that's not good..
#else
#define R10KCBARRIER(addr)
#endif
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..80eab75 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long
base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long
address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
diff --git a/arch/mips/include/asm/posix_types.h
b/arch/mips/include/asm/posix_types.h
index 879aae2..6566ad0 100644
--- a/arch/mips/include/asm/posix_types.h
+++ b/arch/mips/include/asm/posix_types.h
@@ -24,9 +24,15 @@ typedef int __kernel_pid_t;
typedef int__kernel_ipc_pid_t;
typedef int__kernel_uid_t;
typedef int__kernel_gid_t;
+#ifndef CONFIG_MIPS64
typedef unsigned int __kernel_size_t;
typedef int__kernel_ssize_t;
typedef int__kernel_ptrdiff_t;
+#else
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef long __kernel_ptrdiff_t;
+#endif
typedef long __kernel_time_t;
typedef long __kernel_suseconds_t;
typedef long __kernel_clock_t;
--
1.7.9.5
--
Best regards,
Daniel
--
Regards,
Zhizhou Zhang
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Re: [U-Boot] [Patch V5 4/4] MIPS: add board qemu-mips64 support
On Wed, Sep 5, 2012 at 7:12 AM, Daniel Schwierzeck
daniel.schwierz...@gmail.com wrote:
2012/9/4 Zhizhou Zhang etou...@gmail.com:
Both big-endian and little-endian are tested with below commands:
Rom version: (Default, Now we config it as rom version)
qemu-system-mips64el -M mips -bios u-boot.bin -cpu MIPS64R2-generic
-nographic
qemu-system-mips64 -M mips -bios u-boot.bin -cpu MIPS64R2-generic
-nographic
Ram version:
qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot
-nographic
qemu-system-mips64 -M mips -cpu MIPS64R2-generic -kernel u-boot
-nographic
Signed-off-by: Zhizhou Zhang etou...@gmail.com
---
arch/mips/cpu/mips64/Makefile | 45 +++
arch/mips/cpu/mips64/cache.S | 229
+
arch/mips/cpu/mips64/config.mk| 40 ++
arch/mips/cpu/mips64/cpu.c| 111
arch/mips/cpu/mips64/interrupts.c | 34 +
arch/mips/cpu/mips64/start.S | 256
+
arch/mips/cpu/mips64/time.c | 87 +
board/qemu-mips/u-boot.lds|8 ++
boards.cfg|2 +
examples/standalone/mips64.lds| 59 +
include/configs/qemu-mips64.h | 171 +
11 files changed, 1042 insertions(+)
create mode 100644 arch/mips/cpu/mips64/Makefile
create mode 100644 arch/mips/cpu/mips64/cache.S
create mode 100644 arch/mips/cpu/mips64/config.mk
create mode 100644 arch/mips/cpu/mips64/cpu.c
create mode 100644 arch/mips/cpu/mips64/interrupts.c
create mode 100644 arch/mips/cpu/mips64/start.S
create mode 100644 arch/mips/cpu/mips64/time.c
create mode 100644 examples/standalone/mips64.lds
create mode 100644 include/configs/qemu-mips64.h
[...]
diff --git a/include/configs/qemu-mips64.h
b/include/configs/qemu-mips64.h
new file mode 100644
index 000..216326d
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,171 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64
target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 /* MIPS64 CPU core */
+#define CONFIG_QEMU_MIPS1
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600,
115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with
timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ addmisc=setenv bootargs ${bootargs} \
+ console=ttyS0,${baudrate} \
+ panic=1\0 \
+ bootfile=/tftpboot/vmlinux\0 \
+ load=tftp 8050 ${u-boot}\0\
+
+
why have you omitted this?
#define CONFIG_BOOTCOMMAND bootp;bootelf
#define CONFIG_CMD_ELF
Because I haven't tested `bootelf' command. I'm not should it work or not.
Another reason is that when I configure CONFIG_CMD_ELF I will get lots of
warning such as:
cmd_elf.c: In function 'load_elf_image_phdr':
cmd_elf.c:289:15: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
cmd_elf.c: In function 'load_elf_image_shdr':
cmd_elf.c:343:12: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
cmd_elf.c:346:12: warning: cast to pointer from integer of different size
[-Wint-to-pointer-cast]
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include config_cmd_default.h
+#define CONFIG_DP83902A
+
Re: [U-Boot] [Patch V4 4/4] MIPS: add mips64 standalone support
Dear Wolfgang Denk, On Sat, Sep 1, 2012 at 8:48 PM, Wolfgang Denk w...@denx.de wrote: Dear Zhizhou Zhang, In message 1346071750-6634-10-git-send-email-etou...@gmail.com you wrote: Move CONFIG_SYS_TEXT_BASE to the board specified header file. So change qemu-mips.h also. board/qemu-mips/config.mk is not used, then remove it. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- board/qemu-mips/config.mk | 10 --- examples/standalone/mips64.lds | 59 include/configs/qemu-mips.h|1 + 3 files changed, 60 insertions(+), 10 deletions(-) delete mode 100644 board/qemu-mips/config.mk create mode 100644 examples/standalone/mips64.lds This patch appears to be too late in this patch series Either re-order and/or squash with other parts to ensure bisectability. I'm sorry, I can't catch you. So what should I do now? Do you mean I should resend these patch again? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de If I ever needed a brain transplant, I'd choose a teenager's because I'd want a brain that had never been used. -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V4 1/4] MIPS: Add support for MIPS64 cpus
Dear Wolfgang Denk,
On Sat, Sep 1, 2012 at 8:42 PM, Wolfgang Denk w...@denx.de wrote:
Dear Zhizhou Zhang,
In message 1346071750-6634-7-git-send-email-etou...@gmail.com you wrote:
These files are derived from arch/mips/cpu/mips32/*. The main changes
are:
1, changes ABI o32 to n64, 2, add mips64 build cflags.
Signed-off-by: Zhizhou Zhang etou...@gmail.com
Checkpatch reports a number of unnecessary whitespace before a quoted
newline warnings; please fix these.
diff --git a/arch/mips/cpu/mips64/Makefile
b/arch/mips/cpu/mips64/Makefile
new file mode 100644
index 000..f4c88f5
--- /dev/null
+++ b/arch/mips/cpu/mips64/Makefile
...
+sinclude $(obj).depend
+
diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S
Please do not add trailing empty lines. Please fix globally.
...
+++ b/arch/mips/cpu/mips64/config.mk
@@ -0,0 +1,40 @@
...
+CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff8020 -T mips64.lds
As requested before: please don't mix upper and lower case letters in
a number; use a consistent styile everywhere. PLease fix globally.
As requested before: please make sure your patches are bisectable.
This references file mips64.lds, but doesn;t add it, so it cannot
work.
I'm a new learner, Please forgive my faults. So do you mean that we should
can build
u-boot on each submit? If it is, should I resend these patch?
...
+#define cache_op(op, addr) \
+ __asm__ __volatile__( \
+.setpush\n \
+.setnoreorder \n \
+.setmips64\n\t \n \
+cache %0, %1 \n \
+.setpop \n \
Fix checkpatch warnings here (and globally).
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(Hit_Invalidate_I, addr);
We don't allow camel-case identifiers. Please fix globally.
I thought these identifiers come from Linux Kernel and mips spec.
I will fix it as you command
Best regards,
Wolfgang Denk
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HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: w...@denx.de
If it has syntax, it isn't user friendly.
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Re: [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
with current master branch in git://git.denx.de/u-boot-mips.git you can drop the endianess flags which are now handled in arch/mips/config.mk Ok, I have done what you ask for. But I didn't find where does CONFIG_SYS_LITTLE_ENDIAN or CONFIG_SYS_BIG_ENDIAN define. Could you tell where should I put them? It seem that putting it in qemu-mips64.h doesn't affect building flags. currently we cannot use interrupts or setup any interrupt handlers in u-boot-mips. Please leave those functions empty. calling a C function is not supposed to work here because no stack pointer has been setup yet. I checked with Sourcery 2011.09 and 2012.03. The stack is always utilized in cache_probe. Either you rewrite the cache_probe function in assembler or you use the existing config options and you could drop the cache probing. I'm afraid I don't say clearly just now. I mean could I call cache_probe in checkboard()? -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V3 4/4] [MIPS] Disable standalone while building MIPS64
On Fri, Aug 24, 2012 at 8:23 AM, Daniel Schwierzeck daniel.schwierz...@gmail.com wrote: 2012/8/20 Zhizhou Zhang etou...@gmail.com: I think copy mips.lds to mips64.lds with only one line changed is not good. So I disable it in top Makefile. Signed-off-by: Zhizhou Zhang etou...@gmail.com --- Makefile |2 ++ 1 file changed, 2 insertions(+) diff --git a/Makefile b/Makefile index 5ce5cc3..626d888 100644 --- a/Makefile +++ b/Makefile @@ -155,8 +155,10 @@ sinclude $(obj)include/autoconf.mk.dep sinclude $(obj)include/autoconf.mk ifndef CONFIG_SANDBOX +ifndef CONFIG_MIPS64 SUBDIRS += $(SUBDIR_EXAMPLES) endif +endif # load ARCH, BOARD, and CPU configuration include $(obj)include/config.mk -- 1.7.9.5 NAK. Please do what you have done in v1 of your patch series. This is possible now if you use current master of git://git.denx.de/u-boot-mips.git. -- Best regards, Daniel when I add below in examples/standalone/mips.lds, #ifdef CONFIG_64BIT OUTPUT_FORMAT(elf64-tradbigmips, elf64-tradbigmips, elf64-tradlittlemips) #else OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips, elf32-tradlittlemips) #endif I will get a error: /home/zhangzz/work/clfs/sys_root/cross-tools/bin/mips64el-unknown-linux-gnu-ld:mips.lds:27: ignoring invalid character `#' in expression /home/zhangzz/work/clfs/sys_root/cross-tools/bin/mips64el-unknown-linux-gnu-ld:mips.lds:27: syntax error So I find these in top Makefile: $(obj)u-boot.lds: $(LDSCRIPT) $(CPP) $(CPPFLAGS) $(LDPPFLAGS) -ansi -D__ASSEMBLY__ -P - $^ $@ It seems that I can't make mips.lds configurable without a lot modifications in example/standalone/Makefile. So could you give a tip? -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
On Fri, Aug 24, 2012 at 8:22 AM, Daniel Schwierzeck daniel.schwierz...@gmail.com wrote: 2012/8/20 Zhizhou Zhang etou...@gmail.com: These files are derived from arch/mips/cpu/mips32/*. Howerver some Changes are made: *.S: changes ABI o32 to n64 config.mk: add mips64 building cflags cpu.c: add cache size probe interrupts.c: implement enable_interrupts and disable_interrupts Signed-off-by: Zhizhou Zhang etou...@gmail.com --- arch/mips/cpu/mips64/Makefile | 47 +++ arch/mips/cpu/mips64/config.mk| 39 ++ arch/mips/cpu/mips64/cpu.c| 124 ++ arch/mips/cpu/mips64/interrupts.c | 39 ++ arch/mips/cpu/mips64/start.S | 256 + arch/mips/cpu/mips64/time.c | 86 + 6 files changed, 591 insertions(+) create mode 100644 arch/mips/cpu/mips64/Makefile create mode 100644 arch/mips/cpu/mips64/config.mk create mode 100644 arch/mips/cpu/mips64/cpu.c create mode 100644 arch/mips/cpu/mips64/interrupts.c create mode 100644 arch/mips/cpu/mips64/start.S create mode 100644 arch/mips/cpu/mips64/time.c diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..335fe88 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB= $(obj)lib$(CPU).o + +START = start.o +COBJS-y= cpu.o interrupts.o time.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB):$(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/ config.mk new file mode 100644 index 000..26f79e6 --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,39 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS64 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +ENDIANNESS = -EL + +MIPSFLAGS += $(ENDIANNESS) with current master branch in git://git.denx.de/u-boot-mips.git you can drop the endianess flags which are now handled in arch/mips/config.mk + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) +PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT +PLATFORM_LDFLAGS += -m elf64ltsmip + diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c new file mode 100644 index 000..348ccfe --- /dev/null +++ b/arch/mips/cpu/mips64/cpu.c @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2003 + * Wolfgang Denk, DENX Software Engineering, w...@denx.de + * Zhi-zhou Zhang etou...@gmail.com + * + * See file CREDITS for list
Re: [U-Boot] [Patch V3 1/4] [MIPS] Add support for MIPS64 cpus
On Thu, Aug 23, 2012 at 11:07 AM, Mike Frysinger vap...@gentoo.org wrote:
On Monday 20 August 2012 10:22:23 Zhizhou Zhang wrote:
+void __weak _machine_restart(void)
+{
+}
this should be:
void __noreturn __weak _machine_restart(void)
{
while (1);
}
there should also be a prototype for this in one of the mips64 headers
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ fprintf(stderr, *** reset failed ***\n);
+ return 0;
+}
then this would be:
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
_machine_restart();
}
-mike
Yes, you are right. thanks
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Re: [U-Boot] [Patch V3 0/4] add mips64 cpu support
On Thu, Aug 23, 2012 at 11:04 AM, Mike Frysinger vap...@gentoo.org wrote: On Monday 20 August 2012 10:22:22 Zhizhou Zhang wrote: This patch add mips64 cpu support. Changes in V3: - merge related files into one patch, no longer one file one patch. - add detailed commit message. - remove standalone example. it's too complicate. do you keep sending these patchsets in duplicate on purpose ? your v2 and v3 series both were doubly sent. -mike I'm sorry, I'm a fresh to mail-list. I used to think I should send a patch diff from master branch. Thanks for you guidance. -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [[Patch V2] mips: 01/16] add mips64 standalone support
On 8/18/12, Mike Frysinger vap...@gentoo.org wrote: On Saturday 18 August 2012 08:22:51 Zhi-zhou Zhang wrote: On Sat, Aug 18, 2012 at 3:31 AM, Mike Frysinger wrote: On Friday 17 August 2012 11:30:44 Zhizhou Zhang wrote: --- a/arch/mips/config.mk +++ b/arch/mips/config.mk +ifeq $(CPU) mips64 +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff8020 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds +endif the cpu config.mk is sourced after this one. you could change this to: CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x8020 -T mips.lds then in the mips64/config.mk: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff8020 -T mips64.lds Thanks for you advising. But if I changed like so, I should modify mips32/ config.mk and xburst/config.mk as also. why ? my suggestion shouldn't affect any other cpu config.mk. -mike Oh, I'm so sorry, I think that you mean to replace CONFIG_STANDALONE_LOAD_ADDR by DEFAULT_MIPS_STANDALONE_LOAD_ADDR. So your idea is to keep both CONFIG_STANDALONE_LOAD_ADDR and DEFAULT_MIPS_STANDALONE_LOAD_ADDR, one for mips64, anther for mips32. Actually I haven't test standalone example. I add standalone config and build option for I would get an error if didn't do that. It brings me a lot of mess. I want to disable stanalone support in TOP Makefile, could I do that? -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [[Patch V2] mips: 01/16] add mips64 standalone support
On Sat, Aug 18, 2012 at 3:31 AM, Mike Frysinger vap...@gentoo.org wrote: On Friday 17 August 2012 11:30:44 Zhizhou Zhang wrote: --- a/arch/mips/config.mk +++ b/arch/mips/config.mk +ifeq $(CPU) mips64 +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff8020 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds +endif the cpu config.mk is sourced after this one. you could change this to: CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x8020 -T mips.lds then in the mips64/config.mk: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff8020 -T mips64.lds -mike Thanks for you advising. But if I changed like so, I should modify mips32/ config.mk and xburst/config.mk as also. I think that's not good for modified too much files. -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [[Patch V2] mips: 01/16] add mips64 standalone support
On 8/18/12, Mike Frysinger vap...@gentoo.org wrote: On Saturday 18 August 2012 08:22:51 Zhi-zhou Zhang wrote: On Sat, Aug 18, 2012 at 3:31 AM, Mike Frysinger wrote: On Friday 17 August 2012 11:30:44 Zhizhou Zhang wrote: --- a/arch/mips/config.mk +++ b/arch/mips/config.mk +ifeq $(CPU) mips64 +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff8020 -T mips64.lds +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds +endif the cpu config.mk is sourced after this one. you could change this to: CONFIG_STANDALONE_LOAD_ADDR ?= $(DEFAULT_MIPS_STANDALONE_LOAD_ADDR) DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0x8020 -T mips.lds then in the mips64/config.mk: DEFAULT_MIPS_STANDALONE_LOAD_ADDR = 0xFfffFfff8020 -T mips64.lds Thanks for you advising. But if I changed like so, I should modify mips32/ config.mk and xburst/config.mk as also. why ? my suggestion shouldn't affect any other cpu config.mk. -mike Oh, I'm so sorry, I think that you mean to replace CONFIG_STANDALONE_LOAD_ADDR by DEFAULT_MIPS_STANDALONE_LOAD_ADDR. So your idea is to keep both CONFIG_STANDALONE_LOAD_ADDR and DEFAULT_MIPS_STANDALONE_LOAD_ADDR, one for mips64, anther for mips32. Actually I haven't test standalone example. I add standalone config and build option for I would get an error if didn't do that. It brings me a lot of mess. I want to disable stanalone support in TOP Makefile, could I do that? -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [[Patch V2] mips: 14/16] add mips64 standalone link script
On Sat, Aug 18, 2012 at 1:08 AM, Andrew Dyer amd...@gmail.com wrote: I think the OUTPUT_FORMAT line if wrong. This will produce little endian output even if explicitly told by command line switch -EB to make big endian. Yes, But if I want make it configureable, I should modify a lot in standalone/Makefile. I'm afraid that it will affect other boards' build. actually, I want disable mips64's standalone example in top Makefile. -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [[Patch V2] mips: 04/16] add cpu/mips64/cpu.c
On Sat, Aug 18, 2012 at 3:34 AM, Mike Frysinger vap...@gentoo.org wrote:
On Friday 17 August 2012 11:30:47 Zhizhou Zhang wrote:
--- /dev/null
+++ b/arch/mips/cpu/mips64/cpu.c
+void __attribute__((weak)) _machine_restart(void)
+{
+}
change to __weak (include linux/compiler.h if you need to).
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ fprintf(stderr, *** reset failed ***\n);
+ return 0;
+}
this function should never return. add a __noreturn to machine_restart().
+void cache_probe()
(void)
-mike
Thanks for your concern, I will do as said.
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Re: [U-Boot] [Patch 0/17] New 'qemu-mips64' test architecture for U-Boot
On Thu, Aug 16, 2012 at 5:31 AM, Daniel Schwierzeck daniel.schwierz...@gmail.com wrote: Hi, 2012/8/15 Zhi-zhou Zhang etou...@gmail.com: On Tue, Aug 14, 2012 at 11:51 PM, Mike Frysinger vap...@gentoo.org wrote: On Tuesday 14 August 2012 11:49:49 Mike Frysinger wrote: On Tuesday 14 August 2012 11:06:51 Zhi-zhou Zhang wrote: As so far, U-Boot has already supports mips32. But there are some differences between mips64 and mips32. Such as different ABI, different output format. so this patch adds mips64 support. many of your patches are line wrapped. please use `git send-email` rather than whatever client you're using (looks like gmail?) as it won't screw things up. hmm, actually it's worse than that -- the leading whitespace is all mangled too. i'm assuming your code isn't that screwed up, so please resend with git- sendemail. -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot OK, I will retry. actually I sent it by copy-and-paste. I wasn't aware of that. thanks. then you should read http://www.denx.de/wiki/U-Boot/Patches And please do for all MIPS specific patches: - CC me - use the prefix MIPS: in the email subject -- Thanks and regards, Daniel Thanks for all your suggestions. I will improve them in next version. -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [Patch 0/17] New 'qemu-mips64' test architecture for U-Boot
On Tue, Aug 14, 2012 at 11:51 PM, Mike Frysinger vap...@gentoo.org wrote: On Tuesday 14 August 2012 11:49:49 Mike Frysinger wrote: On Tuesday 14 August 2012 11:06:51 Zhi-zhou Zhang wrote: As so far, U-Boot has already supports mips32. But there are some differences between mips64 and mips32. Such as different ABI, different output format. so this patch adds mips64 support. many of your patches are line wrapped. please use `git send-email` rather than whatever client you're using (looks like gmail?) as it won't screw things up. hmm, actually it's worse than that -- the leading whitespace is all mangled too. i'm assuming your code isn't that screwed up, so please resend with git- sendemail. -mike ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot OK, I will retry. actually I sent it by copy-and-paste. I wasn't aware of that. thanks. -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 0/17] New 'qemu-mips64' test architecture for U-Boot
As so far, U-Boot has already supports mips32. But there are some differences between mips64 and mips32. Such as different ABI, different output format. so this patch adds mips64 support. I use cross compiler from clfs and build U-Boot like this: export CROSS_COMPILE=/home/zhangzz/work/clfs/sys_root/cross-tools/bin/mips64el-unknown-linux-gnu- make qemu_mips64_config make And run U-Boot with command below: $ qemu-system-mips64el -M mips -cpu MIPS64R2-generic -kernel u-boot -nographic U-Boot 2012.07-00089-gbbffc64 (Aug 14 2012 - 22:34:02) Board: Qemu -M mips CPU: unknown proc_id=0x1 DRAM: 128 MiB Using default environment In:serial Out: serial Err: serial Net: NE2000 qemu-mips64 # = Detail: 1 Add qemu_mips64_defconfig, and add related build configuration. 2 mips/cpu/mips64/* are derived from mips/cpu/mips32, but mips32 is using ABI O32, we can't build it with mips64 cross compiler. so changes are made. 3 Some address operation didn't take care about mips64, so asm/addrspace.h and io.h were changed. arch/mips/config.mk | 14 +- arch/mips/cpu/mips64/Makefile | 48 + arch/mips/cpu/mips64/cache.S| 229 + arch/mips/cpu/mips64/config.mk | 36 arch/mips/cpu/mips64/cpu.c | 116 +++ arch/mips/cpu/mips64/interrupts.c | 38 arch/mips/cpu/mips64/start.S| 374 +++ arch/mips/cpu/mips64/time.c | 86 arch/mips/include/asm/addrspace.h |2 +- arch/mips/include/asm/io.h | 16 ++ arch/mips/include/asm/posix_types.h |4 + board/qemu-mips/config.mk |7 + board/qemu-mips/u-boot.lds |8 + boards.cfg |1 + examples/standalone/mips64.lds | 59 ++ include/configs/qemu-mips64.h | 168 17 files changed, 1206 insertions(+), 3 deletions(-) -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 1/17] add mips64 build configuration in mips/config.mk
diff --git a/arch/mips/config.mk b/arch/mips/config.mk index 6ab8acd..12df150 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -23,9 +23,13 @@ CROSS_COMPILE ?= mips_4KC- +ifeq $(CPU) mips64 +CONFIG_STANDALONE_LOAD_ADDR ?= 0xFfffFfff8020 -T mips64.lds +PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ -DCONFIG_64BIT +else CONFIG_STANDALONE_LOAD_ADDR ?= 0x8020 -T mips.lds - PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ +endif # # From Linux arch/mips/Makefile @@ -47,8 +51,16 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__ # On the other hand, we want PIC in the U-Boot code to relocate it from ROM # to RAM. $28 is always used as gp. # +ifeq $(CPU) mips64 +PLATFORM_CPPFLAGS += -G 0 -mabicalls -mabi=64 -fpic +PLATFORM_CPPFLAGS += -msoft-float +PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib -m elf64ltsmip +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +LDFLAGS_FINAL += --gc-sections +else PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic PLATFORM_CPPFLAGS += -msoft-float PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections +endif -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 2/17] add mips64/Makefile
diff --git a/arch/mips/cpu/mips64/Makefile b/arch/mips/cpu/mips64/Makefile new file mode 100644 index 000..eb8e005 --- /dev/null +++ b/arch/mips/cpu/mips64/Makefile @@ -0,0 +1,48 @@ +# +# (C) Copyright 2003-2006 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).o + +START = start.o +SOBJS-y = cache.o +COBJS-y = cpu.o interrupts.o time.o + +SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +# + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +# -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 3/16] add mips64/cache.S
diff --git a/arch/mips/cpu/mips64/cache.S b/arch/mips/cpu/mips64/cache.S new file mode 100644 index 000..ba7c1b8 --- /dev/null +++ b/arch/mips/cpu/mips64/cache.S @@ -0,0 +1,229 @@ +/* + * Cache-handling routined for MIPS CPUs + * + * Copyright (c) 2003 Wolfgang Denk w...@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include asm-offsets.h +#include config.h +#include asm/asm.h +#include asm/regdef.h +#include asm/mipsregs.h +#include asm/addrspace.h +#include asm/cacheops.h + +#define RA t9 + +/* + * 16kB is the maximum size of instruction and data caches on MIPS 4K, + * 64kB is on 4KE, 24K, 5K, etc. Set bigger size for convenience. + * + * Note that the above size is the maximum size of primary cache. U-Boot + * doesn't have L2 cache support for now. + */ +#define MIPS_MAX_CACHE_SIZE 0x1 + +#define INDEX_BASE CKSEG0 + + .macro cache_op op addr + .set push + .set noreorder + .set mips3 + cache \op, 0(\addr) + .set pop + .endm + + .macro f_fill64 dst, offset, val + LONG_S \val, (\offset + 0 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 1 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 2 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 3 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 4 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 5 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 6 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 7 * LONGSIZE)(\dst) +#if LONGSIZE == 4 + LONG_S \val, (\offset + 8 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 9 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 10 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 11 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 12 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 13 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 14 * LONGSIZE)(\dst) + LONG_S \val, (\offset + 15 * LONGSIZE)(\dst) +#endif + .endm + +/* + * mips_init_icache(uint PRId, ulong icache_size, unchar icache_linesz) + */ +LEAF(mips_init_icache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear tag to invalidate */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op Index_Store_Tag_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* fill once, so data field parity is correct */ + PTR_LI t0, INDEX_BASE +2: cache_op Fill t0 + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* invalidate again - prudent but not strictly neccessary */ + PTR_LI t0, INDEX_BASE +1: cache_op Index_Store_Tag_I t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_icache) + +/* + * mips_init_dcache(uint PRId, ulong dcache_size, unchar dcache_linesz) + */ +LEAF(mips_init_dcache) + blez a1, 9f + mtc0 zero, CP0_TAGLO + /* clear all tags */ + PTR_LI t0, INDEX_BASE + PTR_ADDU t1, t0, a1 +1: cache_op Index_Store_Tag_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b + /* load from each line (in cached space) */ + PTR_LI t0, INDEX_BASE +2: LONG_L zero, 0(t0) + PTR_ADDU t0, a2 + bne t0, t1, 2b + /* clear all tags */ + PTR_LI t0, INDEX_BASE +1: cache_op Index_Store_Tag_D t0 + PTR_ADDU t0, a2 + bne t0, t1, 1b +9: jr ra + END(mips_init_dcache) + +/* + * mips_cache_reset - low level initialisation of the primary caches + * + * This routine initialises the primary caches to ensure that they have good + * parity. It must be called by the ROM before any cached locations are used + * to prevent the possibility of data with bad parity being written to memory. + * + * To initialise the instruction cache it is essential that a source of data + * with good parity is available. This routine will initialise an area of + * memory starting at location zero to be used as a source of parity. + * + * RETURNS: N/A + * + */ +NESTED(mips_cache_reset, 0, ra) + move RA, ra + li t2, CONFIG_SYS_ICACHE_SIZE + li t3, CONFIG_SYS_DCACHE_SIZE + li t8, CONFIG_SYS_CACHELINE_SIZE + + li v0, MIPS_MAX_CACHE_SIZE + + /* + * Now clear that much memory starting from zero. + */ + PTR_LI a0, CKSEG1 + PTR_ADDU a1, a0, v0 +2: PTR_ADDIU a0, 64 + f_fill64 a0, -64, zero + bne a0, a1, 2b + + /* + * The caches are probably in an indeterminate state, + * so we force good parity into them by doing an + * invalidate, load/fill, invalidate for each line. + */ + + /* + * Assume bottom of RAM will generate good parity for the cache. + */ + + /* + * Initialize the I-cache first, + */ + move a1, t2 + move a2, t8 + PTR_LA v1,
[U-Boot] [Patch 4/16] add mips64/config.mk
diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk new file mode 100644 index 000..cec250a --- /dev/null +++ b/arch/mips/cpu/mips64/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2003 +# Wolfgang Denk, DENX Software Engineering, w...@denx.de +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# Default optimization level for MIPS32 +# +# Note: Toolchains with binutils prior to v2.16 +# are no longer supported by U-Boot MIPS tree! +# +MIPSFLAGS = -march=mips64 + +ENDIANNESS = -EL + +MIPSFLAGS += $(ENDIANNESS) + +PLATFORM_CPPFLAGS += $(MIPSFLAGS) -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 5/16] add mips64/cpu.h
diff --git a/arch/mips/cpu/mips64/cpu.c b/arch/mips/cpu/mips64/cpu.c
new file mode 100644
index 000..1ead349
--- /dev/null
+++ b/arch/mips/cpu/mips64/cpu.c
@@ -0,0 +1,116 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include command.h
+#include netdev.h
+#include asm/mipsregs.h
+#include asm/cacheops.h
+#include asm/reboot.h
+
+#define cache_op(op,addr) \
+ __asm__ __volatile__( \
+ .set push \n \
+ .set noreorder \n \
+ .set mips64\n\t \n \
+ cache %0, %1 \n \
+ .set pop \n \
+ : \
+ : i (op), R (*(unsigned char *)(addr)))
+
+void __attribute__((weak)) _machine_restart(void)
+{
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ _machine_restart();
+
+ fprintf(stderr, *** reset failed ***\n);
+ return 0;
+}
+
+void flush_cache(ulong start_addr, ulong size)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr ~(lsize - 1);
+ unsigned long aend = (start_addr + size - 1) ~(lsize - 1);
+
+ /* aend will be miscalculated when size is zero, so we return here */
+ if (size == 0)
+ return;
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ cache_op(Hit_Invalidate_I, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void flush_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr ~(lsize - 1);
+ unsigned long aend = (stop - 1) ~(lsize - 1);
+
+ while (1) {
+ cache_op(Hit_Writeback_Inv_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void invalidate_dcache_range(ulong start_addr, ulong stop)
+{
+ unsigned long lsize = CONFIG_SYS_CACHELINE_SIZE;
+ unsigned long addr = start_addr ~(lsize - 1);
+ unsigned long aend = (stop - 1) ~(lsize - 1);
+
+ while (1) {
+ cache_op(Hit_Invalidate_D, addr);
+ if (addr == aend)
+ break;
+ addr += lsize;
+ }
+}
+
+void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
+{
+ write_c0_entrylo0(low0);
+ write_c0_pagemask(pagemask);
+ write_c0_entrylo1(low1);
+ write_c0_entryhi(hi);
+ write_c0_index(index);
+ tlb_write_indexed();
+}
+
+int cpu_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_SOC_AU1X00
+ au1x00_enet_initialize(bis);
+#endif
+ return 0;
+}
--
Regards,
Zhizhou Zhang
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[U-Boot] [Patch 6/16] add mips64/interrupts.c
diff --git a/arch/mips/cpu/mips64/interrupts.c
b/arch/mips/cpu/mips64/interrupts.c
new file mode 100644
index 000..27aa179
--- /dev/null
+++ b/arch/mips/cpu/mips64/interrupts.c
@@ -0,0 +1,38 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/mipsregs.h
+
+void enable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status | ST0_IE);
+}
+
+int disable_interrupts(void)
+{
+ int status = read_c0_status();
+ write_c0_status(status ~ST0_IE);
+ return status | ST0_IE;
+}
--
Regards,
Zhizhou Zhang
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[U-Boot] [Patch 7/16] add mips64/start.S
diff --git a/arch/mips/cpu/mips64/start.S b/arch/mips/cpu/mips64/start.S new file mode 100644 index 000..2208b6b --- /dev/null +++ b/arch/mips/cpu/mips64/start.S @@ -0,0 +1,374 @@ +/* + * Startup Code for MIPS64 CPU-core + * + * Copyright (c) 2003 Wolfgang Denk w...@denx.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any dlater version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICUdlaR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Pdlace, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include asm-offsets.h +#include config.h +#include asm/regdef.h +#include asm/mipsregs.h + +#ifndef CONFIG_SYS_MIPS_CACHE_MODE +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT +#endif + + /* + * For the moment disable interrupts, mark the kernel mode and + * set ST0_KX so that the CPU does not spit fire when using + * 64-bit addresses. + */ + .macro setup_c0_status set clr + .set push + mfc0 t0, CP0_STATUS + or t0, ST0_CU0 | \set | 0x1f | \clr + xor t0, 0x1f | \clr + mtc0 t0, CP0_STATUS + .set noreorder + sll zero, 3 # ehb + .set pop + .endm + + .macro setup_c0_status_reset +#ifdef CONFIG_64BIT + setup_c0_status ST0_KX 0 +#else + setup_c0_status 0 0 +#endif + .endm + +#define RVECENT(f,n) \ + b f; \ + nop +#define XVECENT(f,bev) \ + b f ; \ + li k0,bev + + .set noreorder + + .globl _start + .text +_start: + RVECENT(reset,0) # U-boot entry point + RVECENT(reset,1) # software reboot + RVECENT(romReserved,2) + RVECENT(romReserved,3) + RVECENT(romReserved,4) + RVECENT(romReserved,5) + RVECENT(romReserved,6) + RVECENT(romReserved,7) + RVECENT(romReserved,8) + RVECENT(romReserved,9) + RVECENT(romReserved,10) + RVECENT(romReserved,11) + RVECENT(romReserved,12) + RVECENT(romReserved,13) + RVECENT(romReserved,14) + RVECENT(romReserved,15) + RVECENT(romReserved,16) + RVECENT(romReserved,17) + RVECENT(romReserved,18) + RVECENT(romReserved,19) + RVECENT(romReserved,20) + RVECENT(romReserved,21) + RVECENT(romReserved,22) + RVECENT(romReserved,23) + RVECENT(romReserved,24) + RVECENT(romReserved,25) + RVECENT(romReserved,26) + RVECENT(romReserved,27) + RVECENT(romReserved,28) + RVECENT(romReserved,29) + RVECENT(romReserved,30) + RVECENT(romReserved,31) + RVECENT(romReserved,32) + RVECENT(romReserved,33) + RVECENT(romReserved,34) + RVECENT(romReserved,35) + RVECENT(romReserved,36) + RVECENT(romReserved,37) + RVECENT(romReserved,38) + RVECENT(romReserved,39) + RVECENT(romReserved,40) + RVECENT(romReserved,41) + RVECENT(romReserved,42) + RVECENT(romReserved,43) + RVECENT(romReserved,44) + RVECENT(romReserved,45) + RVECENT(romReserved,46) + RVECENT(romReserved,47) + RVECENT(romReserved,48) + RVECENT(romReserved,49) + RVECENT(romReserved,50) + RVECENT(romReserved,51) + RVECENT(romReserved,52) + RVECENT(romReserved,53) + RVECENT(romReserved,54) + RVECENT(romReserved,55) + RVECENT(romReserved,56) + RVECENT(romReserved,57) + RVECENT(romReserved,58) + RVECENT(romReserved,59) + RVECENT(romReserved,60) + RVECENT(romReserved,61) + RVECENT(romReserved,62) + RVECENT(romReserved,63) + XVECENT(romExcHandle,0x200) # bfc00200: R4000 tlbmiss vector + RVECENT(romReserved,65) + RVECENT(romReserved,66) + RVECENT(romReserved,67) + RVECENT(romReserved,68) + RVECENT(romReserved,69) + RVECENT(romReserved,70) + RVECENT(romReserved,71) + RVECENT(romReserved,72) + RVECENT(romReserved,73) + RVECENT(romReserved,74) + RVECENT(romReserved,75) + RVECENT(romReserved,76) + RVECENT(romReserved,77) + RVECENT(romReserved,78) + RVECENT(romReserved,79) + XVECENT(romExcHandle,0x280) # bfc00280: R4000 xtlbmiss vector + RVECENT(romReserved,81) + RVECENT(romReserved,82) + RVECENT(romReserved,83) + RVECENT(romReserved,84) + RVECENT(romReserved,85) + RVECENT(romReserved,86) + RVECENT(romReserved,87) + RVECENT(romReserved,88) + RVECENT(romReserved,89) + RVECENT(romReserved,90) + RVECENT(romReserved,91) + RVECENT(romReserved,92) + RVECENT(romReserved,93) + RVECENT(romReserved,94) + RVECENT(romReserved,95) + XVECENT(romExcHandle,0x300) # bfc00300: R4000 cache vector + RVECENT(romReserved,97) + RVECENT(romReserved,98) + RVECENT(romReserved,99) + RVECENT(romReserved,100) + RVECENT(romReserved,101) + RVECENT(romReserved,102) + RVECENT(romReserved,103) + RVECENT(romReserved,104) + RVECENT(romReserved,105) + RVECENT(romReserved,106) + RVECENT(romReserved,107) + RVECENT(romReserved,108) + RVECENT(romReserved,109) + RVECENT(romReserved,110) +
[U-Boot] [Patch 8/16] add mips64/time.c
diff --git a/arch/mips/cpu/mips64/time.c b/arch/mips/cpu/mips64/time.c
new file mode 100644
index 000..350896a
--- /dev/null
+++ b/arch/mips/cpu/mips64/time.c
@@ -0,0 +1,86 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/mipsregs.h
+
+static unsigned long timestamp;
+
+/* how many counter cycles in a jiffy */
+#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2)
/ CONFIG_SYS_HZ
+
+/*
+ * timer without interrupts
+ */
+
+int timer_init(void)
+{
+ /* Set up the timer for the first expiration. */
+ timestamp = 0;
+ write_c0_compare(read_c0_count() + CYCLES_PER_JIFFY);
+
+ return 0;
+}
+
+ulong get_timer(ulong base)
+{
+ unsigned int count;
+ unsigned int expirelo = read_c0_compare();
+
+ /* Check to see if we have missed any timestamps. */
+ count = read_c0_count();
+ while ((count - expirelo) 0x7fff) {
+ expirelo += CYCLES_PER_JIFFY;
+ timestamp++;
+ }
+ write_c0_compare(expirelo);
+
+ return (timestamp - base);
+}
+
+void __udelay(unsigned long usec)
+{
+ unsigned int tmo;
+
+ tmo = read_c0_count() + (usec * (CONFIG_SYS_MIPS_TIMER_FREQ / 100));
+ while ((tmo - read_c0_count()) 0x7fff)
+ /*NOP*/;
+}
+
+/*
+ * This function is derived from PowerPC code (read timebase as long long).
+ * On MIPS it just returns the timer value.
+ */
+unsigned long long get_ticks(void)
+{
+ return get_timer(0);
+}
+
+/*
+ * This function is derived from PowerPC code (timebase clock frequency).
+ * On MIPS it returns the number of timer ticks per second.
+ */
+ulong get_tbclk(void)
+{
+ return CONFIG_SYS_HZ;
+}
--
Regards,
Zhizhou Zhang
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[U-Boot] [Patch 9/16] make UNCACHED_SDRAM available for mips64
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 3a1e6d6..b768bb5 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -136,7 +136,7 @@ cannot access physical memory directly from core */ #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x2000) #else /* !CONFIG_SOC_AU1X00 */ -#define UNCACHED_SDRAM(a) KSEG1ADDR(a) +#define UNCACHED_SDRAM(a) CKSEG1ADDR(a) #endif /* CONFIG_SOC_AU1X00 */ #endif /* __ASSEMBLY__ */ -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 10/16] add supports to mips64 in io operation
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index 025012a..80eab75 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -120,12 +120,20 @@ static inline void set_io_port_base(unsigned long
base)
*/
extern inline phys_addr_t virt_to_phys(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * phys_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
@@ -133,12 +141,20 @@ extern inline void * phys_to_virt(unsigned long
address)
*/
extern inline unsigned long virt_to_bus(volatile void * address)
{
+#ifndef CONFIG_64BIT
return CPHYSADDR(address);
+#else
+ return XPHYSADDR(address);
+#endif
}
extern inline void * bus_to_virt(unsigned long address)
{
+#ifndef CONFIG_64BIT
return (void *)KSEG0ADDR(address);
+#else
+ return (void *)CKSEG0ADDR(address);
+#endif
}
/*
--
Regards,
Zhizhou Zhang
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[U-Boot] [Patch 13/16] add link script of qemu-mips64
diff --git a/board/qemu-mips/u-boot.lds b/board/qemu-mips/u-boot.lds
index 9460b20..06db68d 100644
--- a/board/qemu-mips/u-boot.lds
+++ b/board/qemu-mips/u-boot.lds
@@ -24,7 +24,11 @@
/*
OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
*/
+#if defined(CONFIG_64BIT)
+OUTPUT_FORMAT(elf64-tradlittlemips, elf64-tradlittlemips,
elf64-tradlittlemips)
+#else
OUTPUT_FORMAT(elf32-tradbigmips, elf32-tradbigmips,
elf32-tradlittlemips)
+#endif
OUTPUT_ARCH(mips)
ENTRY(_start)
SECTIONS
@@ -63,7 +67,11 @@ SECTIONS
}
uboot_end_data = .;
+#if defined(CONFIG_64BIT)
+ num_got_entries = (__got_end - __got_start) 3;
+#else
num_got_entries = (__got_end - __got_start) 2;
+#endif
. = ALIGN(4);
.sbss : { *(.sbss*) }
--
Regards,
Zhizhou Zhang
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[U-Boot] [Patch 12/16] add config about mips64
diff --git a/board/qemu-mips/config.mk b/board/qemu-mips/config.mk index 27cd34a..6a3d7a7 100644 --- a/board/qemu-mips/config.mk +++ b/board/qemu-mips/config.mk @@ -2,9 +2,16 @@ # Qemu -M mips system emulator # See http://fabrice.bellard.free.fr/qemu # +ifeq $(CPU) mips64 +# ROM version +#CONFIG_SYS_TEXT_BASE = 0xFfffFfffbfc0 +# RAM version +CONFIG_SYS_TEXT_BASE = 0x8020 +else # ROM version CONFIG_SYS_TEXT_BASE = 0xbfc0 # RAM version #CONFIG_SYS_TEXT_BASE = 0x80001000 +endif -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 11/16] make size_t equal to unsigned int
err.. maybe a bug of gcc? In my memory, size_t is equaled to unsigned int. diff --git a/arch/mips/include/asm/posix_types.h b/arch/mips/include/asm/posix_types.h index 879aae2..86a866a 100644 --- a/arch/mips/include/asm/posix_types.h +++ b/arch/mips/include/asm/posix_types.h @@ -24,7 +24,11 @@ typedef int __kernel_pid_t; typedef int __kernel_ipc_pid_t; typedef int __kernel_uid_t; typedef int __kernel_gid_t; +#ifndef CONFIG_MIPS64 typedef unsigned int __kernel_size_t; +#else +typedef unsigned long __kernel_size_t; +#endif typedef int __kernel_ssize_t; typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 14/16] add board qemu-mips64
diff --git a/boards.cfg b/boards.cfg index 1af87c0..f368543 100644 --- a/boards.cfg +++ b/boards.cfg @@ -374,6 +374,7 @@ M5485GFE m68kmcf547x_8x m548xevb freescale - M5485HFE m68kmcf547x_8x m548xevbfreescale - M5485EVB:SYS_BUSCLK=1,SYS_BOOTSZ=2,SYS_DRAMSZ=64,SYS_NOR1SZ=16,SYS_VIDEO microblaze-generic microblaze microblaze microblaze-generic xilinx qemu_mipsmipsmips32 qemu-mips - - qemu-mips +qemu_mips64 mipsmips64 qemu-mips - - qemu-mips64 vct_platinum mipsmips32 vct micronas - vct:VCT_PLATINUM vct_platinumavc mipsmips32 vct micronas - vct:VCT_PLATINUMAVC vct_platinumavc_onenand mipsmips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND -- Regards, Zhizhou Zhang ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [Patch 15/16] add standalone link script
diff --git a/examples/standalone/mips64.lds b/examples/standalone/mips64.lds
new file mode 100644
index 000..00b96da
--- /dev/null
+++ b/examples/standalone/mips64.lds
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk Engineering, w...@denx.de
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+OUTPUT_FORMAT(elf32-bigmips, elf32-bigmips, elf32-bigmips)
+*/
+OUTPUT_FORMAT(elf64-tradlittlemips, elf64-tradlittlemips,
elf64-tradlittlemips)
+OUTPUT_ARCH(mips)
+SECTIONS
+{
+ .text :
+ {
+ *(.text*)
+ }
+
+ . = ALIGN(4);
+ .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+ . = ALIGN(4);
+ .data : { *(.data*) }
+
+ . = .;
+ _gp = ALIGN(16) + 0x7ff0;
+
+ .got : {
+ __got_start = .;
+ *(.got)
+ __got_end = .;
+ }
+
+ .sdata : { *(.sdata*) }
+
+ . = ALIGN(4);
+ __bss_start = .;
+ .sbss (NOLOAD) : { *(.sbss*) }
+ .bss (NOLOAD) : { *(.bss*) . = ALIGN(4); }
+
+ _end = .;
+}
--
Regards,
Zhizhou Zhang
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[U-Boot] [Patch 16/16] add configs/qemu-mips64.h
diff --git a/include/configs/qemu-mips64.h b/include/configs/qemu-mips64.h
new file mode 100644
index 000..767d4c3
--- /dev/null
+++ b/include/configs/qemu-mips64.h
@@ -0,0 +1,168 @@
+/*
+ * (C) Copyright 2003
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * This file contains the configuration parameters for qemu-mips64 target.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#define CONFIG_MIPS64 1 /* MIPS64 CPU core */
+#define CONFIG_64BIT 1
+#define CONFIG_QEMU_MIPS 1
+#define CONFIG_MISC_INIT_R
+
+/*IP address is default used by Qemu*/
+#define CONFIG_IPADDR 10.0.2.15 /* Our IP address */
+#define CONFIG_SERVERIP 10.0.2.2 /* Server IP address */
+
+#define CONFIG_BOOTDELAY 10 /* autoboot after 10 seconds */
+
+#define CONFIG_BAUDRATE 115200
+
+/* valid baudrates */
+#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+
+#define CONFIG_TIMESTAMP /* Print image info with timestamp */
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ addmisc=setenv bootargs ${bootargs} \
+ console=ttyS0,${baudrate} \
+ panic=1\0 \
+ bootfile=/tftpboot/vmlinux\0 \
+ load=tftp 8050 ${u-boot}\0 \
+
+
+#define CONFIG_BOOTCOMMAND
+
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_BOOTFILESIZE
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+
+/*
+ * Command line configuration.
+ */
+#include config_cmd_default.h
+#define CONFIG_DP83902A
+
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_EXT2
+#undef CONFIG_CMD_LOADB
+#undef CONFIG_CMD_LOADS
+#define CONFIG_CMD_DHCP
+
+#define CONFIG_DRIVER_NE2000
+#define CONFIG_DRIVER_NE2000_BASE (0xb4000300)
+
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE 1
+#define CONFIG_SYS_NS16550_CLK 115200
+#define CONFIG_SYS_NS16550_COM1 (0xb40003f8)
+#define CONFIG_CONS_INDEX 1
+
+#define CONFIG_CMD_IDE
+#define CONFIG_DOS_PARTITION
+
+#define CONFIG_SYS_IDE_MAXBUS 2
+#define CONFIG_SYS_ATA_IDE0_OFFSET (0x1f0)
+#define CONFIG_SYS_ATA_IDE1_OFFSET (0x170)
+#define CONFIG_SYS_ATA_DATA_OFFSET (0)
+#define CONFIG_SYS_ATA_REG_OFFSET (0)
+#define CONFIG_SYS_ATA_BASE_ADDR (0xb400)
+
+#define CONFIG_SYS_IDE_MAXDEVICE (4)
+
+#define CONFIG_CMD_RARP
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP /* undef to save memory */
+
+#define CONFIG_SYS_PROMPT qemu-mips64 # /* Monitor Command Prompt */
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2
+
+#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
/* Print Buffer Size */
+#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
+
+#define CONFIG_SYS_MALLOC_LEN 128*1024
+
+#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
+
+#define CONFIG_SYS_MHZ 132
+
+#define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 100)
+
+#define CONFIG_SYS_HZ 1000
+
+#define CONFIG_SYS_SDRAM_BASE 0x8000 /* Cached addr */
+
+#define CONFIG_SYS_LOAD_ADDR 0x8100 /* default load address */
+
+#define CONFIG_SYS_MEMTEST_START 0x8010
+#define CONFIG_SYS_MEMTEST_END 0x8080
+
+/*---
+ * FLASH and environment organization
+ */
+#define CONFIG_CMD_NO_FLASH
+#define CONFIG_SYS_NO_FLASH
+#undef CONFIG_CMD_IMLS
+
+/* The following #defines are needed to get flash environment right */
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x40
+#define CONFIG_ENV_IS_NOWHERE 1
+
+/* Address and size of Primary Environment Sector */
+#define CONFIG_ENV_SIZE 0x8000
+
+#define CONFIG_ENV_OVERWRITE 1
+
+#define MEM_SIZE 128
+
+#undef CONFIG_MEMSIZE_IN_BYTES
+
+#define CONFIG_LZA
+
+/*---
+ * Cache Configuration
+ */
+#define CONFIG_SYS_DCACHE_SIZE 16384
+#define CONFIG_SYS_ICACHE_SIZE 16384
+#define CONFIG_SYS_CACHELINE_SIZE 32
+
+#endif /* __CONFIG_H */
--
Regards,
Zhizhou Zhang
