[U-Boot] [PATCH 2/3 v7] S5PC100: Function to configure the SROMC registers.
From: Naveen Krishna CH ch.nav...@samsung.com
Nand Flash, Ethernet, other features might need to configure the
SROMC registers accordingly.
The config_sromc() functions helps with this.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
---
Changes since V1:
1. Funtion config_sromc() is renamed to s5pc1xx_config_sromc().
Comments from Minkyu Kang are fixed
Changes since V2:
1.cpu_is_s5pc100() function is used instead of Macros.
Changes since V3:
1. Comments from Minkyu Kang are fixed.
Changes since V4:
None
Changes since V5:
None
Changes since V6:
None
cpu/arm_cortexa8/s5pc1xx/Makefile |1 +
cpu/arm_cortexa8/s5pc1xx/sromc.c | 53
include/asm-arm/arch-s5pc1xx/smc.h |3 ++
3 files changed, 57 insertions(+), 0 deletions(-)
create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c
diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile
b/cpu/arm_cortexa8/s5pc1xx/Makefile
index 7290c2f..01c93fe 100644
--- a/cpu/arm_cortexa8/s5pc1xx/Makefile
+++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
@@ -34,6 +34,7 @@ SOBJS += reset.o
COBJS += clock.o
COBJS += cpu_info.o
COBJS += gpio.o
+COBJS += sromc.o
COBJS += timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c
new file mode 100644
index 000..380be81
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch ch.nav...@samsung.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/smc.h
+
+/*
+ * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM Bank 0 to 5
+ * smc_bw_conf - SMC Band witdh reg configuration value
+ * smc_bc_conf - SMC Bank Control reg configuration value
+ */
+void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
+{
+ u32 tmp;
+ struct s5pc1xx_smc *srom;
+
+ if (cpu_is_s5pc100())
+ srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE;
+ else
+ srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE;
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom-bw;
+ tmp = ~(0xF (srom_bank * 4));
+ tmp |= smc_bw_conf;
+ srom-bw = tmp;
+
+ /* Configure SMC_BC register */
+ srom-bc[srom_bank] = smc_bc_conf;
+}
diff --git a/include/asm-arm/arch-s5pc1xx/smc.h
b/include/asm-arm/arch-s5pc1xx/smc.h
index e1a5399..88f4ffe 100644
--- a/include/asm-arm/arch-s5pc1xx/smc.h
+++ b/include/asm-arm/arch-s5pc1xx/smc.h
@@ -47,4 +47,7 @@ struct s5pc1xx_smc {
};
#endif /* __ASSEMBLY__ */
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
+
#endif /* __ASM_ARCH_SMC_H_ */
--
1.6.6
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[U-Boot] [PATCH 1/3 v7] S5PC100: Memory SubSystem Header file, register description(SROMC).
From: Naveen Krishna CH ch.nav...@samsung.com
Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
NAND Flash, DDRs.
smc.h is a common place for the register description of Memory subsystem
of S5PC100.
Note: Only SROM related registers are descibed now.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
---
Changes since V1:
1. The header file is renamed to smc.h from smc.h
2. The Macros are renamed according to TRM.
Comments from Minkyu kang are fixed.
Changes since V2:
1. Macros have been modified to be generic.
Comments from Minkyu kang are fixed
Changes since V3:
1. No Changes.
Changes since v4:
1. The header file name int he Description was changed.
Changes since V5:
1. No Changes.
Changes since V6:
1. No Changes.
include/asm-arm/arch-s5pc1xx/smc.h | 50
1 files changed, 50 insertions(+), 0 deletions(-)
create mode 100644 include/asm-arm/arch-s5pc1xx/smc.h
diff --git a/include/asm-arm/arch-s5pc1xx/smc.h
b/include/asm-arm/arch-s5pc1xx/smc.h
new file mode 100644
index 000..e1a5399
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/smc.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch ch.nav...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for Memory subsystem
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *
+ * Only SROMC is defined as of now
+ */
+
+#ifndef __ASM_ARCH_SMC_H_
+#define __ASM_ARCH_SMC_H_
+
+#define SMC_DATA16_WIDTH(x)(1((x*4)+0))
+#define SMC_BYTE_ADDR_MODE(x) (1((x*4)+1)) /* 0- Half-word base address*/
+ /* 1- Byte base address*/
+#define SMC_WAIT_ENABLE(x) (1((x*4)+2))
+#define SMC_BYTE_ENABLE(x) (1((x*4)+3))
+
+#define SMC_BC_TACS(x) (x 28) /* 0clk address set-up */
+#define SMC_BC_TCOS(x) (x 24) /* 4clk chip selection set-up */
+#define SMC_BC_TACC(x) (x 16) /* 14clkaccess cycle */
+#define SMC_BC_TCOH(x) (x 12) /* 1clk chip selection hold */
+#define SMC_BC_TAH(x) (x 8) /* 4clk address holding time */
+#define SMC_BC_TACP(x) (x 4) /* 6clk page mode access cycle */
+#define SMC_BC_PMC(x) (x 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_smc {
+ unsigned intbw;
+ unsigned intbc[6];
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_SMC_H_ */
--
1.6.6
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[U-Boot] [PATCH 2/3 v5] S5PC100: Function to configure the SROMC registers.
From: Naveen Krishna CH ch.nav...@samsung.com
Nand Flash, Ethernet, other features might need to configure the
SROMC registers accordingly.
The config_sromc() functions helps with this.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
---
Changes since V1:
1. Funtion config_sromc() is renamed to s5pc1xx_config_sromc().
Comments from Minkyu Kang are fixed
Changes since V2:
1.cpu_is_s5pc100() function is used instead of Macros.
Changes since V3:
1. Comments from Minkyu Kang are fixed.
Changes since V4:
None
cpu/arm_cortexa8/s5pc1xx/Makefile |1 +
cpu/arm_cortexa8/s5pc1xx/sromc.c | 53
include/asm-arm/arch-s5pc1xx/smc.h |3 ++
3 files changed, 57 insertions(+), 0 deletions(-)
create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c
diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile
b/cpu/arm_cortexa8/s5pc1xx/Makefile
index 7290c2f..01c93fe 100644
--- a/cpu/arm_cortexa8/s5pc1xx/Makefile
+++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
@@ -34,6 +34,7 @@ SOBJS += reset.o
COBJS += clock.o
COBJS += cpu_info.o
COBJS += gpio.o
+COBJS += sromc.o
COBJS += timer.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c
new file mode 100644
index 000..380be81
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch ch.nav...@samsung.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/smc.h
+
+/*
+ * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM Bank 0 to 5
+ * smc_bw_conf - SMC Band witdh reg configuration value
+ * smc_bc_conf - SMC Bank Control reg configuration value
+ */
+void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
+{
+ u32 tmp;
+ struct s5pc1xx_smc *srom;
+
+ if (cpu_is_s5pc100())
+ srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE;
+ else
+ srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE;
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom-bw;
+ tmp = ~(0xF (srom_bank * 4));
+ tmp |= smc_bw_conf;
+ srom-bw = tmp;
+
+ /* Configure SMC_BC register */
+ srom-bc[srom_bank] = smc_bc_conf;
+}
diff --git a/include/asm-arm/arch-s5pc1xx/smc.h
b/include/asm-arm/arch-s5pc1xx/smc.h
index e1a5399..88f4ffe 100644
--- a/include/asm-arm/arch-s5pc1xx/smc.h
+++ b/include/asm-arm/arch-s5pc1xx/smc.h
@@ -47,4 +47,7 @@ struct s5pc1xx_smc {
};
#endif /* __ASSEMBLY__ */
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
+
#endif /* __ASM_ARCH_SMC_H_ */
--
1.6.6
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[U-Boot] [PATCH 3/3 v5] SAMSUNG: SMDKC100: Adds ethernet support.
From: Naveen Krishna CH ch.nav...@samsung.com
Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be
loaded over tftp.
The preinit function will configure GPIO (GPK0CON) SROMC to look
for environment in SROM Bank 3.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
---
Changes since V1:
1. The CONFIG_BOOTP* and Net config Macros are removed from config header.
Comments from Ben Warren are fixed
2. The GPIO configuration is modified Macro and Function are renamed.
Comments from Minkyu Kang are fixedChanges since V2
Changes since V2:
1. GPIO configurations function has been implemented.
Changes since V3:
1. Comments from Minkyu Kang are fixed.
Changes since V4:
None
board/samsung/smdkc100/smdkc100.c | 39 +
include/configs/smdkc100.h| 12 ++-
2 files changed, 50 insertions(+), 1 deletions(-)
diff --git a/board/samsung/smdkc100/smdkc100.c
b/board/samsung/smdkc100/smdkc100.c
index 15a1a27..4fc802e 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -23,10 +23,40 @@
*/
#include common.h
+#include asm/io.h
+#include asm/arch/smc.h
+#include asm/arch/gpio.h
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+static void smc9115_pre_init(void)
+{
+ u32 tmp;
+ u32 smc_bw_conf, smc_bc_conf;
+
+ struct s5pc100_gpio *const gpio =
+ (struct s5pc100_gpio *)S5PC100_GPIO_BASE;
+
+ /* gpio configuration GPK0CON */
+ gpio_cfg_pin(gpio-gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+
+ /* Ethernet needs bus width of 16 bits */
+ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+ smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
+ | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
+ | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
+
+ /* Select and configure the SROMC bank */
+ s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
int board_init(void)
{
+ smc9115_pre_init();
+
gd-bd-bi_arch_number = MACH_TYPE_SMDKC100;
gd-bd-bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -49,3 +79,12 @@ int checkboard(void)
return 0;
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index f12fea3..c8abad6 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -83,7 +83,6 @@
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_NET
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
@@ -235,4 +234,15 @@
#define CONFIG_DOS_PARTITION 1
+/*
+ * Ethernet Contoller driver
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1 /* we have a SMC9115 on-board */
+#define CONFIG_SMC911X_16_BIT 1 /* SMC911X_16_BIT Mode */
+#define CONFIG_SMC911X_BASE0x98800300 /* SMC911X Drive Base */
+#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/
+#endif /* CONFIG_CMD_NET */
+
#endif /* __CONFIG_H */
--
1.6.6
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[U-Boot] [PATCH 1/3 v4] S5PC100: Memory SubSystem Header file, register description(SROMC).
From: Naveen Krishna CH ch.nav...@samsung.com
Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
NAND Flash, DDRs.
mem.h is a common place for the register description of Memory subsystem
of S5PC100.
Note: Only SROM related registers are descibed now.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
---
Changes since V1:
1. The header file is renamed to smc.h from mem.h
2. The Macros are renamed according to TRM.
Comments from Minkyu kang are fixed.
Changes since V2:
1. Macros have been modified to be generic.
Comments from Minkyu kang are fixed
Changes since V3:
1. No Changes.
include/asm-arm/arch-s5pc1xx/smc.h | 50
1 files changed, 50 insertions(+), 0 deletions(-)
create mode 100644 include/asm-arm/arch-s5pc1xx/smc.h
diff --git a/include/asm-arm/arch-s5pc1xx/smc.h
b/include/asm-arm/arch-s5pc1xx/smc.h
new file mode 100644
index 000..e1a5399
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/smc.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch ch.nav...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for Memory subsystem
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *
+ * Only SROMC is defined as of now
+ */
+
+#ifndef __ASM_ARCH_SMC_H_
+#define __ASM_ARCH_SMC_H_
+
+#define SMC_DATA16_WIDTH(x)(1((x*4)+0))
+#define SMC_BYTE_ADDR_MODE(x) (1((x*4)+1)) /* 0- Half-word base address*/
+ /* 1- Byte base address*/
+#define SMC_WAIT_ENABLE(x) (1((x*4)+2))
+#define SMC_BYTE_ENABLE(x) (1((x*4)+3))
+
+#define SMC_BC_TACS(x) (x 28) /* 0clk address set-up */
+#define SMC_BC_TCOS(x) (x 24) /* 4clk chip selection set-up */
+#define SMC_BC_TACC(x) (x 16) /* 14clkaccess cycle */
+#define SMC_BC_TCOH(x) (x 12) /* 1clk chip selection hold */
+#define SMC_BC_TAH(x) (x 8) /* 4clk address holding time */
+#define SMC_BC_TACP(x) (x 4) /* 6clk page mode access cycle */
+#define SMC_BC_PMC(x) (x 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_smc {
+ unsigned intbw;
+ unsigned intbc[6];
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_SMC_H_ */
--
1.6.6
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[U-Boot] [PATCH 3/3 v4] SAMSUNG: SMDKC100: Adds ethernet support.
From: Naveen Krishna CH ch.nav...@samsung.com
Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be
loaded over tftp.
The preinit function will configure GPIO (GPK0CON) SROMC to look
for environment in SROM Bank 3.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
---
Changes since V1:
1. The CONFIG_BOOTP* and Net config Macros are removed from config header.
Comments from Ben Warren are fixed
2. The GPIO configuration is modified Macro and Function are renamed.
Comments from Minkyu Kang are fixedChanges since V2
Changes since V2:
1. GPIO configurations function has been implemented.
Changes since V3:
1. Comments from Minkyu Kang are fixed.
board/samsung/smdkc100/smdkc100.c | 39 +
include/configs/smdkc100.h| 12 ++-
2 files changed, 50 insertions(+), 1 deletions(-)
diff --git a/board/samsung/smdkc100/smdkc100.c
b/board/samsung/smdkc100/smdkc100.c
index 15a1a27..4fc802e 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -23,10 +23,40 @@
*/
#include common.h
+#include asm/io.h
+#include asm/arch/smc.h
+#include asm/arch/gpio.h
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+static void smc9115_pre_init(void)
+{
+ u32 tmp;
+ u32 smc_bw_conf, smc_bc_conf;
+
+ struct s5pc100_gpio *const gpio =
+ (struct s5pc100_gpio *)S5PC100_GPIO_BASE;
+
+ /* gpio configuration GPK0CON */
+ gpio_cfg_pin(gpio-gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+
+ /* Ethernet needs bus width of 16 bits */
+ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+ smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe)
+ | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
+ | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
+
+ /* Select and configure the SROMC bank */
+ s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
int board_init(void)
{
+ smc9115_pre_init();
+
gd-bd-bi_arch_number = MACH_TYPE_SMDKC100;
gd-bd-bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -49,3 +79,12 @@ int checkboard(void)
return 0;
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index f12fea3..c8abad6 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -83,7 +83,6 @@
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_NET
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
@@ -235,4 +234,15 @@
#define CONFIG_DOS_PARTITION 1
+/*
+ * Ethernet Contoller driver
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1 /* we have a SMC9115 on-board */
+#define CONFIG_SMC911X_16_BIT 1 /* SMC911X_16_BIT Mode */
+#define CONFIG_SMC911X_BASE0x98800300 /* SMC911X Drive Base */
+#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/
+#endif /* CONFIG_CMD_NET */
+
#endif /* __CONFIG_H */
--
1.6.6
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[U-Boot] [PATCH 1/3 v3] S5PC100: Memory SubSystem Header file, register description(SROMC).
From: Naveen Krishna CH ch.nav...@samsung.com
Memory subsystem of S5PC100 handles SROM, SRAM, OneDRAM, OneNand,
NAND Flash, DDRs.
mem.h is a common place for the register description of Memory subsystem
of S5PC100.
Note: Only SROM related registers are descibed now.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
---
Changes since V1:
1. The header file is renamed to smc.h from mem.h
2. The Macros are renamed according to TRM.
Comments from Minkyu kang are fixed.
Changes since V2:
1. Macros have been modified to be generic.
Comments from Minkyu kang are fixed
include/asm-arm/arch-s5pc1xx/smc.h | 50
1 files changed, 50 insertions(+), 0 deletions(-)
create mode 100644 include/asm-arm/arch-s5pc1xx/smc.h
diff --git a/include/asm-arm/arch-s5pc1xx/smc.h
b/include/asm-arm/arch-s5pc1xx/smc.h
new file mode 100644
index 000..e1a5399
--- /dev/null
+++ b/include/asm-arm/arch-s5pc1xx/smc.h
@@ -0,0 +1,50 @@
+/*
+ * (C) Copyright 2010 Samsung Electronics
+ * Naveen Krishna Ch ch.nav...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: This file contains the register description for Memory subsystem
+ * (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
+ *
+ * Only SROMC is defined as of now
+ */
+
+#ifndef __ASM_ARCH_SMC_H_
+#define __ASM_ARCH_SMC_H_
+
+#define SMC_DATA16_WIDTH(x)(1((x*4)+0))
+#define SMC_BYTE_ADDR_MODE(x) (1((x*4)+1)) /* 0- Half-word base address*/
+ /* 1- Byte base address*/
+#define SMC_WAIT_ENABLE(x) (1((x*4)+2))
+#define SMC_BYTE_ENABLE(x) (1((x*4)+3))
+
+#define SMC_BC_TACS(x) (x 28) /* 0clk address set-up */
+#define SMC_BC_TCOS(x) (x 24) /* 4clk chip selection set-up */
+#define SMC_BC_TACC(x) (x 16) /* 14clkaccess cycle */
+#define SMC_BC_TCOH(x) (x 12) /* 1clk chip selection hold */
+#define SMC_BC_TAH(x) (x 8) /* 4clk address holding time */
+#define SMC_BC_TACP(x) (x 4) /* 6clk page mode access cycle */
+#define SMC_BC_PMC(x) (x 0) /* normal(1data)page mode configuration */
+
+#ifndef __ASSEMBLY__
+struct s5pc1xx_smc {
+ unsigned intbw;
+ unsigned intbc[6];
+};
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARCH_SMC_H_ */
--
1.6.6
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[U-Boot] [PATCH 2/3 v3] S5PC100: Function to configure the SROMC registers.
From: Naveen Krishna CH ch.nav...@samsung.com
Nand Flash, Ethernet, other features might need to configure the
SROMC registers accordingly.
The config_sromc() functions helps with this.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
---
Changes since V1:
1. Funtion config_sromc() is renamed to s5pc1xx_config_sromc().
Comments from Minkyu Kang are fixed
Changes since V2:
1.cpu_is_s5pc100() function is used instead of Macros.
cpu/arm_cortexa8/s5pc1xx/Makefile |1 +
cpu/arm_cortexa8/s5pc1xx/sromc.c | 53
include/asm-arm/arch-s5pc1xx/smc.h |3 ++
3 files changed, 57 insertions(+), 0 deletions(-)
create mode 100644 cpu/arm_cortexa8/s5pc1xx/sromc.c
diff --git a/cpu/arm_cortexa8/s5pc1xx/Makefile
b/cpu/arm_cortexa8/s5pc1xx/Makefile
index 4f922e6..0a6a9b4 100644
--- a/cpu/arm_cortexa8/s5pc1xx/Makefile
+++ b/cpu/arm_cortexa8/s5pc1xx/Makefile
@@ -34,6 +34,7 @@ SOBJS += reset.o
COBJS += clock.o
COBJS += cpu_info.o
COBJS += timer.o
+COBJS += sromc.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
diff --git a/cpu/arm_cortexa8/s5pc1xx/sromc.c b/cpu/arm_cortexa8/s5pc1xx/sromc.c
new file mode 100644
index 000..7630367
--- /dev/null
+++ b/cpu/arm_cortexa8/s5pc1xx/sromc.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (C) 2010 Samsung Electronics
+ * Naveen Krishna Ch ch.nav...@samsung.com
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include common.h
+#include asm/io.h
+#include asm/arch/smc.h
+
+/*
+ * s5pc1xx_config_sromc() - select the proper SROMC Bank and configure the
+ * band width control and bank control registers
+ * srom_bank - SROM Bank 0 to 5
+ * smc_bw_conf - SMC Band witdh reg configuration value
+ * smc_bc_conf - SMC Bank Control reg configuration value
+ */
+void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf)
+{
+ u32 tmp;
+ struct s5pc1xx_smc *srom;
+
+ if (cpu_is_s5pc100())
+ srom = (struct s5pc1xx_smc *)S5PC100_SROMC_BASE;
+ else
+ srom = (struct s5pc1xx_smc *)S5PC110_SROMC_BASE;
+
+ /* Configure SMC_BW register to handle proper SROMC bank */
+ tmp = srom-bw;
+ tmp = ~(0xF (srom_bank * 4));
+ tmp |= smc_bw_conf;
+ srom-bw = tmp;
+
+ /* Configure SMC_BC register */
+ srom-bc[srom_bank] = smc_bc_conf;
+}
diff --git a/include/asm-arm/arch-s5pc1xx/smc.h
b/include/asm-arm/arch-s5pc1xx/smc.h
index e1a5399..88f4ffe 100644
--- a/include/asm-arm/arch-s5pc1xx/smc.h
+++ b/include/asm-arm/arch-s5pc1xx/smc.h
@@ -47,4 +47,7 @@ struct s5pc1xx_smc {
};
#endif /* __ASSEMBLY__ */
+/* Configure the Band Width and Bank Control Regs for required SROMC Bank */
+void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
+
#endif /* __ASM_ARCH_SMC_H_ */
--
1.6.6
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[U-Boot] [PATCH 3/3 v3] SAMSUNG: SMDKC100: Adds ethernet support.
From: Naveen Krishna CH ch.nav...@samsung.com
Add setup for ethernet on SMDKC100, allowing kernel/ramdisk to be
loaded over tftp.
The preinit function will configure GPIO (GPK0CON) SROMC to look
for environment in SROM Bank 3.
Signed-off-by: Naveen Krishna Ch ch.nav...@samsung.com
---
Changes since V1:
1. The CONFIG_BOOTP* and Net config Macros are removed from config header.
Comments from Ben Warren are fixed
2. The GPIO configuration is modified Macro and Function are renamed.
Comments from Minkyu Kang are fixedChanges since V2
Changes since V2:
1. GPIO configurations function has been implemented.
board/samsung/smdkc100/smdkc100.c | 39 +
include/configs/smdkc100.h| 13 +++-
2 files changed, 51 insertions(+), 1 deletions(-)
diff --git a/board/samsung/smdkc100/smdkc100.c
b/board/samsung/smdkc100/smdkc100.c
index 15a1a27..946f7af 100644
--- a/board/samsung/smdkc100/smdkc100.c
+++ b/board/samsung/smdkc100/smdkc100.c
@@ -23,10 +23,40 @@
*/
#include common.h
+#include asm/io.h
+#include asm/arch/smc.h
+#include asm/arch/gpio.h
+
DECLARE_GLOBAL_DATA_PTR;
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+static void smc9115_pre_init(void)
+{
+ u32 tmp;
+ u32 smc_bw_conf, smc_bc_conf;
+
+ struct s5pc100_gpio *const gpio =
+ (struct s5pc100_gpio *)S5PC100_GPIO_BASE;
+
+ /* gpio configuration GPK0CON */
+ gpio_cfg_pin(gpio-gpio_k0, CONFIG_ENV_SROM_BANK, GPIO_FUNC(2));
+
+ /* Ethernet needs bus width of 16 bits */
+ smc_bw_conf = SMC_DATA16_WIDTH(CONFIG_ENV_SROM_BANK);
+ smc_bc_conf = SMC_BC_TACS(0x0) | SMC_BC_TCOS(0x4) | SMC_BC_TACC(0xe) \
+ | SMC_BC_TCOH(0x1) | SMC_BC_TAH(0x4)
+ | SMC_BC_TACP(0x6) | SMC_BC_PMC(0x0);
+
+ /* Select and configure the SROMC bank */
+ s5pc1xx_config_sromc(CONFIG_ENV_SROM_BANK, smc_bw_conf, smc_bc_conf);
+}
+
int board_init(void)
{
+ smc9115_pre_init();
+
gd-bd-bi_arch_number = MACH_TYPE_SMDKC100;
gd-bd-bi_boot_params = PHYS_SDRAM_1 + 0x100;
@@ -49,3 +79,12 @@ int checkboard(void)
return 0;
}
#endif
+
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0;
+#ifdef CONFIG_SMC911X
+ rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
+#endif
+ return rc;
+}
diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h
index f12fea3..22e8e95 100644
--- a/include/configs/smdkc100.h
+++ b/include/configs/smdkc100.h
@@ -83,7 +83,7 @@
#undef CONFIG_CMD_FLASH
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NAND
-#undef CONFIG_CMD_NET
+#define CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_REGINFO
@@ -235,4 +235,15 @@
#define CONFIG_DOS_PARTITION 1
+/*
+ * Ethernet Contoller driver
+ */
+#ifdef CONFIG_CMD_NET
+#define CONFIG_NET_MULTI
+#define CONFIG_SMC911X 1 /* we have a SMC9115 on-board */
+#define CONFIG_SMC911X_16_BIT 1 /* SMC911X_16_BIT Mode */
+#define CONFIG_SMC911X_BASE0x98800300 /* SMC911X Drive Base */
+#define CONFIG_ENV_SROM_BANK 3 /* Select SROM Bank-3 for Ethernet*/
+#endif /* CONFIG_CMD_NET */
+
#endif /* __CONFIG_H */
--
1.6.6
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