Re: [RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability
在 2023-07-12星期三的 14:13 +0100，Maciej W. Rozycki写道： > On Wed, 28 Jun 2023, Icenowy Zheng wrote: > > > When building the package `rustc` for AOSC OS on HiFive Unmatched, > > random SIGSEGV prevents the package from getting correctly built. > > Downclocking the CPU PLL clock seems to allow rustc to be built, > > although taking much more time. > > > > Downclock the CPU PLL frequency for stability. > > FYI, I've been observing occasional (less than 1 bit per 10GiB of > data > moved) single-bit data corruption on DRAM writes with my HiFive > Unmatched, > but your change does not appear to make any difference with my > system. > > FWIW, given the price and amount of DRAM used I think it makes no > sense > to build computers equipped with a DRAM subsystem without ECC > nowadays. Well the HiFive Unmatched board looks like it has a DRAM chip for ECC, but whether this is activated is not known... > > Maciej
[RFC PATCH] riscv: sifive: fu70: downclock CPU clock for stability
When building the package `rustc` for AOSC OS on HiFive Unmatched,
random SIGSEGV prevents the package from getting correctly built.
Downclocking the CPU PLL clock seems to allow rustc to be built,
although taking much more time.
Downclock the CPU PLL frequency for stability.
Signed-off-by: Icenowy Zheng
---
arch/riscv/dts/fu740-c000-u-boot.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi
b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index 706224b384..6b80cab588 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -8,7 +8,7 @@
/ {
cpus {
assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
- assigned-clock-rates = <12>;
+ assigned-clock-rates = <98800>;
bootph-pre-ram;
cpu0: cpu@0 {
clocks = <&prci FU740_PRCI_CLK_COREPLL>;
--
2.39.1
Re: [PATCH 0/8] SUNIV SPI NAND support in SPL
在 2023-06-05星期一的 15:03 -0600，Sam Edwards写道： > Hey hey Icenowy, > > On 10/13/22 21:05, Icenowy Zheng wrote: > > This patchset tries to extend SPI-based boot code in sunxi SPL to > > support SPI NAND, following the same principle with current SPI NOR > > code > > (mimicking the behavior of sunxi BROM). > > Thank you for your work on this patchset; it works great on T113 as > well! Note that I have had to apply an extra patch to resolve a > bootloop > of "Unknown boot source 4" (find the patch below). > > Also, since on both SUNXI and SUNIV the SPL knows whether it came > from > NOR or NAND, perhaps it would be better to break apart > BOOT_DEVICE_SPI/spl_spi_load_image into specific NOR and NAND > variants, > as opposed to the current try-NAND-then-NOR approach? Well it depends on whether all SoCs differienate between SPI NOR and SPI NAND. Do you have any suggestion on as many chips models as possible boards with SPI NAND? > > Cheers (and thanks again), > Sam > > -- > > diff --git a/arch/arm/include/asm/arch-sunxi/spl.h > b/arch/arm/include/asm/arch-sunxi/spl.h > index 14944a20ea..703aa70a49 100644 > --- a/arch/arm/include/asm/arch-sunxi/spl.h > +++ b/arch/arm/include/asm/arch-sunxi/spl.h > @@ -12,10 +12,11 @@ > #define SPL_ADDR CONFIG_SUNXI_SRAM_ADDRESS > > /* The low 8-bits of the 'boot_media' field in the SPL header */ > -#define SUNXI_BOOTED_FROM_MMC0 0 > -#define SUNXI_BOOTED_FROM_NAND 1 > -#define SUNXI_BOOTED_FROM_MMC2 2 > -#define SUNXI_BOOTED_FROM_SPI 3 > +#define SUNXI_BOOTED_FROM_MMC0 0 > +#define SUNXI_BOOTED_FROM_NAND 1 > +#define SUNXI_BOOTED_FROM_MMC2 2 > +#define SUNXI_BOOTED_FROM_SPI 3 > +#define SUNXI_BOOTED_FROM_SPI_NAND 4 > #define SUNXI_BOOTED_FROM_MMC0_HIGH 0x10 > #define SUNXI_BOOTED_FROM_MMC2_HIGH 0x12 > > diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach- > sunxi/board.c > index a48f5aaa05..9bbd0753e6 100644 > --- a/arch/arm/mach-sunxi/board.c > +++ b/arch/arm/mach-sunxi/board.c > @@ -298,6 +298,7 @@ uint32_t sunxi_get_boot_device(void) > case SUNXI_BOOTED_FROM_MMC2_HIGH: > return BOOT_DEVICE_MMC2; > case SUNXI_BOOTED_FROM_SPI: > + case SUNXI_BOOTED_FROM_SPI_NAND: > return BOOT_DEVICE_SPI; > } >
Re: [PATCH 7/8] [DO NOT MERGE, DIRTY HACK] sunxi: use UBI for environement storage
在 2022-10-14星期五的 11:05 +0800，Icenowy Zheng写道：
> Signed-off-by: Icenowy Zheng
By the way should we have some better way to handle the placement of
environments?
> ---
> board/sunxi/board.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> index 21a2407e06..f4138573d4 100644
> --- a/board/sunxi/board.c
> +++ b/board/sunxi/board.c
> @@ -133,6 +133,7 @@ void i2c_init_board(void)
> */
> enum env_location env_get_location(enum env_operation op, int prio)
> {
> + return prio ? ENVL_UNKNOWN : ENVL_UBI;
> if (prio > 1)
> return ENVL_UNKNOWN;
>
Re: [PATCH 3/8] sunxi: SPL SPI: allow multiple boot attempt
于 2023年1月15日 GMT+08:00 上午3:56:08, Samuel Holland 写到:
>On 10/13/22 22:05, Icenowy Zheng wrote:
>> As we're going to add support for SPI NAND to this code, add code that
>> allows multiple boot attempts with different load offsets and functions.
>>
>> To keep compatibility with loading raw binary on SPI NOR, a bool
>> parameter is used to allow booting without valid magic number when
>> booting with SPI NOR.
>
>So the issue is that when CONFIG_SPL_RAW_IMAGE_SUPPORT=y, then
>spl_parse_image_header() will return 0 even when using the wrong NAND
>parameters? I don't see a better solution, so:
Good point, maybe the next patch needs to add some dependency
of raw image support to SPI NAND support option.
>
>Reviewed-by: Samuel Holland
>Tested-by: Samuel Holland # Orange Pi Zero Plus
>
>> Signed-off-by: Icenowy Zheng
>> ---
>> arch/arm/mach-sunxi/spl_spi_sunxi.c | 58 +++--
>> 1 file changed, 38 insertions(+), 20 deletions(-)
>>
>> diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
>> b/arch/arm/mach-sunxi/spl_spi_sunxi.c
>> index 88c15a3ee9..21be33a23f 100644
>> --- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
>> +++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
>> @@ -340,8 +340,8 @@ static void spi0_read_data(void *buf, u32 addr, u32 len,
>> u32 addr_len)
>> }
>> }
>>
>> -static ulong spi_load_read(struct spl_load_info *load, ulong sector,
>> - ulong count, void *buf)
>> +static ulong spi_load_read_nor(struct spl_load_info *load, ulong sector,
>> + ulong count, void *buf)
>> {
>> spi0_read_data(buf, sector, count, 3);
>>
>> @@ -350,41 +350,59 @@ static ulong spi_load_read(struct spl_load_info *load,
>> ulong sector,
>>
>>
>> /*/
>>
>> -static int spl_spi_load_image(struct spl_image_info *spl_image,
>> - struct spl_boot_device *bootdev)
>> +static int spl_spi_try_load(struct spl_image_info *spl_image,
>> +struct spl_boot_device *bootdev,
>> +struct spl_load_info *load, u32 offset,
>> +bool allow_raw)
>> {
>> int ret = 0;
>> struct legacy_img_hdr *header;
>> -uint32_t load_offset = sunxi_get_spl_size();
>> -
>
>nit: keep this blank line
>
>> header = (struct legacy_img_hdr *)CONFIG_SYS_TEXT_BASE;
>> -load_offset = max_t(uint32_t, load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS);
>> -
>> -spi0_init();
>>
>> -spi0_read_data((void *)header, load_offset, 0x40, 3);
>> +if (load->read(load, offset, 0x40, (void *)header) == 0)
>> +return -EINVAL;
>>
>> if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
>> image_get_magic(header) == FDT_MAGIC) {
>> -struct spl_load_info load;
>>
>> debug("Found FIT image\n");
>> -load.dev = NULL;
>> -load.priv = NULL;
>> -load.filename = NULL;
>> -load.bl_len = 1;
>> -load.read = spi_load_read;
>> -ret = spl_load_simple_fit(spl_image, &load,
>> - load_offset, header);
>> +ret = spl_load_simple_fit(spl_image, load,
>> + offset, header);
>> } else {
>> +if (!allow_raw && image_get_magic(header) != IH_MAGIC)
>> +return -EINVAL;
>> +
>> ret = spl_parse_image_header(spl_image, bootdev, header);
>> if (ret)
>> return ret;
>>
>> -spi0_read_data((void *)spl_image->load_addr,
>> - load_offset, spl_image->size, 3);
>> +if (load->read(load, offset, spl_image->size,
>> + (void *)spl_image->load_addr) == 0)
>> +ret = -EINVAL;
>> }
>>
>> +return ret;
>> +}
>> +
>> +static int spl_spi_load_image(struct spl_image_info *spl_image,
>> + struct spl_boot_device *bootdev)
>> +{
>> +int ret = 0;
>> +uint32_t load_offset = sunxi_get_spl_size();
>> +struct spl_load_info load;
>> +
>> +load_offset = max_t(uint32_t, load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS);
>> +
>> +load.dev = NULL;
>> +load.priv = NULL;
>> +load.filename = NULL;
>> +load.bl_len = 1;
>> +
>> +spi0_init();
>> +
>> +load.read = spi_load_read_nor;
>> +ret = spl_spi_try_load(spl_image, bootdev, &load, load_offset, true);
>> +
>> spi0_deinit();
>>
>> return ret;
>
Re: [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub
在 2023-01-03星期二的 17:38 +，Andre Przywara写道：
> On Tue, 06 Dec 2022 13:55:02 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > 在 2022-12-06星期二的 00:45 +，Andre Przywara写道：
> > > This adds the basic SoC .dtsi devicetree stub for the Allwinner
> > > T113s
> > > SoC. This shares a die with the Allwinner D1 SoC (with RISC-V
> > > cores),
> > > but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V
> > > core.
> > >
> > > Include the existing D1 devicetree stub, but add the ARM specific
> > > nodes,
> > > like for the CPU, the arch timer and the GIC.
> > >
> > > Signed-off-by: Andre Przywara
> > > ---
> > > arch/arm/dts/sun8i-t113s.dtsi | 59
> > > +++
> > > 1 file changed, 59 insertions(+)
> > > create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
> > >
> > > diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-
> > > t113s.dtsi
> > > new file mode 100644
> > > index 000..0919ce559f6
> > > --- /dev/null
> > > +++ b/arch/arm/dts/sun8i-t113s.dtsi
> > > @@ -0,0 +1,59 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> > > +// Copyright (C) 2022 Arm Ltd.
> > > +
> > > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
> > > +
> > > +#include
> > > +#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
> >
> > Should we make a R528 DTSI which includes d1-t113.dtsi, and then
> > T113
> > DTSI which includes d1s-t113.dtsi ?
>
> If I understand Samuel correctly, the T113-s includes the DSP, in
> contrast
> to the D1s, which has fused that off.
> That would make including both sunxi-d1*-t113.dtsi files the right
> choice,
> wouldn't it? According to Samuel's list, sunxi-d1-t113.dtsi contains
> DSP
> related peripherals.
Okay, although I heard that the DSP is not fused off (because DSP RAM
is used by BROM).
>
> I don't know if there is anything DT relevant that the R528 has over
> the
> T113-s, but I don't claim to provide an R528 DT anyway, at least not
> yet,
> so we can leave this for the future, should a board or manual emerge.
>
> So this file here should to be the equivalent of sun20i-d1s.dtsi,
> providing the ARM specific bits.
>
> Does that make sense? If you agree, I would post this to Linux ASAP.
It sounds good.
>
> Cheers,
> Andre
>
>
> > > +#include <../../riscv/dts/sunxi-d1-t113.dtsi>
> > > +
> > > +/ {
> > > + interrupt-parent = <&gic>;
> > > +
> > > + cpus {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + cpu0: cpu@0 {
> > > + compatible = "arm,cortex-a7";
> > > + device_type = "cpu";
> > > + reg = <0>;
> > > + clocks = <&ccu CLK_CPUX>;
> > > + clock-names = "cpu";
> > > + };
> > > +
> > > + cpu1: cpu@1 {
> > > + compatible = "arm,cortex-a7";
> > > + device_type = "cpu";
> > > + reg = <1>;
> > > + clocks = <&ccu CLK_CPUX>;
> > > + clock-names = "cpu";
> > > + };
> > > + };
> > > +
> > > + gic: interrupt-controller@1c81000 {
> > > + compatible = "arm,gic-400";
> > > + reg = <0x03021000 0x1000>,
> > > + <0x03022000 0x2000>,
> > > + <0x03024000 0x2000>,
> > > + <0x03026000 0x2000>;
> > > + interrupts = > > |
> > > IRQ_TYPE_LEVEL_HIGH)>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <3>;
> > > + };
> > > +
> > > + timer {
> > > + compatible = "arm,armv7-timer";
> > > + interrupts = > > |
> > > IRQ_TYPE_LEVEL_LOW)>,
> > > + > > |
> > > IRQ_TYPE_LEVEL_LOW)>,
> > > + > > |
> > > IRQ_TYPE_LEVEL_LOW)>,
> > > + > > |
> > > IRQ_TYPE_LEVEL_LOW)>;
> > > + };
> > > +
> > > + pmu {
> > > + compatible = "arm,cortex-a7-pmu";
> > > + interrupts = ,
> > > + ;
> > > + interrupt-affinity = <&cpu0>, <&cpu1>;
> > > + };
> > > +};
> >
>
Re: [RFC PATCH 2/2] sunxi: add R528/T113-s3/D1(s) DRAM initialisation code
在 2023-01-03星期二的 01:17 +，Andre Przywara写道： > The Allwinner R528/T113-s/D1/D1s SoCs all share the same die, so use > the > same DRAM initialisation code. > Make use of prior art here and lift some code from awboot[1], which > carried init code based on earlier decompilation efforts, but with a > GPL2 license tag. > This code has been heavily reworked and cleaned up, to match previous > DRAM routines for other SoCs, and also to be closer to U-Boot's > coding > style and support routines. > The actual DRAM chip timing parameters are included in the main file, > since they cover all DRAM types, and are protected by a new Kconfig > CONFIG_SUNXI_DRAM_TYPE symbol, which allows the compiler to pick only > the relevant settings, at build time. > > The relevant DRAM chips/board specific configuration parameters are > delivered via Kconfig, so this code here should work for all > supported > SoCs and DRAM chips combinations. The D1 DRAM controller should be similar to the R329 one, which I added (legacy) support at [1]. [1] https://patchwork.ozlabs.org/project/uboot/patch/20210722063015.421923-8-icen...@sipeed.com/ > > Signed-off-by: Andre Przywara > --- > drivers/Makefile | 1 + > drivers/ram/Makefile | 2 + > drivers/ram/sunxi/Kconfig | 55 ++ > drivers/ram/sunxi/Makefile | 4 + > drivers/ram/sunxi/dram_sun20i_d1.c | 1425 > > drivers/ram/sunxi/dram_sun20i_d1.h | 70 ++ > 6 files changed, 1557 insertions(+) > create mode 100644 drivers/ram/sunxi/Makefile > create mode 100644 drivers/ram/sunxi/dram_sun20i_d1.c > create mode 100644 drivers/ram/sunxi/dram_sun20i_d1.h > > diff --git a/drivers/Makefile b/drivers/Makefile > index 6f1de58e003..6a0d1ec2ff0 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -52,6 +52,7 @@ obj-$(CONFIG_$(SPL_)ALTERA_SDRAM) += ddr/altera/ > obj-$(CONFIG_ARCH_IMX8M) += ddr/imx/imx8m/ > obj-$(CONFIG_IMX8ULP_DRAM) += ddr/imx/imx8ulp/ > obj-$(CONFIG_ARCH_IMX9) += ddr/imx/imx9/ > +obj-$(CONFIG_DRAM_SUN8I_R528) += ram/ > obj-$(CONFIG_SPL_DM_RESET) += reset/ > obj-$(CONFIG_SPL_MUSB_NEW) += usb/musb-new/ > obj-$(CONFIG_SPL_USB_GADGET) += usb/gadget/ > diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile > index 5a39611349d..82686046f1d 100644 > --- a/drivers/ram/Makefile > +++ b/drivers/ram/Makefile > @@ -21,4 +21,6 @@ obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o > > obj-$(CONFIG_RAM_SIFIVE) += sifive/ > > +obj-$(CONFIG_DRAM_SUN8I_R528) += sunxi/ > + > obj-$(CONFIG_ARCH_OCTEON) += octeon/ > diff --git a/drivers/ram/sunxi/Kconfig b/drivers/ram/sunxi/Kconfig > index 97e261de542..36875ddf22d 100644 > --- a/drivers/ram/sunxi/Kconfig > +++ b/drivers/ram/sunxi/Kconfig > @@ -11,3 +11,58 @@ config DRAM_SUN8I_R528 > default y if MACH_SUN8I_R528 > help > Select this DRAM controller driver for the R528/T113s SoCs. > + > +config DRAM_SUNXI_ODT_EN > + hex "DRAM ODT EN parameter" > + default 0x1 > + help > + ODT EN value from vendor DRAM settings. > + > +config DRAM_SUNXI_TPR0 > + hex "DRAM TPR0 parameter" > + default 0x0 > + help > + TPR0 value from vendor DRAM settings. > + > +config DRAM_SUNXI_TPR11 > + hex "DRAM TPR11 parameter" > + default 0x0 > + help > + TPR11 value from vendor DRAM settings. > + > +config DRAM_SUNXI_TPR12 > + hex "DRAM TPR12 parameter" > + default 0x0 > + help > + TPR12 value from vendor DRAM settings. > + > +config DRAM_SUNXI_TPR13 > + hex "DRAM TPR13 parameter" > + default 0x0 > + help > + TPR13 value from vendor DRAM settings. It tells which > features > + should be configured. > + > +choice > + prompt "DRAM chip type" > + default SUNXI_DRAM_DDR3 if DRAM_SUN8I_R528 || DRAM_SUN20I_D1 > + > +config SUNXI_DRAM_DDR2 > + bool "DDR2 chips" > + > +config SUNXI_DRAM_DDR3 > + bool "DDR3 chips" > + > +config SUNXI_DRAM_LPDDR2 > + bool "LPDDR2 chips" > + > +config SUNXI_DRAM_LPDDR3 > + bool "LPDDR3 chips" > +endchoice > + > +config SUNXI_DRAM_TYPE > + int > + default 2 if SUNXI_DRAM_DDR2 > + default 3 if SUNXI_DRAM_DDR3 > + default 6 if SUNXI_DRAM_LPDDR2 > + default 7 if SUNXI_DRAM_LPDDR3 > diff --git a/drivers/ram/sunxi/Makefile b/drivers/ram/sunxi/Makefile > new file mode 100644 > index 000..d6fb2cf0b65 > --- /dev/null > +++ b/drivers/ram/sunxi/Makefile > @@ -0,0 +1,4 @@ > +# SPDX-License-Identifier: GPL-2.0+ > + > +obj-$(CONFIG_DRAM_SUN20I_D1) += dram_sun20i_d1.o > +obj-$(CONFIG_DRAM_SUN8I_R528) += dram_sun20i_d1.o > diff --git a/drivers/ram/sunxi/dram_sun20i_d1.c > b/drivers/ram/sunxi/dram_sun20i_d1.c > new file mode 100644 > index 000..06b4cd2c70b > --- /dev/null > +++ b/drivers/ram/sunxi/dram_sun20i_d1.c > @@ -0,0 +1,1425 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Allwinner D1/D1s/R528/T113-sx DRAM initial
Re: [RFC PATCH 16/17] arm: sunxi: add Allwinner T113s devicetree stub
在 2022-12-06星期二的 00:45 +，Andre Przywara写道：
> This adds the basic SoC .dtsi devicetree stub for the Allwinner T113s
> SoC. This shares a die with the Allwinner D1 SoC (with RISC-V cores),
> but uses two Cortex-A7 cores instead of the T-HEAD C906 RISC-V core.
>
> Include the existing D1 devicetree stub, but add the ARM specific
> nodes,
> like for the CPU, the arch timer and the GIC.
>
> Signed-off-by: Andre Przywara
> ---
> arch/arm/dts/sun8i-t113s.dtsi | 59
> +++
> 1 file changed, 59 insertions(+)
> create mode 100644 arch/arm/dts/sun8i-t113s.dtsi
>
> diff --git a/arch/arm/dts/sun8i-t113s.dtsi b/arch/arm/dts/sun8i-
> t113s.dtsi
> new file mode 100644
> index 000..0919ce559f6
> --- /dev/null
> +++ b/arch/arm/dts/sun8i-t113s.dtsi
> @@ -0,0 +1,59 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +// Copyright (C) 2022 Arm Ltd.
> +
> +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI nr
> +
> +#include
> +#include <../../riscv/dts/sunxi-d1s-t113.dtsi>
Should we make a R528 DTSI which includes d1-t113.dtsi, and then T113
DTSI which includes d1s-t113.dtsi ?
> +#include <../../riscv/dts/sunxi-d1-t113.dtsi>
> +
> +/ {
> + interrupt-parent = <&gic>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <0>;
> + clocks = <&ccu CLK_CPUX>;
> + clock-names = "cpu";
> + };
> +
> + cpu1: cpu@1 {
> + compatible = "arm,cortex-a7";
> + device_type = "cpu";
> + reg = <1>;
> + clocks = <&ccu CLK_CPUX>;
> + clock-names = "cpu";
> + };
> + };
> +
> + gic: interrupt-controller@1c81000 {
> + compatible = "arm,gic-400";
> + reg = <0x03021000 0x1000>,
> + <0x03022000 0x2000>,
> + <0x03024000 0x2000>,
> + <0x03026000 0x2000>;
> + interrupts = IRQ_TYPE_LEVEL_HIGH)>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>,
> + IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupts = ,
> + ;
> + interrupt-affinity = <&cpu0>, <&cpu1>;
> + };
> +};
Re: [RFC PATCH 08/17] sunxi: introduce NCAT2 generation model
在 2022-12-06星期二的 00:45 +，Andre Przywara写道： > Allwinner seems to typically stick to a common MMIO memory map for > several SoCs, but from time to time does some breaking changes, which > also introduce new generations of some peripherals. The last time > this > happened with the H6, which apart from re-organising the base > addresses > also changed the clock controller significantly. We added a > CONFIG_SUN50I_GEN_H6 symbol back then to mark SoCs sharing those > traits. > > Now the Allwinner D1 changes the memory map again, and also extends > the > pincontroller, among other peripherals. > To mark this generation of SoCs, add a CONFIG_SUNXI_GEN_NCAT2 symbol, > this name is reportedly used in the Allwinner BSP code, and prevents > us > from inventing our own name. Should we also rename the misleading GEN_SUN50I_H6 to GEN_NCAT ? > > Add this new symbol to some guards that were already checking for the > H6 > generation, since many features are shared between the two (like the > renovated clock controller). > > This paves the way to introduce a first user of this generation. > > Signed-off-by: Andre Przywara > --- > arch/arm/include/asm/arch-sunxi/clock.h | 2 +- > arch/arm/include/asm/arch-sunxi/cpu.h | 2 + > .../include/asm/arch-sunxi/cpu_sunxi_ncat2.h | 54 > +++ > arch/arm/include/asm/arch-sunxi/mmc.h | 2 +- > arch/arm/include/asm/arch-sunxi/prcm.h | 2 +- > arch/arm/include/asm/arch-sunxi/timer.h | 2 +- > arch/arm/mach-sunxi/Kconfig | 14 - > arch/arm/mach-sunxi/Makefile | 1 + > arch/arm/mach-sunxi/board.c | 4 +- > common/spl/Kconfig | 2 +- > drivers/mmc/sunxi_mmc.c | 10 ++-- > include/sunxi_gpio.h | 3 ++ > 12 files changed, 86 insertions(+), 12 deletions(-) > create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h > > diff --git a/arch/arm/include/asm/arch-sunxi/clock.h > b/arch/arm/include/asm/arch-sunxi/clock.h > index 2cfd5407423..3d34261b0e5 100644 > --- a/arch/arm/include/asm/arch-sunxi/clock.h > +++ b/arch/arm/include/asm/arch-sunxi/clock.h > @@ -16,7 +16,7 @@ > /* clock control module regs definition */ > #if defined(CONFIG_MACH_SUN8I_A83T) > #include > -#elif defined(CONFIG_SUN50I_GEN_H6) > +#elif defined(CONFIG_SUN50I_GEN_H6) || > defined(CONFIG_SUNXI_GEN_NCAT2) > #include > #elif defined(CONFIG_MACH_SUN6I) || defined(CONFIG_MACH_SUN8I) || \ > defined(CONFIG_MACH_SUN50I) || defined(CONFIG_MACH_SUNIV) > diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h > b/arch/arm/include/asm/arch-sunxi/cpu.h > index b08f2023748..768c6572d6b 100644 > --- a/arch/arm/include/asm/arch-sunxi/cpu.h > +++ b/arch/arm/include/asm/arch-sunxi/cpu.h > @@ -10,6 +10,8 @@ > #include > #elif defined(CONFIG_SUN50I_GEN_H6) > #include > +#elif defined(CONFIG_SUNXI_GEN_NCAT2) > +#include > #else > #include > #endif > diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h > b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h > new file mode 100644 > index 000..13093085a5e > --- /dev/null > +++ b/arch/arm/include/asm/arch-sunxi/cpu_sunxi_ncat2.h > @@ -0,0 +1,54 @@ > +/* > + * (C) Copyright 2022 Arm Limited > + * > + * SPDX-License-Identifier:GPL-2.0+ > + */ > + > +#ifndef _SUNXI_CPU_SUNXI_NCAT2_H > +#define _SUNXI_CPU_SUNXI_NCAT2_H > + > +#define SUNXI_SRAM_A1_BASE CONFIG_SUNXI_SRAM_ADDRESS > +#define SUNXI_SRAM_C_BASE 0x00028000 > +#define SUNXI_SRAM_A2_BASE 0x0010 > + > +#define SUNXI_SRAMC_BASE 0x0280 > +#define SUNXI_CCM_BASE 0x02001000 > +/* SID address space starts at 0x03006000, but e-fuse is at offset > 0x200 */ > +#define SUNXI_SIDC_BASE0x03006000 > +#define SUNXI_SID_BASE 0x03006200 > +#define SUNXI_TIMER_BASE 0x0205 > + > +#ifdef CONFIG_MACH_SUN50I_H6 > +#define SUNXI_DRAM_COM_BASE0x04002000 > +#define SUNXI_DRAM_CTL0_BASE 0x04003000 > +#define SUNXI_DRAM_PHY0_BASE 0x04005000 > +#endif > +#define SUNXI_MMC0_BASE0x0402 > +#define SUNXI_MMC1_BASE0x04021000 > +#define SUNXI_MMC2_BASE0x04022000 > + > +#define SUNXI_UART0_BASE 0x0250 > +#define SUNXI_UART1_BASE 0x02500400 > +#define SUNXI_UART2_BASE 0x02500800 > +#define SUNXI_UART3_BASE 0x02500C00 > +#define SUNXI_TWI0_BASE0x02502000 > +#define SUNXI_TWI1_BASE0x02502400 > +#define SUNXI_TWI2_BASE0x02502800 > +#define SUNXI_TWI3_BASE0x02502C00 > +#define SUNXI_SPI0_BASE0x04025000 > +#define SUNXI_SPI1_BASE0x04026000 > + > +#define SUNXI_RTC_BASE 0x0700 >
[PATCH 8/8] [DO NOT MERGE] sunxi: add a defconfig for PopStick
--- configs/popstick_defconfig | 35 +++ 1 file changed, 35 insertions(+) create mode 100644 configs/popstick_defconfig diff --git a/configs/popstick_defconfig b/configs/popstick_defconfig new file mode 100644 index 00..6dc21695b7 --- /dev/null +++ b/configs/popstick_defconfig @@ -0,0 +1,35 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SYS_MALLOC_LEN=0x12 +CONFIG_ENV_SIZE=0x1f000 +CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c200s-popstick-v1.1" +CONFIG_SPL=y +CONFIG_MACH_SUNIV=y +CONFIG_DRAM_CLK=156 +CONFIG_DRAM_ZQ=0 +CONFIG_SUNXI_MINIMUM_DRAM_MB=64 +CONFIG_MMC0_CD_PIN="PE3" +# CONFIG_VIDEO_SUNXI is not set +CONFIG_SPL_SPI_SUNXI=y +CONFIG_SPL_SPI_SUNXI_NAND=y +CONFIG_SPL_SPI_SUNXI_NAND_ASSUMED_PAGESIZE=0x800 +CONFIG_SPL_STACK=0x8000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x2 +CONFIG_CMD_MTD=y +# CONFIG_CMD_SF is not set +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +# CONFIG_ENV_IS_IN_FAT is not set +# CONFIG_ENV_IS_IN_SPI_FLASH is not set +CONFIG_ENV_IS_IN_UBI=y +CONFIG_ENV_UBI_PART="ubi" +CONFIG_ENV_UBI_VOLUME="env" +# CONFIG_NET is not set +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_SPI_NAND=y +# CONFIG_SPI_FLASH is not set +CONFIG_SF_DEFAULT_SPEED=2500 +# CONFIG_UBI_SILENCE_MSG is not set +CONFIG_SPI=y +# CONFIG_UBIFS_SILENCE_MSG is not set -- 2.37.1
[PATCH 7/8] [DO NOT MERGE, DIRTY HACK] sunxi: use UBI for environement storage
Signed-off-by: Icenowy Zheng
---
board/sunxi/board.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 21a2407e06..f4138573d4 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -133,6 +133,7 @@ void i2c_init_board(void)
*/
enum env_location env_get_location(enum env_operation op, int prio)
{
+ return prio ? ENVL_UNKNOWN : ENVL_UBI;
if (prio > 1)
return ENVL_UNKNOWN;
--
2.37.1
[PATCH 6/8] [DO NOT MERGE] sunxi: sync DT from my tree for PopStick
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/Makefile| 3 +-
arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 16 +++
arch/arm/dts/suniv-f1c100s.dtsi | 26 +
arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts | 101 +++
4 files changed, 145 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9b00b64509..ef7fff3559 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -529,7 +529,8 @@ dtb-$(CONFIG_STM32H7) += stm32h743i-disco.dtb \
stm32h750i-art-pi.dtb
dtb-$(CONFIG_MACH_SUNIV) += \
- suniv-f1c100s-licheepi-nano.dtb
+ suniv-f1c100s-licheepi-nano.dtb \
+ suniv-f1c200s-popstick-v1.1.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
index 04e59b8381..1935d8c885 100644
--- a/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/dts/suniv-f1c100s-licheepi-nano.dts
@@ -6,6 +6,8 @@
/dts-v1/;
#include "suniv-f1c100s.dtsi"
+#include
+
/ {
model = "Lichee Pi Nano";
compatible = "licheepi,licheepi-nano", "allwinner,suniv-f1c100s";
@@ -50,8 +52,22 @@
};
};
+&otg_sram {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
diff --git a/arch/arm/dts/suniv-f1c100s.dtsi b/arch/arm/dts/suniv-f1c100s.dtsi
index bc563c12e9..6d7b120da2 100644
--- a/arch/arm/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/dts/suniv-f1c100s.dtsi
@@ -133,6 +133,32 @@
#size-cells = <0>;
};
+ usb_otg: usb@1c13000 {
+ compatible = "allwinner,suniv-f1c100s-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,suniv-f1c100s-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
ccu: clock@1c2 {
compatible = "allwinner,suniv-f1c100s-ccu";
reg = <0x01c2 0x400>;
diff --git a/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts
b/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts
new file mode 100644
index 00..121dfc6f60
--- /dev/null
+++ b/arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Icenowy Zheng
+ */
+
+/dts-v1/;
+#include "suniv-f1c100s.dtsi"
+
+#include
+#include
+
+/ {
+ model = "Popcorn Computer PopStick v1.1";
+ compatible = "sourceparts,popstick-v1.1", "sourceparts,popstick",
+"allwinner,suniv-f1c200s", "allwinner,suniv-f1c100s";
+
+ aliases {
+ mmc0 = &mmc0;
+ serial0 = &uart0;
+ spi0 = &spi0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led {
+ function = LED_FUNCTION_STATUS;
+ color = ;
+ gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>; /* PE6 */
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "
[PATCH 5/8] sunxi: enable support for SPI NAND booting on SUNIV
As we added support for SPI NAND to the existing SPL SPI codepath, route
the boot code to it when it detects the BROM loads SPL from SPI NAND, as
for SoCs with both SPI NAND and boot media indicator support, the boot
media indicator is the same for SPI NOR and NAND.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/board.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 220ed80ba7..3a81743e8f 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -210,12 +210,10 @@ static int suniv_get_boot_source(void)
case SUNIV_BOOTED_FROM_MMC0:
return SUNXI_BOOTED_FROM_MMC0;
case SUNIV_BOOTED_FROM_SPI:
+ case SUNIV_BOOTED_FROM_NAND:
return SUNXI_BOOTED_FROM_SPI;
case SUNIV_BOOTED_FROM_MMC1:
return SUNXI_BOOTED_FROM_MMC2;
- /* SPI NAND is not supported yet. */
- case SUNIV_BOOTED_FROM_NAND:
- return SUNXI_INVALID_BOOT_SOURCE;
}
/* If we get here something went wrong try to boot from FEL.*/
printf("Unknown boot source from BROM: 0x%x\n", brom_call);
--
2.37.1
[PATCH 4/8] sunxi: SPL SPI: add initial support for booting from SPI NAND
This commit adds support for booting from SPI NAND to SPL SPI code by
mimicing the behavior of boot ROM (use fixed page size and sequentially
try SPI NOR and NAND).
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig | 16 +++
arch/arm/mach-sunxi/spl_spi_sunxi.c | 74 +
2 files changed, 90 insertions(+)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 840bbc19b3..6afbb4acb5 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1018,6 +1018,22 @@ config SPL_SPI_SUNXI
sunxi SPI Flash. It uses the same method as the boot ROM, so does
not need any extra configuration.
+config SPL_SPI_SUNXI_NAND
+ bool "Support for SPI NAND Flash on Allwinner SoCs in SPL"
+ depends on SPL_SPI_SUNXI
+ help
+ Enable support for SPI NAND Flash. This option allows SPL to mimic
+ Allwinner boot ROM's behavior to gain support for SPI NAND Flash;
+ a fixed page size needs to be assumed when building the SPL image.
+
+config SPL_SPI_SUNXI_NAND_ASSUMED_PAGESIZE
+ hex "Assumed pagesize for SPI NAND Flash in SPL"
+ depends on SPL_SPI_SUNXI_NAND
+ default 0x400 if MACH_SUNIV
+ help
+ Set the page size assumed by the SPL SPI NAND code, the default
+ value is the same with the boot ROM.
+
config PINE64_DT_SELECTION
bool "Enable Pine64 device tree selection code"
depends on MACH_SUN50I
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 21be33a23f..5178908327 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -305,6 +305,49 @@ static void spi0_xfer(const u8 *txbuf, u32 txlen, u8
*rxbuf, u32 rxlen)
}
}
+#if defined(CONFIG_SPL_SPI_SUNXI_NAND)
+static int spi0_nand_switch_page(u32 page)
+{
+ unsigned count;
+ u8 buf[4];
+
+ /* Configure the Page Data Read (13h) command header */
+ buf[0] = 0x13;
+ buf[1] = (u8)(page >> 16);
+ buf[2] = (u8)(page >> 8);
+ buf[3] = (u8)(page);
+
+ spi0_xfer(buf, 4, NULL, 0);
+
+ /* Wait for NAND chip to exit busy state */
+ buf[0] = 0x0f;
+ buf[1] = 0xc0;
+
+ /* Load a NAND page can take up to 2-decimal-digit microseconds */
+ for (count = 0; count < 100; count ++) {
+ udelay(1);
+ spi0_xfer(buf, 2, buf+2, 1);
+ if (!(buf[2] & 0x1))
+ return 0;
+ }
+
+ return -ETIMEDOUT;
+}
+
+static void spi0_nand_reset(void)
+{
+ u8 buf[1];
+
+ /* Configure the Device RESET (ffh) command */
+ buf[0] = 0xff;
+
+ spi0_xfer(buf, 1, NULL, 0);
+
+ /* Wait for the NAND to finish resetting */
+ udelay(10);
+}
+#endif
+
static void spi0_read_data(void *buf, u32 addr, u32 len, u32 addr_len)
{
u8 *buf8 = buf;
@@ -348,6 +391,28 @@ static ulong spi_load_read_nor(struct spl_load_info *load,
ulong sector,
return count;
}
+#if defined(CONFIG_SPL_SPI_SUNXI_NAND)
+static ulong spi_load_read_nand(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
+{
+ const ulong pagesize = CONFIG_SPL_SPI_SUNXI_NAND_ASSUMED_PAGESIZE;
+ ulong remain = count;
+
+ while (remain) {
+ ulong count_in_page = min(remain, pagesize - (sector %
pagesize));
+ ulong current_page = sector / pagesize;
+ if (spi0_nand_switch_page(current_page) != 0)
+ return 0;
+ spi0_read_data(buf, sector % pagesize, count_in_page, 2);
+ remain -= count_in_page;
+ sector += count_in_page;
+ buf += count_in_page;
+ }
+
+ return count;
+}
+#endif
+
/*/
static int spl_spi_try_load(struct spl_image_info *spl_image,
@@ -400,9 +465,18 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
spi0_init();
+#if defined(CONFIG_SPL_SPI_SUNXI_NAND)
+ spi0_nand_reset();
+ load.read = spi_load_read_nand;
+ ret = spl_spi_try_load(spl_image, bootdev, &load, load_offset, false);
+ if (!ret)
+ goto out;
+#endif
+
load.read = spi_load_read_nor;
ret = spl_spi_try_load(spl_image, bootdev, &load, load_offset, true);
+out:
spi0_deinit();
return ret;
--
2.37.1
[PATCH 3/8] sunxi: SPL SPI: allow multiple boot attempt
As we're going to add support for SPI NAND to this code, add code that
allows multiple boot attempts with different load offsets and functions.
To keep compatibility with loading raw binary on SPI NOR, a bool
parameter is used to allow booting without valid magic number when
booting with SPI NOR.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 58 +++--
1 file changed, 38 insertions(+), 20 deletions(-)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 88c15a3ee9..21be33a23f 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -340,8 +340,8 @@ static void spi0_read_data(void *buf, u32 addr, u32 len,
u32 addr_len)
}
}
-static ulong spi_load_read(struct spl_load_info *load, ulong sector,
- ulong count, void *buf)
+static ulong spi_load_read_nor(struct spl_load_info *load, ulong sector,
+ ulong count, void *buf)
{
spi0_read_data(buf, sector, count, 3);
@@ -350,41 +350,59 @@ static ulong spi_load_read(struct spl_load_info *load,
ulong sector,
/*/
-static int spl_spi_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
+static int spl_spi_try_load(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev,
+ struct spl_load_info *load, u32 offset,
+ bool allow_raw)
{
int ret = 0;
struct legacy_img_hdr *header;
- uint32_t load_offset = sunxi_get_spl_size();
-
header = (struct legacy_img_hdr *)CONFIG_SYS_TEXT_BASE;
- load_offset = max_t(uint32_t, load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS);
-
- spi0_init();
- spi0_read_data((void *)header, load_offset, 0x40, 3);
+ if (load->read(load, offset, 0x40, (void *)header) == 0)
+ return -EINVAL;
if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
image_get_magic(header) == FDT_MAGIC) {
- struct spl_load_info load;
debug("Found FIT image\n");
- load.dev = NULL;
- load.priv = NULL;
- load.filename = NULL;
- load.bl_len = 1;
- load.read = spi_load_read;
- ret = spl_load_simple_fit(spl_image, &load,
- load_offset, header);
+ ret = spl_load_simple_fit(spl_image, load,
+ offset, header);
} else {
+ if (!allow_raw && image_get_magic(header) != IH_MAGIC)
+ return -EINVAL;
+
ret = spl_parse_image_header(spl_image, bootdev, header);
if (ret)
return ret;
- spi0_read_data((void *)spl_image->load_addr,
- load_offset, spl_image->size, 3);
+ if (load->read(load, offset, spl_image->size,
+ (void *)spl_image->load_addr) == 0)
+ ret = -EINVAL;
}
+ return ret;
+}
+
+static int spl_spi_load_image(struct spl_image_info *spl_image,
+ struct spl_boot_device *bootdev)
+{
+ int ret = 0;
+ uint32_t load_offset = sunxi_get_spl_size();
+ struct spl_load_info load;
+
+ load_offset = max_t(uint32_t, load_offset, CONFIG_SYS_SPI_U_BOOT_OFFS);
+
+ load.dev = NULL;
+ load.priv = NULL;
+ load.filename = NULL;
+ load.bl_len = 1;
+
+ spi0_init();
+
+ load.read = spi_load_read_nor;
+ ret = spl_spi_try_load(spl_image, bootdev, &load, load_offset, true);
+
spi0_deinit();
return ret;
--
2.37.1
[PATCH 2/8] sunxi: SPL SPI: add support for read command with 2 byte address
This kind of read command is utilized in SPI NANDs for reading data
inside a selected page, which is obviously smaller than how much 2
byte address can address. So 2 bytes are used for the address and one
dummy byte is needed after the real address. As the address is sent out
in bit endian, this makes it not compatible with usual 3 byte address.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 7975457758..88c15a3ee9 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -305,7 +305,7 @@ static void spi0_xfer(const u8 *txbuf, u32 txlen, u8
*rxbuf, u32 rxlen)
}
}
-static void spi0_read_data(void *buf, u32 addr, u32 len)
+static void spi0_read_data(void *buf, u32 addr, u32 len, u32 addr_len)
{
u8 *buf8 = buf;
u32 chunk_len;
@@ -316,9 +316,15 @@ static void spi0_read_data(void *buf, u32 addr, u32 len)
/* Configure the Read Data Bytes (03h) command header */
txbuf[0] = 0x03;
- txbuf[1] = (u8)(addr >> 16);
- txbuf[2] = (u8)(addr >> 8);
- txbuf[3] = (u8)(addr);
+ if (addr_len == 3) {
+ txbuf[1] = (u8)(addr >> 16);
+ txbuf[2] = (u8)(addr >> 8);
+ txbuf[3] = (u8)(addr);
+ } else if (addr_len == 2) {
+ txbuf[1] = (u8)(addr >> 8);
+ txbuf[2] = (u8)(addr);
+ txbuf[3] = 0; /* dummy */
+ }
if (chunk_len > SPI_READ_MAX_SIZE)
chunk_len = SPI_READ_MAX_SIZE;
@@ -337,7 +343,7 @@ static void spi0_read_data(void *buf, u32 addr, u32 len)
static ulong spi_load_read(struct spl_load_info *load, ulong sector,
ulong count, void *buf)
{
- spi0_read_data(buf, sector, count);
+ spi0_read_data(buf, sector, count, 3);
return count;
}
@@ -356,7 +362,7 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
spi0_init();
- spi0_read_data((void *)header, load_offset, 0x40);
+ spi0_read_data((void *)header, load_offset, 0x40, 3);
if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
image_get_magic(header) == FDT_MAGIC) {
@@ -376,7 +382,7 @@ static int spl_spi_load_image(struct spl_image_info
*spl_image,
return ret;
spi0_read_data((void *)spl_image->load_addr,
- load_offset, spl_image->size);
+ load_offset, spl_image->size, 3);
}
spi0_deinit();
--
2.37.1
[PATCH 1/8] sunxi: SPL SPI: extract code for doing SPI transfer
To support SPI NAND flashes, more commands than Read (03h) are needed.
Extract the code for doing SPI transfer from the reading code for code
reuse.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/spl_spi_sunxi.c | 105
1 file changed, 59 insertions(+), 46 deletions(-)
diff --git a/arch/arm/mach-sunxi/spl_spi_sunxi.c
b/arch/arm/mach-sunxi/spl_spi_sunxi.c
index 925bf85f2d..7975457758 100644
--- a/arch/arm/mach-sunxi/spl_spi_sunxi.c
+++ b/arch/arm/mach-sunxi/spl_spi_sunxi.c
@@ -243,77 +243,90 @@ static void spi0_deinit(void)
#define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
-static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
-ulong spi_ctl_reg,
-ulong spi_ctl_xch_bitmask,
-ulong spi_fifo_reg,
-ulong spi_tx_reg,
-ulong spi_rx_reg,
-ulong spi_bc_reg,
-ulong spi_tc_reg,
-ulong spi_bcc_reg)
+static void sunxi_spi0_xfer(const u8 *txbuf, u32 txlen,
+ u8 *rxbuf, u32 rxlen,
+ ulong spi_ctl_reg,
+ ulong spi_ctl_xch_bitmask,
+ ulong spi_fifo_reg,
+ ulong spi_tx_reg,
+ ulong spi_rx_reg,
+ ulong spi_bc_reg,
+ ulong spi_tc_reg,
+ ulong spi_bcc_reg)
{
- writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
- writel(4, spi_tc_reg); /* Transfer counter (bytes to send) */
+ writel(txlen + rxlen, spi_bc_reg); /* Burst counter (total bytes) */
+ writel(txlen, spi_tc_reg); /* Transfer counter (bytes to send)
*/
if (spi_bcc_reg)
- writel(4, spi_bcc_reg); /* SUN6I also needs this */
+ writel(txlen, spi_bcc_reg); /* SUN6I also needs this */
- /* Send the Read Data Bytes (03h) command header */
- writeb(0x03, spi_tx_reg);
- writeb((u8)(addr >> 16), spi_tx_reg);
- writeb((u8)(addr >> 8), spi_tx_reg);
- writeb((u8)(addr), spi_tx_reg);
+ for (u32 i = 0; i < txlen; i++)
+ writeb(*(txbuf++), spi_tx_reg);
/* Start the data transfer */
setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
/* Wait until everything is received in the RX FIFO */
- while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
+ while ((readl(spi_fifo_reg) & 0x7F) < txlen + rxlen)
;
- /* Skip 4 bytes */
- readl(spi_rx_reg);
+ /* Skip txlen bytes */
+ for (u32 i = 0; i < txlen; i++)
+ readb(spi_rx_reg);
/* Read the data */
- while (bufsize-- > 0)
- *buf++ = readb(spi_rx_reg);
+ while (rxlen-- > 0)
+ *rxbuf++ = readb(spi_rx_reg);
+}
+
+static void spi0_xfer(const u8 *txbuf, u32 txlen, u8 *rxbuf, u32 rxlen)
+{
+ uintptr_t base = spi0_base_address();
- /* tSHSL time is up to 100 ns in various SPI flash datasheets */
- udelay(1);
+ if (is_sun6i_gen_spi()) {
+ sunxi_spi0_xfer(txbuf, txlen, rxbuf, rxlen,
+ base + SUN6I_SPI0_TCR,
+ SUN6I_TCR_XCH,
+ base + SUN6I_SPI0_FIFO_STA,
+ base + SUN6I_SPI0_TXD,
+ base + SUN6I_SPI0_RXD,
+ base + SUN6I_SPI0_MBC,
+ base + SUN6I_SPI0_MTC,
+ base + SUN6I_SPI0_BCC);
+ } else {
+ sunxi_spi0_xfer(txbuf, txlen, rxbuf, rxlen,
+ base + SUN4I_SPI0_CTL,
+ SUN4I_CTL_XCH,
+ base + SUN4I_SPI0_FIFO_STA,
+ base + SUN4I_SPI0_TX,
+ base + SUN4I_SPI0_RX,
+ base + SUN4I_SPI0_BC,
+ base + SUN4I_SPI0_TC,
+ 0);
+ }
}
static void spi0_read_data(void *buf, u32 addr, u32 len)
{
u8 *buf8 = buf;
u32 chunk_len;
- uintptr_t base = spi0_base_address();
+ u8 txbuf[4];
while (len > 0) {
chunk_len = len;
+
+ /* Configure the Read Data Bytes (03h) command header */
+ txbuf[0] = 0x03;
+ txbuf[1] = (u8)(addr >> 16);
+ txbuf[2] = (u8)(addr >> 8);
+ txbuf[3] = (u8)(addr);
+
if (chunk_len > SPI_READ_MAX_SIZE)
chunk_len = SPI_READ_MAX_SIZE;
- if (is_sun6i_gen_sp
[PATCH 0/8] SUNIV SPI NAND support in SPL
This patchset tries to extend SPI-based boot code in sunxi SPL to support SPI NAND, following the same principle with current SPI NOR code (mimicking the behavior of sunxi BROM). In addition, as part of test to this patchset, some patches for Source Parts Inc. PopStick is attached, although marked DO NOT MERGE because the DT should come from Linux after it's ready. To keep thr code that accesses SPI NAND as simple as possible, it assumes fixed page size, which is also what sunxi BROM does. The SUNIV SPL assumes 0x400 page size, but here to utilize the space better, in the attached example of PopStick, U-Boot main part is assumed to be with 0x800 page size (which is the real situation of the W25N01 flash used by PopStick). Icenowy Zheng (8): sunxi: SPL SPI: extract code for doing SPI transfer sunxi: SPL SPI: add support for read command with 2 byte address sunxi: SPL SPI: allow multiple boot attempt sunxi: SPL SPI: add initial support for booting from SPI NAND sunxi: enable support for SPI NAND booting on SUNIV [DO NOT MERGE] sunxi: sync DT from my tree for PopStick [DO NOT MERGE, DIRTY HACK] sunxi: use UBI for environement storage [DO NOT MERGE] sunxi: add a defconfig for PopStick arch/arm/dts/Makefile| 3 +- arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 16 ++ arch/arm/dts/suniv-f1c100s.dtsi | 26 ++ arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts | 101 arch/arm/mach-sunxi/Kconfig | 16 ++ arch/arm/mach-sunxi/board.c | 4 +- arch/arm/mach-sunxi/spl_spi_sunxi.c | 247 ++- board/sunxi/board.c | 1 + configs/popstick_defconfig | 35 +++ 9 files changed, 377 insertions(+), 72 deletions(-) create mode 100644 arch/arm/dts/suniv-f1c200s-popstick-v1.1.dts create mode 100644 configs/popstick_defconfig -- 2.37.1
[PATCH 2/2] configs: sunxi: licheepi_nano: enable D-Cache
As the compile error when D-Cache is enabled is gone, we can have D-Cache enabled now. Signed-off-by: Icenowy Zheng --- configs/licheepi_nano_defconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index a9776bbcac..b80d32c502 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -1,7 +1,6 @@ CONFIG_ARM=y CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y -CONFIG_SYS_DCACHE_OFF=y CONFIG_ARCH_SUNXI=y CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano" CONFIG_SPL=y -- 2.37.1
[PATCH 1/2] sunxi: fix SUNIV build when enabling D-Cache
The enable_caches function in architecture-specific board code is only
necessary for V7A CPUs, code for both V8A and ARM926 have already
declared this function.
Only provide our implementation of enable_caches() for V7A CPUs.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/board.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index 62bb40b8c8..60ccf909db 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -488,7 +488,7 @@ void reset_cpu(void)
}
#endif
-#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && defined(CONFIG_CPU_V7A)
void enable_caches(void)
{
/* Enable D-cache. I-cache is already enabled in start.S */
--
2.37.1
[PATCH 0/2] sunxi: fix SUNIV D$ support
Currently D$ support of SUNIV is broken because of duplicated definition of the D$ enabling function. Mask the one in mach-sunxi to fix the build error when D$ is enabled, and enable the D$ on Lichee Pi Nano. Icenowy Zheng (2): sunxi: fix SUNIV build when enabling D-Cache configs: sunxi: licheepi_nano: enable D-Cache arch/arm/mach-sunxi/board.c | 2 +- configs/licheepi_nano_defconfig | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) -- 2.37.1
Re: [PATCH 3/6] sunxi: f1c100: move SKIP_LOWLEVEL_INIT_ONLY into Kconfig
I am against using "f1c100" in commit message, because there is a chip called F1C100 that is part of legacy sun3i instead of suniv. Using "suniv" or "f1c100s" is better. 在 2022-10-12星期三的 17:34 +0100，Andre Przywara写道： > So far we stated the lack of a lowlevel() init function for the > F1C100s > board by defining the respective SKIP_* symbol in the board's > defconfig. However we don't expect any *board* to employ such low > level > code, so expect this to be never used for the ARMv5 Allwinner SoCs. > > Select the appropriate symbols in the Kconfig, so that we can remove > them from the defconfig, and avoid putting them in future defconfigs > for > other boards. > > Signed-off-by: Andre Przywara > --- > arch/arm/mach-sunxi/Kconfig | 2 ++ > configs/licheepi_nano_defconfig | 2 -- > 2 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach- > sunxi/Kconfig > index 9aa66deb9fd..fc5d8bb3c19 100644 > --- a/arch/arm/mach-sunxi/Kconfig > +++ b/arch/arm/mach-sunxi/Kconfig > @@ -185,6 +185,8 @@ config MACH_SUNIV > select CPU_ARM926EJS > select SUNXI_GEN_SUN6I > select SUPPORT_SPL > + select SKIP_LOWLEVEL_INIT_ONLY > + select SPL_SKIP_LOWLEVEL_INIT_ONLY > > config MACH_SUN4I > bool "sun4i (Allwinner A10)" > diff --git a/configs/licheepi_nano_defconfig > b/configs/licheepi_nano_defconfig > index 14e6bcda927..09f1a19cdbe 100644 > --- a/configs/licheepi_nano_defconfig > +++ b/configs/licheepi_nano_defconfig > @@ -1,6 +1,4 @@ > CONFIG_ARM=y > -CONFIG_SKIP_LOWLEVEL_INIT_ONLY=y > -CONFIG_SPL_SKIP_LOWLEVEL_INIT_ONLY=y > CONFIG_SYS_DCACHE_OFF=y > CONFIG_ARCH_SUNXI=y > CONFIG_DEFAULT_DEVICE_TREE="suniv-f1c100s-licheepi-nano"
Re: [PATCH 1/2] dt-bindings: clock: sifive: sync FU740 PRCI clock binding header
在 2022-08-30星期二的 03:26 +，Leo Liang写道：
> Hi Icenowy,
> On Thu, Aug 25, 2022 at 04:11:18PM +0800, Icenowy Zheng wrote:
> > This commit sychornizes the header file for FU740 PRCI clocks with
> > the
> > one from Linux 5.19.
> >
> > The constant values are the same, but all constant names are
> > changed
> > (most are just prefixed with FU740_).
> >
> > Signed-off-by: Icenowy Zheng
> > ---
> > arch/riscv/dts/fu740-c000-u-boot.dtsi | 16 +--
> > arch/riscv/dts/fu740-c000.dtsi | 28 +--
> >
> > drivers/clk/sifive/fu740-prci.c | 18 ++--
> > drivers/clk/sifive/sifive-prci.c | 4 +--
> > include/dt-bindings/clock/sifive-fu740-prci.h | 25 ---
> > --
> > 5 files changed, 45 insertions(+), 46 deletions(-)
> >
> > diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi
> > b/arch/riscv/dts/fu740-c000-u-boot.dtsi
> > index a6f7a0873e..917e9bf163 100644
> > --- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
> > +++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
> > @@ -7,11 +7,11 @@
> >
> > / {
> > cpus {
> > - assigned-clocks = <&prci PRCI_CLK_COREPLL>;
> > + assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
> > assigned-clock-rates = <12>;
> > u-boot,dm-spl;
> > cpu0: cpu@0 {
> > - clocks = <&prci PRCI_CLK_COREPLL>;
> > + clocks = <&prci FU740_PRCI_CLK_COREPLL>;
> > u-boot,dm-spl;
> > status = "okay";
> > cpu0_intc: interrupt-controller {
> > @@ -19,28 +19,28 @@
> > };
> > };
> > cpu1: cpu@1 {
> > - clocks = <&prci PRCI_CLK_COREPLL>;
> > + clocks = <&prci FU740_PRCI_CLK_COREPLL>;
> > u-boot,dm-spl;
> > cpu1_intc: interrupt-controller {
> > u-boot,dm-spl;
> > };
> > };
> > cpu2: cpu@2 {
> > - clocks = <&prci PRCI_CLK_COREPLL>;
> > + clocks = <&prci FU740_PRCI_CLK_COREPLL>;
> > u-boot,dm-spl;
> > cpu2_intc: interrupt-controller {
> > u-boot,dm-spl;
> > };
> > };
> > cpu3: cpu@3 {
> > - clocks = <&prci PRCI_CLK_COREPLL>;
> > + clocks = <&prci FU740_PRCI_CLK_COREPLL>;
> > u-boot,dm-spl;
> > cpu3_intc: interrupt-controller {
> > u-boot,dm-spl;
> > };
> > };
> > cpu4: cpu@4 {
> > - clocks = <&prci PRCI_CLK_COREPLL>;
> > + clocks = <&prci FU740_PRCI_CLK_COREPLL>;
> > u-boot,dm-spl;
> > cpu4_intc: interrupt-controller {
> > u-boot,dm-spl;
> > @@ -76,7 +76,7 @@
> > reg = <0x0 0x100b 0x0 0x0800
> > 0x0 0x100b2000 0x0 0x2000
> > 0x0 0x100b8000 0x0 0x1000>;
> > - clocks = <&prci PRCI_CLK_DDRPLL>;
> > + clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
> > clock-frequency = <93324>;
> > u-boot,dm-spl;
> > };
> > @@ -100,7 +100,7 @@
> > };
> >
> > ð0 {
> > - assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
> > + assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>;
> > assigned-clock-rates = <125125000>;
> > };
> >
> > diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-
> > c000.dtsi
> > index 649efe400a..0e14aa71e7 100644
> > --- a/arch/riscv/dts/fu740-c000.dtsi
> > +++ b/arch/riscv/dts/fu740-c000.dtsi
> > @@ -166,7 +166,7 @@
> > reg = <0x0 0x1001 0x0 0x1000>;
> > interrupt-parent
[PATCH 2/2] riscv: dts: sifive: Synchornize FU740 and Unmatched DT
These DT files are synchornized from Linux 5.19.
Signed-off-by: Icenowy Zheng
---
arch/riscv/dts/fu740-c000.dtsi | 67 +
arch/riscv/dts/hifive-unmatched-a00.dts | 95 +++--
2 files changed, 73 insertions(+), 89 deletions(-)
diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
index 0e14aa71e7..7b77c13496 100644
--- a/arch/riscv/dts/fu740-c000.dtsi
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -1,10 +1,9 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020-2021 SiFive, Inc */
+/* Copyright (c) 2020 SiFive, Inc */
/dts-v1/;
#include
-#include
/ {
#address-cells = <2>;
@@ -139,20 +138,21 @@
soc {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "sifive,fu740-c000", "sifive,fu740", "simple-bus";
+ compatible = "simple-bus";
ranges;
plic0: interrupt-controller@c00 {
#interrupt-cells = <1>;
- compatible = "sifive,plic-1.0.0";
+ #address-cells = <0>;
+ compatible = "sifive,fu540-c000-plic",
"sifive,plic-1.0.0";
reg = <0x0 0xc00 0x0 0x400>;
riscv,ndev = <69>;
interrupt-controller;
- interrupts-extended = <
- &cpu0_intc 0x
- &cpu1_intc 0x &cpu1_intc 9
- &cpu2_intc 0x &cpu2_intc 9
- &cpu3_intc 0x &cpu3_intc 9
- &cpu4_intc 0x &cpu4_intc 9>;
+ interrupts-extended =
+ <&cpu0_intc 0x>,
+ <&cpu1_intc 0x>, <&cpu1_intc 9>,
+ <&cpu2_intc 0x>, <&cpu2_intc 9>,
+ <&cpu3_intc 0x>, <&cpu3_intc 9>,
+ <&cpu4_intc 0x>, <&cpu4_intc 9>;
};
prci: clock-controller@1000 {
compatible = "sifive,fu740-c000-prci";
@@ -203,8 +203,8 @@
};
qspi0: spi@1004 {
compatible = "sifive,fu740-c000-spi", "sifive,spi0";
- reg = <0x0 0x1004 0x0 0x1000
- 0x0 0x2000 0x0 0x1000>;
+ reg = <0x0 0x1004 0x0 0x1000>,
+ <0x0 0x2000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <41>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
@@ -214,8 +214,8 @@
};
qspi1: spi@10041000 {
compatible = "sifive,fu740-c000-spi", "sifive,spi0";
- reg = <0x0 0x10041000 0x0 0x1000
- 0x0 0x3000 0x0 0x1000>;
+ reg = <0x0 0x10041000 0x0 0x1000>,
+ <0x0 0x3000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <42>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
@@ -237,8 +237,8 @@
compatible = "sifive,fu540-c000-gem";
interrupt-parent = <&plic0>;
interrupts = <55>;
- reg = <0x0 0x1009 0x0 0x2000
- 0x0 0x100a 0x0 0x1000>;
+ reg = <0x0 0x1009 0x0 0x2000>,
+ <0x0 0x100a 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk";
clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>,
@@ -251,7 +251,7 @@
compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
reg = <0x0 0x1002 0x0 0x1000>;
interrupt-parent = <&plic0>;
- interrupts = <44 45 46 47>;
+ interrupts = <44>, <45>, <46>, <47>;
clocks = <&prci FU740_PRCI_CLK_PCLK>;
#pwm-cells = <3>;
status = "disa
[PATCH 1/2] dt-bindings: clock: sifive: sync FU740 PRCI clock binding header
This commit sychornizes the header file for FU740 PRCI clocks with the
one from Linux 5.19.
The constant values are the same, but all constant names are changed
(most are just prefixed with FU740_).
Signed-off-by: Icenowy Zheng
---
arch/riscv/dts/fu740-c000-u-boot.dtsi | 16 +--
arch/riscv/dts/fu740-c000.dtsi| 28 +--
drivers/clk/sifive/fu740-prci.c | 18 ++--
drivers/clk/sifive/sifive-prci.c | 4 +--
include/dt-bindings/clock/sifive-fu740-prci.h | 25 -
5 files changed, 45 insertions(+), 46 deletions(-)
diff --git a/arch/riscv/dts/fu740-c000-u-boot.dtsi
b/arch/riscv/dts/fu740-c000-u-boot.dtsi
index a6f7a0873e..917e9bf163 100644
--- a/arch/riscv/dts/fu740-c000-u-boot.dtsi
+++ b/arch/riscv/dts/fu740-c000-u-boot.dtsi
@@ -7,11 +7,11 @@
/ {
cpus {
- assigned-clocks = <&prci PRCI_CLK_COREPLL>;
+ assigned-clocks = <&prci FU740_PRCI_CLK_COREPLL>;
assigned-clock-rates = <12>;
u-boot,dm-spl;
cpu0: cpu@0 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
status = "okay";
cpu0_intc: interrupt-controller {
@@ -19,28 +19,28 @@
};
};
cpu1: cpu@1 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
cpu1_intc: interrupt-controller {
u-boot,dm-spl;
};
};
cpu2: cpu@2 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
cpu2_intc: interrupt-controller {
u-boot,dm-spl;
};
};
cpu3: cpu@3 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
cpu3_intc: interrupt-controller {
u-boot,dm-spl;
};
};
cpu4: cpu@4 {
- clocks = <&prci PRCI_CLK_COREPLL>;
+ clocks = <&prci FU740_PRCI_CLK_COREPLL>;
u-boot,dm-spl;
cpu4_intc: interrupt-controller {
u-boot,dm-spl;
@@ -76,7 +76,7 @@
reg = <0x0 0x100b 0x0 0x0800
0x0 0x100b2000 0x0 0x2000
0x0 0x100b8000 0x0 0x1000>;
- clocks = <&prci PRCI_CLK_DDRPLL>;
+ clocks = <&prci FU740_PRCI_CLK_DDRPLL>;
clock-frequency = <93324>;
u-boot,dm-spl;
};
@@ -100,7 +100,7 @@
};
ð0 {
- assigned-clocks = <&prci PRCI_CLK_GEMGXLPLL>;
+ assigned-clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>;
assigned-clock-rates = <125125000>;
};
diff --git a/arch/riscv/dts/fu740-c000.dtsi b/arch/riscv/dts/fu740-c000.dtsi
index 649efe400a..0e14aa71e7 100644
--- a/arch/riscv/dts/fu740-c000.dtsi
+++ b/arch/riscv/dts/fu740-c000.dtsi
@@ -166,7 +166,7 @@
reg = <0x0 0x1001 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <39>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled";
};
uart1: serial@10011000 {
@@ -174,7 +174,7 @@
reg = <0x0 0x10011000 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <40>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = <&prci FU740_PRCI_CLK_PCLK>;
status = "disabled";
};
i2c0: i2c@1003 {
@@ -182,7 +182,7 @@
reg = <0x0 0x1003 0x0 0x1000>;
interrupt-parent = <&plic0>;
interrupts = <52>;
- clocks = <&prci PRCI_CLK_PCLK>;
+ clocks = &l
[PATCH 0/2] Sync SiFive FU740+Unmatched DT from Linux
This patchset tries to sync FU740 related DT from Linux 5.19. The first patch fetches the DT binding header from Linux, and the second one fetches the main DT files. Icenowy Zheng (2): dt-bindings: clock: sifive: sync FU740 PRCI clock binding header riscv: dts: sifive: Synchornize FU740 and Unmatched DT arch/riscv/dts/fu740-c000-u-boot.dtsi | 16 ++-- arch/riscv/dts/fu740-c000.dtsi| 91 +- arch/riscv/dts/hifive-unmatched-a00.dts | 95 --- drivers/clk/sifive/fu740-prci.c | 18 ++-- drivers/clk/sifive/sifive-prci.c | 4 +- include/dt-bindings/clock/sifive-fu740-prci.h | 25 +++-- 6 files changed, 116 insertions(+), 133 deletions(-) -- 2.37.1
Re: [PATCH 0/6] mtd: nand: sunxi: Convert to devicetree and the driver model
在 2022-07-14星期四的 07:38 +0200，Michael Nazzareno Trimarchi写道： > Hi Samuel > > On Thu, Jul 14, 2022 at 5:15 AM Samuel Holland > wrote: > > > > This series converts the sunxi NAND driver to get its resources > > (clocks, > > resets, pins) from the devicetree, and probe using the driver > > model. > > > > In addition to the immediate cleanup, this allows backporting more > > patches (bugfixes, newer SoC support) from the Linux driver. > > > > > > Samuel Holland (6): > > clk: sunxi: Add NAND clocks and resets > > pinctrl: sunxi: Add NAND pinmuxes > > mtd: nand: sunxi: Remove an unnecessary check > > mtd: nand: sunxi: Convert from fdtdec to ofnode > > mtd: nand: sunxi: Convert to the driver model > > mtd: nand: sunxi: Pass the device to the init function > > > > board/sunxi/board.c | 5 +- > > drivers/clk/sunxi/clk_a10.c | 2 + > > drivers/clk/sunxi/clk_a10s.c | 2 + > > drivers/clk/sunxi/clk_a23.c | 3 + > > drivers/clk/sunxi/clk_a31.c | 6 + > > drivers/clk/sunxi/clk_a64.c | 3 + > > drivers/clk/sunxi/clk_a80.c | 8 ++ > > drivers/clk/sunxi/clk_a83t.c | 3 + > > drivers/clk/sunxi/clk_h3.c | 3 + > > drivers/clk/sunxi/clk_h6.c | 6 + > > drivers/clk/sunxi/clk_h616.c | 6 + > > drivers/clk/sunxi/clk_r40.c | 3 + > > drivers/mtd/nand/raw/sunxi_nand.c | 173 -- > > > > drivers/pinctrl/sunxi/pinctrl-sunxi.c | 13 ++ > > include/fdtdec.h | 1 - > > lib/fdtdec.c | 1 - > > 16 files changed, 138 insertions(+), 100 deletions(-) > > > > Was in our roadmap and thank you for it. We are looking for sunxi > boards that have nand, can you please point where we can find them? NTC C.H.I.P. ? Although NTC does not exist now (well maybe partly because C.H.I.P. uses NAND) > > We are still in the process of setting up our account, anyway we will > review it quickly. > > Michael > > > -- > > 2.35.1 > >
Re: [PATCH sunxi/next] spi: sunxi: use XCH status to detect in-progress transfer
在 2022-07-11星期一的 00:03 +0100，Andre Przywara写道：
> On Tue, 28 Jun 2022 14:49:24 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > The current detection of RX FIFO depth seems to be not reliable,
> > and
> > XCH will self-clear when a transfer is done.
>
> many thanks for sending this, indeed what I put in -next is broken,
> probably for everything except the F1C100 ;-)
>
> Digging a bit deeper this gets more interesting, though:
> I chased the issue down to my very first commit, that is (now
> properly!)
> setting the SPI bus frequency in the SPI controller's CCR register.
> It
> turns out that there are more issues in this driver, which lead to an
> actual frequency limit of 1 MHz[1]. So my commit now actually
> programs
> this value, and apparently it's too slow(?) for the code? Raising the
> default 1 to 4 MHz makes it work again (even without your patch). The
> previous timeout is generous, though, but by looking at the FIFO
> status
> register it just seemed to be stuck after clocking out one byte only,
> with the RX buf staying at 0. Reading FSR after your new loop reveals
> that the condition holds (RX FIFO level == nbytes), so there is
> something quite weird going on. Without your patch, but with some
> udelay(1000) after(!) the loop it also works, interestingly.
>
> As for the actual code change: looking at the XCH bit is probably
> indeed the most robust and clever method of checking for the end of a
> transfer, so I am tempted to take this change. However there are more
> things broken, apparently, and I would like to get to the bottom of
> those issues, before trying to paper over them.
>
> Cheers,
> Andre
>
> [1] The driver (as most U-Boot SPI drivers, actually) tries to read
> spi-max-frequency from the SPI's *controller* DT node, although this
> is
> a SPI *slave* property. It (correctly) doesn't find anything in
> there,
> so falls back to some (assumed) safe value of 1 MHz.
Ooops... It sounds like the SPI framework is broken?
>
> > Check XCH bit when polling for transfer finish.
>
>
> >
> > Signed-off-by: Icenowy Zheng
> > ---
> > drivers/spi/spi-sunxi.c | 14 +-
> > 1 file changed, 5 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
> > index 2f7725..a424c6a98e 100644
> > --- a/drivers/spi/spi-sunxi.c
> > +++ b/drivers/spi/spi-sunxi.c
> > @@ -83,7 +83,7 @@ DECLARE_GLOBAL_DATA_PTR;
> > #endif
> > #define SUN4I_SPI_MIN_RATE 3000
> > #define SUN4I_SPI_DEFAULT_RATE 100
> > -#define SUN4I_SPI_TIMEOUT_US 100
> > +#define SUN4I_SPI_TIMEOUT_MS 1000
> >
> > #define SPI_REG(priv, reg) ((priv)->base + \
> > (priv)->variant->regs[reg])
> > @@ -326,7 +326,6 @@ static int sun4i_spi_xfer(struct udevice *dev,
> > unsigned int bitlen,
> > struct dm_spi_slave_plat *slave_plat =
> > dev_get_parent_plat(dev);
> >
> > u32 len = bitlen / 8;
> > - u32 rx_fifocnt;
> > u8 nbytes;
> > int ret;
> >
> > @@ -364,13 +363,10 @@ static int sun4i_spi_xfer(struct udevice
> > *dev, unsigned int bitlen,
> > setbits_le32(SPI_REG(priv, SPI_TCR),
> > SPI_BIT(priv, SPI_TCR_XCH));
> >
> > - /* Wait till RX FIFO to be empty */
> > - ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR),
> > - rx_fifocnt,
> > - (((rx_fifocnt &
> > - SPI_BIT(priv,
> > SPI_FSR_RF_CNT_MASK)) >>
> > -
> > SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes),
> > - SUN4I_SPI_TIMEOUT_US);
> > + /* Wait for the transfer to be done */
> > + ret = wait_for_bit_le32((const void *)SPI_REG(priv,
> > SPI_TCR),
> > + SPI_BIT(priv, SPI_TCR_XCH),
> > + false,
> > SUN4I_SPI_TIMEOUT_MS, false);
> > if (ret < 0) {
> > printf("ERROR: sun4i_spi: Timeout
> > transferring data\n");
> > sun4i_spi_set_cs(bus, slave_plat->cs,
> > false);
>
[PATCH sunxi/next] spi: sunxi: use XCH status to detect in-progress transfer
The current detection of RX FIFO depth seems to be not reliable, and
XCH will self-clear when a transfer is done.
Check XCH bit when polling for transfer finish.
Signed-off-by: Icenowy Zheng
---
drivers/spi/spi-sunxi.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index 2f7725..a424c6a98e 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -83,7 +83,7 @@ DECLARE_GLOBAL_DATA_PTR;
#endif
#define SUN4I_SPI_MIN_RATE 3000
#define SUN4I_SPI_DEFAULT_RATE 100
-#define SUN4I_SPI_TIMEOUT_US 100
+#define SUN4I_SPI_TIMEOUT_MS 1000
#define SPI_REG(priv, reg) ((priv)->base + \
(priv)->variant->regs[reg])
@@ -326,7 +326,6 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned int
bitlen,
struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
u32 len = bitlen / 8;
- u32 rx_fifocnt;
u8 nbytes;
int ret;
@@ -364,13 +363,10 @@ static int sun4i_spi_xfer(struct udevice *dev, unsigned
int bitlen,
setbits_le32(SPI_REG(priv, SPI_TCR),
SPI_BIT(priv, SPI_TCR_XCH));
- /* Wait till RX FIFO to be empty */
- ret = readl_poll_timeout(SPI_REG(priv, SPI_FSR),
-rx_fifocnt,
-(((rx_fifocnt &
-SPI_BIT(priv, SPI_FSR_RF_CNT_MASK)) >>
-SUN4I_FIFO_STA_RF_CNT_BITS) >= nbytes),
-SUN4I_SPI_TIMEOUT_US);
+ /* Wait for the transfer to be done */
+ ret = wait_for_bit_le32((const void *)SPI_REG(priv, SPI_TCR),
+ SPI_BIT(priv, SPI_TCR_XCH),
+ false, SUN4I_SPI_TIMEOUT_MS, false);
if (ret < 0) {
printf("ERROR: sun4i_spi: Timeout transferring data\n");
sun4i_spi_set_cs(bus, slave_plat->cs, false);
--
2.36.0
Re: [PATCH] sunxi: fix build when CONFIG_UART0_PORT_F is selected
在 2022-03-05星期六的 21:33 +，Andre Przywara写道：
> On Sat, 5 Mar 2022 00:06:01 +0800
> Icenowy Zheng wrote:
>
> Hi Icenowy,
>
> > Currently CONFIG_UART0_PORT_F will forbid the build of sunxi-mmc
> > driver,
> > which leads calls to it in board/sunxi/board.c a undefined
> > reference.
> >
> > Guard that code in #ifndef to fix build.
>
> That's indeed a problem.
>
> > Signed-off-by: Icenowy Zheng
> > ---
> > board/sunxi/board.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/board/sunxi/board.c b/board/sunxi/board.c
> > index 82c52b28f8..8a003d8559 100644
> > --- a/board/sunxi/board.c
> > +++ b/board/sunxi/board.c
> > @@ -539,6 +539,7 @@ int board_mmc_init(struct bd_info *bis)
> > {
> > __maybe_unused struct mmc *mmc0, *mmc1;
> >
> > +#ifndef CONFIG_UART0_PORT_F
>
> Shouldn't it be "#ifdef CONFIG_MMC_SUNXI" instead, which is the
> actual
> reason for the build fail?
> And furthermore, this is just a link failure, and I think we rely on
> toolchain garbage collection anyway, so I managed with:
Well I think we finally shouldn't let CONFIG_UART0_PORT_F conflicts
with CONFIG_MMC_SUNXI, because we should be able to at least use
CONFIG_MMC_SUNXI_SLOT_EXTRA when CONFIG_UART0_PORT_F.
In addition, I don't think toolchain GC is smart enough to remove a
reference.
>
> if (!CONFIG_IS_ENABLED(MMC_SUNXI))
> return 0;
>
> which avoids the nested #ifdef.
> Shall we go with this instead?
>
> > mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
> > mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
> > if (!mmc0)
> > @@ -549,6 +550,7 @@ int board_mmc_init(struct bd_info *bis)
> > mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
> > if (!mmc1)
> > return -1;
> > +#endif
> > #endif
> >
> > return 0;
>
[PATCH] sunxi: fix build when CONFIG_UART0_PORT_F is selected
Currently CONFIG_UART0_PORT_F will forbid the build of sunxi-mmc driver,
which leads calls to it in board/sunxi/board.c a undefined reference.
Guard that code in #ifndef to fix build.
Signed-off-by: Icenowy Zheng
---
board/sunxi/board.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 82c52b28f8..8a003d8559 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -539,6 +539,7 @@ int board_mmc_init(struct bd_info *bis)
{
__maybe_unused struct mmc *mmc0, *mmc1;
+#ifndef CONFIG_UART0_PORT_F
mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
if (!mmc0)
@@ -549,6 +550,7 @@ int board_mmc_init(struct bd_info *bis)
mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
if (!mmc1)
return -1;
+#endif
#endif
return 0;
--
2.35.1
Re: [PATCH 00/11] Add support for SUNIV and F1C100s.
在 2022-01-04星期二的 19:34 -0500，Jesse Taube写道： > This patch set aims to add suport for the SUNIV and F1C100s. > Suport has been in linux for a while now, but not in u-boot. > > This patchset contains: > - CPU specific initialization code > - SUNIV dram driver > - SUNIV clock driver adaption > - SUNIV gpio driver adaption > - SUNIV uart driver adaption > - F1C100s basic support > > I am hoping to get Icenowy's patches in as it seems she hasnt > submitted > in a while. The only edits I made to her code is rebasing it against > ML > and changing some formating. I also re-grouped her commits. I got too lazy to send it (because I think F1C100s is just too weak)... > > I am wondering if the dram driver should be moved into device drivers > rather than in mach-sunxi. > I am also wondering if it is okay to submit some one elses code, > and if so how should I do so. As you are keeping my SoB and adding yours, it's totally okay. Thanks for cleaning up these patches! ;-) > > Icenowy Zheng (11): > arm: arm926ej-s: start.S: port save_boot_params support from armv7 > code > arm: arm926ej-s: add sunxi code > dt-bindings: clock: Add initial suniv headers > dt-bindings: reset: Add initial suniv headers > ARM: sunxi: Add support for F1C100s > sunxi: Add F1C100s DRAM initial support > sunxi: board: Add support for SUNIV > configs: sunxi: Add common SUNIV header > sunxi: Add support for SUNIV architecture > ARM: dts: suniv: Add device tree files for F1C100s > configs: sunxi: Add support for Lichee Pi Nano > > arch/arm/cpu/arm926ejs/Makefile | 1 + > arch/arm/cpu/arm926ejs/start.S | 19 + > arch/arm/cpu/arm926ejs/sunxi/Makefile | 15 + > arch/arm/cpu/arm926ejs/sunxi/config.mk | 6 + > arch/arm/cpu/arm926ejs/sunxi/fel_utils.S | 37 ++ > arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S | 67 +++ > arch/arm/cpu/arm926ejs/sunxi/start.c | 1 + > arch/arm/cpu/arm926ejs/sunxi/timer.c | 114 + > arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds | 62 +++ > arch/arm/dts/Makefile | 2 + > arch/arm/dts/suniv-f1c100s-licheepi-nano.dts | 64 +++ > arch/arm/dts/suniv-f1c100s.dtsi | 6 + > arch/arm/dts/suniv.dtsi | 224 ++ > arch/arm/include/asm/arch-sunxi/clock.h | 2 +- > arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 25 ++ > arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 8 + > arch/arm/include/asm/arch-sunxi/dram.h | 2 + > arch/arm/include/asm/arch-sunxi/dram_suniv.h | 46 ++ > arch/arm/include/asm/arch-sunxi/gpio.h | 1 + > arch/arm/mach-sunxi/Kconfig | 16 +- > arch/arm/mach-sunxi/Makefile | 2 + > arch/arm/mach-sunxi/board.c | 31 +- > arch/arm/mach-sunxi/clock.c | 3 +- > arch/arm/mach-sunxi/clock_sun6i.c | 46 +- > arch/arm/mach-sunxi/cpu_info.c | 2 + > arch/arm/mach-sunxi/dram_helpers.c | 4 + > arch/arm/mach-sunxi/dram_suniv.c | 420 > ++ > board/sunxi/board.c | 4 +- > configs/licheepi_nano_defconfig | 13 + > configs/licheepi_nano_spiflash_defconfig | 25 ++ > include/configs/suniv.h | 14 + > include/configs/sunxi-common.h | 67 ++- > include/dt-bindings/clock/suniv-ccu.h | 68 +++ > include/dt-bindings/reset/suniv-ccu.h | 36 ++ > 34 files changed, 1424 insertions(+), 29 deletions(-) > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/Makefile > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/config.mk > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/fel_utils.S > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/lowlevel_init.S > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/start.c > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/timer.c > create mode 100644 arch/arm/cpu/arm926ejs/sunxi/u-boot-spl.lds > create mode 100644 arch/arm/dts/suniv-f1c100s-licheepi-nano.dts > create mode 100644 arch/arm/dts/suniv-f1c100s.dtsi > create mode 100644 arch/arm/dts/suniv.dtsi > create mode 100644 arch/arm/include/asm/arch-sunxi/dram_suniv.h > create mode 100644 arch/arm/mach-sunxi/dram_suniv.c > create mode 100644 configs/licheepi_nano_defconfig > create mode 100644 configs/licheepi_nano_spiflash_defconfig > create mode 100644 include/configs/suniv.h > create mode 100644 include/dt-bindings/clock/suniv-ccu.h > create mode 100644 include/dt-bindings/reset/suniv-ccu.h >
Re: [PATCH] sunxi: dts: Fix typoed eMMC check
在 2021-12-06星期一的 01:54 +，Andre Przywara写道：
> Commit 03510bf62149 ("sunxi: only include alias for eMMC when mmc2
> used") protected the eMMC alias in U-Boot's DT stub the with the
> associated Kconfig symbol, but was actually using the wrong name.
>
> Fix the name of the symbol to match what's defined in Kconfig and
> what
> the defconfig files actually use.
>
> Fixes: 03510bf62149 ("sunxi: only include alias for eMMC when mmc2
> used")
> Signed-off-by: Andre Przywara
> Reported-by: 5...@5kft.org
LGTM. I am just too careless.
Reviewed-by: Icenowy Zheng
> ---
> arch/arm/dts/sunxi-u-boot.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-
> boot.dtsi
> index b7244c1112a..f2d7361b84f 100644
> --- a/arch/arm/dts/sunxi-u-boot.dtsi
> +++ b/arch/arm/dts/sunxi-u-boot.dtsi
> @@ -13,7 +13,7 @@
> / {
> aliases {
> mmc0 = &mmc0;
> -#if CONFIG_MMC_SUNXI_EXTRA_SLOT == 2
> +#if CONFIG_MMC_SUNXI_SLOT_EXTRA == 2
> mmc1 = &mmc2;
> #endif
> };
Re: Pull request: u-boot-sunxi/master for 2021.10 - 2nd part
在 2021-10-29星期五的 10:41 -0400，Tom Rini写道：
> On Fri, Oct 29, 2021 at 10:20:32PM +0800, Icenowy Zheng wrote:
> > 在 2021-10-29星期五的 11:53 +0100，Andre Przywara写道：
> > > On Mon, 25 Oct 2021 14:29:10 -0400
> > > Tom Rini wrote:
> > >
> > > Hi Tom,
> > >
> > > > On Mon, Oct 25, 2021 at 03:06:58PM +0100, Andre Przywara wrote:
> > > >
> > > > > Hi Tom,
> > > > >
> > > > > please pull the second sunxi PR for the 2021.10 merge window.
> > > > > I decided to merge most of Samuel's rework and some smaller
> > > > > patches that
> > > > > pave the way for more DM transitions and for accommodating
> > > > > the
> > > > > RISC-V SoC
> > > > > in the future. Merging them now gives us the opportunity to
> > > > > get
> > > > > some wider
> > > > > testing, since those subtle changes tend to break things.
> > > > >
> > > > > Compile-tested for all 159 sunxi boards, boot-tested on
> > > > > Pine64-
> > > > > LTS
> > > > > and OrangePi Zero.
> > > > >
> > > > > Summary:
> > > > > - Add and enable watchdog driver
> > > > > - Prepare for SYSRESET driven AXP poweroff
> > > > > - Prepare for SoCs without MMC2
> > > > > - Some fixes for extending SPL (SPL-DM for RISC-V)
> > > > > - Some preparations for proper VBUS management
> > > > > - Fix secure monitor move
> > > > >
> > > > > Thanks,
> > > > > Andre
> > > > >
> > > > >
> > > > > The following changes since commit
> > > > > 355d1e24f6143c4839be3c015c191421c4e9449c:
> > > > >
> > > > > Merge
> > > > > https://source.denx.de/u-boot/custodians/u-boot-spi (2021-10-
> > > > > 23
> > > > > 10:49:28 -0400)
> > > > >
> > > > > are available in the Git repository at:
> > > > >
> > > > >
> > > > > https://source.denx.de/u-boot/custodians/u-boot-sunxi.git mas
> > > > > ter
> > > > >
> > > > > for you to fetch changes up to
> > > > > c846fe43f0561311eb7261b34023a04646cdbd0d:
> > > > >
> > > > > mmc: sunxi: conditionally include MMC2 initialization code
> > > > > (2021-10-25 14:54:57 +0100)
> > > > >
> > > >
> > > > So first, up, this is now applied to u-boot/master.
> > >
> > > Many thanks, and sorry for the late push!
> > >
> > > > Next, I dug out my original Kickstarted Pine A64 board (as it's
> > > > the
> > > > only
> > > > sunxi platform I have), and I see it's detected with 1GB memory
> > > > and
> > > > as
> > > > Pine64+ which seems wrong, with the pine64_plus_defconfig
> > > > (which is
> > > > what
> > > > I thought handled all of the A64 platforms).
> > >
> > > For the naming: There are three SKUs for the original Pine A64
> > > board:
> > > - Pine A64: 512 MB with 100Mbit Ethernet PHY, lacking display and
> > > camera
> > > connectors (rare, mostly to meet the original 15 USD price tag)
> > > - Pine A64+ 1GB: 1GB DRAM with 1Gbit Ethernet PHY, with all
> > > connectors
> > > - Pine A64+ 2GB: 2GB DRAM with 1Gbit Ethernet PHY, with all
> > > connectors
> >
> > You can check whether your board is non-Plus or Plus 1G by the
> > model of
> > the Ethernet PHY (non-Plus has RTL8201) or not soldered FPC
> > connectors.
> > They do share a PCB design. Plus 2G is a dedicated PCB design as it
> > needs to use 4x 512MB DRAM chips.
>
> OK, mine has an RTL8211E and is 1G for sure now that I look harder at
> it.
>
> On a related note, this board will draw power via the UART, is there
> any
> easy HW change I can do, to fix that? It's otherwise a lot harder to
> put this in to my CI lab.
What UART pins are you using? The ones in Euler bus or the ones in EXP
bus?
The UART pins in EXP bus should have transistors to prevent power
leakage...
>
> > > Also note that for those first boards from Pine64 the name of the
> > > company (Pine64) is sometimes uses for the boards as well
> > > ("Pine64
> > > board"), even tho
Re: Pull request: u-boot-sunxi/master for 2021.10 - 2nd part
在 2021-10-29星期五的 11:53 +0100，Andre Przywara写道：
> On Mon, 25 Oct 2021 14:29:10 -0400
> Tom Rini wrote:
>
> Hi Tom,
>
> > On Mon, Oct 25, 2021 at 03:06:58PM +0100, Andre Przywara wrote:
> >
> > > Hi Tom,
> > >
> > > please pull the second sunxi PR for the 2021.10 merge window.
> > > I decided to merge most of Samuel's rework and some smaller
> > > patches that
> > > pave the way for more DM transitions and for accommodating the
> > > RISC-V SoC
> > > in the future. Merging them now gives us the opportunity to get
> > > some wider
> > > testing, since those subtle changes tend to break things.
> > >
> > > Compile-tested for all 159 sunxi boards, boot-tested on Pine64-
> > > LTS
> > > and OrangePi Zero.
> > >
> > > Summary:
> > > - Add and enable watchdog driver
> > > - Prepare for SYSRESET driven AXP poweroff
> > > - Prepare for SoCs without MMC2
> > > - Some fixes for extending SPL (SPL-DM for RISC-V)
> > > - Some preparations for proper VBUS management
> > > - Fix secure monitor move
> > >
> > > Thanks,
> > > Andre
> > >
> > >
> > > The following changes since commit
> > > 355d1e24f6143c4839be3c015c191421c4e9449c:
> > >
> > > Merge
> > > https://source.denx.de/u-boot/custodians/u-boot-spi (2021-10-23
> > > 10:49:28 -0400)
> > >
> > > are available in the Git repository at:
> > >
> > >
> > > https://source.denx.de/u-boot/custodians/u-boot-sunxi.git master
> > >
> > > for you to fetch changes up to
> > > c846fe43f0561311eb7261b34023a04646cdbd0d:
> > >
> > > mmc: sunxi: conditionally include MMC2 initialization code
> > > (2021-10-25 14:54:57 +0100)
> > >
> >
> > So first, up, this is now applied to u-boot/master.
>
> Many thanks, and sorry for the late push!
>
> > Next, I dug out my original Kickstarted Pine A64 board (as it's the
> > only
> > sunxi platform I have), and I see it's detected with 1GB memory and
> > as
> > Pine64+ which seems wrong, with the pine64_plus_defconfig (which is
> > what
> > I thought handled all of the A64 platforms).
>
> For the naming: There are three SKUs for the original Pine A64 board:
> - Pine A64: 512 MB with 100Mbit Ethernet PHY, lacking display and
> camera
> connectors (rare, mostly to meet the original 15 USD price tag)
> - Pine A64+ 1GB: 1GB DRAM with 1Gbit Ethernet PHY, with all
> connectors
> - Pine A64+ 2GB: 2GB DRAM with 1Gbit Ethernet PHY, with all
> connectors
You can check whether your board is non-Plus or Plus 1G by the model of
the Ethernet PHY (non-Plus has RTL8201) or not soldered FPC connectors.
They do share a PCB design. Plus 2G is a dedicated PCB design as it
needs to use 4x 512MB DRAM chips.
>
> Also note that for those first boards from Pine64 the name of the
> company (Pine64) is sometimes uses for the boards as well ("Pine64
> board"), even though this should be "Pine A64 board from Pine64".
> That
> is somewhat reflected in the defconfig name. In hindsight the
> defconfig
> should have been named more "pine-a64_defconfig", but I guess this is
> too late now? I see a lot of inconsistencies in naming, especially
> regarding capitalisation and dashes vs. underscores, check
> configs/[bB]anana* for instance, but probably renaming causes more
> harm
> than good?
>
> So I guess you have the middle one (the most common among the first
> wave), so that all seems correct? We differentiate between the non-
> plus
> and plus version at runtime, by the amount of DRAM detected, so
> that's
> pretty reliable. The 1GB and 2GB are otherwise the same, so same DT.
> The actual non-plus versions are somewhat rare, I guess most people
> just added the 4(!) bucks to get more RAM and Gigabit Ethernet.
>
> > I've not booted this up in
> > forever, and Armbian (the first binary I grabbed) does this as well
> > with
> > v2020.10 (and I'm using the same TF-A rev of 87311b4) so maybe the
> > answer is I should just e-waste this board and pick up something
> > else?
>
> Not sure exactly why? Is there anything that's broken, apart from the
> presumed misnaming? I would be happy to hear about any issues you
> have,
> in my experience those "outsider" inputs are very useful (I am far
> too
> familiar with all those tiny quirks).
> When U-Boot starts, UEFI boot should work out of the box, just pop a
> generic arm64 Debian/SuSE/Fedora/Ubuntu EFI installer USB stick in,
> should work even with HDMI and USB keyboard.
>
> Cheers,
> Andre
Re: [PATCH] phy: rockchip: inno-usb2: fix hang when multiple controllers exit
在 2021-10-23星期六的 13:23 -0400，Siva Mahadevan写道：
> Icenowy Zheng wrote:
> > The OHCI and EHCI controllers are both bound to the same PHY. They
> > will
> > both do init and power_on operations when the controller is brought
> > up
> > and both do power_off and exit when the controller is stopped.
> > However,
> > the PHY uclass of U-Boot is not as sane as we thought -- they won't
> > maintain a status mark for PHYs, and thus the functions of the PHYs
> > could be called for multiple times. Calling init/power_on for
> > multiple
> > times have no severe problems, however calling power_off/exit for
> > multiple times have a problem -- the first exit call will stop the
> > PHY
> > clock, and power_off/exit calls after it still trying to write to
> > PHY
> > registers. The write operation to PHY registers will fail because
> > clock
> > is already stopped.
> >
> > Adapt the count mechanism from phy-sun4i-usb to both init/exit and
> > power_on/power_off functions to phy-rockchip-inno-usb2 to fix this
> > problem. With this stopping USB controllers (manually or before
> > booting
> > a kernel) will work.
> >
> > Signed-off-by: Icenowy Zheng
> > Fixes: ac97a9ece14e ("phy: rockchip: Add Rockchip USB2PHY driver")
> > ---
> > drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 21
> > +++
> > 1 file changed, 21 insertions(+)
> >
> > diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> > b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> > index 62b8ba3a4a..be9cc99d90 100644
> > --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> > +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
> > @@ -62,6 +62,8 @@ struct rockchip_usb2phy {
> > void *reg_base;
> > struct clk phyclk;
> > const struct rockchip_usb2phy_cfg *phy_cfg;
> > + int init_count;
> > + int power_on_count;
> > };
> >
> > static inline int property_enable(void *reg_base,
> > @@ -92,6 +94,10 @@ static int rockchip_usb2phy_power_on(struct phy
> > *phy)
> > struct rockchip_usb2phy *priv = dev_get_priv(parent);
> > const struct rockchip_usb2phy_port_cfg *port_cfg =
> > us2phy_get_port(phy);
> >
> > + priv->power_on_count++;
> > + if (priv->power_on_count != 1)
> > + return 0;
> > +
> > property_enable(priv->reg_base, &port_cfg->phy_sus, false);
> >
> > /* waiting for the utmi_clk to become stable */
> > @@ -106,6 +112,10 @@ static int rockchip_usb2phy_power_off(struct
> > phy *phy)
> > struct rockchip_usb2phy *priv = dev_get_priv(parent);
> > const struct rockchip_usb2phy_port_cfg *port_cfg =
> > us2phy_get_port(phy);
> >
> > + priv->power_on_count--;
> > + if (priv->power_on_count != 0)
> > + return 0;
> > +
> > property_enable(priv->reg_base, &port_cfg->phy_sus, true);
> >
> > return 0;
> > @@ -118,6 +128,10 @@ static int rockchip_usb2phy_init(struct phy
> > *phy)
> > const struct rockchip_usb2phy_port_cfg *port_cfg =
> > us2phy_get_port(phy);
> > int ret;
> >
> > + priv->init_count++;
> > + if (priv->init_count != 1)
> > + return 0;
> > +
> > ret = clk_enable(&priv->phyclk);
> > if (ret) {
> > dev_err(phy->dev, "failed to enable phyclk
> > (ret=%d)\n", ret);
> > @@ -140,6 +154,10 @@ static int rockchip_usb2phy_exit(struct phy
> > *phy)
> > struct udevice *parent = dev_get_parent(phy->dev);
> > struct rockchip_usb2phy *priv = dev_get_priv(parent);
> >
> > + priv->init_count--;
> > + if (priv->init_count != 0)
> > + return 0;
> > +
> > clk_disable(&priv->phyclk);
> >
> > return 0;
> > @@ -212,6 +230,9 @@ static int rockchip_usb2phy_probe(struct
> > udevice *dev)
> > return ret;
> > }
> >
> > + priv->power_on_count = 0;
> > + priv->init_count = 0;
> > +
> > return 0;
> > }
> >
> > --
> > 2.30.2
>
> Are there any plans of submitting this patch to u-boot mainline? I
> recently got a pinebook pro and got u-boot mainline working as-is
> plus
> this patch. I can confirm that this fixes the issue for me.
The current maintainer wants a fix in PHY framework instead of the
specific driver, but I am recently not interested in fixing it (because
PBP is my daily driver now, and I don't dare to do dangerous BL
development that will lead to regression on it).
Re: [PATCH 19/27] arm: dts: sunxi: do not renumber if mmc2 does not exist
在 2021-07-25星期日的 19:16 -0400，Yifan Gu写道：
> We renumber mmc2 to mmc1 for sunxi devices, but if mmc2 does not exist
> dts will not build.
>
> This patch prevents that by checking CONFIG_MMC_SUNXI_SLOT_EXTRA.
I have a similar patch at
https://patchwork.ozlabs.org/project/uboot/patch/20210722063015.421923-3-icen...@sipeed.com/
> ---
> arch/arm/dts/sunxi-u-boot.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-
> boot.dtsi
> index 06da009fa2..53db622144 100644
> --- a/arch/arm/dts/sunxi-u-boot.dtsi
> +++ b/arch/arm/dts/sunxi-u-boot.dtsi
> @@ -13,7 +13,9 @@
> / {
> aliases {
> mmc0 = &mmc0;
> +#if CONFIG_MMC_SUNXI_SLOT_EXTRA > 1
> mmc1 = &mmc2;
> +#endif
> };
>
> binman: binman {
[RFC PATCH 13/13] sunxi: add support for Sipeed Maix IIA Dock board
Maix IIA is a SoM by Sipeed, and a official baseboard is sold with it. Add support for this official baseboard with Maix IIA attached. Signed-off-by: Icenowy Zheng --- board/sunxi/MAINTAINERS| 5 + configs/sipeed_maix_iia_dock_defconfig | 8 2 files changed, 13 insertions(+) create mode 100644 configs/sipeed_maix_iia_dock_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 4fc26077b2..ae7c6a131a 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -493,6 +493,11 @@ M: VishnuPatekar S: Maintained F: configs/Sinovoip_BPI_M3_defconfig +SIPEED MAIX IIA DOCK BOARD +M: Icenowy Zheng +S: Maintained +F: configs/sipeed_maix_iia_dock_defconfig + SOPINE BOARD M: Icenowy Zheng S: Maintained diff --git a/configs/sipeed_maix_iia_dock_defconfig b/configs/sipeed_maix_iia_dock_defconfig new file mode 100644 index 00..a839f65e10 --- /dev/null +++ b/configs/sipeed_maix_iia_dock_defconfig @@ -0,0 +1,8 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="sun50i-r329-maix-iia-dock" +CONFIG_SPL=y +CONFIG_MACH_SUN50I_R329=y +CONFIG_MMC0_CD_PIN="PF6" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_ENV_FAT_DEVICE_AND_PART="1:auto" -- 2.30.2
[RFC PATCH 11/13] mmc: sunxi: add support for R329 MMC controller
R329 SoC has similar MMC controllers with previous Allwinner SoCs.
Add support for it by adding its compatible string.
Signed-off-by: Icenowy Zheng
---
drivers/mmc/sunxi_mmc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 6b809c001f..59cc28794d 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -734,6 +734,7 @@ static const struct udevice_id sunxi_mmc_ids[] = {
{ .compatible = "allwinner,sun50i-h6-emmc" },
{ .compatible = "allwinner,sun50i-a100-mmc" },
{ .compatible = "allwinner,sun50i-a100-emmc" },
+ { .compatible = "allwinner,sun50i-r329-mmc" },
{ /* sentinel */ }
};
--
2.30.2
[RFC PATCH 12/13] sunxi: sync R329 DTs from internal WIP kernel tree
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/Makefile | 2 +
arch/arm/dts/sun50i-r329-maix-iia-dock.dts | 36
arch/arm/dts/sun50i-r329-maix-iia.dtsi | 45 +
arch/arm/dts/sun50i-r329.dtsi | 225 +
4 files changed, 308 insertions(+)
create mode 100644 arch/arm/dts/sun50i-r329-maix-iia-dock.dts
create mode 100644 arch/arm/dts/sun50i-r329-maix-iia.dtsi
create mode 100644 arch/arm/dts/sun50i-r329.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3941a08cf4..cfafb80a5f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -643,6 +643,8 @@ dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-tanix-tx6.dtb
dtb-$(CONFIG_MACH_SUN50I_H616) += \
sun50i-h616-orangepi-zero2.dtb
+dtb-$(CONFIG_MACH_SUN50I_R329) += \
+ sun50i-r329-maix-iia-dock.dtb
dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-amarula-relic.dtb \
sun50i-a64-bananapi-m64.dtb \
diff --git a/arch/arm/dts/sun50i-r329-maix-iia-dock.dts
b/arch/arm/dts/sun50i-r329-maix-iia-dock.dts
new file mode 100644
index 00..2588eb6adb
--- /dev/null
+++ b/arch/arm/dts/sun50i-r329-maix-iia-dock.dts
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2021 Sipeed
+
+/dts-v1/;
+
+#include "sun50i-r329-maix-iia.dtsi"
+
+/ {
+ model = "Sipeed MAIX-II A Dock";
+ compatible = "sipeed,maix-iia-dock", "sipeed,maix-iia",
+"allwinner,sun50i-r329";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pb_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pf_pins>;
+
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-r329-maix-iia.dtsi
b/arch/arm/dts/sun50i-r329-maix-iia.dtsi
new file mode 100644
index 00..ac5c5a88d3
--- /dev/null
+++ b/arch/arm/dts/sun50i-r329-maix-iia.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2021 Sipeed
+
+#include "sun50i-r329.dtsi"
+
+#include
+
+/ {
+ ext_osc32k: ext_osc32k_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ clock-output-names = "ext_osc32k";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 1 0 GPIO_ACTIVE_LOW>; /* PM0 */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&rtc {
+ clocks = <&ext_osc32k>;
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_clk_pg0>, <&mmc1_cmd_pg1>, <&mmc1_d0_pg2>,
+ <&mmc1_d1_pg3>, <&mmc1_d2_pg4>, <&mmc1_d3_pg5>;
+
+ vmmc-supply = <®_vcc3v3>;
+ vqmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-r329.dtsi b/arch/arm/dts/sun50i-r329.dtsi
new file mode 100644
index 00..b4752020df
--- /dev/null
+++ b/arch/arm/dts/sun50i-r329.dtsi
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright (c) 2021 Sipeed
+
+#include
+#include
+#include
+#include
+#include
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <0>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a53";
+ device_type = "cpu";
+ reg = <1>;
+ enable-method = "psci&quo
[RFC PATCH 09/13] sunxi: sync R329 CCU binding headers from internal WIP kernel tree
Signed-off-by: Icenowy Zheng --- include/dt-bindings/clock/sun50i-r329-ccu.h | 73 +++ include/dt-bindings/clock/sun50i-r329-r-ccu.h | 32 include/dt-bindings/reset/sun50i-r329-ccu.h | 45 include/dt-bindings/reset/sun50i-r329-r-ccu.h | 23 ++ 4 files changed, 173 insertions(+) create mode 100644 include/dt-bindings/clock/sun50i-r329-ccu.h create mode 100644 include/dt-bindings/clock/sun50i-r329-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-r329-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-r329-r-ccu.h diff --git a/include/dt-bindings/clock/sun50i-r329-ccu.h b/include/dt-bindings/clock/sun50i-r329-ccu.h new file mode 100644 index 00..769a40a175 --- /dev/null +++ b/include/dt-bindings/clock/sun50i-r329-ccu.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Sipeed + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_R329_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_R329_CCU_H_ + +#define CLK_CPUX 1 + +#define CLK_APB1 5 + +#define CLK_CE 7 +#define CLK_BUS_CE 8 +#define CLK_AIPU 9 +#define CLK_BUS_VE 10 +#define CLK_BUS_DMA11 +#define CLK_BUS_MSGBOX 12 +#define CLK_BUS_SPINLOCK 13 +#define CLK_BUS_HSTIMER14 +#define CLK_AVS15 +#define CLK_BUS_DBG16 +#define CLK_BUS_PWM17 + +#define CLK_MBUS_DMA 19 +#define CLK_MBUS_CE20 +#define CLK_MBUS_NAND 21 +#define CLK_MBUS_CSI 22 +#define CLK_MBUS_ISP 23 + +#define CLK_NAND0 25 +#define CLK_NAND1 26 +#define CLK_BUS_NAND 27 +#define CLK_MMC0 28 +#define CLK_MMC1 29 +#define CLK_BUS_MMC0 30 +#define CLK_BUS_MMC1 31 +#define CLK_BUS_UART0 32 +#define CLK_BUS_UART1 33 +#define CLK_BUS_UART2 34 +#define CLK_BUS_UART3 35 +#define CLK_BUS_I2C0 36 +#define CLK_BUS_I2C1 37 +#define CLK_BUS_SCR38 +#define CLK_SPI0 39 +#define CLK_SPI1 40 +#define CLK_BUS_SPI0 41 +#define CLK_BUS_SPI1 42 +#define CLK_EMAC_25M_DIV 43 +#define CLK_EMAC_25M 44 +#define CLK_BUS_EMAC 45 +#define CLK_IR_RX 46 +#define CLK_BUS_IR_RX 47 +#define CLK_IR_TX 48 +#define CLK_BUS_IR_TX 49 +#define CLK_I2S0 50 +#define CLK_I2S1 51 +#define CLK_BUS_I2S0 52 +#define CLK_BUS_I2S1 53 +#define CLK_SPDIF 54 +#define CLK_BUS_SPDIF 55 +#define CLK_USB_OHCI0 56 +#define CLK_USB_PHY0 57 +#define CLK_USB_OHCI1 58 +#define CLK_USB_PHY1 59 +#define CLK_BUS_OHCI0 60 +#define CLK_BUS_OHCI1 61 +#define CLK_BUS_EHCI0 62 +#define CLK_BUS_OTG63 +#define CLK_LEDC 64 +#define CLK_BUS_LEDC 65 + +#endif /* _DT_BINDINGS_CLK_SUN50I_R329_CCU_H_ */ diff --git a/include/dt-bindings/clock/sun50i-r329-r-ccu.h b/include/dt-bindings/clock/sun50i-r329-r-ccu.h new file mode 100644 index 00..2044d25383 --- /dev/null +++ b/include/dt-bindings/clock/sun50i-r329-r-ccu.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2021 Sipeed + */ + +#ifndef _DT_BINDINGS_CLK_SUN50I_R329_R_CCU_H_ +#define _DT_BINDINGS_CLK_SUN50I_R329_R_CCU_H_ + +#define CLK_R_APB1 12 + +#define CLK_R_BUS_GPADC14 +#define CLK_R_BUS_THS 15 +#define CLK_R_PWM 16 +#define CLK_R_BUS_PWM 17 +#define CLK_R_CODEC_ADC18 +#define CLK_R_CODEC_DAC19 +#define CLK_R_BUS_CODEC20 +#define CLK_R_DMIC 21 +#define CLK_R_BUS_DMIC 22 +#define CLK_R_BUS_LRADC23 +#define CLK_R_I2S 24 +#define CLK_R_I2S_ASRC 25 +#define CLK_R_BUS_I2S 26 +#define CLK_R_BUS_UART 27 +#define CLK_R_BUS_I2C 28 +#define CLK_R_IR 29 +#define CLK_R_BUS_IR 30 +#define CLK_R_BUS_MSGBOX 31 +#define CLK_R_BUS_SPINLOCK 32 +#define CLK_R_BUS_RTC 33 + +#endif /* _DT_BINDINGS_CLK_SUN50I_R329_R_CCU_H_ */ diff --git a/include/dt-bindings/reset/sun50i-r329-ccu.h b/include/dt-bindings/reset/sun50i-r329-ccu.h new file mode 100644 index 00..bb704a8244 --- /dev/null +++ b/include/dt-bindings/reset/sun50i-r329-ccu.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2021 Sipeed + */ + +#ifndef _DT_BINDINGS_RST_SUN50I_R329_CCU_H_ +#define _DT_BINDINGS_RST_SUN50I_R329_CCU_H_ + +#define RST_MBUS 0 +#define RST_BUS_CE 1 +#define RST_BUS_AIPU 2 +#define RST_BUS_DMA3 +#define RST_BUS_MSGBOX 4 +#define RST_BUS_SPINLOCK
[RFC PATCH 10/13] clk: sunxi: add support for R329 in sunxi DM clock driver
Currently only a subset of clocks/resets (similar to other SoCs) are
supported.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi/Kconfig| 7 +++
drivers/clk/sunxi/Makefile | 1 +
drivers/clk/sunxi/clk_r329.c | 94
3 files changed, 102 insertions(+)
create mode 100644 drivers/clk/sunxi/clk_r329.c
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index bf084fa7a8..8dd3be4683 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -86,6 +86,13 @@ config CLK_SUN50I_H616
This enables common clock driver support for platforms based
on Allwinner H616 SoC.
+config CLK_SUN50I_R329
+ bool "Clock driver for Allwinner R329"
+ default MACH_SUN50I_R329
+ help
+ This enables common clock driver support for platforms based
+ on Allwinner R329 SoC.
+
config CLK_SUN50I_A64
bool "Clock driver for Allwinner A64"
default MACH_SUN50I
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 4f9282a8b9..050f7ecc46 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -19,4 +19,5 @@ obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
+obj-$(CONFIG_CLK_SUN50I_R329) += clk_r329.o
obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/drivers/clk/sunxi/clk_r329.c b/drivers/clk/sunxi/clk_r329.c
new file mode 100644
index 00..17157214b6
--- /dev/null
+++ b/drivers/clk/sunxi/clk_r329.c
@@ -0,0 +1,94 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Sipeed
+ * Based on clk_h616.c, which is:
+ * Copyright (C) 2021 Jernej Skrabec
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct ccu_clk_gate r329_gates[] = {
+ [CLK_BUS_MMC0] = GATE(0x84c, BIT(0)),
+ [CLK_BUS_MMC1] = GATE(0x84c, BIT(1)),
+
+ [CLK_BUS_UART0] = GATE(0x90c, BIT(0)),
+ [CLK_BUS_UART1] = GATE(0x90c, BIT(1)),
+ [CLK_BUS_UART2] = GATE(0x90c, BIT(2)),
+ [CLK_BUS_UART3] = GATE(0x90c, BIT(3)),
+
+ [CLK_SPI0] = GATE(0x940, BIT(31)),
+ [CLK_SPI1] = GATE(0x944, BIT(31)),
+
+ [CLK_BUS_SPI0] = GATE(0x96c, BIT(0)),
+ [CLK_BUS_SPI1] = GATE(0x96c, BIT(1)),
+
+ [CLK_BUS_EMAC] = GATE(0x97c, BIT(0)),
+
+ [CLK_USB_PHY0] = GATE(0xa70, BIT(29)),
+ [CLK_USB_OHCI0] = GATE(0xa70, BIT(31)),
+
+ [CLK_USB_PHY1] = GATE(0xa74, BIT(29)),
+ [CLK_USB_OHCI1] = GATE(0xa74, BIT(31)),
+
+ [CLK_BUS_OHCI0] = GATE(0xa8c, BIT(0)),
+ [CLK_BUS_OHCI1] = GATE(0xa8c, BIT(1)),
+ [CLK_BUS_EHCI0] = GATE(0xa8c, BIT(4)),
+ [CLK_BUS_OTG] = GATE(0xa8c, BIT(8)),
+};
+
+static struct ccu_reset r329_resets[] = {
+ [RST_BUS_MMC0] = RESET(0x84c, BIT(16)),
+ [RST_BUS_MMC1] = RESET(0x84c, BIT(17)),
+
+ [RST_BUS_UART0] = RESET(0x90c, BIT(16)),
+ [RST_BUS_UART1] = RESET(0x90c, BIT(17)),
+ [RST_BUS_UART2] = RESET(0x90c, BIT(18)),
+ [RST_BUS_UART3] = RESET(0x90c, BIT(19)),
+
+ [RST_BUS_SPI0] = RESET(0x96c, BIT(16)),
+ [RST_BUS_SPI1] = RESET(0x96c, BIT(17)),
+
+ [RST_BUS_EMAC] = RESET(0x97c, BIT(16)),
+
+ [RST_USB_PHY0] = RESET(0xa70, BIT(30)),
+
+ [RST_USB_PHY1] = RESET(0xa74, BIT(30)),
+
+ [RST_BUS_OHCI0] = RESET(0xa8c, BIT(16)),
+ [RST_BUS_OHCI1] = RESET(0xa8c, BIT(17)),
+ [RST_BUS_EHCI0] = RESET(0xa8c, BIT(20)),
+ [RST_BUS_OTG] = RESET(0xa8c, BIT(24)),
+};
+
+static const struct ccu_desc r329_ccu_desc = {
+ .gates = r329_gates,
+ .resets = r329_resets,
+};
+
+static int r329_clk_bind(struct udevice *dev)
+{
+ return sunxi_reset_bind(dev, ARRAY_SIZE(r329_resets));
+}
+
+static const struct udevice_id r329_ccu_ids[] = {
+ { .compatible = "allwinner,sun50i-r329-ccu",
+ .data = (ulong)&r329_ccu_desc },
+ { }
+};
+
+U_BOOT_DRIVER(clk_sun50i_r329) = {
+ .name = "sun50i_r329_ccu",
+ .id = UCLASS_CLK,
+ .of_match = r329_ccu_ids,
+ .priv_auto = sizeof(struct ccu_priv),
+ .ops= &sunxi_clk_ops,
+ .probe = sunxi_clk_probe,
+ .bind = r329_clk_bind,
+};
--
2.30.2
[RFC PATCH 08/13] sunxi: add Kconfig option for R329
As most code are ready for basic R329 support, let's add a Kconfig
option for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/Kconfig| 14 +-
arch/arm/mach-sunxi/cpu_info.c | 2 ++
common/spl/Kconfig | 1 +
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index c9bb47a8bd..9d3ec82497 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -128,6 +128,7 @@ config SUN8I_RSB
config SUNXI_SRAM_ADDRESS
hex
default 0x1 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
+ default 0x10 if MACH_SUN50I_R329
default 0x2 if SUN50I_GEN_H6
default 0x0
---help---
@@ -371,6 +372,12 @@ config MACH_SUN50I_H616
select DRAM_SUN50I_H616
select SUN50I_GEN_H6
+config MACH_SUN50I_R329
+ bool "sun50i (Allwinner R329)"
+ select ARM64
+ select DRAM_SUN50I_R329
+ select SUN50I_GEN_H6
+
endchoice
# The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
@@ -420,7 +427,8 @@ config SUNXI_DRAM_LPDDR3
choice
prompt "DRAM Type and Timing"
- default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
+ default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S && !MACH_SUN50I_R329
+ default SUNXI_DRAM_DDR3_R329 if MACH_SUN50I_R329
default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
config SUNXI_DRAM_DDR3_1333
@@ -488,6 +496,7 @@ config DRAM_CLK
MACH_SUN8I_V3S
default 672 if MACH_SUN50I
default 744 if MACH_SUN50I_H6
+ default 775 if MACH_SUN50I_R329
default 720 if MACH_SUN50I_H616
---help---
Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
@@ -510,6 +519,7 @@ config DRAM_ZQ
MACH_SUN8I_A23 || MACH_SUN8I_A33 || MACH_SUN8I_A83T
default 127 if MACH_SUN7I
default 14779 if MACH_SUN8I_V3S
+ default 3067 if MACH_SUN50I_R329
default 3881979 if MACH_SUNXI_H3_H5 || MACH_SUN8I_R40 || MACH_SUN50I_H6
default 4145117 if MACH_SUN9I
default 3881915 if MACH_SUN50I
@@ -616,6 +626,7 @@ config SYS_CLK_FREQ
default 100800 if MACH_SUN9I
default 88800 if MACH_SUN50I_H6
default 100800 if MACH_SUN50I_H616
+ default 100800 if MACH_SUN50I_R329
config SYS_CONFIG_NAME
default "sun4i" if MACH_SUN4I
@@ -627,6 +638,7 @@ config SYS_CONFIG_NAME
default "sun50i" if MACH_SUN50I
default "sun50i" if MACH_SUN50I_H6
default "sun50i" if MACH_SUN50I_H616
+ default "sun50i" if MACH_SUN50I_R329
config SYS_BOARD
default "sunxi"
diff --git a/arch/arm/mach-sunxi/cpu_info.c b/arch/arm/mach-sunxi/cpu_info.c
index ba33ef2430..8021f4c307 100644
--- a/arch/arm/mach-sunxi/cpu_info.c
+++ b/arch/arm/mach-sunxi/cpu_info.c
@@ -101,6 +101,8 @@ int print_cpuinfo(void)
puts("CPU: Allwinner H6 (SUN50I)\n");
#elif defined CONFIG_MACH_SUN50I_H616
puts("CPU: Allwinner H616 (SUN50I)\n");
+#elif defined CONFIG_MACH_SUN50I_R329
+ puts("CPU: Allwinner R329 (SUN50I)\n");
#else
#warning Please update cpu_info.c with correct CPU information
puts("CPU: SUNXI Family\n");
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index 2df3e5d869..ed4477ff93 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -150,6 +150,7 @@ config SPL_TEXT_BASE
hex "SPL Text Base"
default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
+ default 0x100060 if MACH_SUN50I_R329
default 0x20060 if SUN50I_GEN_H6
default 0x00060 if ARCH_SUNXI
default 0xfffc if ARCH_ZYNQMP
--
2.30.2
[RFC PATCH 05/13] sunxi: add support for R329 clocks
R329 has a quite different clock tree than other SoCs. It has only 4
PLLs and its PLL-PERIPH has two post dividers, one for the normal
PLL-PERIPH-2x output and another for a special PLL-PERIPH-800M output.
In addition, its PLL configuration registers are in PRCM memory zone,
not the ordinary CPUX CCU one.
Add support for basical R329 clock initialization.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/clock_sun50i_h6.c | 49 ---
1 file changed, 44 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-sunxi/clock_sun50i_h6.c
b/arch/arm/mach-sunxi/clock_sun50i_h6.c
index a947463e0a..28bc5fccd8 100644
--- a/arch/arm/mach-sunxi/clock_sun50i_h6.c
+++ b/arch/arm/mach-sunxi/clock_sun50i_h6.c
@@ -9,6 +9,13 @@ void clock_init_safe(void)
{
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#ifdef CONFIG_MACH_SUN50I_R329
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ struct sunxi_prcm_reg *const pllccm = prcm;
+#else
+ struct sunxi_ccm_reg *const pllccm = ccm;
+#endif
/* this seems to enable PLLs on H616 */
if (IS_ENABLED(CONFIG_MACH_SUN50I_H616))
@@ -16,22 +23,26 @@ void clock_init_safe(void)
clock_set_pll1(40800);
- writel(CCM_PLL6_DEFAULT, &ccm->pll6_cfg);
- while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_LOCK))
+ writel(CCM_PLL6_DEFAULT, &pllccm->pll6_cfg);
+ while (!(readl(&pllccm->pll6_cfg) & CCM_PLL6_LOCK))
;
clrsetbits_le32(&ccm->cpu_axi_cfg, CCM_CPU_AXI_APB_MASK |
CCM_CPU_AXI_AXI_MASK,
CCM_CPU_AXI_DEFAULT_FACTORS);
writel(CCM_PSI_AHB1_AHB2_DEFAULT, &ccm->psi_ahb1_ahb2_cfg);
+#ifdef CCM_AHB3_DEFAULT
writel(CCM_AHB3_DEFAULT, &ccm->ahb3_cfg);
+#endif
writel(CCM_APB1_DEFAULT, &ccm->apb1_cfg);
+#ifndef CONFIG_MACH_SUN50I_R329
/*
* The mux and factor are set, but the clock will be enabled in
* DRAM initialization code.
*/
writel(MBUS_CLK_SRC_PLL6X2 | MBUS_CLK_M(3), &ccm->mbus_cfg);
+#endif
}
#endif
@@ -60,8 +71,20 @@ void clock_set_pll1(unsigned int clk)
{
struct sunxi_ccm_reg * const ccm =
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
+#ifdef CONFIG_MACH_SUN50I_R329
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+ struct sunxi_prcm_reg *const pllccm = prcm;
+#else
+ struct sunxi_ccm_reg *const pllccm = ccm;
+#endif
u32 val;
+#ifdef CONFIG_MACH_SUN50I_R329
+ /* Fix undervoltage reset threshold */
+ clrsetbits_le32(0x070901f4, 0xfff, 0xc0);
+#endif
+
/* Do not support clocks < 288MHz as they need factor P */
if (clk < 28800) clk = 28800;
@@ -73,11 +96,11 @@ void clock_set_pll1(unsigned int clk)
/* clk = 24*n/p, p is ignored if clock is >288MHz */
writel(CCM_PLL1_CTRL_EN | CCM_PLL1_LOCK_EN | CCM_PLL1_CLOCK_TIME_2 |
-#ifdef CONFIG_MACH_SUN50I_H616
+#ifndef CONFIG_MACH_SUN50I_H6
CCM_PLL1_OUT_EN |
#endif
- CCM_PLL1_CTRL_N(clk / 2400), &ccm->pll1_cfg);
- while (!(readl(&ccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
+ CCM_PLL1_CTRL_N(clk / 2400), &pllccm->pll1_cfg);
+ while (!(readl(&pllccm->pll1_cfg) & CCM_PLL1_LOCK)) {}
/* Switch CPU to PLL1 */
val = readl(&ccm->cpu_axi_cfg);
@@ -87,6 +110,7 @@ void clock_set_pll1(unsigned int clk)
}
#endif
+#ifndef CONFIG_MACH_SUN50I_R329
unsigned int clock_get_pll6(void)
{
struct sunxi_ccm_reg *const ccm =
@@ -102,6 +126,21 @@ unsigned int clock_get_pll6(void)
/* The register defines PLL6-2X or PLL6-4X, not plain PLL6 */
return 2400 / m * n / div1 / div2;
}
+#else
+unsigned int clock_get_pll6(void)
+{
+ struct sunxi_prcm_reg *const prcm =
+ (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
+
+ uint32_t rval = readl(&prcm->pll6_cfg);
+ int m = ((rval & CCM_PLL6_CTRL_M_MASK) >> CCM_PLL6_CTRL_M_SHIFT) + 1;
+ int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
+ int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
+ CCM_PLL6_CTRL_DIV1_SHIFT) + 1;
+ /* The register defines PLL6-2X, not plain PLL6 */
+ return 2400 / m * n / div1 / 2;
+}
+#endif
int clock_twi_onoff(int port, int state)
{
--
2.30.2
[RFC PATCH 06/13] sunxi: add support for basical pinmux setup on R329
Allwinner R329 SoC is the first known Allwinner SoC that has two
possible pinmux setups for MMC0 controller.
Support configuration of both setups of MMC0 and UART0 at PB4/5.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
arch/arm/mach-sunxi/Kconfig| 7 +++
arch/arm/mach-sunxi/board.c| 4
board/sunxi/board.c| 20
4 files changed, 34 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 2969a530ae..da9acfab78 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -166,12 +166,14 @@ enum sunxi_gpio_number {
#define SUN8I_A83T_GPB_UART0 2
#define SUN8I_V3S_GPB_UART03
#define SUN50I_GPB_UART0 4
+#define SUN50I_R329_GPB_UART0 2
#define SUNXI_GPC_NAND 2
#define SUNXI_GPC_SPI0 3
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
#define SUN50I_GPC_SPI04
+#define SUN50I_R329_GPC_SDC0 3
#define SUN8I_GPD_SDC1 3
#define SUNXI_GPD_LCD0 2
@@ -185,6 +187,7 @@ enum sunxi_gpio_number {
#define SUNXI_GPF_SDC0 2
#define SUNXI_GPF_UART04
#define SUN8I_GPF_UART03
+#define SUN50I_R329_GPF_SDC0 5
#define SUN4I_GPG_SDC1 4
#define SUN5I_GPG_SDC1 2
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 49f94f095c..391a3dd9e5 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -672,6 +672,13 @@ config MMC3_CD_PIN
---help---
See MMC0_CD_PIN help text.
+config MMC0_PINS
+ string "Pins for mmc0"
+ default "PF"
+ depends on MACH_SUN50I_R329
+ ---help---
+ See MMC1_PINS help text.
+
config MMC1_PINS
string "Pins for mmc1"
default ""
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index e979e426dd..1aa31c7e05 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -129,6 +129,10 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H616_GPH_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H616_GPH_UART0);
sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
+#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_R329)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(4), SUN50I_R329_GPB_UART0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(5), SUN50I_R329_GPB_UART0);
+ sunxi_gpio_set_pull(SUNXI_GPB(5), SUNXI_GPIO_PULL_UP);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index 67acc01d83..bfc90345d9 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -417,12 +417,32 @@ static void mmc_pinmux_setup(int sdc)
switch (sdc) {
case 0:
+#if defined(CONFIG_MACH_SUN50I_R329)
+ pins = sunxi_name_to_gpio_bank(CONFIG_MMC0_PINS);
+
+ if (pins == SUNXI_GPIO_C) {
+ /* SDC0: PC0-PC6 */
+ for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(6); pin++) {
+ sunxi_gpio_set_cfgpin(pin,
SUN50I_R329_GPC_SDC0);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ } else {
+ /* SDC0: PF0-PF5 */
+ for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
+ sunxi_gpio_set_cfgpin(pin,
SUN50I_R329_GPF_SDC0);
+ sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
+ sunxi_gpio_set_drv(pin, 2);
+ }
+ }
+#else
/* SDC0: PF0-PF5 */
for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
sunxi_gpio_set_drv(pin, 2);
}
+#endif
break;
case 1:
--
2.30.2
[RFC PATCH 03/13] mmc: sunxi: conditionally include MMC2 initialization code
Allwinner R329 has no MMC2. Only include the code of MMC2 if the base address of it is defined. Signed-off-by: Icenowy Zheng --- drivers/mmc/sunxi_mmc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c index 178b8cf106..6b809c001f 100644 --- a/drivers/mmc/sunxi_mmc.c +++ b/drivers/mmc/sunxi_mmc.c @@ -73,10 +73,12 @@ static int mmc_resource_init(int sdc_no) priv->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; priv->mclkreg = &ccm->sd1_clk_cfg; break; +#ifdef SUNXI_MMC2_BASE case 2: priv->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; priv->mclkreg = &ccm->sd2_clk_cfg; break; +#endif #ifdef SUNXI_MMC3_BASE case 3: priv->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; -- 2.30.2
[RFC PATCH 04/13] sunxi: add memory addresses for R329 SoC
Allwinner R329 SoC has a different memory map with previous post-H6
SoCs.
Add the memory map to a dedicated header file, fill everywhere that
uses a hardcoded MMIO address and specify the SPL/ATF load address.
Signed-off-by: Icenowy Zheng
---
arch/arm/cpu/armv8/fel_utils.S| 2 +-
arch/arm/dts/sunxi-u-boot.dtsi| 2 +
arch/arm/include/asm/arch-sunxi/boot0.h | 4 +-
.../include/asm/arch-sunxi/clock_sun50i_h6.h | 17 ++
arch/arm/include/asm/arch-sunxi/cpu.h | 2 +
.../include/asm/arch-sunxi/cpu_sun50i_r329.h | 58 +++
arch/arm/include/asm/arch-sunxi/prcm_sun50i.h | 33 +++
include/configs/sunxi-common.h| 3 +
8 files changed, 119 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sun50i_r329.h
diff --git a/arch/arm/cpu/armv8/fel_utils.S b/arch/arm/cpu/armv8/fel_utils.S
index 7def44ad1d..aa16d79df9 100644
--- a/arch/arm/cpu/armv8/fel_utils.S
+++ b/arch/arm/cpu/armv8/fel_utils.S
@@ -40,7 +40,7 @@ ENTRY(return_to_fel)
str w2, [x1]
ldr x0, =0xfa50392f // CPU hotplug magic
-#ifdef CONFIG_MACH_SUN50I_H616
+#if defined(CONFIG_MACH_SUN50I_H616) || defined(CONFIG_MACH_SUN50I_R329)
ldr x2, =(SUNXI_R_CPUCFG_BASE + 0x1c0)
str w0, [x2], #0x4
#elif CONFIG_MACH_SUN50I_H6
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index b7244c1112..9bb6fffeb4 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -5,6 +5,8 @@
#define SCP_ADDR 0x114000
#elif defined(CONFIG_MACH_SUN50I_H616)
#define BL31_ADDR 0x4000
+#elif defined(CONFIG_MACH_SUN50I_R329)
+#define BL31_ADDR 0x124000
#else
#define BL31_ADDR 0x44000
#define SCP_ADDR 0x5
diff --git a/arch/arm/include/asm/arch-sunxi/boot0.h
b/arch/arm/include/asm/arch-sunxi/boot0.h
index e8e8e38f05..a791c7c403 100644
--- a/arch/arm/include/asm/arch-sunxi/boot0.h
+++ b/arch/arm/include/asm/arch-sunxi/boot0.h
@@ -39,7 +39,9 @@
.word 0xf57ff06f // isb sy
.word 0xe320f003 // wfi
.word 0xeafd // b @wfi
-#ifndef CONFIG_SUN50I_GEN_H6
+#if defined(CONFIG_MACH_SUN50I_R329)
+ .word 0x08100040 // writeable RVBAR mapping address
+#elif !defined(CONFIG_SUN50I_GEN_H6)
.word 0x017000a0 // writeable RVBAR mapping address
#else
.word 0x09010040 // writeable RVBAR mapping address
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
index 37df4410ea..6c3b8ea351 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun50i_h6.h
@@ -250,10 +250,19 @@ struct sunxi_ccm_reg {
#define CCM_PLL6_LOCK BIT(28)
#define CCM_PLL6_CTRL_N_SHIFT 8
#define CCM_PLL6_CTRL_N_MASK (0xff << CCM_PLL6_CTRL_N_SHIFT)
+#ifndef CONFIG_MACH_SUN50I_R329
#define CCM_PLL6_CTRL_DIV1_SHIFT 0
#define CCM_PLL6_CTRL_DIV1_MASK(0x1 <<
CCM_PLL6_CTRL_DIV1_SHIFT)
#define CCM_PLL6_CTRL_DIV2_SHIFT 1
#define CCM_PLL6_CTRL_DIV2_MASK(0x1 <<
CCM_PLL6_CTRL_DIV2_SHIFT)
+#else
+#define CCM_PLL6_CTRL_M_SHIFT 1
+#define CCM_PLL6_CTRL_M_MASK (0x1 << CCM_PLL6_CTRL_DIV2_SHIFT)
+#define CCM_PLL6_CTRL_DIV1_SHIFT 16
+#define CCM_PLL6_CTRL_DIV1_MASK(0x7 <<
CCM_PLL6_CTRL_DIV1_SHIFT)
+#define CCM_PLL6_CTRL_DIV2_SHIFT 20
+#define CCM_PLL6_CTRL_DIV2_MASK(0x7 <<
CCM_PLL6_CTRL_DIV2_SHIFT)
+#endif
/* cpu_axi bit field*/
#define CCM_CPU_AXI_MUX_MASK (0x3 << 24)
@@ -285,6 +294,14 @@ struct sunxi_ccm_reg {
/* apb1 bit field */
#define CCM_APB1_DEFAULT 0x03000102
+#elif CONFIG_MACH_SUN50I_R329
+#define CCM_PLL6_DEFAULT 0xa8216300
+
+/* ahb bit field */
+#define CCM_PSI_AHB1_AHB2_DEFAULT 0x0302
+
+/* apb1 bit field */
+#define CCM_APB1_DEFAULT 0x0201
#endif
/* apb2 bit field */
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index b08f202374..20d04cac74 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -8,6 +8,8 @@
#if defined(CONFIG_MACH_SUN9I)
#include
+#elif defined(CONFIG_MACH_SUN50I_R329)
+#include
#elif defined(CONFIG_SUN50I_GEN_H6)
#include
#else
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_r329.h
b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_r329.h
new file mode 100644
index 00..3d2237a59f
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_r329.h
@@ -0,0 +1,58 @@
+/*
+ * (C) Copyright 2021 Sipeed
+ *
+ * SPDX-License-Identifier:GPL-2.0+
+ */
+
+#ifndef _SUNXI_CPU_SUN50I_H6_H
+#define _SUNXI_CPU_SUN50I_H6_H
+
+#define SUNXI_SRAM_A1_BASE 0x0002
+#define SUNXI_SRAM_A2_BASE
[RFC PATCH 01/13] sunxi: decide the inclusion of SCP by SCP_ADDR existence
There are more Allwinner SoCs that do not have a SCP now.
When there's no SCP_ADDR macro defined, we can assume there's no SCP
available.
Drop the scp part of FIT description when SCP_ADDR does not exist.
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/sunxi-u-boot.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 06da009fa2..4a6ed3a7dd 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -64,7 +64,7 @@
};
};
-#ifndef CONFIG_MACH_SUN50I_H616
+#ifdef SCP_ADDR
scp {
description = "SCP firmware";
type = "firmware";
@@ -92,7 +92,7 @@
@config-SEQ {
description = "NAME";
firmware = "atf";
-#ifdef CONFIG_MACH_SUN50I_H616
+#ifndef SCP_ADDR
loadables = "uboot";
#else
loadables = "scp", "uboot";
--
2.30.2
[RFC PATCH 07/13] sunxi: add support for R329 DRAM controller
R329 has a new DRAM controller, which looks like a combination of the
H6/H616 MCTL_COM part and the SUNXI_DW MCTL_CTL part. This design has
already got reused by Allwinner, and V831/V833 SoCs have similar
memory controller.
Add support for it. To prepare for further support of other SoCs,
routines with socid parameter are added, although not checked now.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
arch/arm/include/asm/arch-sunxi/dram.h| 2 +
.../include/asm/arch-sunxi/dram_sun50i_r329.h | 232 +++
arch/arm/mach-sunxi/Kconfig | 16 +-
arch/arm/mach-sunxi/Makefile | 2 +
arch/arm/mach-sunxi/dram_sun50i_r329.c| 377 ++
arch/arm/mach-sunxi/dram_timings/Makefile | 1 +
arch/arm/mach-sunxi/dram_timings/ddr3_r329.c | 89 +
8 files changed, 719 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_r329.h
create mode 100644 arch/arm/mach-sunxi/dram_sun50i_r329.c
create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_r329.c
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 20d04cac74..a968af6012 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -21,5 +21,6 @@
#define SOCID_V3S 0x1681
#define SOCID_H5 0x1718
#define SOCID_R40 0x1701
+#define SOCID_R329 0x1851
#endif /* _SUNXI_CPU_H */
diff --git a/arch/arm/include/asm/arch-sunxi/dram.h
b/arch/arm/include/asm/arch-sunxi/dram.h
index c3b3e1f512..36549a47c5 100644
--- a/arch/arm/include/asm/arch-sunxi/dram.h
+++ b/arch/arm/include/asm/arch-sunxi/dram.h
@@ -31,6 +31,8 @@
#include
#elif defined(CONFIG_MACH_SUN50I_H616)
#include
+#elif defined(CONFIG_MACH_SUN50I_R329)
+#include
#else
#include
#endif
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_r329.h
b/arch/arm/include/asm/arch-sunxi/dram_sun50i_r329.h
new file mode 100644
index 00..723c687670
--- /dev/null
+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_r329.h
@@ -0,0 +1,232 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * sun50i R329 platform dram controller register and constant defines
+ *
+ * (C) Copyright 2021 Sipeed
+ *
+ * based on dram_sun50i_h6.h, which is:
+ * (C) Copyright 2017 Icenowy Zheng
+ *
+ * based on dram_sun8i_h3.h, which is:
+ * (C) Copyright 2007-2015 Allwinner Technology Co.
+ * Jerry Wang
+ * (C) Copyright 2015 Vishnu Patekar
+ * (C) Copyright 2014-2015 Hans de Goede
+ * (C) Copyright 2015 Jens Kuske
+ */
+
+#ifndef _SUNXI_DRAM_SUN8I_H3_H
+#define _SUNXI_DRAM_SUN8I_H3_H
+
+#include
+
+struct sunxi_mctl_com_reg {
+ u32 cr; /* 0x000 control register */
+ u32 cr_r1; /* 0x004 control register for 2nd rank */
+ u32 unk_0x008; /* 0x008 */
+ u32 tmr;/* 0x00c timer register */
+ u8 reserved_0x010[4]; /* 0x010 */
+ u32 unk_0x014; /* 0x014 */
+ u8 reserved_0x018[8]; /* 0x018 */
+ u32 maer0; /* 0x020 master enable register 0 */
+ u32 maer1; /* 0x024 master enable register 1 */
+ u32 maer2; /* 0x028 master enable register 2 */
+ u8 reserved_0x02c[468]; /* 0x02c */
+ u32 bwcr; /* 0x200 bandwidth control register */
+ u8 reserved_0x204[12]; /* 0x204 */
+ /*
+* The last master configured by BSP libdram is at 0x49x, so the
+* size of this struct array is set to 41 (0x29) now.
+*/
+ struct {
+ u32 cfg0; /* 0x0 */
+ u32 cfg1; /* 0x4 */
+ u8 reserved_0x8[8]; /* 0x8 */
+ } master[41]; /* 0x210 + index * 0x10 */
+};
+check_member(sunxi_mctl_com_reg, master[40].reserved_0x8, 0x498);
+
+#define MCTL_CR_BL8(0x4 << 20)
+
+#define MCTL_CR_1T (0x1 << 19)
+#define MCTL_CR_2T (0x0 << 19)
+
+#define MCTL_CR_LPDDR3 (0x7 << 16)
+#define MCTL_CR_LPDDR2 (0x6 << 16)
+#define MCTL_CR_DDR3 (0x3 << 16)
+#define MCTL_CR_DDR2 (0x2 << 16)
+
+#define MCTL_CR_SEQUENTIAL (0x1 << 15)
+#define MCTL_CR_INTERLEAVED(0x0 << 15)
+
+#define MCTL_CR_FULL_WIDTH (0x1 << 12)
+#define MCTL_CR_HALF_WIDTH (0x0 << 12)
+#define MCTL_CR_BUS_FULL_WIDTH(x) ((x) << 12)
+
+#define MCTL_CR_PAGE_SIZE(x) ((fls(x) - 4) << 8)
+#define MCTL_CR_ROW_BITS(x)(((x) - 1) << 4)
+#define MCTL_CR_EIGHT_BANKS(0x1 << 2)
+#define MCTL_CR_FOUR_BANKS (0x0 << 2)
+#define MCTL_CR_DUAL_RANK (0x1 << 0)
+#define MCTL_CR_SINGLE_RANK(0x0 << 0)
+
+struct sunxi_mctl_ctl_reg {
+ u32 pir;/* 0x00 PHY initialization register */
+ u32 pwrct
[RFC PATCH 02/13] sunxi: only include alias for eMMC when mmc2 used
Some Allwinner SoCs (e.g. R329) doesn't have a MMC2 controller at all,
and on boards that we do not utilize MMC2, the alias for it is just
useless.
Only include the alias when we specify CONFIG_MMC_SUNXI_EXTRA_SLOT to 2.
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/sunxi-u-boot.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/sunxi-u-boot.dtsi b/arch/arm/dts/sunxi-u-boot.dtsi
index 4a6ed3a7dd..b7244c1112 100644
--- a/arch/arm/dts/sunxi-u-boot.dtsi
+++ b/arch/arm/dts/sunxi-u-boot.dtsi
@@ -13,7 +13,9 @@
/ {
aliases {
mmc0 = &mmc0;
+#if CONFIG_MMC_SUNXI_EXTRA_SLOT == 2
mmc1 = &mmc2;
+#endif
};
binman: binman {
--
2.30.2
[RFC PATCH 00/13] Add support for Allwinner R329
This patchset adds Allwinner R329 support to U-Boot. First, some code refactors happen for SoCs w/o SCP/MMC2. Then the basical support for R329 come as several parts (memory map, clocks, pinmux, DRAM, final Kconfig option). Then, as the RFC part of this patchset, some device tree related changes. Finally it comes the defconfig file for a R329 board, Sipeed Maix IIA Dock. This patchset is RFC mainly because of the DT-related part, as no DT binding is mainlined in Linux now (it's still WIP). All other patches are ready for being reviewed and, if proper, merged. Icenowy Zheng (13): sunxi: decide the inclusion of SCP by SCP_ADDR existence sunxi: only include alias for eMMC when mmc2 used mmc: sunxi: conditionally include MMC2 initialization code sunxi: add memory addresses for R329 SoC sunxi: add support for R329 clocks sunxi: add support for basical pinmux setup on R329 sunxi: add support for R329 DRAM controller sunxi: add Kconfig option for R329 sunxi: sync R329 CCU binding headers from internal WIP kernel tree clk: sunxi: add support for R329 in sunxi DM clock driver mmc: sunxi: add support for R329 MMC controller sunxi: sync R329 DTs from internal WIP kernel tree sunxi: add support for Sipeed Maix IIA Dock board arch/arm/cpu/armv8/fel_utils.S| 2 +- arch/arm/dts/Makefile | 2 + arch/arm/dts/sun50i-r329-maix-iia-dock.dts| 36 ++ arch/arm/dts/sun50i-r329-maix-iia.dtsi| 45 +++ arch/arm/dts/sun50i-r329.dtsi | 225 +++ arch/arm/dts/sunxi-u-boot.dtsi| 8 +- arch/arm/include/asm/arch-sunxi/boot0.h | 4 +- .../include/asm/arch-sunxi/clock_sun50i_h6.h | 17 + arch/arm/include/asm/arch-sunxi/cpu.h | 3 + .../include/asm/arch-sunxi/cpu_sun50i_r329.h | 58 +++ arch/arm/include/asm/arch-sunxi/dram.h| 2 + .../include/asm/arch-sunxi/dram_sun50i_r329.h | 232 +++ arch/arm/include/asm/arch-sunxi/gpio.h| 3 + arch/arm/include/asm/arch-sunxi/prcm_sun50i.h | 33 ++ arch/arm/mach-sunxi/Kconfig | 37 +- arch/arm/mach-sunxi/Makefile | 2 + arch/arm/mach-sunxi/board.c | 4 + arch/arm/mach-sunxi/clock_sun50i_h6.c | 49 ++- arch/arm/mach-sunxi/cpu_info.c| 2 + arch/arm/mach-sunxi/dram_sun50i_r329.c| 377 ++ arch/arm/mach-sunxi/dram_timings/Makefile | 1 + arch/arm/mach-sunxi/dram_timings/ddr3_r329.c | 89 + board/sunxi/MAINTAINERS | 5 + board/sunxi/board.c | 20 + common/spl/Kconfig| 1 + configs/sipeed_maix_iia_dock_defconfig| 8 + drivers/clk/sunxi/Kconfig | 7 + drivers/clk/sunxi/Makefile| 1 + drivers/clk/sunxi/clk_r329.c | 94 + drivers/mmc/sunxi_mmc.c | 3 + include/configs/sunxi-common.h| 3 + include/dt-bindings/clock/sun50i-r329-ccu.h | 73 include/dt-bindings/clock/sun50i-r329-r-ccu.h | 32 ++ include/dt-bindings/reset/sun50i-r329-ccu.h | 45 +++ include/dt-bindings/reset/sun50i-r329-r-ccu.h | 23 ++ 35 files changed, 1535 insertions(+), 11 deletions(-) create mode 100644 arch/arm/dts/sun50i-r329-maix-iia-dock.dts create mode 100644 arch/arm/dts/sun50i-r329-maix-iia.dtsi create mode 100644 arch/arm/dts/sun50i-r329.dtsi create mode 100644 arch/arm/include/asm/arch-sunxi/cpu_sun50i_r329.h create mode 100644 arch/arm/include/asm/arch-sunxi/dram_sun50i_r329.h create mode 100644 arch/arm/mach-sunxi/dram_sun50i_r329.c create mode 100644 arch/arm/mach-sunxi/dram_timings/ddr3_r329.c create mode 100644 configs/sipeed_maix_iia_dock_defconfig create mode 100644 drivers/clk/sunxi/clk_r329.c create mode 100644 include/dt-bindings/clock/sun50i-r329-ccu.h create mode 100644 include/dt-bindings/clock/sun50i-r329-r-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-r329-ccu.h create mode 100644 include/dt-bindings/reset/sun50i-r329-r-ccu.h -- 2.30.2
Re: [PATCH v2 1/4] mkimage: add a flag to describe whether -A is specified
在 2021-06-27星期日的 13:32 -0600，Simon Glass写道：
> Hi Icenowy,
>
> On Sat, 26 Jun 2021 at 17:57, Icenowy Zheng wrote:
> >
> > 在 2021-06-26星期六的 12:31 -0600，Simon Glass写道：
> > > Hi Icenowy,
> > >
> > > On Sat, 19 Jun 2021 at 03:19, Icenowy Zheng
> > > wrote:
> > > >
> > > > The sunxi_egon type used to take no -A argument (because we
> > > > assume
> > > > sunxi
> > > > targets are all ARM). However, as Allwinner D1 appears as the
> > > > first
> > > > RISC-V sunxi target, we need to support -A; in addition, as
> > > > external
> > > > projects rely on U-Boot mkimage to generate sunxi eGON.BT0
> > > > header,
> > > > we
> > > > need to keep compatibility with command line without -A.
> > > >
> > > > As the default value of arch in mkimage is not proper
> > > > (IH_ARCH_PPC
> > > > instead of IH_ARCH_INVALID), to keep more compatibility, add an
> > > > Aflag
> > > > field to image parameters to describe whether an architecture
> > > > is
> > > > explicitly specified.
> > > >
> > > > Reviewed-by: Tom Rini
> > > > Signed-off-by: Icenowy Zheng
> > > > ---
> > > > Changes in v2:
> > > > - Added Tom Rini's Review tag.
> > >
> > > This is not actually a change so should not appear in the log.
> > >
> > > Also note 'patman status' can be used to automatically collect
> > > these.
> > >
> > > >
> > > > tools/imagetool.h | 1 +
> > > > tools/mkimage.c | 1 +
> > > > 2 files changed, 2 insertions(+)
> > > >
> > > > diff --git a/tools/imagetool.h b/tools/imagetool.h
> > > > index e229a34ffc..5dc28312c2 100644
> > > > --- a/tools/imagetool.h
> > > > +++ b/tools/imagetool.h
> > > > @@ -51,6 +51,7 @@ struct image_tool_params {
> > > > int pflag;
> > > > int vflag;
> > > > int xflag;
> > > > + int Aflag;
> > >
> > > aflag
> >
> > I think a problem is that -a is a different flag than -A.
> >
> > -a is addr, -A is architecture.
>
> Yes OK, but the code style doesn't allow capital letters, as I
> understand it.
>
> How about addr_flag ?
maybe we just call -a aflag, and -A arch_flag?
>
>
> >
> > >
> > > > int skipcpy;
> > > > int os;
> > > > int arch;
> > > > diff --git a/tools/mkimage.c b/tools/mkimage.c
> > > > index cc7b242faf..54d8e3835a 100644
> > > > --- a/tools/mkimage.c
> > > > +++ b/tools/mkimage.c
> > > > @@ -168,6 +168,7 @@ static void process_args(int argc, char
> > > > **argv)
> > > > show_valid_options(IH_ARCH);
> > > > usage("Invalid architecture");
> > > > }
> > > > + params.Aflag = 1;
> > > > break;
> > > > case 'b':
> > > > if (add_content(IH_TYPE_FLATDT,
> > > > optarg)) {
> > > > --
> > > > 2.30.2
>
> Regards,
> Simon
Re: [PATCH v2 1/4] mkimage: add a flag to describe whether -A is specified
在 2021-06-26星期六的 12:31 -0600，Simon Glass写道：
> Hi Icenowy,
>
> On Sat, 19 Jun 2021 at 03:19, Icenowy Zheng wrote:
> >
> > The sunxi_egon type used to take no -A argument (because we assume
> > sunxi
> > targets are all ARM). However, as Allwinner D1 appears as the first
> > RISC-V sunxi target, we need to support -A; in addition, as
> > external
> > projects rely on U-Boot mkimage to generate sunxi eGON.BT0 header,
> > we
> > need to keep compatibility with command line without -A.
> >
> > As the default value of arch in mkimage is not proper (IH_ARCH_PPC
> > instead of IH_ARCH_INVALID), to keep more compatibility, add an
> > Aflag
> > field to image parameters to describe whether an architecture is
> > explicitly specified.
> >
> > Reviewed-by: Tom Rini
> > Signed-off-by: Icenowy Zheng
> > ---
> > Changes in v2:
> > - Added Tom Rini's Review tag.
>
> This is not actually a change so should not appear in the log.
>
> Also note 'patman status' can be used to automatically collect these.
>
> >
> > tools/imagetool.h | 1 +
> > tools/mkimage.c | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/tools/imagetool.h b/tools/imagetool.h
> > index e229a34ffc..5dc28312c2 100644
> > --- a/tools/imagetool.h
> > +++ b/tools/imagetool.h
> > @@ -51,6 +51,7 @@ struct image_tool_params {
> > int pflag;
> > int vflag;
> > int xflag;
> > + int Aflag;
>
> aflag
I think a problem is that -a is a different flag than -A.
-a is addr, -A is architecture.
>
> > int skipcpy;
> > int os;
> > int arch;
> > diff --git a/tools/mkimage.c b/tools/mkimage.c
> > index cc7b242faf..54d8e3835a 100644
> > --- a/tools/mkimage.c
> > +++ b/tools/mkimage.c
> > @@ -168,6 +168,7 @@ static void process_args(int argc, char **argv)
> > show_valid_options(IH_ARCH);
> > usage("Invalid architecture");
> > }
> > + params.Aflag = 1;
> > break;
> > case 'b':
> > if (add_content(IH_TYPE_FLATDT, optarg)) {
> > --
> > 2.30.2
>
> Regards,
> Simon
[PATCH v2 4/4] sunxi: specify architecture when generating SPL boot image
As mkimage -T sunxi_egon now gains support for -A parameter, specify the architecture when generating SPL boot image for sunxi. Signed-off-by: Icenowy Zheng --- No changes in v2. scripts/Makefile.spl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 5be1a9ba1b..c13a41a243 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -414,7 +414,7 @@ endif $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mkimage) -MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \ +MKIMAGEFLAGS_sunxi-spl.bin = -A $(ARCH) -T sunxi_egon \ -n $(CONFIG_DEFAULT_DEVICE_TREE) OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) -- 2.30.2
[PATCH v2 3/4] mkimage: sunxi_egon: add support for riscv
There's now a sun20i family in sunxi, which uses RISC-V CPU.
Add support for making eGON.BT0 image for RISC-V.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Removed changes that should belong to the previous patch in v1.
tools/sunxi_egon.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c
index 062c9bc151..836e99a6e6 100644
--- a/tools/sunxi_egon.c
+++ b/tools/sunxi_egon.c
@@ -29,6 +29,7 @@ static int egon_check_params(struct image_tool_params *params)
*/
switch (arch) {
case IH_ARCH_ARM:
+ case IH_ARCH_RISCV:
break;
default:
return EXIT_FAILURE;
@@ -60,6 +61,10 @@ static int egon_verify_header(unsigned char *ptr, int
image_size,
if ((le32_to_cpu(header->b_instruction) & 0xff00) !=
0xea00)
return EXIT_FAILURE;
break;
+ case IH_ARCH_RISCV:
+ if ((le32_to_cpu(header->b_instruction) & 0x0fff) !=
0x006f)
+ return EXIT_FAILURE;
+ break;
default:
return EXIT_FAILURE; /* Unknown architecture */
}
@@ -128,6 +133,24 @@ static void egon_set_header(void *buf, struct stat *sbuf,
int infd,
value = 0xea00 | (sizeof(struct boot_file_head) / 4 - 2);
header->b_instruction = cpu_to_le32(value);
break;
+ case IH_ARCH_RISCV:
+ /*
+* Generate a RISC-V JAL instruction with rd=x0
+* (pseudo instruction J, jump without side effects).
+*
+* The following weird bit operation maps imm[20]
+* to inst[31], imm[10:1] to inst[30:21],
+* imm[11] to inst[20], imm[19:12] to inst[19:12],
+* and imm[0] is dropped (because 1-byte RISC-V instruction
+* is not allowed).
+*/
+ value = 0x006f |
+ ((sizeof(struct boot_file_head) & 0x0010) << 11) |
+ ((sizeof(struct boot_file_head) & 0x07fe) << 20) |
+ ((sizeof(struct boot_file_head) & 0x0800) << 9) |
+ ((sizeof(struct boot_file_head) & 0x000ff000) << 0);
+ header->b_instruction = cpu_to_le32(value);
+ break;
}
memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));
--
2.30.2
[PATCH v2 2/4] mkimage: sunxi_egon: refactor for multi-architecture support
Refactor some functions in mkimage sunxi_egon type, in order to prepare
for adding support for more CPU architectures (e.g. RISC-V). In
addition, compatibility for operation w/o specified architecture is
kept, in this case the architecture is assumed as ARM.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Merged fixes in the next patch in v1 (patch rebase issue).
tools/sunxi_egon.c | 63 --
1 file changed, 56 insertions(+), 7 deletions(-)
diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c
index a5299eb6a1..062c9bc151 100644
--- a/tools/sunxi_egon.c
+++ b/tools/sunxi_egon.c
@@ -16,7 +16,25 @@
static int egon_check_params(struct image_tool_params *params)
{
- /* We just need a binary image file. */
+ int arch;
+
+ /* Assume ARM when no architecture specified for compatibility */
+ if (params->Aflag)
+ arch = params->arch;
+ else
+ arch = IH_ARCH_ARM;
+
+ /*
+* Check whether the architecture is supported.
+*/
+ switch (arch) {
+ case IH_ARCH_ARM:
+ break;
+ default:
+ return EXIT_FAILURE;
+ }
+
+ /* We need a binary image file. */
return !params->dflag;
}
@@ -25,10 +43,26 @@ static int egon_verify_header(unsigned char *ptr, int
image_size,
{
const struct boot_file_head *header = (void *)ptr;
uint32_t length;
+ int arch;
- /* First 4 bytes must be an ARM branch instruction. */
- if ((le32_to_cpu(header->b_instruction) & 0xff00) != 0xea00)
- return EXIT_FAILURE;
+ /* Assume ARM when no architecture specified for compatibility */
+ if (params->Aflag)
+ arch = params->arch;
+ else
+ arch = IH_ARCH_ARM;
+
+ /*
+* First 4 bytes must be a branch instruction of the corresponding
+* architecture.
+*/
+ switch (arch) {
+ case IH_ARCH_ARM:
+ if ((le32_to_cpu(header->b_instruction) & 0xff00) !=
0xea00)
+ return EXIT_FAILURE;
+ break;
+ default:
+ return EXIT_FAILURE; /* Unknown architecture */
+ }
if (memcmp(header->magic, BOOT0_MAGIC, sizeof(header->magic)))
return EXIT_FAILURE;
@@ -76,10 +110,25 @@ static void egon_set_header(void *buf, struct stat *sbuf,
int infd,
uint32_t *buf32 = buf;
uint32_t checksum = 0, value;
int i;
+ int arch;
- /* Generate an ARM branch instruction to jump over the header. */
- value = 0xea00 | (sizeof(struct boot_file_head) / 4 - 2);
- header->b_instruction = cpu_to_le32(value);
+ /* Assume ARM when no architecture specified for compatibility */
+ if (params->Aflag)
+ arch = params->arch;
+ else
+ arch = IH_ARCH_ARM;
+
+ /*
+* Different architectures need different first instruction to
+* branch to the body.
+*/
+ switch (arch) {
+ case IH_ARCH_ARM:
+ /* Generate an ARM branch instruction to jump over the header.
*/
+ value = 0xea00 | (sizeof(struct boot_file_head) / 4 - 2);
+ header->b_instruction = cpu_to_le32(value);
+ break;
+ }
memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));
header->check_sum = cpu_to_le32(BROM_STAMP_VALUE);
--
2.30.2
[PATCH v2 1/4] mkimage: add a flag to describe whether -A is specified
The sunxi_egon type used to take no -A argument (because we assume sunxi
targets are all ARM). However, as Allwinner D1 appears as the first
RISC-V sunxi target, we need to support -A; in addition, as external
projects rely on U-Boot mkimage to generate sunxi eGON.BT0 header, we
need to keep compatibility with command line without -A.
As the default value of arch in mkimage is not proper (IH_ARCH_PPC
instead of IH_ARCH_INVALID), to keep more compatibility, add an Aflag
field to image parameters to describe whether an architecture is
explicitly specified.
Reviewed-by: Tom Rini
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Added Tom Rini's Review tag.
tools/imagetool.h | 1 +
tools/mkimage.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/tools/imagetool.h b/tools/imagetool.h
index e229a34ffc..5dc28312c2 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -51,6 +51,7 @@ struct image_tool_params {
int pflag;
int vflag;
int xflag;
+ int Aflag;
int skipcpy;
int os;
int arch;
diff --git a/tools/mkimage.c b/tools/mkimage.c
index cc7b242faf..54d8e3835a 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -168,6 +168,7 @@ static void process_args(int argc, char **argv)
show_valid_options(IH_ARCH);
usage("Invalid architecture");
}
+ params.Aflag = 1;
break;
case 'b':
if (add_content(IH_TYPE_FLATDT, optarg)) {
--
2.30.2
[PATCH v2 0/4] mkimage: sunxi_egon: add riscv support
This patchset tries to make mkimage -T sunxi_egon to be able to generate an eGON.BT0 image for Allwinner RISC-V SoCs (e.g. D1). In addition, to keep the compatibility, it will still consider the architecture to be ARM when no architecture is specified. Icenowy Zheng (4): mkimage: add a flag to describe whether -A is specified mkimage: sunxi_egon: refactor for multi-architecture support mkimage: sunxi_egon: add support for riscv sunxi: specify architecture when generating SPL boot image scripts/Makefile.spl | 2 +- tools/imagetool.h| 1 + tools/mkimage.c | 1 + tools/sunxi_egon.c | 86 4 files changed, 82 insertions(+), 8 deletions(-) -- 2.30.2
[RFC PATCH 4/4] sunxi: specify architecture when generating SPL boot image
As mkimage -T sunxi_egon now gains support for -A parameter, specify the architecture when generating SPL boot image for sunxi. Signed-off-by: Icenowy Zheng --- scripts/Makefile.spl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 5be1a9ba1b..c13a41a243 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -414,7 +414,7 @@ endif $(obj)/$(SPL_BIN).sfp: $(obj)/$(SPL_BIN).bin FORCE $(call if_changed,mkimage) -MKIMAGEFLAGS_sunxi-spl.bin = -T sunxi_egon \ +MKIMAGEFLAGS_sunxi-spl.bin = -A $(ARCH) -T sunxi_egon \ -n $(CONFIG_DEFAULT_DEVICE_TREE) OBJCOPYFLAGS_u-boot-spl-dtb.hex := -I binary -O ihex --change-address=$(CONFIG_SPL_TEXT_BASE) -- 2.30.2
[RFC PATCH 3/4] mkimage: sunxi_egon: add support for riscv
There's now a sun20i family in sunxi, which uses RISC-V CPU.
Add support for making eGON.BT0 image for RISC-V.
Signed-off-by: Icenowy Zheng
---
tools/sunxi_egon.c | 35 +--
1 file changed, 29 insertions(+), 6 deletions(-)
diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c
index af649c392e..0fff25843f 100644
--- a/tools/sunxi_egon.c
+++ b/tools/sunxi_egon.c
@@ -19,7 +19,7 @@ static int egon_check_params(struct image_tool_params *params)
int arch;
/* Assume ARM when no architecture specified for compatibility */
- if (params->Aflags)
+ if (params->Aflag)
arch = params->arch;
else
arch = IH_ARCH_ARM;
@@ -27,8 +27,9 @@ static int egon_check_params(struct image_tool_params *params)
/*
* Check whether the architecture is supported.
*/
- switch(params->arch) {
+ switch(arch) {
case IH_ARCH_ARM:
+ case IH_ARCH_RISCV:
break;
default:
return EXIT_FAILURE;
@@ -46,7 +47,7 @@ static int egon_verify_header(unsigned char *ptr, int
image_size,
int arch;
/* Assume ARM when no architecture specified for compatibility */
- if (params->Aflags)
+ if (params->Aflag)
arch = params->arch;
else
arch = IH_ARCH_ARM;
@@ -55,11 +56,15 @@ static int egon_verify_header(unsigned char *ptr, int
image_size,
* First 4 bytes must be a branch instruction of the corresponding
* architecture.
*/
- switch(params->arch) {
+ switch(arch) {
case IH_ARCH_ARM:
if ((le32_to_cpu(header->b_instruction) & 0xff00) !=
0xea00)
return EXIT_FAILURE;
break;
+ case IH_ARCH_RISCV:
+ if ((le32_to_cpu(header->b_instruction) & 0x0fff) !=
0x006f)
+ return EXIT_FAILURE;
+ break;
default:
return EXIT_FAILURE; /* Unknown architecture */
}
@@ -113,7 +118,7 @@ static void egon_set_header(void *buf, struct stat *sbuf,
int infd,
int arch;
/* Assume ARM when no architecture specified for compatibility */
- if (params->Aflags)
+ if (params->Aflag)
arch = params->arch;
else
arch = IH_ARCH_ARM;
@@ -122,12 +127,30 @@ static void egon_set_header(void *buf, struct stat *sbuf,
int infd,
* Different architectures need different first instruction to
* branch to the body.
*/
- switch (params->arch) {
+ switch (arch) {
case IH_ARCH_ARM:
/* Generate an ARM branch instruction to jump over the header.
*/
value = 0xea00 | (sizeof(struct boot_file_head) / 4 - 2);
header->b_instruction = cpu_to_le32(value);
break;
+ case IH_ARCH_RISCV:
+ /*
+* Generate a RISC-V JAL instruction with rd=x0
+* (pseudo instruction J, jump without side effects).
+*
+* The following weird bit operation maps imm[20]
+* to inst[31], imm[10:1] to inst[30:21],
+* imm[11] to inst[20], imm[19:12] to inst[19:12],
+* and imm[0] is dropped (because 1-byte RISC-V instruction
+* is not allowed).
+*/
+ value = 0x006f |
+ ((sizeof(struct boot_file_head) & 0x0010) << 11) |
+ ((sizeof(struct boot_file_head) & 0x07fe) << 20) |
+ ((sizeof(struct boot_file_head) & 0x0800) << 9) |
+ ((sizeof(struct boot_file_head) & 0x000ff000) << 0);
+ header->b_instruction = cpu_to_le32(value);
+ break;
}
memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));
--
2.30.2
[RFC PATCH 2/4] mkimage: sunxi_egon: refactor for multi-architecture support
Refactor some functions in mkimage sunxi_egon type, in order to prepare
for adding support for more CPU architectures (e.g. RISC-V). In
addition, compatibility for operation w/o specified architecture is
kept, in this case the architecture is assumed as ARM.
Signed-off-by: Icenowy Zheng
---
tools/sunxi_egon.c | 63 --
1 file changed, 56 insertions(+), 7 deletions(-)
diff --git a/tools/sunxi_egon.c b/tools/sunxi_egon.c
index a5299eb6a1..af649c392e 100644
--- a/tools/sunxi_egon.c
+++ b/tools/sunxi_egon.c
@@ -16,7 +16,25 @@
static int egon_check_params(struct image_tool_params *params)
{
- /* We just need a binary image file. */
+ int arch;
+
+ /* Assume ARM when no architecture specified for compatibility */
+ if (params->Aflags)
+ arch = params->arch;
+ else
+ arch = IH_ARCH_ARM;
+
+ /*
+* Check whether the architecture is supported.
+*/
+ switch(params->arch) {
+ case IH_ARCH_ARM:
+ break;
+ default:
+ return EXIT_FAILURE;
+ }
+
+ /* We need a binary image file. */
return !params->dflag;
}
@@ -25,10 +43,26 @@ static int egon_verify_header(unsigned char *ptr, int
image_size,
{
const struct boot_file_head *header = (void *)ptr;
uint32_t length;
+ int arch;
- /* First 4 bytes must be an ARM branch instruction. */
- if ((le32_to_cpu(header->b_instruction) & 0xff00) != 0xea00)
- return EXIT_FAILURE;
+ /* Assume ARM when no architecture specified for compatibility */
+ if (params->Aflags)
+ arch = params->arch;
+ else
+ arch = IH_ARCH_ARM;
+
+ /*
+* First 4 bytes must be a branch instruction of the corresponding
+* architecture.
+*/
+ switch(params->arch) {
+ case IH_ARCH_ARM:
+ if ((le32_to_cpu(header->b_instruction) & 0xff00) !=
0xea00)
+ return EXIT_FAILURE;
+ break;
+ default:
+ return EXIT_FAILURE; /* Unknown architecture */
+ }
if (memcmp(header->magic, BOOT0_MAGIC, sizeof(header->magic)))
return EXIT_FAILURE;
@@ -76,10 +110,25 @@ static void egon_set_header(void *buf, struct stat *sbuf,
int infd,
uint32_t *buf32 = buf;
uint32_t checksum = 0, value;
int i;
+ int arch;
- /* Generate an ARM branch instruction to jump over the header. */
- value = 0xea00 | (sizeof(struct boot_file_head) / 4 - 2);
- header->b_instruction = cpu_to_le32(value);
+ /* Assume ARM when no architecture specified for compatibility */
+ if (params->Aflags)
+ arch = params->arch;
+ else
+ arch = IH_ARCH_ARM;
+
+ /*
+* Different architectures need different first instruction to
+* branch to the body.
+*/
+ switch (params->arch) {
+ case IH_ARCH_ARM:
+ /* Generate an ARM branch instruction to jump over the header.
*/
+ value = 0xea00 | (sizeof(struct boot_file_head) / 4 - 2);
+ header->b_instruction = cpu_to_le32(value);
+ break;
+ }
memcpy(header->magic, BOOT0_MAGIC, sizeof(header->magic));
header->check_sum = cpu_to_le32(BROM_STAMP_VALUE);
--
2.30.2
[RFC PATCH 1/4] mkimage: add a flag to describe whether -A is specified
The sunxi_egon type used to take no -A argument (because we assume sunxi
targets are all ARM). However, as Allwinner D1 appears as the first
RISC-V sunxi target, we need to support -A; in addition, as external
projects rely on U-Boot mkimage to generate sunxi eGON.BT0 header, we
need to keep compatibility with command line without -A.
As the default value of arch in mkimage is not proper (IH_ARCH_PPC
instead of IH_ARCH_INVALID), to keep more compatibility, add an Aflag
field to image parameters to describe whether an architecture is
explicitly specified.
Signed-off-by: Icenowy Zheng
---
tools/imagetool.h | 1 +
tools/mkimage.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/tools/imagetool.h b/tools/imagetool.h
index e229a34ffc..5dc28312c2 100644
--- a/tools/imagetool.h
+++ b/tools/imagetool.h
@@ -51,6 +51,7 @@ struct image_tool_params {
int pflag;
int vflag;
int xflag;
+ int Aflag;
int skipcpy;
int os;
int arch;
diff --git a/tools/mkimage.c b/tools/mkimage.c
index cc7b242faf..54d8e3835a 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c
@@ -168,6 +168,7 @@ static void process_args(int argc, char **argv)
show_valid_options(IH_ARCH);
usage("Invalid architecture");
}
+ params.Aflag = 1;
break;
case 'b':
if (add_content(IH_TYPE_FLATDT, optarg)) {
--
2.30.2
[RFC PATCH 0/4] mkimage: sunxi_egon: add riscv support
This patchset tries to make mkimage -T sunxi_egon to be able to generate an eGON.BT0 image for Allwinner RISC-V SoCs (e.g. D1). In addition, to keep the compatibility, it will still consider the architecture to be ARM when no architecture is specified. This patchset is RFC because I have no idea whether the change to mkimage common code is proper (maybe we should just change default value to IH_ARCH_INVALID?). Icenowy Zheng (4): mkimage: add a flag to describe whether -A is specified mkimage: sunxi_egon: refactor for multi-architecture support mkimage: sunxi_egon: add support for riscv sunxi: specify architecture when generating SPL boot image scripts/Makefile.spl | 2 +- tools/imagetool.h| 1 + tools/mkimage.c | 1 + tools/sunxi_egon.c | 86 4 files changed, 82 insertions(+), 8 deletions(-) -- 2.30.2
Re: [PATCH] efi_loader: allow to disable GOP support
在 2021-06-16星期三的 15:06 +0100，Peter Robinson写道：
> On Wed, Jun 16, 2021 at 1:20 PM Icenowy Zheng
> wrote:
> >
> > 在 2021-06-16星期三的 06:59 +0200，Heinrich Schuchardt写道：
> > > Am 15. Juni 2021 23:10:28 MESZ schrieb Icenowy Zheng
> > > :
> > > > Sometimes EFI GOP support may be not wanted (e.g. because the
> > > > operating
> > > > system cannot operate well with it) even if video support in U-
> > > > Boot
> > > > is
> > > > needed.
> > >
> > > Which OS has which problem?
> > > Why don't you fix the OS?
> >
> > I'm trying RK3399 with Linux. EFIFB never works as intended (maybe
> > it's
> > because IOMMU is reconfigured), and rockchipdrmfb will be fb1
> > (leave
> > non-working EFIFB as fb0), makes fbcon unusable.
>
> It's due to bugs in Linux, it will be fixed in 5.14 with these
> patches
> from our Fedora testing:
> https://lists.freedesktop.org/archives/dri-devel/2021-May/306803.html
I think this patch should get backported.
BTW a point of using EFI boot is to support existing distros, which
won't have this patch.
>
> There's also this enhancement, also should land in 5.14, which is
> dependent on the feature that's in the second link:
>
> https://lists.freedesktop.org/archives/dri-devel/2021-May/306803.html
> https://lists.freedesktop.org/archives/dri-devel/2021-April/303291.html
>
> With that first patch it mostly works for me, the second two series
> improves on that some more.
>
> Peter
>
> > The second problem has a proposed fix, but the first problem is
> > mystery.
> >
> > >
> > > Best regards
> > >
> > > Heinrich
> > >
> > >
> > > >
> > > > Allow to disable EFI GOP support with a Kconfig option.
> > > >
> > > > Signed-off-by: Icenowy Zheng
> > > > ---
> > > > lib/efi_loader/Kconfig | 8
> > > > lib/efi_loader/Makefile | 3 +--
> > > > lib/efi_loader/efi_setup.c | 11 ++-
> > > > 3 files changed, 15 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> > > > index 6242caceb7..5ba0ce6a44 100644
> > > > --- a/lib/efi_loader/Kconfig
> > > > +++ b/lib/efi_loader/Kconfig
> > > > @@ -282,6 +282,14 @@ config EFI_HAVE_RUNTIME_RESET
> > > > depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET
> > > > ||
> > > > \
> > > > SANDBOX || SYSRESET_X86
> > > >
> > > > +config EFI_GOP_PROTOCOL
> > > > + bool "EFI_GOP_PROTOCOL support"
> > > > + default y
> > > > + depends on DM_VIDEO || LCD
> > > > + help
> > > > + Provide a EFI_GOP_PROTOCOL implementation using the
> > > > graphics
> > > > + hardware initialized by U-Boot.
> > > > +
> > > > config EFI_GRUB_ARM32_WORKAROUND
> > > > bool "Workaround for GRUB on 32bit ARM"
> > > > default n if ARCH_BCM283X || ARCH_SUNXI || ARCH_QEMU
> > > > diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
> > > > index fd344cea29..826563d9a7 100644
> > > > --- a/lib/efi_loader/Makefile
> > > > +++ b/lib/efi_loader/Makefile
> > > > @@ -54,8 +54,7 @@ obj-$(CONFIG_EFI_VARIABLES_PRESEED) +=
> > > > efi_var_seed.o
> > > > endif
> > > > obj-y += efi_watchdog.o
> > > > obj-$(CONFIG_EFI_ESRT) += efi_esrt.o
> > > > -obj-$(CONFIG_LCD) += efi_gop.o
> > > > -obj-$(CONFIG_DM_VIDEO) += efi_gop.o
> > > > +obj-$(CONFIG_EFI_GOP_PROTOCOL) += efi_gop.o
> > > > obj-$(CONFIG_PARTITIONS) += efi_disk.o
> > > > obj-$(CONFIG_NET) += efi_net.o
> > > > obj-$(CONFIG_GENERATE_ACPI_TABLE) += efi_acpi.o
> > > > diff --git a/lib/efi_loader/efi_setup.c
> > > > b/lib/efi_loader/efi_setup.c
> > > > index 3c5cf9a435..98deb63777 100644
> > > > --- a/lib/efi_loader/efi_setup.c
> > > > +++ b/lib/efi_loader/efi_setup.c
> > > > @@ -254,11 +254,12 @@ efi_status_t efi_init_obj_list(void)
> > > > if (ret != EFI_SUCCESS)
> > > > goto out;
> > > >
> > > > -#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
> > > > - ret = efi_gop_register();
> > > > - if (ret != EFI_SUCCESS)
> > > > - goto out;
> > > > -#endif
> > > > + if (IS_ENABLED(CONFIG_EFI_GOP_PROTOCOL)) {
> > > > + ret = efi_gop_register();
> > > > + if (ret != EFI_SUCCESS)
> > > > + goto out;
> > > > + }
> > > > +
> > > > #ifdef CONFIG_NET
> > > > ret = efi_net_register();
> > > > if (ret != EFI_SUCCESS)
> >
Re: [PATCH] efi_loader: allow to disable GOP support
在 2021-06-16星期三的 15:20 +0200，Heinrich Schuchardt写道：
> Am 16. Juni 2021 14:19:41 MESZ schrieb Icenowy Zheng
> :
> > 在 2021-06-16星期三的 06:59 +0200，Heinrich Schuchardt写道：
> > > Am 15. Juni 2021 23:10:28 MESZ schrieb Icenowy Zheng
> > > :
> > > > Sometimes EFI GOP support may be not wanted (e.g. because the
> > > > operating
> > > > system cannot operate well with it) even if video support in U-
> > > > Boot
> > > > is
> > > > needed.
> > >
> > > Which OS has which problem?
> > > Why don't you fix the OS?
> >
> > I'm trying RK3399 with Linux. EFIFB never works as intended (maybe
> > it's
> > because IOMMU is reconfigured), and rockchipdrmfb will be fb1
> > (leave
> > non-working EFIFB as fb0), makes fbcon unusable.
>
> The GOP driver is not available after ExitBootServices. You can't use
> it after the EFI stub hands over to main Linux.
I think Linux will remember a FB address before ExitBootServices, and
continue to use it then.
>
> Shouldn't the Panfrost driver and Mesa be used for RK3399?
> https://wiki.debian.org/PanfrostLima ,
> https://www.collabora.com/news-and-blog/blog/2019/08/06/rockpi-panfrost-wayland/
>
Well, you made a common error that thinks on embedded systems GPUs are
responsible for display. It's not, for display (not 3D rendering)
rockchipdrm is the driver.
> Best regards
>
> Heinrich
>
>
> >
> > The second problem has a proposed fix, but the first problem is
> > mystery.
> >
> > >
> > > Best regards
> > >
> > > Heinrich
> > >
> > >
> > > >
> > > > Allow to disable EFI GOP support with a Kconfig option.
> > > >
> > > > Signed-off-by: Icenowy Zheng
> > > > ---
> > > > lib/efi_loader/Kconfig | 8
> > > > lib/efi_loader/Makefile | 3 +--
> > > > lib/efi_loader/efi_setup.c | 11 ++-
> > > > 3 files changed, 15 insertions(+), 7 deletions(-)
> > > >
> > > > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> > > > index 6242caceb7..5ba0ce6a44 100644
> > > > --- a/lib/efi_loader/Kconfig
> > > > +++ b/lib/efi_loader/Kconfig
> > > > @@ -282,6 +282,14 @@ config EFI_HAVE_RUNTIME_RESET
> > > > depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET
> > > > ||
> > > > \
> > > > SANDBOX || SYSRESET_X86
> > > >
> > > > +config EFI_GOP_PROTOCOL
> > > > + bool "EFI_GOP_PROTOCOL support"
> > > > + default y
> > > > + depends on DM_VIDEO || LCD
> > > > + help
> > > > + Provide a EFI_GOP_PROTOCOL implementation using the
> > > > graphics
> > > > + hardware initialized by U-Boot.
> > > > +
> > > > config EFI_GRUB_ARM32_WORKAROUND
> > > > bool "Workaround for GRUB on 32bit ARM"
> > > > default n if ARCH_BCM283X || ARCH_SUNXI || ARCH_QEMU
> > > > diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
> > > > index fd344cea29..826563d9a7 100644
> > > > --- a/lib/efi_loader/Makefile
> > > > +++ b/lib/efi_loader/Makefile
> > > > @@ -54,8 +54,7 @@ obj-$(CONFIG_EFI_VARIABLES_PRESEED) +=
> > > > efi_var_seed.o
> > > > endif
> > > > obj-y += efi_watchdog.o
> > > > obj-$(CONFIG_EFI_ESRT) += efi_esrt.o
> > > > -obj-$(CONFIG_LCD) += efi_gop.o
> > > > -obj-$(CONFIG_DM_VIDEO) += efi_gop.o
> > > > +obj-$(CONFIG_EFI_GOP_PROTOCOL) += efi_gop.o
> > > > obj-$(CONFIG_PARTITIONS) += efi_disk.o
> > > > obj-$(CONFIG_NET) += efi_net.o
> > > > obj-$(CONFIG_GENERATE_ACPI_TABLE) += efi_acpi.o
> > > > diff --git a/lib/efi_loader/efi_setup.c
> > > > b/lib/efi_loader/efi_setup.c
> > > > index 3c5cf9a435..98deb63777 100644
> > > > --- a/lib/efi_loader/efi_setup.c
> > > > +++ b/lib/efi_loader/efi_setup.c
> > > > @@ -254,11 +254,12 @@ efi_status_t efi_init_obj_list(void)
> > > > if (ret != EFI_SUCCESS)
> > > > goto out;
> > > >
> > > > -#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
> > > > - ret = efi_gop_register();
> > > > - if (ret != EFI_SUCCESS)
> > > > - goto out;
> > > > -#endif
> > > > + if (IS_ENABLED(CONFIG_EFI_GOP_PROTOCOL)) {
> > > > + ret = efi_gop_register();
> > > > + if (ret != EFI_SUCCESS)
> > > > + goto out;
> > > > + }
> > > > +
> > > > #ifdef CONFIG_NET
> > > > ret = efi_net_register();
> > > > if (ret != EFI_SUCCESS)
Re: [PATCH] efi_loader: allow to disable GOP support
在 2021-06-16星期三的 06:59 +0200，Heinrich Schuchardt写道：
> Am 15. Juni 2021 23:10:28 MESZ schrieb Icenowy Zheng
> :
> > Sometimes EFI GOP support may be not wanted (e.g. because the
> > operating
> > system cannot operate well with it) even if video support in U-Boot
> > is
> > needed.
>
> Which OS has which problem?
> Why don't you fix the OS?
I'm trying RK3399 with Linux. EFIFB never works as intended (maybe it's
because IOMMU is reconfigured), and rockchipdrmfb will be fb1 (leave
non-working EFIFB as fb0), makes fbcon unusable.
The second problem has a proposed fix, but the first problem is
mystery.
>
> Best regards
>
> Heinrich
>
>
> >
> > Allow to disable EFI GOP support with a Kconfig option.
> >
> > Signed-off-by: Icenowy Zheng
> > ---
> > lib/efi_loader/Kconfig | 8
> > lib/efi_loader/Makefile | 3 +--
> > lib/efi_loader/efi_setup.c | 11 ++-
> > 3 files changed, 15 insertions(+), 7 deletions(-)
> >
> > diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
> > index 6242caceb7..5ba0ce6a44 100644
> > --- a/lib/efi_loader/Kconfig
> > +++ b/lib/efi_loader/Kconfig
> > @@ -282,6 +282,14 @@ config EFI_HAVE_RUNTIME_RESET
> > depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET ||
> > \
> > SANDBOX || SYSRESET_X86
> >
> > +config EFI_GOP_PROTOCOL
> > + bool "EFI_GOP_PROTOCOL support"
> > + default y
> > + depends on DM_VIDEO || LCD
> > + help
> > + Provide a EFI_GOP_PROTOCOL implementation using the
> > graphics
> > + hardware initialized by U-Boot.
> > +
> > config EFI_GRUB_ARM32_WORKAROUND
> > bool "Workaround for GRUB on 32bit ARM"
> > default n if ARCH_BCM283X || ARCH_SUNXI || ARCH_QEMU
> > diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
> > index fd344cea29..826563d9a7 100644
> > --- a/lib/efi_loader/Makefile
> > +++ b/lib/efi_loader/Makefile
> > @@ -54,8 +54,7 @@ obj-$(CONFIG_EFI_VARIABLES_PRESEED) +=
> > efi_var_seed.o
> > endif
> > obj-y += efi_watchdog.o
> > obj-$(CONFIG_EFI_ESRT) += efi_esrt.o
> > -obj-$(CONFIG_LCD) += efi_gop.o
> > -obj-$(CONFIG_DM_VIDEO) += efi_gop.o
> > +obj-$(CONFIG_EFI_GOP_PROTOCOL) += efi_gop.o
> > obj-$(CONFIG_PARTITIONS) += efi_disk.o
> > obj-$(CONFIG_NET) += efi_net.o
> > obj-$(CONFIG_GENERATE_ACPI_TABLE) += efi_acpi.o
> > diff --git a/lib/efi_loader/efi_setup.c
> > b/lib/efi_loader/efi_setup.c
> > index 3c5cf9a435..98deb63777 100644
> > --- a/lib/efi_loader/efi_setup.c
> > +++ b/lib/efi_loader/efi_setup.c
> > @@ -254,11 +254,12 @@ efi_status_t efi_init_obj_list(void)
> > if (ret != EFI_SUCCESS)
> > goto out;
> >
> > -#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
> > - ret = efi_gop_register();
> > - if (ret != EFI_SUCCESS)
> > - goto out;
> > -#endif
> > + if (IS_ENABLED(CONFIG_EFI_GOP_PROTOCOL)) {
> > + ret = efi_gop_register();
> > + if (ret != EFI_SUCCESS)
> > + goto out;
> > + }
> > +
> > #ifdef CONFIG_NET
> > ret = efi_net_register();
> > if (ret != EFI_SUCCESS)
[PATCH] efi_loader: allow to disable GOP support
Sometimes EFI GOP support may be not wanted (e.g. because the operating
system cannot operate well with it) even if video support in U-Boot is
needed.
Allow to disable EFI GOP support with a Kconfig option.
Signed-off-by: Icenowy Zheng
---
lib/efi_loader/Kconfig | 8
lib/efi_loader/Makefile| 3 +--
lib/efi_loader/efi_setup.c | 11 ++-
3 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index 6242caceb7..5ba0ce6a44 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -282,6 +282,14 @@ config EFI_HAVE_RUNTIME_RESET
depends on ARCH_BCM283X || FSL_LAYERSCAPE || PSCI_RESET || \
SANDBOX || SYSRESET_X86
+config EFI_GOP_PROTOCOL
+ bool "EFI_GOP_PROTOCOL support"
+ default y
+ depends on DM_VIDEO || LCD
+ help
+ Provide a EFI_GOP_PROTOCOL implementation using the graphics
+ hardware initialized by U-Boot.
+
config EFI_GRUB_ARM32_WORKAROUND
bool "Workaround for GRUB on 32bit ARM"
default n if ARCH_BCM283X || ARCH_SUNXI || ARCH_QEMU
diff --git a/lib/efi_loader/Makefile b/lib/efi_loader/Makefile
index fd344cea29..826563d9a7 100644
--- a/lib/efi_loader/Makefile
+++ b/lib/efi_loader/Makefile
@@ -54,8 +54,7 @@ obj-$(CONFIG_EFI_VARIABLES_PRESEED) += efi_var_seed.o
endif
obj-y += efi_watchdog.o
obj-$(CONFIG_EFI_ESRT) += efi_esrt.o
-obj-$(CONFIG_LCD) += efi_gop.o
-obj-$(CONFIG_DM_VIDEO) += efi_gop.o
+obj-$(CONFIG_EFI_GOP_PROTOCOL) += efi_gop.o
obj-$(CONFIG_PARTITIONS) += efi_disk.o
obj-$(CONFIG_NET) += efi_net.o
obj-$(CONFIG_GENERATE_ACPI_TABLE) += efi_acpi.o
diff --git a/lib/efi_loader/efi_setup.c b/lib/efi_loader/efi_setup.c
index 3c5cf9a435..98deb63777 100644
--- a/lib/efi_loader/efi_setup.c
+++ b/lib/efi_loader/efi_setup.c
@@ -254,11 +254,12 @@ efi_status_t efi_init_obj_list(void)
if (ret != EFI_SUCCESS)
goto out;
-#if defined(CONFIG_LCD) || defined(CONFIG_DM_VIDEO)
- ret = efi_gop_register();
- if (ret != EFI_SUCCESS)
- goto out;
-#endif
+ if (IS_ENABLED(CONFIG_EFI_GOP_PROTOCOL)) {
+ ret = efi_gop_register();
+ if (ret != EFI_SUCCESS)
+ goto out;
+ }
+
#ifdef CONFIG_NET
ret = efi_net_register();
if (ret != EFI_SUCCESS)
--
2.30.2
Re: [PATCH 5/6] dts: sunxi: v3s: enable emac support
于 2021年5月20日 GMT+08:00 上午5:44:30, Andre Przywara 写到:
>On Wed, 19 May 2021 21:42:07 +0200
>Andreas Rehn wrote:
>
>Hi,
>
>> h3 and v3s have internal phys and can share the same driver.
>> Furthermore sun8i-v3s-emac is not available, use sun8i-h3-emac
>instead
>> - add emac pins
>> - enable emac for licheepi-zero-dock as it provides a ethernet port
>
>So first, this is not how we handle DT changes in U-Boot. They would
>need to go through the Linux tree first, then can be synced back to
>U-Boot. Sorry.
>
>Looking more into the details:
>
>>
>> Signed-off-by: Andreas Rehn
>> ---
>> arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 11 +++
>> arch/arm/dts/sun8i-v3s.dtsi | 10 +-
>> 2 files changed, 20 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
>b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
>> index db5cd0b857..083ac11b94 100644
>> --- a/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
>> +++ b/arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
>> @@ -49,6 +49,10 @@
>> compatible = "licheepi,licheepi-zero-dock",
>"licheepi,licheepi-zero",
>> "allwinner,sun8i-v3s";
>>
>> +aliases {
>> +ethernet0 = &emac;
>> +};
>> +
>> leds {
>> /* The LEDs use PG0~2 pins, which conflict with MMC1 */
>> status = "disabled";
>> @@ -94,3 +98,10 @@
>> voltage = <80>;
>> };
>> };
>> +
>> +&emac {
>> +allwinner,leds-active-low;
>> +status = "okay";
>> +pinctrl-names = "default";
>> +pinctrl-0 = <&emac_rgmii_pins>;
>
>I don't think this is correct. If I understand correctly, the V3s does
>not expose any MAC pins, instead relies entirely on the internal PHY.
>Those pins are not muxed, so don't need any pinctrl properties.
>
>> +};
>> diff --git a/arch/arm/dts/sun8i-v3s.dtsi
>b/arch/arm/dts/sun8i-v3s.dtsi
>> index 0c73416769..35cc4d63f7 100644
>> --- a/arch/arm/dts/sun8i-v3s.dtsi
>> +++ b/arch/arm/dts/sun8i-v3s.dtsi
>> @@ -342,6 +342,14 @@
>> function = "csi";
>> };
>>
>> +emac_rgmii_pins: emac-rgmii-pins {
>> +pins = "PD0", "PD1", "PD2", "PD3", "PD4",
>> + "PD5", "PD7", "PD8", "PD9", "PD10",
>> + "PD12", "PD13", "PD15", "PD16",
>> "PD17";
>> +function = "emac";
>> +drive-strength = <40>;
>> +};
>
>This is wrong (and not needed): The V3s does not expose MAC pins. If I
>understand correctly, the V3 and V3s share the same die, so the pin
>controller has those registers, but the whole port is connected
>nowhere.
>
>> i2c0_pins: i2c0-pins {
>> pins = "PB6", "PB7";
>> function = "i2c0";
>> @@ -468,7 +476,7 @@
>> };
>>
>> emac: ethernet@1c3 {
>> -compatible = "allwinner,sun8i-v3s-emac";
>> +compatible = "allwinner,sun8i-h3-emac";
>
>You can't just change the compatible string this way, the original one
>is there for a reason. In this case the difference is that the V3s does
>not support Gigabit Ethernet - because the only MAC pins connected are
>the internal MII ones. I believe the MAC itself could probably still
>handle GBit, but it can't talk to the outside in this mode.
You got it right. However, we choose to just use v3s compatible
on V3/S3 too.
>
>Instead just add the v3s compatible string to the sun8i-emac driver.
>Assign a new type and add this new type wherever you see H3_EMAC, but
>not in the RGMII part.
Maybe we can just make v3s situation a copy of h3 one.
>
>Cheers,
>Andre
>
>> syscon = <&syscon>;
>> reg = <0x01c3 0x1>;
>> interrupts = ;
Re: [PATCH 4/6] net: sun8i-emac: add v3s pinmux setting
于 2021年5月20日 GMT+08:00 上午5:44:07, Andre Przywara 写到: >On Wed, 19 May 2021 21:42:06 +0200 >Andreas Rehn wrote: > >Hi, > >> Driver uses pinmux instead of emac type. >> Add v3s pinmux to support SoC. > >So if I understand this correctly, then the v3s does NOT expose the MAC >pins (MII/RMII/RGMII) on its package (only the V3 does this)? Yes. *MII is at PD GPIO bank and PD is just not wired out on V3s. (on V3/S3 it is, but I haven't seen a board that utilizes external PHY.) >Instead there are internal pins, connecting the MAC directly to the >internal PHY only. Those don't need to be muxed, so do not require a >pinctrl-0 property. > >So this whole patch would not be necessary. > >If you want to avoid the message, please send a patch for that. > >Cheers, >Andre > >> Signed-off-by: Andreas Rehn >> --- >> drivers/net/sun8i_emac.c | 3 +++ >> 1 file changed, 3 insertions(+) >> >> diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c >> index 5a1b38bf80..0e7ad3b0d4 100644 >> --- a/drivers/net/sun8i_emac.c >> +++ b/drivers/net/sun8i_emac.c >> @@ -89,6 +89,7 @@ >> #define SUN8I_IOMUX_R40 5 >> #define SUN8I_IOMUX_H6 5 >> #define SUN8I_IOMUX_H6162 >> +#define SUN8I_IOMUX_V3S 2 >> #define SUN8I_IOMUX 4 >> >> /* H3/A64 EMAC Register's offset */ >> @@ -566,6 +567,8 @@ static int parse_phy_pins(struct udevice *dev) >> iomux = SUN8I_IOMUX; >> else if (IS_ENABLED(CONFIG_MACH_SUN50I)) >> iomux = SUN8I_IOMUX; >> +else if (IS_ENABLED(CONFIG_MACH_SUN8I_V3S)) >> +iomux = SUN8I_IOMUX_V3S; >> else >> BUILD_BUG_ON_MSG(1, "missing pinmux value for Ethernet pins"); >>
Re: [PATCH 1/6] dts: sunxi: add licheepi-zero-dock
于 2021年5月20日 GMT+08:00 上午5:42:38, Andre Przywara 写到: >On Wed, 19 May 2021 21:42:03 +0200 >Andreas Rehn wrote: > >Hi Andreas, > >> licheepi-zero dock is the second gen licheepi-zero board >> and brings addtional periperals like >> mic, speaker, ethernet, MIPI Camera Interface, 4 push buttons, >> second TF Card slot for Wifi or SD. >> >> As the device tree is synchronized in a previous commit, just add it >to >> Makefile, create a new MAINTAINER item and provide a defconfig. > >Thanks for upstreaming this! > >> >> Signed-off-by: Andreas Rehn >> --- >> arch/arm/dts/Makefile| 3 ++- >> board/sunxi/MAINTAINERS | 5 + >> configs/LicheePi_Zero_dock_defconfig | 7 +++ >> 3 files changed, 14 insertions(+), 1 deletion(-) >> create mode 100644 configs/LicheePi_Zero_dock_defconfig >> >> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile >> index 9c601a5c98..a5253ac112 100644 >> --- a/arch/arm/dts/Makefile >> +++ b/arch/arm/dts/Makefile >> @@ -609,7 +609,8 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ >> sun8i-v40-bananapi-m2-berry.dtb >> dtb-$(CONFIG_MACH_SUN8I_V3S) += \ >> sun8i-s3-pinecube.dtb \ >> -sun8i-v3s-licheepi-zero.dtb >> +sun8i-v3s-licheepi-zero.dtb \ >> +sun8i-v3s-licheepi-zero-dock.dtb >> dtb-$(CONFIG_MACH_SUN50I_H5) += \ >> sun50i-h5-bananapi-m2-plus.dtb \ >> sun50i-h5-emlid-neutis-n5-devboard.dtb \ >> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS >> index 76eba2ad20..e956087b76 100644 >> --- a/board/sunxi/MAINTAINERS >> +++ b/board/sunxi/MAINTAINERS >> @@ -266,6 +266,11 @@ M: Icenowy Zheng >> S: Maintained >> F: configs/LicheePi_Zero_defconfig >> >> +LICHEEPI-ZERO-DOCK BOARD >> +M: Icenowy Zheng > >Does she know about this? How it normally works is that the submitter >of the defconfig takes "maintainership". Which mostly means that he >or she owns the board and can be reached for questions or testing >requests. Well I do have it, and I can be responsible for it. > >Cheers, >Andre > >> +S: Maintained >> +F: configs/LicheePi_Zero_dock_defconfig >> + >> LINKSPRITE-PCDUINO BOARD >> M: Zoltan Herpai >> S: Maintained >> diff --git a/configs/LicheePi_Zero_dock_defconfig >b/configs/LicheePi_Zero_dock_defconfig >> new file mode 100644 >> index 00..d890151f80 >> --- /dev/null >> +++ b/configs/LicheePi_Zero_dock_defconfig >> @@ -0,0 +1,7 @@ >> +CONFIG_ARM=y >> +CONFIG_ARCH_SUNXI=y >> +CONFIG_SPL=y >> +CONFIG_MACH_SUN8I_V3S=y >> +CONFIG_DRAM_CLK=360 >> +CONFIG_DEFAULT_DEVICE_TREE="sun8i-v3s-licheepi-zero-dock" >> +CONFIG_SUN8I_EMAC=y
Re: [PATCH] phy: rockchip: inno-usb2: fix hang when multiple controllers exit
于 2021年4月7日 GMT+08:00 下午3:28:53, Frank Wang 写到:
>Hi,
>
>
>On 2021/4/7 14:43, Icenowy Zheng wrote:
>>
>> 于 2021年4月7日 GMT+08:00 下午2:42:34, Frank Wang
> 写到:
>>> Hi Icenowy Zheng,
>>>
>>> In my view, it is better to implement this mechanism in phy-uclass
>>> which
>>> resemble Linux Kernel have implemented that can avoid do duplication
>of
>>>
>>> work in each SoC's PHY driver.
>> I'm afraid of breaking existing drivers when implementing it in
>uclass,
>> although I agree this will be more clean.
>
>Why would it break existing drivers?
>Refer to clk-uclass, the count mechanism was also introduced later from
>
>commit "e6849e2fd clk: introduce enable_count".
>So fix it in framework codes is much better than in each instance
>drivers just like clk-uclass.
Okay, I will try.
>
>BR.
>Frank
>
>>
>>>
>>> BR.
>>> Frank
>>>
>>> On 2021/4/6 23:10, Icenowy Zheng wrote:
>>>> The OHCI and EHCI controllers are both bound to the same PHY. They
>>> will
>>>> both do init and power_on operations when the controller is brought
>>> up
>>>> and both do power_off and exit when the controller is stopped.
>>> However,
>>>> the PHY uclass of U-Boot is not as sane as we thought -- they won't
>>>> maintain a status mark for PHYs, and thus the functions of the PHYs
>>>> could be called for multiple times. Calling init/power_on for
>>> multiple
>>>> times have no severe problems, however calling power_off/exit for
>>>> multiple times have a problem -- the first exit call will stop the
>>> PHY
>>>> clock, and power_off/exit calls after it still trying to write to
>PHY
>>>> registers. The write operation to PHY registers will fail because
>>> clock
>>>> is already stopped.
>>>>
>>>> Adapt the count mechanism from phy-sun4i-usb to both init/exit and
>>>> power_on/power_off functions to phy-rockchip-inno-usb2 to fix this
>>>> problem. With this stopping USB controllers (manually or before
>>> booting
>>>> a kernel) will work.
>>>>
>>>> Signed-off-by: Icenowy Zheng
>>>> Fixes: ac97a9ece14e ("phy: rockchip: Add Rockchip USB2PHY driver")
>>>> ---
>>>>drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 21
>>> +++
>>>>1 file changed, 21 insertions(+)
>>>>
>>>> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>>> b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>>>> index 62b8ba3a4a..be9cc99d90 100644
>>>> --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>>>> +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>>>> @@ -62,6 +62,8 @@ struct rockchip_usb2phy {
>>>>void *reg_base;
>>>>struct clk phyclk;
>>>>const struct rockchip_usb2phy_cfg *phy_cfg;
>>>> + int init_count;
>>>> + int power_on_count;
>>>>};
>>>>
>>>>static inline int property_enable(void *reg_base,
>>>> @@ -92,6 +94,10 @@ static int rockchip_usb2phy_power_on(struct phy
>>> *phy)
>>>>struct rockchip_usb2phy *priv = dev_get_priv(parent);
>>>>const struct rockchip_usb2phy_port_cfg *port_cfg =
>>> us2phy_get_port(phy);
>>>>
>>>> + priv->power_on_count++;
>>>> + if (priv->power_on_count != 1)
>>>> + return 0;
>>>> +
>>>>property_enable(priv->reg_base, &port_cfg->phy_sus, false);
>>>>
>>>>/* waiting for the utmi_clk to become stable */
>>>> @@ -106,6 +112,10 @@ static int rockchip_usb2phy_power_off(struct
>phy
>>> *phy)
>>>>struct rockchip_usb2phy *priv = dev_get_priv(parent);
>>>>const struct rockchip_usb2phy_port_cfg *port_cfg =
>>> us2phy_get_port(phy);
>>>>
>>>> + priv->power_on_count--;
>>>> + if (priv->power_on_count != 0)
>>>> + return 0;
>>>> +
>>>>property_enable(priv->reg_base, &port_cfg->phy_sus, true);
>>>>
>>>>return 0;
>>>> @@ -118,6 +128,10 @@ static int rockchip_usb2phy_init(struct phy
>>> *phy)
>>>>const struct rockchip_usb2phy_port_cfg *port_cfg =
>>> us2phy_get_port(phy);
>>>>int ret;
>>>>
>>>> + priv->init_count++;
>>>> + if (priv->init_count != 1)
>>>> + return 0;
>>>> +
>>>>ret = clk_enable(&priv->phyclk);
>>>>if (ret) {
>>>>dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n",
>>>> ret);
>>>> @@ -140,6 +154,10 @@ static int rockchip_usb2phy_exit(struct phy
>>> *phy)
>>>>struct udevice *parent = dev_get_parent(phy->dev);
>>>>struct rockchip_usb2phy *priv = dev_get_priv(parent);
>>>>
>>>> + priv->init_count--;
>>>> + if (priv->init_count != 0)
>>>> + return 0;
>>>> +
>>>>clk_disable(&priv->phyclk);
>>>>
>>>>return 0;
>>>> @@ -212,6 +230,9 @@ static int rockchip_usb2phy_probe(struct
>udevice
>>> *dev)
>>>>return ret;
>>>>}
>>>>
>>>> + priv->power_on_count = 0;
>>>> + priv->init_count = 0;
>>>> +
>>>>return 0;
>>>>}
>>>>
>>
>>
Re: [PATCH] phy: rockchip: inno-usb2: fix hang when multiple controllers exit
于 2021年4月7日 GMT+08:00 下午2:42:34, Frank Wang 写到:
>Hi Icenowy Zheng,
>
>In my view, it is better to implement this mechanism in phy-uclass
>which
>resemble Linux Kernel have implemented that can avoid do duplication of
>
>work in each SoC's PHY driver.
I'm afraid of breaking existing drivers when implementing it in uclass,
although I agree this will be more clean.
>
>
>BR.
>Frank
>
>On 2021/4/6 23:10, Icenowy Zheng wrote:
>> The OHCI and EHCI controllers are both bound to the same PHY. They
>will
>> both do init and power_on operations when the controller is brought
>up
>> and both do power_off and exit when the controller is stopped.
>However,
>> the PHY uclass of U-Boot is not as sane as we thought -- they won't
>> maintain a status mark for PHYs, and thus the functions of the PHYs
>> could be called for multiple times. Calling init/power_on for
>multiple
>> times have no severe problems, however calling power_off/exit for
>> multiple times have a problem -- the first exit call will stop the
>PHY
>> clock, and power_off/exit calls after it still trying to write to PHY
>> registers. The write operation to PHY registers will fail because
>clock
>> is already stopped.
>>
>> Adapt the count mechanism from phy-sun4i-usb to both init/exit and
>> power_on/power_off functions to phy-rockchip-inno-usb2 to fix this
>> problem. With this stopping USB controllers (manually or before
>booting
>> a kernel) will work.
>>
>> Signed-off-by: Icenowy Zheng
>> Fixes: ac97a9ece14e ("phy: rockchip: Add Rockchip USB2PHY driver")
>> ---
>> drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 21
>+++
>> 1 file changed, 21 insertions(+)
>>
>> diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>> index 62b8ba3a4a..be9cc99d90 100644
>> --- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>> +++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
>> @@ -62,6 +62,8 @@ struct rockchip_usb2phy {
>> void *reg_base;
>> struct clk phyclk;
>> const struct rockchip_usb2phy_cfg *phy_cfg;
>> +int init_count;
>> +int power_on_count;
>> };
>>
>> static inline int property_enable(void *reg_base,
>> @@ -92,6 +94,10 @@ static int rockchip_usb2phy_power_on(struct phy
>*phy)
>> struct rockchip_usb2phy *priv = dev_get_priv(parent);
>> const struct rockchip_usb2phy_port_cfg *port_cfg =
>us2phy_get_port(phy);
>>
>> +priv->power_on_count++;
>> +if (priv->power_on_count != 1)
>> +return 0;
>> +
>> property_enable(priv->reg_base, &port_cfg->phy_sus, false);
>>
>> /* waiting for the utmi_clk to become stable */
>> @@ -106,6 +112,10 @@ static int rockchip_usb2phy_power_off(struct phy
>*phy)
>> struct rockchip_usb2phy *priv = dev_get_priv(parent);
>> const struct rockchip_usb2phy_port_cfg *port_cfg =
>us2phy_get_port(phy);
>>
>> +priv->power_on_count--;
>> +if (priv->power_on_count != 0)
>> +return 0;
>> +
>> property_enable(priv->reg_base, &port_cfg->phy_sus, true);
>>
>> return 0;
>> @@ -118,6 +128,10 @@ static int rockchip_usb2phy_init(struct phy
>*phy)
>> const struct rockchip_usb2phy_port_cfg *port_cfg =
>us2phy_get_port(phy);
>> int ret;
>>
>> +priv->init_count++;
>> +if (priv->init_count != 1)
>> +return 0;
>> +
>> ret = clk_enable(&priv->phyclk);
>> if (ret) {
>> dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
>> @@ -140,6 +154,10 @@ static int rockchip_usb2phy_exit(struct phy
>*phy)
>> struct udevice *parent = dev_get_parent(phy->dev);
>> struct rockchip_usb2phy *priv = dev_get_priv(parent);
>>
>> +priv->init_count--;
>> +if (priv->init_count != 0)
>> +return 0;
>> +
>> clk_disable(&priv->phyclk);
>>
>> return 0;
>> @@ -212,6 +230,9 @@ static int rockchip_usb2phy_probe(struct udevice
>*dev)
>> return ret;
>> }
>>
>> +priv->power_on_count = 0;
>> +priv->init_count = 0;
>> +
>> return 0;
>> }
>>
[PATCH] phy: rockchip: inno-usb2: fix hang when multiple controllers exit
The OHCI and EHCI controllers are both bound to the same PHY. They will
both do init and power_on operations when the controller is brought up
and both do power_off and exit when the controller is stopped. However,
the PHY uclass of U-Boot is not as sane as we thought -- they won't
maintain a status mark for PHYs, and thus the functions of the PHYs
could be called for multiple times. Calling init/power_on for multiple
times have no severe problems, however calling power_off/exit for
multiple times have a problem -- the first exit call will stop the PHY
clock, and power_off/exit calls after it still trying to write to PHY
registers. The write operation to PHY registers will fail because clock
is already stopped.
Adapt the count mechanism from phy-sun4i-usb to both init/exit and
power_on/power_off functions to phy-rockchip-inno-usb2 to fix this
problem. With this stopping USB controllers (manually or before booting
a kernel) will work.
Signed-off-by: Icenowy Zheng
Fixes: ac97a9ece14e ("phy: rockchip: Add Rockchip USB2PHY driver")
---
drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 21 +++
1 file changed, 21 insertions(+)
diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
index 62b8ba3a4a..be9cc99d90 100644
--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
@@ -62,6 +62,8 @@ struct rockchip_usb2phy {
void *reg_base;
struct clk phyclk;
const struct rockchip_usb2phy_cfg *phy_cfg;
+ int init_count;
+ int power_on_count;
};
static inline int property_enable(void *reg_base,
@@ -92,6 +94,10 @@ static int rockchip_usb2phy_power_on(struct phy *phy)
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+ priv->power_on_count++;
+ if (priv->power_on_count != 1)
+ return 0;
+
property_enable(priv->reg_base, &port_cfg->phy_sus, false);
/* waiting for the utmi_clk to become stable */
@@ -106,6 +112,10 @@ static int rockchip_usb2phy_power_off(struct phy *phy)
struct rockchip_usb2phy *priv = dev_get_priv(parent);
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
+ priv->power_on_count--;
+ if (priv->power_on_count != 0)
+ return 0;
+
property_enable(priv->reg_base, &port_cfg->phy_sus, true);
return 0;
@@ -118,6 +128,10 @@ static int rockchip_usb2phy_init(struct phy *phy)
const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy);
int ret;
+ priv->init_count++;
+ if (priv->init_count != 1)
+ return 0;
+
ret = clk_enable(&priv->phyclk);
if (ret) {
dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret);
@@ -140,6 +154,10 @@ static int rockchip_usb2phy_exit(struct phy *phy)
struct udevice *parent = dev_get_parent(phy->dev);
struct rockchip_usb2phy *priv = dev_get_priv(parent);
+ priv->init_count--;
+ if (priv->init_count != 0)
+ return 0;
+
clk_disable(&priv->phyclk);
return 0;
@@ -212,6 +230,9 @@ static int rockchip_usb2phy_probe(struct udevice *dev)
return ret;
}
+ priv->power_on_count = 0;
+ priv->init_count = 0;
+
return 0;
}
--
2.30.2
Re: [PATCH] configs: add PineTab defconfig
于 2021年3月8日 GMT+08:00 上午8:12:24, Andre Przywara 写到: >On Sun, 7 Mar 2021 13:53:56 +0100 >Nicolas Boulenguez wrote: > >Hi, > >> From: Arnaud Ferraris >> >> The PineTab device-tree is already in u-boot, this commit adds the >corresponding >> defconfig, based on pinephone_defconfig. >> >> Signed-off-by: Arnaud Ferraris >> >> --- a/board/sunxi/MAINTAINERS >> +++ b/board/sunxi/MAINTAINERS >> @@ -471,6 +471,11 @@ M: Samuel Holland >> S: Maintained >> F: configs/pinephone_defconfig >> >> +PINETAB BOARD >> +M: Arnaud Ferraris >> +S: Maintained >> +F: configs/pinetab_defconfig > >Arnaud, do you agree with this? >Happy to take your patch via Nicolas, but for the maintainer entry I >would like to have some confirmation. > >> + >> R16 EVB PARROT BOARD >> M: Quentin Schulz >> S: Maintained >> --- /dev/null >> +++ b/configs/pinetab_defconfig >> @@ -0,0 +1,21 @@ >> +CONFIG_ARM=y >> +CONFIG_ARCH_SUNXI=y >> +CONFIG_SPL=y >> +CONFIG_IDENT_STRING="" > >Having "Allwinner Technology" here is indeed weird and probably not >really justified anymore, given the "support" we see from Allwinner. >I wonder if we should scrap this for all boards. Also it makes the line >longer than 80 characters. But if we do so, it should be in Kconfig, not defconfig. > >> +CONFIG_MACH_SUN50I=y >> +CONFIG_SUNXI_DRAM_LPDDR3_STOCK=y >> +CONFIG_DRAM_CLK=552 >> +CONFIG_DRAM_ZQ=3881949 >> +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 >> +# CONFIG_VIDEO_DE2 is not set >> +CONFIG_DEFAULT_DEVICE_TREE="sun50i-a64-pinetab" >> +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set >> +CONFIG_BOOTDELAY=0 > >I answered in the other email about the boot delay already. > >So what is the reason for all those other options below? >Is there any particular reason they were all disabled? >I can buy CONFIG_NET, but the rest seems unnecessary. There doesn't >seem to be a driver for the PineTab panel in U-Boot, so this is solely >suppressing a few lines on the serial? Since this would be surely for >debug only, I think it's useful to have them, normal users wouldn't see >them anyway. > >> +CONFIG_SYS_CONSOLE_INFO_QUIET=y >> +# CONFIG_DISPLAY_CPUINFO is not set >> +# CONFIG_DISPLAY_BOARDINFO is not set >> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set >> +# CONFIG_SPL_BANNER_PRINT is not set >> +# CONFIG_SPL_POWER_SUPPORT is not set >> +# CONFIG_NET is not set >> +# CONFIG_EFI_LOADER is not set > >We should definitely keep EFI_LOADER. > >Cheers, >Andre
Re: [linux-sunxi] Re: [PATCH 2/2] sunxi: enable dual rank memory on R40
在 2021-03-02星期二的 15:19 +，Andre Przywara写道： > On Tue, 02 Mar 2021 21:50:49 +0800 > Icenowy Zheng wrote: > > Hi Icenowy, > > > 于 2021年3月2日 GMT+08:00 下午9:40:44, Andre Przywara < > > andre.przyw...@arm.com> 写到: > > > On Fri, 26 Feb 2021 00:13:25 +0800 > > > Icenowy Zheng wrote: > > > > > > > Previously we do not have proper dual rank memory detection on > > > > R40 > > > > (because we omitted PIR_QSGATE, which does not work on R40 with > > > > our > > > > configuration), and dual rank memory is just simply disabled as > > > > early > > > > R40 boards available (Banana Pi M2 Ultra and Berry) have single > > > > rank > > > > memory. > > > > > > > > As a board with dual rank memory (Forlinx OKA40i-C) is now > > > > known to > > > us, > > > > we need to have a way to do memory rank detection to support > > > > that > > > board. > > > > > > > > Add some routine to detect memory rank by trying to access the > > > > memory > > > > in rank 1 and check for error status of the memory controller, > > > > and > > > then > > > > enable dual rank memory on R40. > > > > > > > > Similar routine can be used to detect half DQ width (which is > > > > also > > > > detected by PIR_QSGATE on other SoCs), but it's left > > > > unimplemented > > > > because there's no known R40 board with half DQ width now. > > > > > > So when looking at the SPL size I realised that this patch breaks > > > the > > > socid constant parameter propagation, especially for > > > mctl_set_cr(). I > > > don't see immediately why, this whole code here should be > > > compiled out > > > on any A64 builds, for instance. Instead GCC turns > > > ":" into ":", and passes > > > 0x1689 > > > around everytime. I tried GCC 10.2.0 and 9.2.0, also tried adding > > > const > > > everywhere, to amplify the constant nature of this value. Patch > > > 1/2 added to the code size, but kept the const propagation (only > > > one > > > instance of 0x1689 in the disassembly). This patch here should be > > > for > > > free on A64, but adds 104 bytes. > > > > > > Does anyone have a clue why this is happening? Is this a compiler > > > issue? > > > > Maybe the issue is that I assume this codepath is only for R40 and > > I didn't add socid to it? > > But that's clearly visible by this function only being called inside > "if > (socid == SOCID_R40)". And that works very well for the H3 ZQ > calibration quirk, for instance. > > > Could you try to add a socid parameter to > > mctl_r40_detect_rank_count()? > > I just tried that, and apart from looking weird it didn't do > anything. > > To be clear: Your code is absolutely fine, exactly the way it should > be > written. It's just that the compiler is playing stupid suddenly. I > was > thinking that your dummy readl might have upset it, but even with > that > commented out it's still happening. > > > Or maybe it makes mctl_calc_rank_size() not inlined? > > So the assembly looks like everything apart from mctl_set_cr() and > mctl_auto_detect_dram_size_rank() is inlined. Those are extra because > they are called multiple times and we are using -Os. > > > (Well I think the code looks noop on non-R40) > > Exactly that was my thinking: when compiling for the A64, it should > be > totally compiled out, and the object file should be the same before > and > after. > > > BTW, original rank/width detection part won't get called on R40. > > But > > R40 is not where we are tight on code size, so I didn't bother to > > ignore > > it on R40. > > I see. Yeah, I am not concerned about R40 either, but I want to avoid > the A64 bloating up. > > > Or should we switch back to #if's and do not rely on compiler > > behavior any longer? > > I'd rather not do that. We are doing the right thing, and it works > marvellously so far. > > To be clear: it's not a show stopper, I was just curious why this > happens. > The code size is not really critical on the A64 at the moment, so I'd > merge it as it, even if we don't find a solution. Maybe just leave a > hint about it in the code should people need to come back to this. > &g
Re: [linux-sunxi] Re: [PATCH 2/2] sunxi: enable dual rank memory on R40
在 2021-03-02星期二的 15:19 +，Andre Przywara写道： > On Tue, 02 Mar 2021 21:50:49 +0800 > Icenowy Zheng wrote: > > Hi Icenowy, > > > 于 2021年3月2日 GMT+08:00 下午9:40:44, Andre Przywara < > > andre.przyw...@arm.com> 写到: > > > On Fri, 26 Feb 2021 00:13:25 +0800 > > > Icenowy Zheng wrote: > > > > > > > Previously we do not have proper dual rank memory detection on > > > > R40 > > > > (because we omitted PIR_QSGATE, which does not work on R40 with > > > > our > > > > configuration), and dual rank memory is just simply disabled as > > > > early > > > > R40 boards available (Banana Pi M2 Ultra and Berry) have single > > > > rank > > > > memory. > > > > > > > > As a board with dual rank memory (Forlinx OKA40i-C) is now > > > > known to > > > us, > > > > we need to have a way to do memory rank detection to support > > > > that > > > board. > > > > > > > > Add some routine to detect memory rank by trying to access the > > > > memory > > > > in rank 1 and check for error status of the memory controller, > > > > and > > > then > > > > enable dual rank memory on R40. > > > > > > > > Similar routine can be used to detect half DQ width (which is > > > > also > > > > detected by PIR_QSGATE on other SoCs), but it's left > > > > unimplemented > > > > because there's no known R40 board with half DQ width now. > > > > > > So when looking at the SPL size I realised that this patch breaks > > > the > > > socid constant parameter propagation, especially for > > > mctl_set_cr(). I > > > don't see immediately why, this whole code here should be > > > compiled out > > > on any A64 builds, for instance. Instead GCC turns > > > ":" into ":", and passes > > > 0x1689 > > > around everytime. I tried GCC 10.2.0 and 9.2.0, also tried adding > > > const > > > everywhere, to amplify the constant nature of this value. Patch > > > 1/2 added to the code size, but kept the const propagation (only > > > one > > > instance of 0x1689 in the disassembly). This patch here should be > > > for > > > free on A64, but adds 104 bytes. > > > > > > Does anyone have a clue why this is happening? Is this a compiler > > > issue? > > > > Maybe the issue is that I assume this codepath is only for R40 and > > I didn't add socid to it? > > But that's clearly visible by this function only being called inside > "if > (socid == SOCID_R40)". And that works very well for the H3 ZQ > calibration quirk, for instance. > > > Could you try to add a socid parameter to > > mctl_r40_detect_rank_count()? > > I just tried that, and apart from looking weird it didn't do > anything. > > To be clear: Your code is absolutely fine, exactly the way it should > be > written. It's just that the compiler is playing stupid suddenly. I > was > thinking that your dummy readl might have upset it, but even with > that > commented out it's still happening. > > > Or maybe it makes mctl_calc_rank_size() not inlined? > > So the assembly looks like everything apart from mctl_set_cr() and > mctl_auto_detect_dram_size_rank() is inlined. Those are extra because > they are called multiple times and we are using -Os. > > > (Well I think the code looks noop on non-R40) > > Exactly that was my thinking: when compiling for the A64, it should > be > totally compiled out, and the object file should be the same before > and > after. > > > BTW, original rank/width detection part won't get called on R40. > > But > > R40 is not where we are tight on code size, so I didn't bother to > > ignore > > it on R40. > > I see. Yeah, I am not concerned about R40 either, but I want to avoid > the A64 bloating up. > > > Or should we switch back to #if's and do not rely on compiler > > behavior any longer? > > I'd rather not do that. We are doing the right thing, and it works > marvellously so far. > > To be clear: it's not a show stopper, I was just curious why this > happens. > The code size is not really critical on the A64 at the moment, so I'd > merge it as it, even if we don't find a solution. Maybe just leave a > hint about it in the code should people nee
Re: [PATCH 2/2] sunxi: enable dual rank memory on R40
于 2021年3月2日 GMT+08:00 下午9:40:44, Andre Przywara 写到:
>On Fri, 26 Feb 2021 00:13:25 +0800
>Icenowy Zheng wrote:
>
>> Previously we do not have proper dual rank memory detection on R40
>> (because we omitted PIR_QSGATE, which does not work on R40 with our
>> configuration), and dual rank memory is just simply disabled as early
>> R40 boards available (Banana Pi M2 Ultra and Berry) have single rank
>> memory.
>>
>> As a board with dual rank memory (Forlinx OKA40i-C) is now known to
>us,
>> we need to have a way to do memory rank detection to support that
>board.
>>
>> Add some routine to detect memory rank by trying to access the memory
>> in rank 1 and check for error status of the memory controller, and
>then
>> enable dual rank memory on R40.
>>
>> Similar routine can be used to detect half DQ width (which is also
>> detected by PIR_QSGATE on other SoCs), but it's left unimplemented
>> because there's no known R40 board with half DQ width now.
>
>So when looking at the SPL size I realised that this patch breaks the
>socid constant parameter propagation, especially for mctl_set_cr(). I
>don't see immediately why, this whole code here should be compiled out
>on any A64 builds, for instance. Instead GCC turns
>":" into ":", and passes 0x1689
>around everytime. I tried GCC 10.2.0 and 9.2.0, also tried adding const
>everywhere, to amplify the constant nature of this value. Patch
>1/2 added to the code size, but kept the const propagation (only one
>instance of 0x1689 in the disassembly). This patch here should be for
>free on A64, but adds 104 bytes.
>
>Does anyone have a clue why this is happening? Is this a compiler
>issue?
Maybe the issue is that I assume this codepath is only for R40 and
I didn't add socid to it?
Could you try to add a socid parameter to mctl_r40_detect_rank_count()?
Or maybe it makes mctl_calc_rank_size() not inlined?
(Well I think the code looks noop on non-R40)
BTW, original rank/width detection part won't get called on R40. But
R40 is not where we are tight on code size, so I didn't bother to ignore
it on R40.
Or should we switch back to #if's and do not rely on compiler behavior any
longer?
>
>Cheers,
>Andre
>
>> Signed-off-by: Icenowy Zheng
>> ---
>> arch/arm/mach-sunxi/dram_sunxi_dw.c | 55
>+
>> 1 file changed, 49 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c
>b/arch/arm/mach-sunxi/dram_sunxi_dw.c
>> index 2b9d631d49..b86ae7cdf3 100644
>> --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
>> +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
>> @@ -414,11 +414,9 @@ static void mctl_set_cr(uint16_t socid, struct
>dram_para *para)
>> }
>>
>> if (socid == SOCID_R40) {
>> -if (para->dual_rank)
>> -panic("Dual rank memory not supported\n");
>> -
>> /* Mux pin to A15 address line for single rank memory. */
>> -setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
>> +if (!para->dual_rank)
>> +setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
>> }
>> }
>>
>> @@ -702,8 +700,55 @@ static unsigned long mctl_calc_rank_size(struct
>rank_para *rank)
>> return (1UL << (rank->row_bits + rank->bank_bits)) *
>rank->page_size;
>> }
>>
>> +/*
>> + * Because we cannot do mctl_phy_init(PIR_QSGATE) on R40 now (which
>leads
>> + * to failure), it's needed to detect the rank count of R40 in
>another way.
>> + *
>> + * The code here is modelled after time_out_detect() in BSP, which
>tries to
>> + * access the memory and check for error code.
>> + *
>> + * TODO: auto detect half DQ width here
>> + */
>> +static void mctl_r40_detect_rank_count(struct dram_para *para)
>> +{
>> +ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE +
>> + mctl_calc_rank_size(¶->ranks[0]);
>> +struct sunxi_mctl_ctl_reg * const mctl_ctl =
>> +(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
>> +
>> +/* Enable read time out */
>> +setbits_le32(&mctl_ctl->pgcr[0], 0x1 << 25);
>> +
>> +(void) readl((void *) rank1_base);
>> +udelay(10);
>> +
>> +if (readl(&mctl_ctl->pgsr[0]) & (0x1 << 13)) {
>> +clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
>> +para->dual_rank = 0;
>> +}
>
[PATCH 2/2] sunxi: enable dual rank memory on R40
Previously we do not have proper dual rank memory detection on R40
(because we omitted PIR_QSGATE, which does not work on R40 with our
configuration), and dual rank memory is just simply disabled as early
R40 boards available (Banana Pi M2 Ultra and Berry) have single rank
memory.
As a board with dual rank memory (Forlinx OKA40i-C) is now known to us,
we need to have a way to do memory rank detection to support that board.
Add some routine to detect memory rank by trying to access the memory
in rank 1 and check for error status of the memory controller, and then
enable dual rank memory on R40.
Similar routine can be used to detect half DQ width (which is also
detected by PIR_QSGATE on other SoCs), but it's left unimplemented
because there's no known R40 board with half DQ width now.
Signed-off-by: Icenowy Zheng
---
arch/arm/mach-sunxi/dram_sunxi_dw.c | 55 +
1 file changed, 49 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index 2b9d631d49..b86ae7cdf3 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -414,11 +414,9 @@ static void mctl_set_cr(uint16_t socid, struct dram_para
*para)
}
if (socid == SOCID_R40) {
- if (para->dual_rank)
- panic("Dual rank memory not supported\n");
-
/* Mux pin to A15 address line for single rank memory. */
- setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
+ if (!para->dual_rank)
+ setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
}
}
@@ -702,8 +700,55 @@ static unsigned long mctl_calc_rank_size(struct rank_para
*rank)
return (1UL << (rank->row_bits + rank->bank_bits)) * rank->page_size;
}
+/*
+ * Because we cannot do mctl_phy_init(PIR_QSGATE) on R40 now (which leads
+ * to failure), it's needed to detect the rank count of R40 in another way.
+ *
+ * The code here is modelled after time_out_detect() in BSP, which tries to
+ * access the memory and check for error code.
+ *
+ * TODO: auto detect half DQ width here
+ */
+static void mctl_r40_detect_rank_count(struct dram_para *para)
+{
+ ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE +
+ mctl_calc_rank_size(¶->ranks[0]);
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ /* Enable read time out */
+ setbits_le32(&mctl_ctl->pgcr[0], 0x1 << 25);
+
+ (void) readl((void *) rank1_base);
+ udelay(10);
+
+ if (readl(&mctl_ctl->pgsr[0]) & (0x1 << 13)) {
+ clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
+ para->dual_rank = 0;
+ }
+
+ /* Reset PHY FIFO to clear it */
+ clrbits_le32(&mctl_ctl->pgcr[0], 0x1 << 26);
+ udelay(100);
+ setbits_le32(&mctl_ctl->pgcr[0], 0x1 << 26);
+
+ /* Clear error status */
+ setbits_le32(&mctl_ctl->pgcr[0], 0x1 << 24);
+
+ /* Clear time out flag */
+ clrbits_le32(&mctl_ctl->pgsr[0], 0x1 << 13);
+
+ /* Disable read time out */
+ clrbits_le32(&mctl_ctl->pgcr[0], 0x1 << 25);
+}
+
static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
{
+ if (socid == SOCID_R40) {
+ mctl_r40_detect_rank_count(para);
+ mctl_set_cr(socid, para);
+ }
+
mctl_auto_detect_dram_size_rank(socid, para,
(ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]);
if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) {
@@ -854,8 +899,6 @@ unsigned long sunxi_dram_init(void)
uint16_t socid = SOCID_H3;
#elif defined(CONFIG_MACH_SUN8I_R40)
uint16_t socid = SOCID_R40;
- /* Currently we cannot support R40 with dual rank memory */
- para.dual_rank = 0;
#elif defined(CONFIG_MACH_SUN8I_V3S)
uint16_t socid = SOCID_V3S;
#elif defined(CONFIG_MACH_SUN50I)
--
2.30.0
[PATCH 1/2] sunxi: support asymmetric dual rank DRAM on A64/R40
Previously we have known that R40 has a configuration register for its
rank 1, which allows different configuration than rank 0. Reverse
engineering of newest libdram of A64 from Allwinner shows that A64 has
this register too. It's bit 0 (which enables dual rank in rank 0
configuration register) means a dedicated rank size setup is used for
rank 1.
Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB
rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank
DRAM support necessary.
Add this support. The code could support both A64 and R40, but because
dual rank detection is broken on R40 now, we cannot really use it on R40
currently.
Signed-off-by: Icenowy Zheng
---
.../include/asm/arch-sunxi/dram_sunxi_dw.h| 11 ++-
arch/arm/mach-sunxi/dram_sunxi_dw.c | 94 +++
2 files changed, 82 insertions(+), 23 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
index a5a7ebde44..e843c14202 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
@@ -215,12 +215,17 @@ struct sunxi_mctl_ctl_reg {
#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
/* The eight data lines (DQn) plus DM, DQS and DQSN */
#define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3)
-struct dram_para {
+
+struct rank_para {
u16 page_size;
- u8 bus_full_width;
- u8 dual_rank;
u8 row_bits;
u8 bank_bits;
+};
+
+struct dram_para {
+ u8 dual_rank;
+ u8 bus_full_width;
+ struct rank_para ranks[2];
const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 ac_delays[31];
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index d0600011ff..2b9d631d49 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -399,11 +399,19 @@ static void mctl_set_cr(uint16_t socid, struct dram_para
*para)
#else
#error Unsupported DRAM type!
#endif
- (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS :
MCTL_CR_FOUR_BANKS) |
+ (para->ranks[0].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS :
MCTL_CR_FOUR_BANKS) |
MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
- MCTL_CR_PAGE_SIZE(para->page_size) |
- MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
+ MCTL_CR_PAGE_SIZE(para->ranks[0].page_size) |
+ MCTL_CR_ROW_BITS(para->ranks[0].row_bits), &mctl_com->cr);
+
+ if (para->dual_rank && (socid == SOCID_A64 || socid == SOCID_R40)) {
+ writel((para->ranks[1].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS :
MCTL_CR_FOUR_BANKS) |
+ MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
+ MCTL_CR_DUAL_RANK |
+ MCTL_CR_PAGE_SIZE(para->ranks[1].page_size) |
+ MCTL_CR_ROW_BITS(para->ranks[1].row_bits),
&mctl_com->cr_r1);
+ }
if (socid == SOCID_R40) {
if (para->dual_rank)
@@ -646,35 +654,63 @@ static int mctl_channel_init(uint16_t socid, struct
dram_para *para)
return 0;
}
-static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
+/*
+ * Test if memory at offset offset matches memory at a certain base
+ */
+static bool mctl_mem_matches_base(u32 offset, ulong base)
+{
+ /* Try to write different values to RAM at two addresses */
+ writel(0, base);
+ writel(0xaa55aa55, base + offset);
+ dsb();
+ /* Check if the same value is actually observed when reading back */
+ return readl(base) ==
+ readl(base + offset);
+}
+
+static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para
*para, ulong base, struct rank_para *rank)
{
/* detect row address bits */
- para->page_size = 512;
- para->row_bits = 16;
- para->bank_bits = 2;
+ rank->page_size = 512;
+ rank->row_bits = 16;
+ rank->bank_bits = 2;
mctl_set_cr(socid, para);
- for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
- if (mctl_mem_matches((1 << (para->row_bits + para->bank_bits))
* para->page_size))
+ for (rank->row_bits = 11; rank->row_bits < 16; rank->row_bits++)
+ if (mctl_mem_matches_base((1 << (rank->row_bits +
rank->bank_bits)) * rank->page_size, base))
break;
/* detect bank address bits */
- para->bank_bits = 3;
+ rank->bank_bits = 3;
mctl_set_cr(socid, para);
- for (para->bank_bits = 2; para->bank_bits < 3; para-&
[PATCH 0/2] A64/R40 DRAM controller dual-rank-related changes
This patchset contains two patches. The first one enables asymmetric dual rank DRAM on A64. This is needed for 3GiB PinePhone, which has 2GiB rank 0 and 1GiB rank 1. This patch is already used by the firmware flashed to PinePhone by factory. The second one enables dual rank (and asymmetric dual rank, although not tested because of lack of real board) on R40. In order to support single rank and dual rank at the same time, a new rank detection code is implemented (because PIR_QSGATE-based one does not work on R40). The code enables some error report facility of the DRAM controller, and then tries to access rank 1 and then check for error. It's placed at 2nd patch because it depends on the function that calculates rank 0 size (and rank 1 base address) introduced in PATCH 1. Icenowy Zheng (2): sunxi: support asymmetric dual rank DRAM on A64/R40 sunxi: enable dual rank memory on R40 .../include/asm/arch-sunxi/dram_sunxi_dw.h| 11 +- arch/arm/mach-sunxi/dram_sunxi_dw.c | 149 +++--- 2 files changed, 131 insertions(+), 29 deletions(-) -- 2.30.0
Re: [linux-sunxi] [PATCH] sunxi: Add arm64 FEL support
在 2020-11-19星期四的 10:54 +，Andre Przywara写道： > So far we did not support the BootROM based FEL USB debug mode on the > 64-bit builds for Allwinner SoCs: The BootROM is using AArch32, but > the > SPL runs in AArch64. > Returning back to AArch32 was not working as expected, since the RMR > reset into 32-bit mode always starts execution in the BootROM, but > not > in the FEL routine. > > After some debug and research and with help via IRC, the CPU hotplug > mechanism emerged as a solution: If a certain R_CPUCFG register > contains > some magic, the BootROM will immediately branch to an address stored > in > some other register. This works well for our purposes. > > Enable the FEL feature by providing early AArch32 code to first save > the > FEL state, *before* initially entering AArch64. > If we eventually determine that we should return to FEL, we reset > back > into AArch32, and use the CPU hotplug mechanism to run some small > AArch32 code snippet that restores the initially saved FEL state. > > That allows the normal AArch64 SPL build to be loaded via the sunxi- > fel > tool, with it returning into FEL mode, so that other payloads can be > transferred via FEL as well. > > Tested on A64, H5 and H6. > > Signed-off-by: Andre Przywara Tested-by: Icenowy Zheng > --- > arch/arm/cpu/armv8/Makefile | 2 + > arch/arm/cpu/armv8/fel_utils.S | 78 > + > arch/arm/include/asm/arch-sunxi/boot0.h | 14 + > include/configs/sunxi-common.h | 2 - > 4 files changed, 94 insertions(+), 2 deletions(-) > create mode 100644 arch/arm/cpu/armv8/fel_utils.S > > diff --git a/arch/arm/cpu/armv8/Makefile > b/arch/arm/cpu/armv8/Makefile > index 93d26f98568..f7b4a5ee46c 100644 > --- a/arch/arm/cpu/armv8/Makefile > +++ b/arch/arm/cpu/armv8/Makefile > @@ -27,6 +27,8 @@ obj-$(CONFIG_ARM_SMCCC) += smccc-call.o > > ifndef CONFIG_SPL_BUILD > obj-$(CONFIG_ARMV8_SPIN_TABLE) += spin_table.o spin_table_v8.o > +else > +obj-$(CONFIG_ARCH_SUNXI) += fel_utils.o > endif > obj-$(CONFIG_$(SPL_)ARMV8_SEC_FIRMWARE_SUPPORT) += sec_firmware.o > sec_firmware_asm.o > > diff --git a/arch/arm/cpu/armv8/fel_utils.S > b/arch/arm/cpu/armv8/fel_utils.S > new file mode 100644 > index 000..334fdef7fa0 > --- /dev/null > +++ b/arch/arm/cpu/armv8/fel_utils.S > @@ -0,0 +1,78 @@ > +/* > + * Utility functions for FEL mode, when running SPL in AArch64. > + * > + * Copyright (c) 2017 Arm Ltd. > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#include > +#include > +#include > +#include > + > +/* > + * We don't overwrite save_boot_params() here, to save the FEL state > upon > + * entry, since this would run *after* the RMR reset, which clobbers > that > + * state. > + * Instead we store the state _very_ early in the boot0 hook, > *before* > + * resetting to AArch64. > + */ > + > +/* > + * The FEL routines in BROM run in AArch32. > + * Reset back into 32-bit mode here and restore the saved FEL state > + * afterwards. > + * Resetting back into AArch32/EL3 using the RMR always enters the > BROM, > + * but we can use the CPU hotplug mechanism to branch back to our > code > + * immediately. > + */ > +ENTRY(return_to_fel) > + /* > + * the RMR reset will clear all registers, so save the > arguments > + * (LR and SP) in the fel_stash structure, which we read > anyways later > + */ > + adr x2, fel_stash > + str w0, [x2] > + str w1, [x2, #4] > + > + adr x1, fel_stash_addr // to find the fel_stash > address in AA32 > + str w2, [x1] > + > + ldr x0, =0xfa50392f // CPU hotplug magic > +#ifndef CONFIG_MACH_SUN50I_H6 > + ldr x2, =(SUNXI_CPUCFG_BASE + 0x1a4) // offset for CPU > hotplug base > + str w0, [x2, #0x8] > +#else > + ldr x2, =(SUNXI_RTC_BASE + 0x1b8) // > BOOT_CPU_HP_FLAG_REG > + str w0, [x2], #0x4 > +#endif > + adr x0, back_in_32 > + str w0, [x2] > + > + dsb sy > + isb sy > + mov x0, #2 // RMR reset into AArch32 > + dsb sy > + msr RMR_EL3, x0 > + isb sy > +1: wfi > + b 1b > + > +/* AArch32 code to restore the state from fel_stash and return back > to FEL. */ > +back_in_32: > + .word 0xe59f0028 // ldr r0, [pc, #40] ; load > fel_stash address > + .word 0xe5901008 // ldr r1, [r0, #8] > + .word 0xe129f001 // msr CPSR_fc, r1 > + .word 0xf57ff06f // isb > + .word 0xe590d000 // ldr
[PATCH v3] sunxi: add PineCube board
PineCube is an IP camera development kit released by Pine64. It comes with the following compoents: - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC, a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps Ethernet port and FPC connectors for camera and daughter board. - An OV5640-based camera module which is connected to the parallel CSI bus of the mainboard. - A daughterboard with several buttons, a SD slot, some IR LEDs, a microphone and a speaker connector. As the device tree is synchronized in a previous commit, just add it to Makefile, create a new MAINTAINER item and provide a defconfig. Signed-off-by: Icenowy Zheng --- Changes since v2: - Add Makefile reference to DT. Changes since v1: - Dropped LDO3 quirk. arch/arm/dts/Makefile | 1 + board/sunxi/MAINTAINERS| 5 + configs/pinecube_defconfig | 15 +++ 3 files changed, 21 insertions(+) create mode 100644 configs/pinecube_defconfig diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7d1a369845..e6993733b0 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -587,6 +587,7 @@ dtb-$(CONFIG_MACH_SUN8I_R40) += \ sun8i-r40-bananapi-m2-ultra.dtb \ sun8i-v40-bananapi-m2-berry.dtb dtb-$(CONFIG_MACH_SUN8I_V3S) += \ + sun8i-s3-pinecube.dtb \ sun8i-v3s-licheepi-zero.dtb dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-bananapi-m2-plus.dtb \ diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index d3755ae41a..735801ae1d 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -440,6 +440,11 @@ M: Vasily Khoruzhick S: Maintained F: configs/pinebook_defconfig +PINECUBE BOARD: +M: Icenowy Zheng +S: Maintained +F: configs/pinecube_defconfig + PINE64 BOARDS M: Andre Przywara S: Maintained diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig new file mode 100644 index 00..a8c404f6b1 --- /dev/null +++ b/configs/pinecube_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_V3S=y +CONFIG_SUNXI_DRAM_DDR3_1333=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ODT_EN=y +CONFIG_I2C0_ENABLE=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_NETDEVICES is not set +CONFIG_AXP209_POWER=y +CONFIG_AXP_DCDC2_VOLT=1250 +CONFIG_AXP_DCDC3_VOLT=3300 +CONFIG_CONS_INDEX=3 -- 2.28.0
[PATCH v2] sunxi: add PineCube board
PineCube is an IP camera development kit released by Pine64. It comes with the following compoents: - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC, a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps Ethernet port and FPC connectors for camera and daughter board. - An OV5640-based camera module which is connected to the parallel CSI bus of the mainboard. - A daughterboard with several buttons, a SD slot, some IR LEDs, a microphone and a speaker connector. As the device tree is synchronized in a previous commit, just add MAINTAINER item and a defconfig. Signed-off-by: Icenowy Zheng --- Changes in v2: - Removed LDO3 hack in U-Boot because LDO3 is kept disabled in U-Boot. board/sunxi/MAINTAINERS| 5 + configs/pinecube_defconfig | 15 +++ 2 files changed, 20 insertions(+) create mode 100644 configs/pinecube_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index d3755ae41a..735801ae1d 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -440,6 +440,11 @@ M: Vasily Khoruzhick S: Maintained F: configs/pinebook_defconfig +PINECUBE BOARD: +M: Icenowy Zheng +S: Maintained +F: configs/pinecube_defconfig + PINE64 BOARDS M: Andre Przywara S: Maintained diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig new file mode 100644 index 00..a8c404f6b1 --- /dev/null +++ b/configs/pinecube_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_V3S=y +CONFIG_SUNXI_DRAM_DDR3_1333=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ODT_EN=y +CONFIG_I2C0_ENABLE=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_NETDEVICES is not set +CONFIG_AXP209_POWER=y +CONFIG_AXP_DCDC2_VOLT=1250 +CONFIG_AXP_DCDC3_VOLT=3300 +CONFIG_CONS_INDEX=3 -- 2.28.0
Re: [linux-sunxi] Re: [PATCH 6/6] sunxi: add PineCube board
于 2020年10月27日 GMT+08:00 上午2:32:30, Maxime Ripard 写到: >On Mon, Oct 26, 2020 at 10:21:00PM +0800, Icenowy Zheng wrote: >> PineCube is an IP camera development kit released by Pine64. >> >> It comes with the following compoents: >> >> - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC, >> a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps >> Ethernet port and FPC connectors for camera and daughter board. >> - An OV5640-based camera module which is connected to the parallel >CSI >> bus of the mainboard. >> - A daughterboard with several buttons, a SD slot, some IR LEDs, a >> microphone and a speaker connector. >> >> As the device tree is synchronized in a previous commit, just add >> MAINTAINER item and a defconfig. >> >> Signed-off-by: Icenowy Zheng >> --- >> board/sunxi/MAINTAINERS| 5 + >> configs/pinecube_defconfig | 17 + >> 2 files changed, 22 insertions(+) >> create mode 100644 configs/pinecube_defconfig >> >> diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS >> index 1180b86db3..5c53b2c878 100644 >> --- a/board/sunxi/MAINTAINERS >> +++ b/board/sunxi/MAINTAINERS >> @@ -440,6 +440,11 @@ M: Vasily Khoruzhick >> S: Maintained >> F: configs/pinebook_defconfig >> >> +PINECUBE BOARD: >> +M: Icenowy Zheng >> +S: Maintained >> +F: configs/pinecube_defconfig >> + >> PINE64 BOARDS >> M: Andre Przywara >> S: Maintained >> diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig >> new file mode 100644 >> index 00..107562ee49 >> --- /dev/null >> +++ b/configs/pinecube_defconfig >> @@ -0,0 +1,17 @@ >> +CONFIG_ARM=y >> +CONFIG_ARCH_SUNXI=y >> +CONFIG_SPL=y >> +CONFIG_MACH_SUN8I_V3S=y >> +CONFIG_SUNXI_DRAM_DDR3_1333=y >> +CONFIG_DRAM_CLK=504 >> +CONFIG_DRAM_ODT_EN=y >> +CONFIG_I2C0_ENABLE=y >> +CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" >> +CONFIG_SPL_I2C_SUPPORT=y >> +# CONFIG_NETDEVICES is not set >> +CONFIG_AXP209_POWER=y >> +CONFIG_AXP_DCDC2_VOLT=1250 >> +CONFIG_AXP_DCDC3_VOLT=3300 >> +CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y >> +CONFIG_AXP_ALDO3_INRUSH_QUIRK=y > >It would be worth mentioning in the commit log why you need those >options. For the ALDO3 options, they might be not necessary in U-Boot stage, because it's finally only used in Linux stage. I don't know whether these are still needed when we declared the hack in DT for Linux. > >With that fixed, the whole series is >Acked-by: Maxime Ripard > >Thanks! >Maxime
[PATCH 6/6] sunxi: add PineCube board
PineCube is an IP camera development kit released by Pine64. It comes with the following compoents: - A mainboard with Sochip S3 SoC, a 16MByte SPI Flash, AXP209 PMIC, a power-only microUSB connector, a USB Type-A connector, a 10/100Mbps Ethernet port and FPC connectors for camera and daughter board. - An OV5640-based camera module which is connected to the parallel CSI bus of the mainboard. - A daughterboard with several buttons, a SD slot, some IR LEDs, a microphone and a speaker connector. As the device tree is synchronized in a previous commit, just add MAINTAINER item and a defconfig. Signed-off-by: Icenowy Zheng --- board/sunxi/MAINTAINERS| 5 + configs/pinecube_defconfig | 17 + 2 files changed, 22 insertions(+) create mode 100644 configs/pinecube_defconfig diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 1180b86db3..5c53b2c878 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -440,6 +440,11 @@ M: Vasily Khoruzhick S: Maintained F: configs/pinebook_defconfig +PINECUBE BOARD: +M: Icenowy Zheng +S: Maintained +F: configs/pinecube_defconfig + PINE64 BOARDS M: Andre Przywara S: Maintained diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig new file mode 100644 index 00..107562ee49 --- /dev/null +++ b/configs/pinecube_defconfig @@ -0,0 +1,17 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN8I_V3S=y +CONFIG_SUNXI_DRAM_DDR3_1333=y +CONFIG_DRAM_CLK=504 +CONFIG_DRAM_ODT_EN=y +CONFIG_I2C0_ENABLE=y +CONFIG_DEFAULT_DEVICE_TREE="sun8i-s3-pinecube" +CONFIG_SPL_I2C_SUPPORT=y +# CONFIG_NETDEVICES is not set +CONFIG_AXP209_POWER=y +CONFIG_AXP_DCDC2_VOLT=1250 +CONFIG_AXP_DCDC3_VOLT=3300 +CONFIG_AXP_ALDO3_VOLT_SLOPE_08=y +CONFIG_AXP_ALDO3_INRUSH_QUIRK=y +CONFIG_CONS_INDEX=3 -- 2.28.0
[PATCH 5/6] sunxi: dts: sync Allwinner V3s-related DTs from Linux 5.10-rc1
This commit imports device tree files that are related to Allwinner V3
series from Linux commit 3650b228f83a ("Linux 5.10-rc1").
Signed-off-by: Icenowy Zheng
---
arch/arm/dts/sun8i-s3-lichee-zero-plus.dts| 53 +++
arch/arm/dts/sun8i-s3-pinecube.dts| 235 +
arch/arm/dts/sun8i-v3.dtsi| 27 ++
arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 96 ++
arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 26 +-
arch/arm/dts/sun8i-v3s.dtsi | 318 --
6 files changed, 725 insertions(+), 30 deletions(-)
create mode 100644 arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
create mode 100644 arch/arm/dts/sun8i-s3-pinecube.dts
create mode 100644 arch/arm/dts/sun8i-v3.dtsi
create mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts
diff --git a/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
new file mode 100644
index 00..d18192d51d
--- /dev/null
+++ b/arch/arm/dts/sun8i-s3-lichee-zero-plus.dts
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Icenowy Zheng
+ */
+
+/dts-v1/;
+#include "sun8i-v3.dtsi"
+
+#include
+
+/ {
+ model = "Sipeed Lichee Zero Plus";
+ compatible = "sipeed,lichee-zero-plus", "sochip,s3",
+"allwinner,sun8i-v3";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ reg_vcc3v3: vcc3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ };
+};
+
+&mmc0 {
+ broken-cd;
+ bus-width = <4>;
+ vmmc-supply = <®_vcc3v3>;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-0 = <&uart0_pb_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun8i-s3-pinecube.dts
b/arch/arm/dts/sun8i-s3-pinecube.dts
new file mode 100644
index 00..9bab6b7f40
--- /dev/null
+++ b/arch/arm/dts/sun8i-s3-pinecube.dts
@@ -0,0 +1,235 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * Copyright 2019 Icenowy Zheng
+ */
+
+/dts-v1/;
+#include "sun8i-v3.dtsi"
+#include
+#include
+
+/ {
+ model = "PineCube IP Camera";
+ compatible = "pine64,pinecube", "allwinner,sun8i-s3";
+
+ aliases {
+ serial0 = &uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led1 {
+ label = "pine64:ir:led1";
+ gpios = <&pio 1 10 GPIO_ACTIVE_LOW>; /* PB10 */
+ };
+
+ led2 {
+ label = "pine64:ir:led2";
+ gpios = <&pio 1 12 GPIO_ACTIVE_LOW>; /* PB12 */
+ };
+ };
+
+ reg_vcc5v0: vcc5v0 {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ };
+
+ reg_vcc_wifi: vcc-wifi {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc-wifi";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&pio 1 2 GPIO_ACTIVE_LOW>; /* PB2 WIFI-EN */
+ vin-supply = <®_dcdc3>;
+ startup-delay-us = <20>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&pio 1 3 GPIO_ACTIVE_LOW>; /* PB3 WIFI-RST */
+ post-power-on-delay-ms = <200>;
+ };
+};
+
+&csi1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&csi1_8bit_pins>;
+ status = "okay";
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ csi1_ep: endpoint {
+ remote-endpoint = <&ov5640_ep>;
+ bus-width = <8>;
+ hsync-active = <1>; /* Active high */
+ vsync-active = <0>; /* Active low */
+
[PATCH 4/6] sunxi: allow to use AXP20[39] attached to I2C0 on V3 series
The reference design of Allwinner V3 series uses an
AXP203 or AXP209 PMIC attached to the I2C0 bus of the SoC, although the
first community-available V3s board, Lichee Pi Zero, omitted it.
Allow to introduce support for the PMIC on boards with it.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/gpio.h | 1 +
board/sunxi/board.c| 4
drivers/power/Kconfig | 4 ++--
3 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index a646ea6a3c..f817d328f4 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -158,6 +158,7 @@ enum sunxi_gpio_number {
#define SUN5I_GPB_TWI1 2
#define SUN4I_GPB_TWI2 2
#define SUN5I_GPB_TWI2 2
+#define SUN8I_V3S_GPB_TWI0 2
#define SUN4I_GPB_UART02
#define SUN5I_GPB_UART02
#define SUN8I_GPB_UART22
diff --git a/board/sunxi/board.c b/board/sunxi/board.c
index a5cf0b65c7..3796213b9f 100644
--- a/board/sunxi/board.c
+++ b/board/sunxi/board.c
@@ -101,6 +101,10 @@ void i2c_init_board(void)
sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
clock_twi_onoff(0, 1);
+#elif defined(CONFIG_MACH_SUN8I_V3S)
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
+ sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
+ clock_twi_onoff(0, 1);
#elif defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 5910926fac..02050f6f35 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -14,7 +14,7 @@ choice
default AXP209_POWER if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default AXP221_POWER if MACH_SUN6I || MACH_SUN8I_A23 || MACH_SUN8I_A33
|| MACH_SUN8I_R40
default AXP818_POWER if MACH_SUN8I_A83T
- default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I
+ default SUNXI_NO_PMIC if MACH_SUNXI_H3_H5 || MACH_SUN50I ||
MACH_SUN8I_V3S
config SUNXI_NO_PMIC
bool "board without a pmic"
@@ -32,7 +32,7 @@ config AXP152_POWER
config AXP209_POWER
bool "axp209 pmic support"
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
+ depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_V3S
select AXP_PMIC_BUS
select CMD_POWEROFF
---help---
--
2.28.0
[PATCH 3/6] clk: sunxi: add compatible string for V3
A new compatible string is introduced for V3 CCU, because it has a few
extra features available.
Add the compatible string to the clock driver. As the extra features are
not touched, just share the description struct now.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi/clk_v3s.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index b79446cc4f..f3fc06ab31 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -56,6 +56,8 @@ static int v3s_clk_bind(struct udevice *dev)
static const struct udevice_id v3s_clk_ids[] = {
{ .compatible = "allwinner,sun8i-v3s-ccu",
.data = (ulong)&v3s_ccu_desc },
+ { .compatible = "allwinner,sun8i-v3-ccu",
+ .data = (ulong)&v3s_ccu_desc },
{ }
};
--
2.28.0
[PATCH 2/6] sunxi: gpio: introduce compatible string for V3 GPIO
A new compatible string is introduced for V3 GPIO, because it has more
pins available than V3s.
Add the compatible string to the GPIO driver.
Signed-off-by: Icenowy Zheng
---
drivers/gpio/sunxi_gpio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
index 3efccf496f..02c3471b56 100644
--- a/drivers/gpio/sunxi_gpio.c
+++ b/drivers/gpio/sunxi_gpio.c
@@ -351,6 +351,7 @@ static const struct udevice_id sunxi_gpio_ids[] = {
ID("allwinner,sun8i-a83t-pinctrl", a_all),
ID("allwinner,sun8i-h3-pinctrl",a_all),
ID("allwinner,sun8i-r40-pinctrl", a_all),
+ ID("allwinner,sun8i-v3-pinctrl",a_all),
ID("allwinner,sun8i-v3s-pinctrl", a_all),
ID("allwinner,sun9i-a80-pinctrl", a_all),
ID("allwinner,sun50i-a64-pinctrl", a_all),
--
2.28.0
[PATCH 0/6] Allwinner V3/S3 support + PineCube support
This patchset tries to add support for Allwinner V3/S3 and Pine64 PineCube to U-Boot. First 3 patches adds support for Allwinner V3/S3 to U-Boot by expanding the code of V3s and add compatible strings to individual drivers. Then a patch allows V3 series chips to utilize the AXP20x driver in U-Boot. Finally the device tree is synchorized from Linux v5.10-rc1 (which contains the PineCube DT) and PineCube defconfig is added. Icenowy Zheng (6): sunxi: add V3/S3 support sunxi: gpio: introduce compatible string for V3 GPIO clk: sunxi: add compatible string for V3 sunxi: allow to use AXP20[39] attached to I2C0 on V3 series sunxi: dts: sync Allwinner V3s-related DTs from Linux 5.10-rc1 sunxi: add PineCube board arch/arm/dts/sun8i-s3-lichee-zero-plus.dts| 53 +++ arch/arm/dts/sun8i-s3-pinecube.dts| 235 + arch/arm/dts/sun8i-v3.dtsi| 27 ++ arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts | 96 ++ arch/arm/dts/sun8i-v3s-licheepi-zero.dts | 26 +- arch/arm/dts/sun8i-v3s.dtsi | 318 -- arch/arm/include/asm/arch-sunxi/gpio.h| 1 + arch/arm/mach-sunxi/Kconfig | 3 +- board/sunxi/MAINTAINERS | 5 + board/sunxi/board.c | 4 + configs/pinecube_defconfig| 17 + drivers/clk/sunxi/clk_v3s.c | 2 + drivers/gpio/sunxi_gpio.c | 1 + drivers/power/Kconfig | 4 +- 14 files changed, 758 insertions(+), 34 deletions(-) create mode 100644 arch/arm/dts/sun8i-s3-lichee-zero-plus.dts create mode 100644 arch/arm/dts/sun8i-s3-pinecube.dts create mode 100644 arch/arm/dts/sun8i-v3.dtsi create mode 100644 arch/arm/dts/sun8i-v3s-licheepi-zero-dock.dts create mode 100644 configs/pinecube_defconfig -- 2.28.0
[PATCH 1/6] sunxi: add V3/S3 support
Allwinner V3/Sochip S3 uses the same die with Allwinner V3s/S3L, but V3 comes with no co-packaged DDR (DDR3 is usually used externally), and S3L comes with co-packaged DDR3. Add support for Allwinner V3/S3 chips by add SoC names to original V3s choice, and allow to select DDR3. Signed-off-by: Icenowy Zheng --- arch/arm/mach-sunxi/Kconfig | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig index be0822bfb7..31339ac2a1 100644 --- a/arch/arm/mach-sunxi/Kconfig +++ b/arch/arm/mach-sunxi/Kconfig @@ -253,7 +253,7 @@ config MACH_SUN8I_R40 select PHY_SUN4I_USB config MACH_SUN8I_V3S - bool "sun8i (Allwinner V3s)" + bool "sun8i (Allwinner V3/V3s/S3/S3L)" select CPU_V7A select CPU_V7_HAS_NONSEC select CPU_V7_HAS_VIRT @@ -363,7 +363,6 @@ choice config SUNXI_DRAM_DDR3_1333 bool "DDR3 1333" select SUNXI_DRAM_DDR3 - depends on !MACH_SUN8I_V3S ---help--- This option is the original only supported memory type, which suits many H3/H5/A64 boards available now. -- 2.28.0
[PATCH] sunxi: make V3s DRAM initialization more proper
Previously, because we have no source code about the DRAM initialization
of V3s and missing some configurations (delays and MBUS QoS info), our
V3s DRAM initialization sequence is hacked from the H3 one.
As the SDK shipped with PineCube contains source code for V3s libdram,
we can retrieve these information from it and tweak some other magic
bits.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/cpu.h | 1 +
arch/arm/mach-sunxi/dram_sunxi_dw.c | 91 +--
2 files changed, 87 insertions(+), 5 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h
b/arch/arm/include/asm/arch-sunxi/cpu.h
index 4c399b0a15..8b57d24e2f 100644
--- a/arch/arm/include/asm/arch-sunxi/cpu.h
+++ b/arch/arm/include/asm/arch-sunxi/cpu.h
@@ -16,6 +16,7 @@
#define SOCID_A64 0x1689
#define SOCID_H3 0x1680
+#define SOCID_V3S 0x1681
#define SOCID_H5 0x1718
#define SOCID_R40 0x1701
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index a462538521..d0600011ff 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -63,6 +63,8 @@ enum {
MBUS_PORT_CSI = 5,
MBUS_PORT_NAND = 6,
MBUS_PORT_SS= 7,
+ MBUS_PORT_DE_V3S= 8,
+ MBUS_PORT_DE_CFD_V3S= 9,
MBUS_PORT_TS= 8,
MBUS_PORT_DI= 9,
MBUS_PORT_DE= 10,
@@ -134,6 +136,29 @@ static void mctl_set_master_priority_h3(void)
MBUS_CONF(DE_CFD, true,HIGH, 0, 1024, 288, 64);
}
+static void mctl_set_master_priority_v3s(void)
+{
+ struct sunxi_mctl_com_reg * const mctl_com =
+ (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
+
+ /* enable bandwidth limit windows and set windows size 1us */
+ writel((1 << 16) | (400 << 0), &mctl_com->bwcr);
+
+ /* set cpu high priority */
+ writel(0x0001, &mctl_com->mapr);
+
+ MBUS_CONF( CPU, true, HIGHEST, 0, 160, 100, 80);
+ MBUS_CONF( GPU, true,HIGH, 0, 1792, 1536,0);
+ MBUS_CONF(UNUSED, true, HIGHEST, 0, 256, 128, 80);
+ MBUS_CONF( DMA, true,HIGH, 0, 256, 100,0);
+ MBUS_CONF(VE, true,HIGH, 0, 2048, 1600,0);
+ MBUS_CONF( CSI, true, HIGHEST, 0, 384, 256,0);
+ MBUS_CONF( NAND, true,HIGH, 0, 100, 50,0);
+ MBUS_CONF(SS, true,HIGH, 0, 384, 256,0);
+ MBUS_CONF(DE_V3S, false,HIGH, 0, 8192, 4096,0);
+ MBUS_CONF(DE_CFD_V3S, true,HIGH, 0, 640, 256,0);
+}
+
static void mctl_set_master_priority_a64(void)
{
struct sunxi_mctl_com_reg * const mctl_com =
@@ -231,6 +256,9 @@ static void mctl_set_master_priority(uint16_t socid)
case SOCID_H3:
mctl_set_master_priority_h3();
return;
+ case SOCID_V3S:
+ mctl_set_master_priority_v3s();
+ return;
case SOCID_A64:
mctl_set_master_priority_a64();
return;
@@ -334,6 +362,28 @@ static void mctl_h3_zq_calibration_quirk(struct dram_para
*para)
}
}
+static void mctl_v3s_zq_calibration_quirk(struct dram_para *para)
+{
+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
+
+ u32 reg_val;
+
+ clrsetbits_le32(&mctl_ctl->zqcr, 0xff,
+ CONFIG_DRAM_ZQ & 0xff);
+ mctl_phy_init(PIR_ZCAL);
+
+ reg_val = readl(&mctl_ctl->zqdr[0]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[0]);
+
+ reg_val = readl(&mctl_ctl->zqdr[1]);
+ reg_val &= (0x1f << 16) | (0x1f << 0);
+ reg_val |= reg_val << 8;
+ writel(reg_val, &mctl_ctl->zqdr[1]);
+}
+
static void mctl_set_cr(uint16_t socid, struct dram_para *para)
{
struct sunxi_mctl_com_reg * const mctl_com =
@@ -391,7 +441,7 @@ static void mctl_sys_init(uint16_t socid, struct dram_para
*para)
CCM_DRAMCLK_CFG_DIV(1) |
CCM_DRAMCLK_CFG_SRC_PLL11 |
CCM_DRAMCLK_CFG_UPD);
- } else if (socid == SOCID_H3 || socid == SOCID_H5) {
+ } else if (socid == SOCID_H3 || socid == SOCID_H5 || socid ==
SOCID_V3S) {
clock_set_pll5(CONFIG_DRAM_CLK * 2 * 100, false);
clrsetbits_le32(&ccm->dram_clk_cfg,
CCM_DRAMCLK_CFG_DIV_MASK |
@@ -474,6 +524,13 @@ static int mctl_channel_init(uint16_t socid, struct
dram_para *para)
/* dphy & aphy phase select 270 degree */
clrsetbits_le32(&mctl_ctl->pgcr
[PATCH] ARM: add Kconfig option for PSCI 0.1
We still have some platforms that only implements functionalities in PSCI 0.1 (e.g. Allwinner ARMv7 SoCs). Add a Kconfig option for exporting only PSCI 0.1. The code to export PSCI 0.1 is still available and gets activated by this patch. In addition, default ARCH_SUNXI U-Boot PSCI implementation to export PSCI 0.1, to fix poweroff/reboot regression on Allwinner multi-core ARMv7 SoCs. Signed-off-by: Icenowy Zheng --- arch/arm/cpu/armv7/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig index 8eee801dce..60bb0a9e1e 100644 --- a/arch/arm/cpu/armv7/Kconfig +++ b/arch/arm/cpu/armv7/Kconfig @@ -44,6 +44,7 @@ config ARMV7_PSCI choice prompt "Supported PSCI version" depends on ARMV7_PSCI + default ARMV7_PSCI_0_1 if ARCH_SUNXI default ARMV7_PSCI_1_0 help Select the supported PSCI version. @@ -53,6 +54,9 @@ config ARMV7_PSCI_1_0 config ARMV7_PSCI_0_2 bool "PSCI V0.2" + +config ARMV7_PSCI_0_1 + bool "PSCI V0.1" endchoice config ARMV7_PSCI_NR_CPUS -- 2.27.0
Re: [linux-sunxi] Re: [RFC PATCH] sunxi: support asymmetric dual rank DRAM on A64/R40
于 2020年6月24日 GMT+08:00 上午8:28:39, "André Przywara" 写到:
>On 19/06/2020 13:16, Icenowy Zheng wrote:
>
>Hi Icenowy,
>
>> Previously we have known that R40 has a configuration register for
>its
>> rank 1, which allows different configuration than rank 0. Reverse
>> engineering of newest libdram of A64 from Allwinner shows that A64
>has
>> this register too. It's bit 0 (which enables dual rank in rank 0
>> configuration register) means a dedicated rank size setup is used for
>> rank 1.
>
>Ah! That's a nice discovery, as it probably explains how my Eachlink H6
>TV box works with its asymmetric 3GB DRAM config!
Wait. The configuration of H6 DRAM controller is totally different. it uses
ADDRMAP registers in DRAM controller, instead of specifying parameters
in MCTL_COM part.
>
>> Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB
>> rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank
>> DRAM support necessary.
>>
>> Add this support. As we have gained knowledge of asymmetric dual
>rank,
>> we can now allow R40 dual rank memory setup to work too.
>>
>> Signed-off-by: Icenowy Zheng
>> ---
>> Testing on R40 boards and A64 single rank boards (e.g. the original
>Pine
>> A64+) is welcomed. I have these boards, but I get too lazy to take
>them
>> out and test them.
>
>I briefly tested this on a Bananapi M2 Berry (R40, 1GB), Pine64 512MB
>and Pine64+ 2GB. All three boot happily into U-Boot, tested the Pine64+
>to the Linux prompt as well.
>
>I will do a proper review shortly.
>
>Thanks for the patch!
>
>Cheers,
>Andre
>
>>
>> .../include/asm/arch-sunxi/dram_sunxi_dw.h| 11 +-
>> arch/arm/mach-sunxi/dram_sunxi_dw.c | 100
>+-
>> 2 files changed, 84 insertions(+), 27 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
>b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
>> index a5a7ebde44..e843c14202 100644
>> --- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
>> +++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
>> @@ -215,12 +215,17 @@ struct sunxi_mctl_ctl_reg {
>> #define NR_OF_BYTE_LANES(32 / BITS_PER_BYTE)
>> /* The eight data lines (DQn) plus DM, DQS and DQSN */
>> #define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
>> -struct dram_para {
>> +
>> +struct rank_para {
>> u16 page_size;
>> -u8 bus_full_width;
>> -u8 dual_rank;
>> u8 row_bits;
>> u8 bank_bits;
>> +};
>> +
>> +struct dram_para {
>> +u8 dual_rank;
>> +u8 bus_full_width;
>> +struct rank_para ranks[2];
>> const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
>> const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
>> const u8 ac_delays[31];
>> diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c
>b/arch/arm/mach-sunxi/dram_sunxi_dw.c
>> index a462538521..7a40d92349 100644
>> --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
>> +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
>> @@ -349,18 +349,24 @@ static void mctl_set_cr(uint16_t socid, struct
>dram_para *para)
>> #else
>> #error Unsupported DRAM type!
>> #endif
>> - (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS :
>MCTL_CR_FOUR_BANKS) |
>> + (para->ranks[0].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS :
>MCTL_CR_FOUR_BANKS) |
>> MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
>> (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK)
>|
>> - MCTL_CR_PAGE_SIZE(para->page_size) |
>> - MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
>> + MCTL_CR_PAGE_SIZE(para->ranks[0].page_size) |
>> + MCTL_CR_ROW_BITS(para->ranks[0].row_bits), &mctl_com->cr);
>>
>> -if (socid == SOCID_R40) {
>> -if (para->dual_rank)
>> -panic("Dual rank memory not supported\n");
>> +if (socid == SOCID_A64 || socid == SOCID_R40) {
>> +writel((para->ranks[1].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS :
>MCTL_CR_FOUR_BANKS) |
>> + MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
>> + (para->dual_rank ? MCTL_CR_DUAL_RANK :
>> MCTL_CR_SINGLE_RANK)
>|
>> + MCTL_CR_PAGE_SIZE(para->ranks[1].page_size) |
>> + MCTL_CR_ROW_BITS(para->ranks[1].row_bits),
>&mctl_com->cr_r1);
>> +}
>>
>> +if (socid == SOCID_R40) {
>>
[RFC PATCH] sunxi: support asymmetric dual rank DRAM on A64/R40
Previously we have known that R40 has a configuration register for its
rank 1, which allows different configuration than rank 0. Reverse
engineering of newest libdram of A64 from Allwinner shows that A64 has
this register too. It's bit 0 (which enables dual rank in rank 0
configuration register) means a dedicated rank size setup is used for
rank 1.
Now, Pine64 scheduled to use a 3GiB LPDDR3 DRAM chip (which has 2GiB
rank 0 and 1GiB rank 1) on PinePhone, that makes asymmetric dual rank
DRAM support necessary.
Add this support. As we have gained knowledge of asymmetric dual rank,
we can now allow R40 dual rank memory setup to work too.
Signed-off-by: Icenowy Zheng
---
Testing on R40 boards and A64 single rank boards (e.g. the original Pine
A64+) is welcomed. I have these boards, but I get too lazy to take them
out and test them.
.../include/asm/arch-sunxi/dram_sunxi_dw.h| 11 +-
arch/arm/mach-sunxi/dram_sunxi_dw.c | 100 +-
2 files changed, 84 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
index a5a7ebde44..e843c14202 100644
--- a/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
+++ b/arch/arm/include/asm/arch-sunxi/dram_sunxi_dw.h
@@ -215,12 +215,17 @@ struct sunxi_mctl_ctl_reg {
#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
/* The eight data lines (DQn) plus DM, DQS and DQSN */
#define LINES_PER_BYTE_LANE(BITS_PER_BYTE + 3)
-struct dram_para {
+
+struct rank_para {
u16 page_size;
- u8 bus_full_width;
- u8 dual_rank;
u8 row_bits;
u8 bank_bits;
+};
+
+struct dram_para {
+ u8 dual_rank;
+ u8 bus_full_width;
+ struct rank_para ranks[2];
const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
const u8 ac_delays[31];
diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c
b/arch/arm/mach-sunxi/dram_sunxi_dw.c
index a462538521..7a40d92349 100644
--- a/arch/arm/mach-sunxi/dram_sunxi_dw.c
+++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c
@@ -349,18 +349,24 @@ static void mctl_set_cr(uint16_t socid, struct dram_para
*para)
#else
#error Unsupported DRAM type!
#endif
- (para->bank_bits == 3 ? MCTL_CR_EIGHT_BANKS :
MCTL_CR_FOUR_BANKS) |
+ (para->ranks[0].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS :
MCTL_CR_FOUR_BANKS) |
MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
- MCTL_CR_PAGE_SIZE(para->page_size) |
- MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
+ MCTL_CR_PAGE_SIZE(para->ranks[0].page_size) |
+ MCTL_CR_ROW_BITS(para->ranks[0].row_bits), &mctl_com->cr);
- if (socid == SOCID_R40) {
- if (para->dual_rank)
- panic("Dual rank memory not supported\n");
+ if (socid == SOCID_A64 || socid == SOCID_R40) {
+ writel((para->ranks[1].bank_bits == 3 ? MCTL_CR_EIGHT_BANKS :
MCTL_CR_FOUR_BANKS) |
+ MCTL_CR_BUS_FULL_WIDTH(para->bus_full_width) |
+ (para->dual_rank ? MCTL_CR_DUAL_RANK :
MCTL_CR_SINGLE_RANK) |
+ MCTL_CR_PAGE_SIZE(para->ranks[1].page_size) |
+ MCTL_CR_ROW_BITS(para->ranks[1].row_bits),
&mctl_com->cr_r1);
+ }
+ if (socid == SOCID_R40) {
/* Mux pin to A15 address line for single rank memory. */
- setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
+ if (!para->dual_rank)
+ setbits_le32(&mctl_com->cr_r1, MCTL_CR_R1_MUX_A15);
}
}
@@ -584,35 +590,63 @@ static int mctl_channel_init(uint16_t socid, struct
dram_para *para)
return 0;
}
-static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para)
+/*
+ * Test if memory at offset offset matches memory at a certain base
+ */
+static bool mctl_mem_matches_base(u32 offset, ulong base)
+{
+ /* Try to write different values to RAM at two addresses */
+ writel(0, base);
+ writel(0xaa55aa55, base + offset);
+ dsb();
+ /* Check if the same value is actually observed when reading back */
+ return readl(base) ==
+ readl(base + offset);
+}
+
+static void mctl_auto_detect_dram_size_rank(uint16_t socid, struct dram_para
*para, ulong base, struct rank_para *rank)
{
/* detect row address bits */
- para->page_size = 512;
- para->row_bits = 16;
- para->bank_bits = 2;
+ rank->page_size = 512;
+ rank->row_bits = 16;
+ rank->bank_bits = 2;
mctl_set_cr(socid, para);
- for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
-
Re: [U-Boot] [linux-sunxi] [PATCH v2 3/7] sunxi: H6: move LPDDR3 timing definition into separate file
>- &mctl_ctl->dramtmg[2]);
>- writel((tmrw << 20) | (tmrd << 12) | tmod, &mctl_ctl->dramtmg[3]);
>- writel((trcd << 24) | (tccd << 16) | (trrd << 8) | trp,
>- &mctl_ctl->dramtmg[4]);
>- writel((tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | tcke,
>- &mctl_ctl->dramtmg[5]);
>- /* Value suggested by ZynqMP manual and used by libdram */
>- writel((txp + 2) | 0x0202, &mctl_ctl->dramtmg[6]);
>- writel((txsfast << 24) | (txsabort << 16) | (txsdll << 8) | txs,
>- &mctl_ctl->dramtmg[8]);
>- writel(txsr, &mctl_ctl->dramtmg[14]);
>-
>- clrsetbits_le32(&mctl_ctl->init[0], (3 << 30), (1 << 30));
>- writel(0, &mctl_ctl->dfimisc);
>- clrsetbits_le32(&mctl_ctl->rankctl, 0xff0, 0x660);
>-
>- /*
>- * Set timing registers of the PHY.
>- * Note: the PHY is clocked 2x from the DRAM frequency.
>- */
>- writel((trrd << 25) | (tras << 17) | (trp << 9) | (trtp << 1),
>- &mctl_phy->dtpr[0]);
>- writel((tfaw << 17) | 0x28000400 | (tmrd << 1), &mctl_phy->dtpr[1]);
>- writel(((txs << 6) - 1) | (tcke << 17), &mctl_phy->dtpr[2]);
>- writel(((txsdll << 22) - (0x1 << 16)) | twtr_sa | (tcksrea << 8),
>- &mctl_phy->dtpr[3]);
>- writel((txp << 1) | (trfc << 17) | 0x800, &mctl_phy->dtpr[4]);
>- writel((trc << 17) | (trcd << 9) | (twtr << 1), &mctl_phy->dtpr[5]);
>- writel(0x0505, &mctl_phy->dtpr[6]);
>-
>- /* Configure DFI timing */
>- writel(tcl | 0x2000200 | (t_rdata_en << 16) | 0x808000,
>- &mctl_ctl->dfitmg0);
>- writel(0x040201, &mctl_ctl->dfitmg1);
>-
>- /* Configure PHY timing */
>- writel(tdinit0 | (tdinit1 << 20), &mctl_phy->ptr[3]);
>- writel(tdinit2 | (tdinit3 << 18), &mctl_phy->ptr[4]);
>-
>- /* set refresh timing */
>- writel((trefi << 16) | trfc, &mctl_ctl->rfshtmg);
>-}
>-
> static void mctl_sys_init(struct dram_para *para)
> {
> struct sunxi_ccm_reg * const ccm =
>@@ -735,12 +589,14 @@ unsigned long sunxi_dram_init(void)
> (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
> struct dram_para para = {
> .clk = CONFIG_DRAM_CLK,
>+#ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
> .type = SUNXI_DRAM_TYPE_LPDDR3,
> .ranks = 2,
> .cols = 11,
> .rows = 14,
> .dx_read_delays = SUN50I_H6_DX_READ_DELAYS,
> .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
>+#endif
> };
>
> unsigned long size;
>diff --git a/arch/arm/mach-sunxi/dram_timings/Makefile
>b/arch/arm/mach-sunxi/dram_timings/Makefile
>index 278a8a14cc..c3e74362eb 100644
>--- a/arch/arm/mach-sunxi/dram_timings/Makefile
>+++ b/arch/arm/mach-sunxi/dram_timings/Makefile
>@@ -1,3 +1,4 @@
> obj-$(CONFIG_SUNXI_DRAM_DDR3_1333)+= ddr3_1333.o
> obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o
> obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o
>+obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3)+= h6_lpddr3_1333.o
>diff --git a/arch/arm/mach-sunxi/dram_timings/h6_lpddr3_1333.c
>b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3_1333.c
>new file mode 100644
>index 00..1000860113
>--- /dev/null
>+++ b/arch/arm/mach-sunxi/dram_timings/h6_lpddr3_1333.c
>@@ -0,0 +1,132 @@
>+/*
>+ * sun50i H6 LPDDR3 timings
>+ *
>+ * (C) Copyright 2017 Icenowy Zheng
>+ *
>+ * SPDX-License-Identifier: GPL-2.0+
>+ */
>+
>+#include
>+#include
>+#include
>+
>+static u32 mr_lpddr3[12] = {
>+ 0x, 0x0043, 0x001a, 0x0001,
>+ 0x, 0x, 0x0048, 0x,
>+ 0x, 0x, 0x, 0x0003,
>+};
>+
>+/* TODO: flexible timing */
>+void mctl_set_timing_params(struct dram_para *para)
>+{
>+ struct sunxi_mctl_ctl_reg * const mctl_ctl =
>+ (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
>+ struct sunxi_mctl_phy_reg * const mctl_phy =
>+ (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
>+ int i;
>+
>+ u8 tccd = 2;
>+ u8 tfaw = max(ns_to_t(50), 4);
>+ u8 trrd = max(ns_to_t(10), 2);
>+ u8 trcd = max(ns_to_t(24), 2);
>+ u8 trc = ns_to_t(70);
>+ u8 txp = max(ns_to_t(8), 2);
>+
Re: [U-Boot] [linux-sunxi] [PATCH 2/6] sunxi: gpio: Enable support for H6 pin controller
于 2019年5月16日 GMT+08:00 上午9:26:29, Andre Przywara 写到:
>The Allwinner H6 pin controller is not really special, at least not
>when
>it comes to normal GPIO operation.
>
>Add the H6 compatible strings to the list of recognised strings, to
>make
>GPIOs work for H6 boards.
>
>Signed-off-by: Andre Przywara
>---
> drivers/gpio/sunxi_gpio.c | 2 ++
> 1 file changed, 2 insertions(+)
>
>diff --git a/drivers/gpio/sunxi_gpio.c b/drivers/gpio/sunxi_gpio.c
>index cbed8d42b7..780c39962a 100644
>--- a/drivers/gpio/sunxi_gpio.c
>+++ b/drivers/gpio/sunxi_gpio.c
>@@ -354,12 +354,14 @@ static const struct udevice_id sunxi_gpio_ids[] =
>{
> ID("allwinner,sun8i-v3s-pinctrl", a_all),
> ID("allwinner,sun9i-a80-pinctrl", a_all),
> ID("allwinner,sun50i-a64-pinctrl", a_all),
>+ ID("allwinner,sun50i-h6-pinctrl", a_all),
> ID("allwinner,sun6i-a31-r-pinctrl", l_2),
> ID("allwinner,sun8i-a23-r-pinctrl", l_1),
> ID("allwinner,sun8i-a83t-r-pinctrl",l_1),
> ID("allwinner,sun8i-h3-r-pinctrl", l_1),
> ID("allwinner,sun9i-a80-r-pinctrl", l_3),
> ID("allwinner,sun50i-a64-r-pinctrl",l_1),
>+ ID("allwinner,sun50i-h6-r-pinctrl", l_1),
Should be l_2 because H6 has PM bank.
> { }
> };
>
--
使用 K-9 Mail 发送自我的Android设备。
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Re: [U-Boot] [PATCH] sunxi: set PIO voltage to hardware-detected value on startup on H6
在 2019-04-24三的 13:44 +0800，Icenowy Zheng写道：
> The Allwinner H6 SoC has a register to set the PIO banks' voltage.
> When
> it mismatches the real voltage supplied to the VCC to the PIO supply,
> the PIO will work improperly.
>
> The PIO controller also has a register that contains the status of
> each
> VCC rail of the PIO supplies, and it has the same definition with the
> configuration register. so we can just copy the content of this
> register
> to the configuration register at startup, to ensure the configuration
> is
> correct at startup stage.
>
> Signed-off-by: Icenowy Zheng
> ---
> arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
> arch/arm/mach-sunxi/board.c| 9 +
> 2 files changed, 12 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
> b/arch/arm/include/asm/arch-sunxi/gpio.h
> index 40a3f845d0..a646ea6a3c 100644
> --- a/arch/arm/include/asm/arch-sunxi/gpio.h
> +++ b/arch/arm/include/asm/arch-sunxi/gpio.h
> @@ -73,6 +73,9 @@ struct sunxi_gpio_reg {
> struct sunxi_gpio_int gpio_int;
> };
>
> +#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
> +#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
> +
> #define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
> &((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
> &((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank)
> - SUNXI_GPIO_L])
> diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-
> sunxi/board.c
> index c6dd7b8e54..bd3b5d8303 100644
> --- a/arch/arm/mach-sunxi/board.c
> +++ b/arch/arm/mach-sunxi/board.c
> @@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map;
>
> static int gpio_init(void)
> {
> + __maybe__unused uint val;
Sorry for the extra _ here. Should be __maybe_unused.
> #if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
> #if defined(CONFIG_MACH_SUN4I) || \
> defined(CONFIG_MACH_SUN7I) || \
> @@ -139,6 +140,14 @@ static int gpio_init(void)
> #error Unsupported console port number. Please fix pin mux settings
> in board.c
> #endif
>
> +#ifdef CONFIG_MACH_SUN50I_H6
> + /* Update PIO power bias configuration by copy hardware
> detected value */
> + val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> + writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> + val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
> + writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
> +#endif
> +
> return 0;
> }
>
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[U-Boot] [PATCH] sunxi: set PIO voltage to hardware-detected value on startup on H6
The Allwinner H6 SoC has a register to set the PIO banks' voltage. When
it mismatches the real voltage supplied to the VCC to the PIO supply,
the PIO will work improperly.
The PIO controller also has a register that contains the status of each
VCC rail of the PIO supplies, and it has the same definition with the
configuration register. so we can just copy the content of this register
to the configuration register at startup, to ensure the configuration is
correct at startup stage.
Signed-off-by: Icenowy Zheng
---
arch/arm/include/asm/arch-sunxi/gpio.h | 3 +++
arch/arm/mach-sunxi/board.c| 9 +
2 files changed, 12 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h
b/arch/arm/include/asm/arch-sunxi/gpio.h
index 40a3f845d0..a646ea6a3c 100644
--- a/arch/arm/include/asm/arch-sunxi/gpio.h
+++ b/arch/arm/include/asm/arch-sunxi/gpio.h
@@ -73,6 +73,9 @@ struct sunxi_gpio_reg {
struct sunxi_gpio_int gpio_int;
};
+#define SUN50I_H6_GPIO_POW_MOD_SEL 0x340
+#define SUN50I_H6_GPIO_POW_MOD_VAL 0x348
+
#define BANK_TO_GPIO(bank) (((bank) < SUNXI_GPIO_L) ? \
&((struct sunxi_gpio_reg *)SUNXI_PIO_BASE)->gpio_bank[bank] : \
&((struct sunxi_gpio_reg *)SUNXI_R_PIO_BASE)->gpio_bank[(bank) -
SUNXI_GPIO_L])
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
index c6dd7b8e54..bd3b5d8303 100644
--- a/arch/arm/mach-sunxi/board.c
+++ b/arch/arm/mach-sunxi/board.c
@@ -65,6 +65,7 @@ struct mm_region *mem_map = sunxi_mem_map;
static int gpio_init(void)
{
+ __maybe__unused uint val;
#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
#if defined(CONFIG_MACH_SUN4I) || \
defined(CONFIG_MACH_SUN7I) || \
@@ -139,6 +140,14 @@ static int gpio_init(void)
#error Unsupported console port number. Please fix pin mux settings in board.c
#endif
+#ifdef CONFIG_MACH_SUN50I_H6
+ /* Update PIO power bias configuration by copy hardware detected value
*/
+ val = readl(SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+ val = readl(SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_VAL);
+ writel(val, SUNXI_R_PIO_BASE + SUN50I_H6_GPIO_POW_MOD_SEL);
+#endif
+
return 0;
}
--
2.18.1
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[U-Boot] [PATCH v4] sun50i: a64: Add Olimex A64-Teres-I board initial support
From: Jonas Smedegaard
Olimex A64-Teres-I board is a mainboard (the only one so far)
for Olimex Teres-I DIY laptop kit.
Key features:
- Allwinner A64 Cortex-A53
- Mali-400MP2 GPU
- AXP803 PMIC
- 2GB DDR3 RAM
- MicroSD Slot
- 16GB eMMC Flash
- eDP LCD display
- HDMI
- USB Host
- Battery management
- 5V DC power supply
- Certified Open Source Hardware (OSHW)
Works:
- i2C
- MMC/SD
- PWM backlight
Known broken:
- Internal keyboard (seems to be because the keyboard firmware loads a
bootloader first, and then disconnects bootloader and connect real
keyboard). External ones connected to the USB port work fine.
This patch enables support for the A64-Teres-I board to u-boot,
including enabling screen backlight (lacking from Linux device-tree).
Linux commit details about the sun50i-a64-teres-i.dts sync:
"arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins"
(sha1: d91ebb95b96c8840932dc3a10c9f243712555467)
Cosmetic warnings regarding whitespace and placement of SPDX notice for
dts file was ignored.
config and .dtsi file are adapted from pinebook files.
Tested-by: Jonas Smedegaard
Signed-off-by: Jonas Smedegaard
Signed-off-by: Icenowy Zheng
---
Changes for v4:
* Added Vbus activision for USB.
* Dropped links in the commit message.
* Dropped Jonas's personal tree in MAINTAINERS item.
* Moved board-related MAINTAINERS item to board/sunxi/MAINTAINERS.
Changes for v3:
* Use tags sun50i a64 (not sunxi)
* List key, working, and known broken features
* Reference upstream pages.
* Reference linux commit
Changes for v2:
* List Icenowy and Jonas as MAINTAINERS
* Add commit hash in linux tree for sun50i-a64-teres-i.dts
* Drop superfluous and unsupported Author: tag
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi | 41 +++
arch/arm/dts/sun50i-a64-teres-i.dts | 270
board/sunxi/MAINTAINERS | 6 +
configs/teres_i_defconfig | 22 ++
5 files changed, 341 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi
create mode 100644 arch/arm/dts/sun50i-a64-teres-i.dts
create mode 100644 configs/teres_i_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 0aee8dfde0..eabe9e1ae3 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -483,7 +483,8 @@ dtb-$(CONFIG_MACH_SUN50I) += \
sun50i-a64-pine64-plus.dtb \
sun50i-a64-pine64.dtb \
sun50i-a64-pinebook.dtb \
- sun50i-a64-sopine-baseboard.dtb
+ sun50i-a64-sopine-baseboard.dtb \
+ sun50i-a64-teres-i.dtb
dtb-$(CONFIG_MACH_SUN9I) += \
sun9i-a80-optimus.dtb \
sun9i-a80-cubieboard4.dtb \
diff --git a/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi
b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi
new file mode 100644
index 00..1a64b7d09c
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-teres-i-u-boot.dtsi
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2019 Vasily Khoruzhick
+ *
+ */
+
+#include "sunxi-u-boot.dtsi"
+
+/ {
+ vdd_bl: regulator@0 {
+ compatible = "regulator-fixed";
+ regulator-name = "bl-3v3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ enable-active-high;
+ };
+
+ backlight: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm 0 5 0>;
+ brightness-levels = <0 5 10 15 20 30 40 55 70 85 100>;
+ default-brightness-level = <2>;
+ enable-gpios = <&pio 3 23 GPIO_ACTIVE_HIGH>; /* PD23 */
+ power-supply = <&vdd_bl>;
+ };
+};
+
+/* The ANX6345 eDP-bridge is on i2c */
+&i2c0 {
+ anx6345: edp-bridge@38 {
+ compatible = "analogix,anx6345";
+ reg = <0x38>;
+ reset-gpios = <&pio 3 24 GPIO_ACTIVE_LOW>; /* PD24 */
+ status = "okay";
+ };
+};
+
+&pwm {
+ status = "okay";
+};
diff --git a/arch/arm/dts/sun50i-a64-teres-i.dts
b/arch/arm/dts/sun50i-a64-teres-i.dts
new file mode 100644
index 00..c455b24dd0
--- /dev/null
+++ b/arch/arm/dts/sun50i-a64-teres-i.dts
@@ -0,0 +1,270 @@
+/*
+ * Copyright (C) Harald Geyer
+ * based on sun50i-a64-olinuxino.dts by Jagan Teki
+ *
+ * SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ */
+
+/dts-v1/;
+
+#include "sun50i-a64.dtsi"
+
+#include
+#include
+#include
+
+/ {
+ model = "Olimex A64 Teres-I";
+ compatible = "olimex,a64-teres-i", "allwinner,sun50i-a64";
+
+ aliases {
+ serial0 = &uar
