Re: [PATCH v5 1/2] arm: mediatek: add mt8195 SOC support
Marcel Ziswiler 於 2023年11月11日 週六 上午4:24寫道： > [snip] > > Changes for v5: > > - Fix Copyright year to 2023. > > - Fix memory map in dram_init() to support 8GB onboard memory. > > - Add '#if !IS_ENABLED(CONFIG_SYSRESET)' with reset_cpu(). > > - Correct reset_cpu() function prototype. > > - rebase patchset to v2023-10.rc1 > > - Add missing arch/arm/mach-mediatek/mt8195/Kconfig. > > [snip] > > I finally got my hands on an EVK and gave this a try. However, I did not get > that far. This is with latest > downstream TF-A as I still struggle with upstream there as well. Any ideas? > > U-Boot 2024.01-rc1-00056-g5237f2b48bb (Nov 10 2023 - 15:33:34 +0100) > > CPU: MediaTek MT8195 > DRAM: 8 GiB > mtu3 usb@1120: clks of sts1 are not stable! > mtu3-peripheral ssusb@1120: device enable failed -110 > mtu3-peripheral ssusb@1120: mtu3 hw init failed:-110 > board_init: Cannot find USB device > initcall failed at call ffe46a50 (err=-110) > ### ERROR ### Please RESET the board ### > > Cheers > > Marcel I'm glad you've get a board and tested our patches. Currently we're busy on other tasks so the improvement to the patch v5 has been postponed. :~( These error is because the power supplement settings are in the later patches. Hence the clock might not stable for the cold boot up. You can just press the key on the board and warm reset it, the clock issue should be disappear. > mtu3-peripheral ssusb@1120: device enable failed -110 > mtu3-peripheral ssusb@1120: mtu3 hw init failed:-110 You can refer to the user guide and public domain code. https://mediatek.gitlab.io/aiot/doc/aiot-dev-guide/master/sw/yocto/get-started.html https://mediatek.gitlab.io/aiot/doc/aiot-dev-guide/master/sw/yocto/get-started/build-code/build-steps.html The latest u-boot code is here. https://gitlab.com/mediatek/aiot/bsp/u-boot/-/tree/mtk-v2022.10?ref_type=heads -- Best regards, Macpaul Lin
[PATCH v5 2/2] board: mediatek: add mt8195 demo board
From: Fabien Parent
Add mt8195-demo board support.
This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent
Signed-off-by: Amjad Ouled-Ameur
Signed-off-by: Macpaul Lin
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8195-demo.dts| 122
board/mediatek/mt8195/MAINTAINERS | 6 ++
board/mediatek/mt8195/Makefile | 3 +
board/mediatek/mt8195/README| 65 +++
board/mediatek/mt8195/mt8195_demo.c | 38 +
configs/mt8195_demo_defconfig | 99 ++
include/configs/mt8195.h| 46 +++
9 files changed, 381 insertions(+)
create mode 100644 arch/arm/dts/mt8195-demo.dts
create mode 100644 board/mediatek/mt8195/MAINTAINERS
create mode 100644 board/mediatek/mt8195/Makefile
create mode 100644 board/mediatek/mt8195/README
create mode 100644 board/mediatek/mt8195/mt8195_demo.c
create mode 100644 configs/mt8195_demo_defconfig
create mode 100644 include/configs/mt8195.h
Changes for v2 and v3:
- no change.
Changes for v4:
- Remove CONFIG_SYS_NS16550 related settings in mt8195.h.
Changes for v5:
- Fix Copyright year to 2023.
- Fix build error by adding 'CONFIG_TEXT_BASE' in defconfig.
- Add README for mt8195-demo board includes toolchain setting
'CROSS_COMPILE=aarch64-linux-gnu-'
- Fix 'CONFIG_EXTRA_ENV_SETTINGS' with 'CFG_EXTRA_ENV_SETTINGS'
according to checkpatch error.
- Update dram to 8GB size.
- dts
- Add optee and pcsi support in firmware section.
- mt8195_demo_defconfig
- enable I2C, DFU, GPT, MBR support
- enable some USB ethernet adaptors
- rebase patchset to v2023-10.rc1
diff --git a/MAINTAINERS b/MAINTAINERS
index 4d0f017e7e..454d3615f4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -396,6 +396,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/configs/mt8195.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index e66c32e268..d7104b77bf 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1342,6 +1342,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts
new file mode 100644
index 00..e4063cd143
--- /dev/null
+++ b/arch/arm/dts/mt8195-demo.dts
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Copyright (C) 2023 BayLibre SAS.
+ * Author: Macpaul Lin
+ * Author: Fabien Parent
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ memory@4000 {
+ /* 8GB */
+ device_type = "memory";
+ reg = <0 0x4000 2 0x>;
+ };
+
+ firmware: firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ psci: psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@5460 {
+ no-map;
+ reg = <0 0x5460 0x0 0x20>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+* +---+ 0x43e0_
+* | SHMEM 2MiB |
+* +---+ 0x43c0_
+* || TA_RAM 8MiB |
+* + TZDRAM +--+ 0x4340_
+* || TEE_RAM 2MiB |
+* +---+ 0x4320_
+*/
+ optee_reserved: optee@4320 {
+ no-map;
+ reg = <0 0x4320 0 0x00c0>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulat
[PATCH v5 1/2] arm: mediatek: add mt8195 SOC support
From: Fabien Parent
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent
Signed-off-by: Macpaul Lin
---
MAINTAINERS| 2 +
arch/arm/dts/mt8195.dtsi | 370 +
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile| 1 +
arch/arm/mach-mediatek/mt8195/Kconfig | 13 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 97 +++
7 files changed, 498 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Kconfig
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
Changes for v3:
- Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
Changes for v4:
- No change.
Changes for v5:
- Fix Copyright year to 2023.
- Fix memory map in dram_init() to support 8GB onboard memory.
- Add '#if !IS_ENABLED(CONFIG_SYSRESET)' with reset_cpu().
- Correct reset_cpu() function prototype.
- rebase patchset to v2023-10.rc1
- Add missing arch/arm/mach-mediatek/mt8195/Kconfig.
diff --git a/MAINTAINERS b/MAINTAINERS
index 47581cf6fb..4d0f017e7e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -369,8 +369,10 @@ ARM MEDIATEK
M: Ryder Lee
M: Weijie Gao
M: Chunfeng Yun
+M: Macpaul Lin
R: GSS_MTK_Uboot_upstream
S: Maintained
+F: arch/arm/dts/mt8195.dtsi
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 00..14cb28d008
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 MediaTek Inc.
+ * Copyright (C) 2023 BayLibre, SAS
+ * Author: Ben Ho
+ * Erin Lo
+ * Fabien Parent
+ * Macpaul Lin
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+
[PATCH v4 1/2] arm: mediatek: add mt8195 SOC support
From: Fabien Parent
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent
Signed-off-by: Macpaul Lin
---
MAINTAINERS| 2 +
arch/arm/dts/mt8195.dtsi | 370 +
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile| 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 ++
6 files changed, 469 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
Changes for v3:
- Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
Changes for v4:
- No change.
diff --git a/MAINTAINERS b/MAINTAINERS
index 75b27bc1cc..f2fe78dfc7 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -363,8 +363,10 @@ ARM MEDIATEK
M: Ryder Lee
M: Weijie Gao
M: Chunfeng Yun
+M: Macpaul Lin
R: GSS_MTK_Uboot_upstream
S: Maintained
+F: arch/arm/dts/mt8195.dtsi
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 00..bb6dead834
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Ben Ho
+ * Erin Lo
+ * Fabien Parent
+ * Macpaul Lin
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+
[PATCH v4 2/2] board: mediatek: add mt8195 demo board
From: Fabien Parent
Add mt8195-demo board support.
This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent
Signed-off-by: Amjad Ouled-Ameur
Signed-off-by: Macpaul Lin
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8195-demo.dts| 109
board/mediatek/mt8195/MAINTAINERS | 6 ++
board/mediatek/mt8195/Makefile | 3 +
board/mediatek/mt8195/mt8195_demo.c | 38 ++
configs/mt8195_demo_defconfig | 89 +++
include/configs/mt8195.h| 28 +++
8 files changed, 275 insertions(+)
create mode 100644 arch/arm/dts/mt8195-demo.dts
create mode 100644 board/mediatek/mt8195/MAINTAINERS
create mode 100644 board/mediatek/mt8195/Makefile
create mode 100644 board/mediatek/mt8195/mt8195_demo.c
create mode 100644 configs/mt8195_demo_defconfig
create mode 100644 include/configs/mt8195.h
Changes for v2 and v3:
- no change.
Changes for v4:
- Remove CONFIG_SYS_NS16550 related settings in mt8195.h
- Tested with u-boot/next.
diff --git a/MAINTAINERS b/MAINTAINERS
index f2fe78dfc7..3c7db798be 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -390,6 +390,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/configs/mt8195.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b3baaf4829..5ab10ac3db 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1278,6 +1278,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts
new file mode 100644
index 00..bd0952b248
--- /dev/null
+++ b/arch/arm/dts/mt8195-demo.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS.
+ * Author: Macpaul Lin
+ * Author: Fabien Parent
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x8000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@5460 {
+ no-map;
+ reg = <0 0x5460 0x0 0x20>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+* +---+ 0x43e0_
+* | SHMEM 2MiB |
+* +---+ 0x43c0_
+* || TA_RAM 8MiB |
+* + TZDRAM +--+ 0x4340_
+* || TEE_RAM 2MiB |
+* +---+ 0x4320_
+*/
+ optee_reserved: optee@4320 {
+ no-map;
+ reg = <0 0x4320 0 0x00c0>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&ssusb {
+ mediatek,force-vbus;
+ maximum-speed = "high-speed";
+ dr_mode = "perip
Re: [PATCH v3 2/2] board: mediatek: add mt8195 demo board
On 12/13/22 03:02, Tom Rini wrote: On Mon, Dec 12, 2022 at 01:53:05PM -0500, Tom Rini wrote: On Mon, Dec 12, 2022 at 11:53:04AM -0500, Tom Rini wrote: On Thu, Nov 10, 2022 at 03:34:53PM +0800, Macpaul Lin wrote: From: Fabien Parent Add mt8195-demo board support. This demo purpose board uses MediaTek's MT8195 SoC. Signed-off-by: Fabien Parent Signed-off-by: Amjad Ouled-Ameur Signed-off-by: Macpaul Lin [snip] +#include + +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE-4 +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SYS_NS16550_COM10x11002000 +#define CONFIG_SYS_NS16550_CLK 2600 This is unused, I believe. But when trying to build with current next I get: Error: Load Address must be set. Error: Bad parameters for image type Please rebase on top of current next and repost, thanks! Thanks for the information, will send patch v4 later. Sorry for the noise, this failed due to another patch that needs to be reworked instead. Welp, I should have finished my re-testing. The patch that broke phycore-rk3288 and I assumed broke this platform too, did not break this platform, there's still some other problem here. I've tested it on uboot/next and got the following result. $ make ARCH=arm phycore-rk3288_defconfig $ make ARCH=arm scripts/kconfig/conf --syncconfig Kconfig UPD include/config.h CFG u-boot.cfg GEN include/autoconf.mk GEN include/autoconf.mk.dep CFG spl/u-boot.cfg GEN spl/include/autoconf.mk UPD include/config/uboot.release UPD include/generated/version_autogenerated.h UPD include/generated/timestamp_autogenerated.h UPD include/generated/dt.h ENVCinclude/generated/env.txt ENVPinclude/generated/env.in ENVTinclude/generated/environment.h CC lib/asm-offsets.s cc1: error: bad value (‘generic-armv7-a’) for ‘-mtune=’ switch cc1: note: valid arguments to ‘-mtune=’ switch are: nocona core2 nehalem corei7 westmere sandybridge corei7-avx ivybridge core-avx-i haswell core-avx2 broadwell skylake skylake-avx512 bonnell atom silvermont slm knl intel x86-64 eden-x2 nano nano-1000 nano-2000 nano-3000 nano-x2 eden-x4 nano-x4 k8 k8-sse3 opteron opteron-sse3 athlon64 athlon64-sse3 athlon-fx amdfam10 barcelona bdver1 bdver2 bdver3 bdver4 znver1 btver1 btver2 generic scripts/Makefile.build:147: recipe for target 'lib/asm-offsets.s' failed make[1]: *** [lib/asm-offsets.s] Error 1 Makefile:1932: recipe for target 'prepare0' failed make: *** [prepare0] Error 2 I'm not sure should I test it on custodian tree: arm/next, too. This failure seems not related to the 2nd patch of mt8195-demo board. Thanks Macpaul Lin
[PATCH v3 1/2] arm: mediatek: add mt8195 SOC support
From: Fabien Parent
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent
Signed-off-by: Macpaul Lin
---
MAINTAINERS| 2 +
arch/arm/dts/mt8195.dtsi | 370 +
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile| 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 ++
6 files changed, 469 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
Changes for v3:
- Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cf99c1393..5528dd28c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -362,8 +362,10 @@ ARM MEDIATEK
M: Ryder Lee
M: Weijie Gao
M: Chunfeng Yun
+M: Macpaul Lin
R: GSS_MTK_Uboot_upstream
S: Maintained
+F: arch/arm/dts/mt8195.dtsi
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 00..33282d21d1
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Ben Ho
+ * Erin Lo
+ * Fabien Parent
+ * Macpaul Lin
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+
[PATCH v3 2/2] board: mediatek: add mt8195 demo board
From: Fabien Parent
Add mt8195-demo board support.
This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent
Signed-off-by: Amjad Ouled-Ameur
Signed-off-by: Macpaul Lin
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8195-demo.dts| 109
board/mediatek/mt8195/MAINTAINERS | 6 ++
board/mediatek/mt8195/Makefile | 3 +
board/mediatek/mt8195/mt8195_demo.c | 38 ++
configs/mt8195_demo_defconfig | 89 +++
include/configs/mt8195.h| 34 +
8 files changed, 281 insertions(+)
create mode 100644 arch/arm/dts/mt8195-demo.dts
create mode 100644 board/mediatek/mt8195/MAINTAINERS
create mode 100644 board/mediatek/mt8195/Makefile
create mode 100644 board/mediatek/mt8195/mt8195_demo.c
create mode 100644 configs/mt8195_demo_defconfig
create mode 100644 include/configs/mt8195.h
Changes for v2 and v3:
- no change.
diff --git a/MAINTAINERS b/MAINTAINERS
index 5528dd28c3..5aaeeb02cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -389,6 +389,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/configs/mt8195.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 791838733c..994f7ebcc0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1271,6 +1271,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts
new file mode 100644
index 00..bd0952b248
--- /dev/null
+++ b/arch/arm/dts/mt8195-demo.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS.
+ * Author: Macpaul Lin
+ * Author: Fabien Parent
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x8000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@5460 {
+ no-map;
+ reg = <0 0x5460 0x0 0x20>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+* +---+ 0x43e0_
+* | SHMEM 2MiB |
+* +---+ 0x43c0_
+* || TA_RAM 8MiB |
+* + TZDRAM +--+ 0x4340_
+* || TEE_RAM 2MiB |
+* +---+ 0x4320_
+*/
+ optee_reserved: optee@4320 {
+ no-map;
+ reg = <0 0x4320 0 0x00c0>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&ssusb {
+ mediatek,force-vbus;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
[PATCH v2 2/2] board: mediatek: add mt8195 demo board
From: Fabien Parent
Add mt8195-demo board support.
This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent
Signed-off-by: Amjad Ouled-Ameur
Signed-off-by: Macpaul Lin
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8195-demo.dts| 109
board/mediatek/mt8195/MAINTAINERS | 6 ++
board/mediatek/mt8195/Makefile | 3 +
board/mediatek/mt8195/mt8195_demo.c | 38 ++
configs/mt8195_demo_defconfig | 89 +++
include/configs/mt8195.h| 34 +
8 files changed, 281 insertions(+)
create mode 100644 arch/arm/dts/mt8195-demo.dts
create mode 100644 board/mediatek/mt8195/MAINTAINERS
create mode 100644 board/mediatek/mt8195/Makefile
create mode 100644 board/mediatek/mt8195/mt8195_demo.c
create mode 100644 configs/mt8195_demo_defconfig
create mode 100644 include/configs/mt8195.h
Changes for v2:
- no change.
diff --git a/MAINTAINERS b/MAINTAINERS
index 5528dd28c3..5aaeeb02cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -389,6 +389,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/configs/mt8195.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 791838733c..994f7ebcc0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1271,6 +1271,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts
new file mode 100644
index 00..bd0952b248
--- /dev/null
+++ b/arch/arm/dts/mt8195-demo.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS.
+ * Author: Macpaul Lin
+ * Author: Fabien Parent
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x8000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@5460 {
+ no-map;
+ reg = <0 0x5460 0x0 0x20>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+* +---+ 0x43e0_
+* | SHMEM 2MiB |
+* +---+ 0x43c0_
+* || TA_RAM 8MiB |
+* + TZDRAM +--+ 0x4340_
+* || TEE_RAM 2MiB |
+* +---+ 0x4320_
+*/
+ optee_reserved: optee@4320 {
+ no-map;
+ reg = <0 0x4320 0 0x00c0>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&ssusb {
+ mediatek,force-vbus;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
[PATCH v2 1/2] arm: mediatek: add mt8195 SOC support
From: Fabien Parent
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent
Signed-off-by: Macpaul Lin
---
MAINTAINERS| 2 +
arch/arm/dts/mt8195.dtsi | 370 +
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile| 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 ++
6 files changed, 469 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cf99c1393..5528dd28c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -362,8 +362,10 @@ ARM MEDIATEK
M: Ryder Lee
M: Weijie Gao
M: Chunfeng Yun
+M: Macpaul Lin
R: GSS_MTK_Uboot_upstream
S: Maintained
+F: arch/arm/dts/mt8195.dtsi
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 00..33282d21d1
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Ben Ho
+ * Erin Lo
+ * Fabien Parent
+ * Macpaul Lin
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+
Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
On 11/9/22 15:32, Macpaul Lin wrote:
On 11/9/22 10:07, Chunfeng Yun (云春峰) wrote:
On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote:
From: Fabien Parent
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent
Signed-off-by: Macpaul Lin
---
MAINTAINERS | 2 +
arch/arm/dts/mt8195.dtsi | 317
+
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 +++
6 files changed, 416 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
[deleted]
+ xhci3: xhci3@112b {
change node name as xhci? prefer to use the same name
Since there are other board manufacturers will use the
other HOST ports, like xhci1 or xhci2 with USB mass storage
function by their needs.
I'll add these 2 node in dtsi in next version.
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
remove "mac"
Will fix it in next version.
Dear Chunfeng,
Unfortunately, if we remove "mac" register here for HOST only node like
xhci3, the driver will complain about probing fail. Please check the
following log.
=> usb start
starting USB...
Bus xhci3@112b: xhci-mtk xhci3@112b: failed to get xHCI base address
probe failed, error -6
No working controllers found
I'll add "mac" back to HOST only nodes.
Thanks!
Macpaul Lin
Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
On 11/9/22 10:07, Chunfeng Yun (云春峰) wrote:
On Tue, 2022-11-08 at 11:21 +0800, Macpaul Lin wrote:
From: Fabien Parent
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73
and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and
hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent
Signed-off-by: Macpaul Lin
---
MAINTAINERS| 2 +
arch/arm/dts/mt8195.dtsi | 317
+
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile| 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 +++
6 files changed, 416 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
[deleted]
+ u3phy0: usb-phy@11f4 {
change node name as t-phy as u3phy3?
Got it, will fix it in next version.
+ compatible = "mediatek,generic-tphy-v2";
prefer to add "mediatek,mt8195-tphy" before generic's
Will fix it in next version.
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e4 0xe00>;
+ status = "okay";
+
+ u2port0: usb-phy@0 {
+ reg = <0 0x700>;
+ clocks = <&clk26m>,
+<&clk26m>;
+ clock-names = "ref", "da_ref";
these two clocks are optional, if sw can't control it, no need add it
here.
MediaTek's clock driver developer will upstream clock driver when
refactoring
work has been completed. Before clock driver is applied to trunk, we can use
clk26m only.
Will fix it in next version.
+ #phy-cells = <1>;
+ status = "okay";
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&clk26m>,
+<&clk26m>;
+ clock-names = "ref", "da_ref";
ditto
Will fix it in next version.
+ #phy-cells = <1>;
+ status = "okay";
+ };
+ };
+
+ usb: usb@1120 {
+ compatible ="mediatek,mt8195-mtu3",
"mediatek,mtu3";
+ reg = <0 0x1120 0 0x3e00>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
"mac" can be removed, the driver get it from the first child node
Will fix it in next version.
+ phys = <&u2port0 PHY_TYPE_USB2>;
+ clocks = <&clk26m>,
+<&clk26m>,
+<&clk26m>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ status = "disabled";
+
+ ssusb: ssusb@1120 {
+ compatible = "mediatek,ssusb";
+ reg = <0 0x1120 0 0x3e00>;
+ reg-names = "mac";
+ interrupts = ;
+ status = "disabled";
+ };
+
+ xhci0: xhci@1120 {
+ compatible = "mediatek,mtk-xhci";
+ reg = <0 0x1120 0 0x1000>;
+ reg-names = "mac";
+ interrupts = ;
+ clocks = <&clk26m>,
+<&clk26m>,
+<&clk26m>,
+<&clk26m>;
+ clock-names = "sys_ck", "xhci_ck",
"ref_ck", "mcu_ck";
+ status = "disabled";
+ };
+ };
+
+ u3phy3: t-phy@11c5 {
+ compatible = "mediatek,generic-t
Re: [PATCH 1/2] arm: mediatek: add mt8195 SOC support
On 11/8/22 15:57, Pali Rohár wrote: Hello! I'm not mediatek maintainer and if this patch series is not something important for me which should I review then please do not send me lot of these emails... As I would have time to review stuff which are important. I'm so sorry for bothering you and other developers. I've used ./scripts/get_maintainer.pl to check these 2 patches and found you all in the suggestion list. Result: "Pali Rohár" (added_lines:16/253=6%,removed_lines:12/76=16%) I'll remove Pali when I send next version. Who else don't want to be involved in these reviewing activities of MediaTek platforms, please let us know. [deleted] Thanks! Macpaul Lin
[PATCH 1/2] arm: mediatek: add mt8195 SOC support
From: Fabien Parent
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and
a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,
SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3
and LPDDR4 options.
Signed-off-by: Fabien Parent
Signed-off-by: Macpaul Lin
---
MAINTAINERS| 2 +
arch/arm/dts/mt8195.dtsi | 317 +
arch/arm/mach-mediatek/Kconfig | 13 +-
arch/arm/mach-mediatek/Makefile| 1 +
arch/arm/mach-mediatek/mt8195/Makefile | 3 +
arch/arm/mach-mediatek/mt8195/init.c | 81 +++
6 files changed, 416 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/mt8195.dtsi
create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile
create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 1cf99c1393..5528dd28c3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -362,8 +362,10 @@ ARM MEDIATEK
M: Ryder Lee
M: Weijie Gao
M: Chunfeng Yun
+M: Macpaul Lin
R: GSS_MTK_Uboot_upstream
S: Maintained
+F: arch/arm/dts/mt8195.dtsi
F: arch/arm/mach-mediatek/
F: arch/arm/include/asm/arch-mediatek/
F: board/mediatek/
diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi
new file mode 100644
index 00..d28b038d57
--- /dev/null
+++ b/arch/arm/dts/mt8195.dtsi
@@ -0,0 +1,317 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre, SAS
+ * Author: Ben Ho
+ * Erin Lo
+ * Fabien Parent
+ * Macpaul Lin
+ */
+
+#include
+#include
+#include
+#include
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x000>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x001>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x002>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x003>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <741>;
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a73";
+ reg = <0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ };
+
+ cpu5: cpu@101 {
+
[PATCH 2/2] board: mediatek: add mt8195 demo board
From: Fabien Parent
Add mt8195-demo board support.
This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent
Signed-off-by: Amjad Ouled-Ameur
Signed-off-by: Macpaul Lin
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt8195-demo.dts| 109
board/mediatek/mt8195/MAINTAINERS | 6 ++
board/mediatek/mt8195/Makefile | 3 +
board/mediatek/mt8195/mt8195_demo.c | 38 ++
configs/mt8195_demo_defconfig | 89 +++
include/configs/mt8195.h| 34 +
8 files changed, 281 insertions(+)
create mode 100644 arch/arm/dts/mt8195-demo.dts
create mode 100644 board/mediatek/mt8195/MAINTAINERS
create mode 100644 board/mediatek/mt8195/Makefile
create mode 100644 board/mediatek/mt8195/mt8195_demo.c
create mode 100644 configs/mt8195_demo_defconfig
create mode 100644 include/configs/mt8195.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 5528dd28c3..5aaeeb02cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -389,6 +389,7 @@ F: drivers/watchdog/mtk_wdt.c
F: drivers/net/mtk_eth.c
F: drivers/net/mtk_eth.h
F: drivers/reset/reset-mediatek.c
+F: include/configs/mt8195.h
F: tools/mtk_image.c
F: tools/mtk_image.h
F: tools/mtk_nand_headers.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 791838733c..994f7ebcc0 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1271,6 +1271,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt7986a-emmc-rfb.dtb \
mt7986b-emmc-rfb.dtb \
mt8183-pumpkin.dtb \
+ mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \
mt8516-pumpkin.dtb \
mt8518-ap1-emmc.dtb
diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts
new file mode 100644
index 00..bd0952b248
--- /dev/null
+++ b/arch/arm/dts/mt8195-demo.dts
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ * Copyright (C) 2022 BayLibre SAS.
+ * Author: Macpaul Lin
+ * Author: Fabien Parent
+ */
+
+/dts-v1/;
+
+#include
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 demo board";
+ compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0 0x4000 0 0x8000>;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ bl31_secmon_reserved: secmon@5460 {
+ no-map;
+ reg = <0 0x5460 0x0 0x20>;
+ };
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+* +---+ 0x43e0_
+* | SHMEM 2MiB |
+* +---+ 0x43c0_
+* || TA_RAM 8MiB |
+* + TZDRAM +--+ 0x4340_
+* || TEE_RAM 2MiB |
+* +---+ 0x4320_
+*/
+ optee_reserved: optee@4320 {
+ no-map;
+ reg = <0 0x4320 0 0x00c0>;
+ };
+ };
+
+ chosen {
+ stdout-path = &uart0;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+&watchdog {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ max-frequency = <2>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ cap-mmc-hw-reset;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_1p8v>;
+ non-removable;
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+};
+
+&ssusb {
+ mediatek,force-vbus;
+ maximum-speed = "high-speed";
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci3 {
+ status
[U-Boot] Change of NDS32 Custodian
Hi, Here is a short announcement about a change in the U-boot NDS32 custodian. I have no longer working in Andes Technology Corporation and cannot provide the community the best support on NDS32 architecture. Kuan-Yu Kuo (a.k.a. Ken Kuo) will be the next custodian of u-boot-nds32 branch. Thanks for the great support and co-working guide from Wolfgang, Tom, Po-Yu Chuang, Mike, Marek and many people. Thanks for your help which made the u-boot porting work of NDS32 architecture becomes the first open source mainline contribution of NDS32. The official custodian e-mail of NDS32 will be changed to "ub...@andestech.com". Ken will send the patchwork permission request, patches to MAINTAINERS file, and update the U-boot Wiki later. Thanks all! Best Regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] nds32: Enable FPU if the version of CPU supported
Hi Kuan-Yu, 2013/7/25 Kuan-Yu Kuo : > Some version of Andes core support FPU coprocessor, > if this is the case, and toolchain support FPU instruction set, > we should enable it at low level initialization time. > > Signed-off-by: Kuan-Yu Kuo > Cc: Macpaul Lin > --- > Change for v2: >- Add compile option to determine if current used toolchain support > FPU instruction or not. > > arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 26 ++ > arch/nds32/cpu/n1213/ag102/lowlevel_init.S | 26 ++ > 2 files changed, 52 insertions(+) > Applied to u-boot-nds32. Thanks! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32: Convert Makefiles to use COBJS-y style
Hi Kuan-Yu, 2013/7/25 Kuan-Yu Kuo : > Signed-off-by: Kuan-Yu Kuo > Cc: Macpaul Lin > --- > arch/nds32/cpu/n1213/Makefile |4 ++-- > arch/nds32/cpu/n1213/ag101/Makefile |8 > arch/nds32/cpu/n1213/ag102/Makefile |8 > arch/nds32/lib/Makefile |9 ++--- > board/AndesTech/adp-ag101/Makefile |6 +++--- > board/AndesTech/adp-ag101p/Makefile |6 +++--- > board/AndesTech/adp-ag102/Makefile |4 ++-- > 7 files changed, 24 insertions(+), 21 deletions(-) > Applied to u-boot-nds32. Thanks! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32: Update and with SPDX license identifiers
Hi Tom, 2013/7/24 Tom Rini : > Signed-off-by: Tom Rini > --- > arch/nds32/include/asm/io.h|4 +--- > arch/nds32/include/asm/setup.h |4 +--- > 2 files changed, 2 insertions(+), 6 deletions(-) > Applied to u-boot-nds32. Thanks! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request v2: u-boot-nds32
Hi Tom, Please pull the following patch from u-boot-nds32 into your tree. Thanks! The following changes since commit 62c175fbb8a0f9a926c88294ea9f7e88eb898f6c: Prepare v2013.07 (2013-07-23 07:58:13 -0400) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to c54fd3efa497876a33cc3c6e7df514ae53abc729: nds32: Enable FPU if the version of CPU supported (2013-07-25 16:54:19 +0800) Axel Lin (1): nds32: ag101/ag102: Fix setting lastdec and now values Gabor Juhos (6): nds32: introduce macros for bit manipulation mmc: ftsdc010_mci: fix build error if CONFIG_FTSDC010_SDIO is not defined block: constify sect_buf argument of ide_write_data pci: add prototype for pci_ftpci_init() function pci: move pci_ftpci100.h to include/faraday/ftpci100.h nds32: adp-ag102: use 'faraday/ftpci100.h' for pci_ftpci_init Tom Rini (1): nds32: Update and with SPDX license identifiers ken kuo (5): nds32: Enable two banks of SDRAM on Andes board nds32: Enable SDIO and EXT2 command support for Andes board nds32: Enable the function of passing parameters to Linux nds32: Convert Makefiles to use COBJS-y style nds32: Enable FPU if the version of CPU supported arch/nds32/cpu/n1213/Makefile| 4 ++-- arch/nds32/cpu/n1213/ag101/Makefile | 8 arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 32 - arch/nds32/cpu/n1213/ag101/timer.c | 7 --- arch/nds32/cpu/n1213/ag102/Makefile | 8 arch/nds32/cpu/n1213/ag102/lowlevel_init.S | 26 arch/nds32/cpu/n1213/ag102/timer.c | 7 --- arch/nds32/include/asm/io.h | 41 ++--- arch/nds32/include/asm/setup.h | 190 arch/nds32/lib/Makefile | 9 ++--- board/AndesTech/adp-ag101/Makefile | 6 +++--- board/AndesTech/adp-ag101/adp-ag101.c| 10 +- board/AndesTech/adp-ag101p/Makefile | 6 +++--- board/AndesTech/adp-ag101p/adp-ag101p.c | 10 +- board/AndesTech/adp-ag102/Makefile | 4 ++-- board/AndesTech/adp-ag102/adp-ag102.c| 3 +-- doc/driver-model/UDM-block.txt | 2 +- drivers/block/ftide020.c | 2 +- drivers/mmc/ftsdc010_mci.c | 6 +- drivers/pci/pci_ftpci100.c | 4 ++-- include/common.h | 1 + include/configs/adp-ag101.h | 19 +- include/configs/adp-ag101p.h | 18 - drivers/pci/pci_ftpci100.h => include/faraday/ftpci100.h | 2 ++ include/ide.h| 2 +- 25 files changed, 384 insertions(+), 43 deletions(-) create mode 100644 arch/nds32/include/asm/setup.h rename drivers/pci/pci_ftpci100.h => include/faraday/ftpci100.h (98%) -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Pull request: u-boot-nds32
Hi Tom 2013/7/24 Macpaul Lin : > Hi Tom, > > Please pull the following patch from u-boot-nds32 into your tree. > Thanks! > Because of there are new patches and compile error fix, please ignore this pull-request. I'll review those new patches and resend this pull-request later. Thanks! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32: Enable FPU if the version of CPU supported
Hi Kuan-Yu, 2013/7/18 : > Hi Kuan-Yu Kuo, > ... >> +enable_fpu: >> + mfsr$r0, $CPU_VER /* enable FPU if it exists */ >> + srli$r0, $r0, 3 >> + andi$r0, $r0, 1 >> + beqz$r0, 1f /* skip if >> no COP */ >> + mfsr$r0, $FUCOP_EXIST >> + srli$r0, $r0, 31 >> + beqz$r0, 1f /* skip if >> no FPU */ >> + mfsr$r0, $FUCOP_CTL >> + ori $r0, $r0, 1 >> + mtsr$r0, $FUCOP_CTL WARNING: line over 80 characters #53: FILE: arch/nds32/cpu/n1213/ag101/lowlevel_init.S:249: + beqz$r0, 1f /* skip if no COP */ WARNING: line over 80 characters #56: FILE: arch/nds32/cpu/n1213/ag101/lowlevel_init.S:252: + beqz$r0, 1f /* skip if no FPU */ WARNING: line over 80 characters #93: FILE: arch/nds32/cpu/n1213/ag102/lowlevel_init.S:304: + beqz$r0, 1f /* skip if no COP */ WARNING: line over 80 characters #96: FILE: arch/nds32/cpu/n1213/ag102/lowlevel_init.S:307: + beqz$r0, 1f /* skip if no FPU */ 1. Please clean up this patch and check with checkpatch.pl then resend it. > > There are two kinds of toolchain in Andes architecture, one is FPU supported > and the other is not, for the latter one, there is no need to enable FPU even > if the processor supports it. > This code snippet only useful for the toolchain that will generate FPU > instructions, so add compile option to determine Andes predefined macros > would be better. > For example: > #if defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP) > > Andes Technology Corporation 2. According to the official suggestion from Andes Technology Corporation, your patch will be better to reorganized with these macro definitions to help the toolchain to distinguish the differences. But! The most users cannot distinguish the differences of these toolchain-with-SoC combination, hence I think to keep the most Error-Proof protection will be better. Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] nds32: Add bitwise operation macros for drivers
Hi Kuan-Yu, 2013/7/24 Macpaul Lin : > Hi Kuan-Yu, > > 2013/6/8 Kuan-Yu Kuo : >> Add clrbits_* setbits_* clrsetbits_* for peripheral drivers >> >> Signed-off-by: Kuan-Yu Kuo >> Cc: Macpaul Lin >> --- >> arch/nds32/include/asm/io.h | 38 ++ >> 1 file changed, 38 insertions(+) >> > > Applied to u-boot-nds32/master > Thanks for your help! > Sorry for correcting this reply! This patch you've sent was identical to commit "bea2868f5e5f994db3f6cf23a6111cfd6ac79fc3" Gabor Juhos, "nds32: introduce macros for bit manipulation" Since Gabor sent this patch earlier, so I take his patch. Thanks for both of your work! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/4] nds32: Enable the function of passing parameters to Linux
Hi Kuan-Yu, 2013/6/8 Kuan-Yu Kuo : > Add a header file, setup.h, which copy from Linux source code, > this file contain structures are used to pass initialisation parameters > to Linux. Enable this function on adp-ag101/adp-ag101p target > > Signed-off-by: Kuan-Yu Kuo > Cc: Macpaul Lin Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/4] nds32: Enable SDIO and EXT2 command support for Andes board
Hi Kuan-Yu, 2013/6/8 Kuan-Yu Kuo : > Signed-off-by: Kuan-Yu Kuo > Cc: Macpaul Lin Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/4] nds32: Add bitwise operation macros for drivers
Hi Kuan-Yu, 2013/6/8 Kuan-Yu Kuo : > Add clrbits_* setbits_* clrsetbits_* for peripheral drivers > > Signed-off-by: Kuan-Yu Kuo > Cc: Macpaul Lin > --- > arch/nds32/include/asm/io.h | 38 ++ > 1 file changed, 38 insertions(+) > Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/4] nds32: Enable two banks of SDRAM on Andes board
Hi Kuan-YU 2013/6/8 Kuan-Yu Kuo : > The original adp-ag101/adp-ag101p initialize only one bank(64MB) > by default at boot time, but it is not enough for some application, > so increasing to two banks(128M). > > Signed-off-by: Kuan-Yu Kuo > Cc: Macpaul Lin Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32: ag101/ag102: Fix setting lastdec and now values
Hi Axel, 2013/7/8 Axel Lin : > The timer3 counter unit for lastdesc and now values are inconsistent in > current > code. The unit of "readl(&tmr->timer3_counter) / (CONFIG_SYS_CLK_FREQ / 2)" is > second. However, CONFIG_SYS_HZ is defined as 1000 in board config file. > This means the accuracy of "lastdec" and "now" should be in millisecond, > thus fix the equation to set lastdec and now variables accordingly. > > Signed-off-by: Axel Lin > --- > Hi Kuan-Yu, > This change is based on your suggestion. > I don't have this hardware, can you test if this patch works? > > Thanks, Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 6/6] nds32: adp-ag102: use 'faraday/ftpci100.h' for pci_ftpci_init
Hi Gabor, 2013/5/26 Gabor Juhos : > Due to improper external function declaration, > building U-Boot for the adp-ag102 board shows > this warning: > > adp-ag102.c: In function 'pci_init_board': > adp-ag102.c:95: warning: function declaration isn't a prototype > > Include the 'faraday/ftpci100.h' header which > provides the proper declaration and remove the > local declaration to get rid of the warning. > > Compile tested only. Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 5/6] pci: move pci_ftpci100.h to include/faraday/ftpci100.h
Hi Gabor, 2013/5/26 Gabor Juhos : > Even though the header files is used only by the > pci_ftpci100 driver, it contains declaration for > a function which is used by external code. > > Move the header file to a common location which > lets external code use it. > > Compile tested only. Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 4/6] pci: add prototype for pci_ftpci_init() function
Hi Gabor, 2013/5/26 Gabor Juhos : > The pci_ftpci_init() function is implemented > in 'drivers/pci/pci_ftpci100.c' however it is > always called by external code. > > Add function declaration into ftpci100.h to > make it visible for external code. > > Compile tested only. > Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/6] block: constify sect_buf argument of ide_write_data
Hi Gabor, 2013/5/26 Gabor Juhos : > Add a const keyword to the sect_buf argument of > ide_write_data to fix the following warning: > Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/6] nds32: introduce macros for bit manipulation
Hi Gabor, 2013/5/26 Gabor Juhos : > U-Boot does not compile for the adp-ag101 boards since > commit f6c3b34697bf8bf05cb4e81c2fd3cadb9a98daea (mmc: > update Faraday FTSDC010 for rw performance) > > The driver assumes that the bit manipulation macros > are provided by all architectures. This is not the > case for nds32 and it causes a build error like this: > Applied to u-boot-nds32/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-nds32
Hi Tom, Please pull the following patch from u-boot-nds32 into your tree. Thanks! The following changes since commit 62c175fbb8a0f9a926c88294ea9f7e88eb898f6c: Prepare v2013.07 (2013-07-23 07:58:13 -0400) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to 4fc967051396e8e82138c65fd65a353f73e51b89: nds32: ag101/ag102: Fix setting lastdec and now values (2013-07-24 11:50:28 +0800) Axel Lin (1): nds32: ag101/ag102: Fix setting lastdec and now values Gabor Juhos (6): nds32: introduce macros for bit manipulation mmc: ftsdc010_mci: fix build error if CONFIG_FTSDC010_SDIO is not defined block: constify sect_buf argument of ide_write_data pci: add prototype for pci_ftpci_init() function pci: move pci_ftpci100.h to include/faraday/ftpci100.h nds32: adp-ag102: use 'faraday/ftpci100.h' for pci_ftpci_init ken kuo (3): nds32: Enable two banks of SDRAM on Andes board nds32: Enable SDIO and EXT2 command support for Andes board nds32: Enable the function of passing parameters to Linux arch/nds32/cpu/n1213/ag101/lowlevel_init.S | 6 +- arch/nds32/cpu/n1213/ag101/timer.c | 7 --- arch/nds32/cpu/n1213/ag102/timer.c | 7 --- arch/nds32/include/asm/io.h | 37 + arch/nds32/include/asm/setup.h | 192 board/AndesTech/adp-ag101/adp-ag101.c| 10 - board/AndesTech/adp-ag101p/adp-ag101p.c | 10 - board/AndesTech/adp-ag102/adp-ag102.c| 3 +-- doc/driver-model/UDM-block.txt | 2 +- drivers/block/ftide020.c | 2 +- drivers/mmc/ftsdc010_mci.c | 6 +- drivers/pci/pci_ftpci100.c | 4 ++-- include/common.h | 1 + include/configs/adp-ag101.h | 19 - include/configs/adp-ag101p.h | 18 - drivers/pci/pci_ftpci100.h => include/faraday/ftpci100.h | 2 ++ include/ide.h| 2 +- 17 files changed, 309 insertions(+), 19 deletions(-) create mode 100644 arch/nds32/include/asm/setup.h rename drivers/pci/pci_ftpci100.h => include/faraday/ftpci100.h (98%) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-nds32
Hi Tom, Please pull the following patch from u-boot-nds32 into your tree. Thanks! The following changes since commit 7e7501f4bb0d550fbc6960e7e2fb2bc84d9795cf: Merge branch 'master' of git://www.denx.de/git/u-boot-mmc (2013-05-07 10:09:00 -0400) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to fe8e4dbad1d31c452af3fbabba21e72b210381b3: nds32: Use sections header to obtain link symbols (2013-05-08 12:38:10 +0800) Kuan-Yu Kuo (1): nds32: Use sections header to obtain link symbols arch/nds32/include/asm/u-boot-nds32.h | 5 - arch/nds32/lib/board.c| 3 ++- 2 files changed, 2 insertions(+), 6 deletions(-) -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32: Use sections header to obtain link symbols
Hi Ken, 2013/4/24 ken kuo > > From: Kuan-Yu Kuo > > Include this header to get access to link symbols, which are otherwise > removed. > > Signed-off-by: Kuan-Yu Kuo > Cc: Macpaul Lin This link script fix has been applied to u-boot-nds32.git. Thanks! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32: Add a basic errno.h
Hi Simon, 2013/1/6 Simon Glass > > This is available on other architectures, and nds32 will start to break > without it as code starts to use error numbers more. > > Signed-off-by: Simon Glass > --- > arch/nds32/include/asm/errno.h |1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > create mode 100644 arch/nds32/include/asm/errno.h > This bug fix has been applied to u-boot-nds32.git/master Thanks for your help! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [GIT PULL] Please pull u-boot-nds32/master into your branch
Hi Tom, Please pull a bug fix for the missing of including header which cause broken on NDS32 (board adp-ag102). Thanks, Macpaul Lin The following changes since commit ea6bd08b7717bf0d3f69ad9f016bf3b03b3eaf16: nds32: Add a basic errno.h (2013-02-18 15:29:07 +0800) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to ea6bd08b7717bf0d3f69ad9f016bf3b03b3eaf16: nds32: Add a basic errno.h (2013-02-18 15:29:07 +0800) -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] How to add new device driver from Linux driver source
Hi Jack, 2013/1/25 "Chen, Jack C.W. (陳志偉 IES)" > Dears, > > Our system used u-boot as the boot code, and it would be like to support > SD card. > > We get the SD controller driver from vendor, it is linux source code. > What platform do you working with? Does the boot code and the peripherals are already in u-boot main line source tree? If the platform is already supported in mainline u-boot would be better for you to port this SD controller driver in mainline u-boot. People will be easier to review and test your driver on this platform and give you some comment. So if the platform is already supported in mainline u-boot, please send the patch of this SD card driver (in GPL way) then to add the extensibility of this platform in u-boot project. And if your driver is modified from Linux driver, please add the comment about where the Linux source and what version that you modified from. > Do you have any comments or documents about how to port this source code > into u-boot source tree. > > We would like to build it and try if this can work or should do modify on > this source. > > You can start by checking the definitions, data structures, and APIs in include/mmc.h. Hope we can see your patch of this SD driver, soon. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32: Add a basic errno.h
Hi Simon, 2013/1/6 Simon Glass > This is available on other architectures, and nds32 will start to break > without it as code starts to use error numbers more. > > +++ b/arch/nds32/include/asm/errno.h > @@ -0,0 +1 @@ > +#include ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] nds32: Change macro from BOARD_LATE_INIT to CONFIG_BOARD_LATE_INIT
Hi Tom, 2012/10/17 Tom Rini > On Tue, Apr 17, 2012 at 04:41:14PM -, Nobuhiro Iwamatsu wrote: > > > With almost all the architecture and board BOARD_LATE_INIT does not use. > > CONFIG_BOARD_LATE_INIT is used instead. > > This changed CONFIG_BOARD_LATE_INIT from BOARD_LATE_INIT. > > > > Signed-off-by: Nobuhiro Iwamatsu > > CC: Macpaul Lin > > Modified to apply again, applied to u-boot/master, thanks! > > This was strange. I didn' found the original patch in my mailbox of macp...@andestech.com. I guess I'd better to ask IT to figure out the problem. Anyway. Thanks Tom and Nobuhiron. :) -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-nds32
Dear Wolfgang, Please pull the following 3 patches from u-boot-nds32 into your tree. Thanks! Macpaul Lin. The following changes since commit 4d3c95f5ea7c737a21cd6b9c59435ee693b3f127: zfs: Add ZFS filesystem support (2012-08-09 23:42:20 +0200) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to 11a05fbde76765e4b256b86aa3b82ea3184e3c08: nds32: fix unused pmu_init warning (2012-08-11 00:43:28 +0800) Mike Frysinger (3): nds32: drop bi_enetaddr from global data nds32: delete unused local variable nds32: fix unused pmu_init warning arch/nds32/include/asm/u-boot.h | 1 - arch/nds32/lib/board.c | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 3/3] nds32: fix unused pmu_init warning
Hi Mike, 2012/8/7 Mike Frysinger : > Fixes the build-time warning: > board.c: At top level: > board.c:106: warning: 'pmu_init' defined but not used > > This makes the ifdef logic at the call site match the logic at the > function definition. > > Signed-off-by: Mike Frysinger Applied to u-boot-nds32.git/master Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 2/3] nds32: delete unused local variable
Hi Mike, 2012/8/7 Mike Frysinger : > Fixes the build-time warning: > board.c: In function 'board_init_r': > board.c:304: warning: unused variable 's' > > Signed-off-by: Mike Frysinger Applied to u-boot-nds32.git/master Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/3] nds32: drop bi_enetaddr from global data
Hi Mike, 2012/8/7 Mike Frysinger : > Nothing is using this, so punt it from the gd. Seems to just be a copy > & paste wart from the initial port. > > Signed-off-by: Mike Frysinger > --- > arch/nds32/include/asm/u-boot.h |1 - > 1 file changed, 1 deletion(-) Applied to u-boot-nds32.git/master Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-nds32
Dear Wolfgang, Please pull the following 1 patch from u-boot-nds32 into your tree. Thanks! Macpaul Lin. The following changes since commit 3ec81d758c09d6887a77a1b1259d044a2905bc8e: Merge branch 'master' of git://git.denx.de/u-boot-usb (2012-07-20 09:12:43 +0200) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master for you to fetch changes up to 8d732840ba1cd4d41c12242ba07f1cf58b6429bf: nds32: split common cache access from cpu into lib (2012-07-20 23:55:52 +0800) -------- Macpaul Lin (1): nds32: split common cache access from cpu into lib arch/nds32/cpu/n1213/ag101/cpu.c | 112 arch/nds32/cpu/n1213/ag102/cpu.c | 112 arch/nds32/lib/Makefile | 2 +- arch/nds32/lib/cache.c | 157 +++ 4 files changed, 158 insertions(+), 225 deletions(-) create mode 100644 arch/nds32/lib/cache.c ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] nds32: split common cache access from cpu into lib
Hi Macpaul, 2012/7/17 Macpaul Lin > This commit does the following updates. > 1. Split the common cache access from cpu.c into lib folder. > 2. Rename the following cache api to adapt common.h > - dcache_flush_rang -> flush_dcache_rang > - icache_inval_range -> invalidate_icache_range > 3. Add invalidate_dcache_range > > Signed-off-by: Macpaul Lin > --- > Changes for v2: > - flush_dcache_range: merge two asm calls into a single >asm volatile() block. > - Replace __asm__ __volatile__ block into asm volatile() > This commit has been applied into u-boot-nds32/master Thanks! ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32: split common cache access from cpu into lib
Hi Marek and Mike, > sounds like we should rip all this cache stuff out of common.h and into > > like cache.h so we can document the API expectations. i think Wolfgang > > was against this before, but maybe that was just creating a header for > one > > specific cache macro and not all cache stuff ? > > Certainly this sounds good. We'd also be able to add some nice > instrumentation > while at that, to detect problematic cases with DEBUG enabled or so. The > cache > stuff is starting to get really crazy. > > Best regards, > Marek Vasut > Since this discussion hasn't been finished, and we haven't decide the final action about the new policy about cache.h and common.h. I'd like to pick this patch v2 for the coming release for fixing build error for board adp-ag102. What do you think? :-) -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32: split common cache access from cpu into lib
Hi Mike
2012/7/19 Mike Frysinger
> On Sunday 15 July 2012 04:12:45 Marek Vasut wrote:
> > Dear Macpaul Lin,
> > > +void flush_cache(unsigned long addr, unsigned long size)
> > > +{
> > > + flush_dcache_range(addr, addr + size);
> > > + invalidate_icache_range(addr, addr + size);
> >
> > You probably want to flush dcache in here and that's it.
>
> i don't think so ... i think that's what flush_dcache_range() is for. and
> our
> common/cmd_*.c files assume that flush_cache() will invalidate icache (see
> the
> bootm/load funcs that write executable content into memory and then flush
> the
> regions).
> -mike
>
Thanks for clarification.
The patch v2 I've submitted 2 days ago didn't add a dcache flush here. :-)
--
Best regards,
Macpaul Lin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] nds32: split common cache access from cpu into lib
This commit does the following updates.
1. Split the common cache access from cpu.c into lib folder.
2. Rename the following cache api to adapt common.h
- dcache_flush_rang -> flush_dcache_rang
- icache_inval_range -> invalidate_icache_range
3. Add invalidate_dcache_range
Signed-off-by: Macpaul Lin
---
Changes for v2:
- flush_dcache_range: merge two asm calls into a single
asm volatile() block.
- Replace __asm__ __volatile__ block into asm volatile()
arch/nds32/cpu/n1213/ag101/cpu.c | 112 ---
arch/nds32/cpu/n1213/ag102/cpu.c | 112 ---
arch/nds32/lib/Makefile |2 +-
arch/nds32/lib/cache.c | 157 ++
4 files changed, 158 insertions(+), 225 deletions(-)
create mode 100644 arch/nds32/lib/cache.c
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
index c2636b1..a9991e7 100644
--- a/arch/nds32/cpu/n1213/ag101/cpu.c
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -82,115 +82,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
/*NOTREACHED*/
}
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
- if (cache == ICACHE)
- return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
- >> ICM_CFG_OFF_ISZ) - 1);
- else
- return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
- >> DCM_CFG_OFF_DSZ) - 1);
-}
-
-void dcache_flush_range(unsigned long start, unsigned long end)
-{
- unsigned long line_size;
-
- line_size = CACHE_LINE_SIZE(DCACHE);
-
- while (end > start) {
- __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
- __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
- start += line_size;
- }
-}
-
-void icache_inval_range(unsigned long start, unsigned long end)
-{
- unsigned long line_size;
-
- line_size = CACHE_LINE_SIZE(ICACHE);
- while (end > start) {
- __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
- start += line_size;
- }
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
- dcache_flush_range(addr, addr + size);
- icache_inval_range(addr, addr + size);
-}
-
-void icache_enable(void)
-{
- __asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "ori$p0, $p0, 0x01\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-void icache_disable(void)
-{
- __asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "li $p1, ~0x01\n\t"
- "and$p0, $p0, $p1\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-int icache_status(void)
-{
- int ret;
-
-__asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "andi %0, $p0, 0x01\n\t"
- : "=r" (ret)
- :
- : "memory"
- );
-
-return ret;
-}
-
-void dcache_enable(void)
-{
-__asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "ori$p0, $p0, 0x02\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-void dcache_disable(void)
-{
-__asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "li $p1, ~0x02\n\t"
- "and$p0, $p0, $p1\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-int dcache_status(void)
-{
- int ret;
-
- __asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "andi %0, $p0, 0x02\n\t"
- : "=r" (ret)
- :
- : "memory"
-);
-
-return ret;
-}
diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c
index ed88b52..252b69d 100644
--- a/arch/nds32/cpu/n1213/ag102/cpu.c
+++ b/arch/nds32/cpu/n1213/ag102/cpu.c
@@ -81,115 +81,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
/*NOTREACHED*/
}
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
- if (cache == ICACHE)
- return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
- >> ICM_CFG_OFF_ISZ) - 1);
- else
- return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
- >> DCM_CFG_OFF_DSZ) - 1);
-}
-
-void dcache_f
Re: [U-Boot] [PATCH] nds32: split common cache access from cpu into lib
Hi Marek,
2012/7/15 Marek Vasut :
> Dear Macpaul Lin,
>
>> This commit does the following updates.
>> 1. Split the common cache access from cpu.c into lib folder.
>> 2. Rename the following cache api to adapt common.h
>> - dcache_flush_rang -> flush_dcache_rang
>> - icache_inval_range -> invalidate_icache_range
>> 3. Add invalidate_dcache_range
>
> So basically this connects it to standard cache api?
Yes! Basically this is compatible with all nds32 cpu family if they
have cache inside.
The cache is configurable by the customer if they used softcore FPGA.
This API could help them to figure out the hardware configuration in
software level.
> [...]
>> diff --git a/arch/nds32/lib/cache.c b/arch/nds32/lib/cache.c
> [...]
>> +static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
>> +{
>> + if (cache == ICACHE)
>> + return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
>> + >> ICM_CFG_OFF_ISZ) - 1);
>
> These crazy macros can be probably done easier and can share some code maybe?
> Maybe not though, I dunno, just a thought.
>
The macro GET_ICM_CFG() is inside arch/nds32/include/cache.h
#define DEFINE_GET_SYS_REG(reg) \
static inline unsigned long GET_##reg(void) \
Since the assembly is really long, rewrite them into macros should be
easier to maintain and read.
I'll prefer not to modify this function to call CACHE_LINE_SIZE.
>> +void flush_dcache_range(unsigned long start, unsigned long end)
>> + while (end > start) {
>> + __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
>> + __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
>
> You probably want to do those two calls in one asm volatile () block. And this
> too ... use "asm volatile()" and not "__asm__ volatile" or "asm __volatile__"
> and similar combinations of these, just a nit ;-)
Ok, it will be fixed. :)
>> +void flush_cache(unsigned long addr, unsigned long size)
>> +{
>> + flush_dcache_range(addr, addr + size);
>> + invalidate_icache_range(addr, addr + size);
>
> You probably want to flush dcache in here and that's it.
>
>> +}
>> +
>> +void icache_enable(void)
>> +{
>> + __asm__ __volatile__ (
>
> See my nit above for the rest ;-) But all in all it's good, we should be
> applying this around V2-V3 of this patch, for the -next release. Thanks for
> your
> patch!
It looks like this fix cannot be checkin before this coming rc1 or rc2.
But I think it is okay for users to wait until the -next release. :)
--
Best regards,
Macpaul Lin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] nds32: split common cache access from cpu into lib
This commit does the following updates.
1. Split the common cache access from cpu.c into lib folder.
2. Rename the following cache api to adapt common.h
- dcache_flush_rang -> flush_dcache_rang
- icache_inval_range -> invalidate_icache_range
3. Add invalidate_dcache_range
Signed-off-by: Macpaul Lin
---
arch/nds32/cpu/n1213/ag101/cpu.c | 112 --
arch/nds32/cpu/n1213/ag102/cpu.c | 112 --
arch/nds32/lib/Makefile | 2 +-
arch/nds32/lib/cache.c | 145 +++
4 files changed, 146 insertions(+), 225 deletions(-)
create mode 100644 arch/nds32/lib/cache.c
diff --git a/arch/nds32/cpu/n1213/ag101/cpu.c b/arch/nds32/cpu/n1213/ag101/cpu.c
index c2636b1..a9991e7 100644
--- a/arch/nds32/cpu/n1213/ag101/cpu.c
+++ b/arch/nds32/cpu/n1213/ag101/cpu.c
@@ -82,115 +82,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
/*NOTREACHED*/
}
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
- if (cache == ICACHE)
- return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
- >> ICM_CFG_OFF_ISZ) - 1);
- else
- return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
- >> DCM_CFG_OFF_DSZ) - 1);
-}
-
-void dcache_flush_range(unsigned long start, unsigned long end)
-{
- unsigned long line_size;
-
- line_size = CACHE_LINE_SIZE(DCACHE);
-
- while (end > start) {
- __asm__ volatile ("\n\tcctl %0, L1D_VA_WB" : : "r"(start));
- __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL" : : "r"(start));
- start += line_size;
- }
-}
-
-void icache_inval_range(unsigned long start, unsigned long end)
-{
- unsigned long line_size;
-
- line_size = CACHE_LINE_SIZE(ICACHE);
- while (end > start) {
- __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL" : : "r"(start));
- start += line_size;
- }
-}
-
-void flush_cache(unsigned long addr, unsigned long size)
-{
- dcache_flush_range(addr, addr + size);
- icache_inval_range(addr, addr + size);
-}
-
-void icache_enable(void)
-{
- __asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "ori$p0, $p0, 0x01\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-void icache_disable(void)
-{
- __asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "li $p1, ~0x01\n\t"
- "and$p0, $p0, $p1\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-int icache_status(void)
-{
- int ret;
-
-__asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "andi %0, $p0, 0x01\n\t"
- : "=r" (ret)
- :
- : "memory"
- );
-
-return ret;
-}
-
-void dcache_enable(void)
-{
-__asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "ori$p0, $p0, 0x02\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-void dcache_disable(void)
-{
-__asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "li $p1, ~0x02\n\t"
- "and$p0, $p0, $p1\n\t"
- "mtsr $p0, $mr8\n\t"
- "isb\n\t"
- );
-}
-
-int dcache_status(void)
-{
- int ret;
-
- __asm__ __volatile__ (
- "mfsr $p0, $mr8\n\t"
- "andi %0, $p0, 0x02\n\t"
- : "=r" (ret)
- :
- : "memory"
-);
-
-return ret;
-}
diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c
index ed88b52..252b69d 100644
--- a/arch/nds32/cpu/n1213/ag102/cpu.c
+++ b/arch/nds32/cpu/n1213/ag102/cpu.c
@@ -81,115 +81,3 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *
const argv[])
/*NOTREACHED*/
}
-
-static inline unsigned long CACHE_LINE_SIZE(enum cache_t cache)
-{
- if (cache == ICACHE)
- return 8 << (((GET_ICM_CFG() & ICM_CFG_MSK_ISZ) \
- >> ICM_CFG_OFF_ISZ) - 1);
- else
- return 8 << (((GET_DCM_CFG() & DCM_CFG_MSK_DSZ) \
- >> DCM_CFG_OFF_DSZ) - 1);
-}
-
-void dcache_flush_range(unsigned long start, unsigned long end)
-{
- unsigned long line_size;
-
- line_size = CACHE_LINE_SIZE(DCACHE);
-
- while
Re: [U-Boot] [PATCH 2/3] usb/gadget: add the fastboot gadget
Hi Wolfgang and Mike, > > missing comment block with license/copyright/etc... > > -mike > > [strip] > Are you 100% sure this is a GPLv2+ compatible license??? I don't think > so... [strip] > > For U-Boot, we need GPLv2+. Please see bullet # 3 at > http://www.denx.de/wiki/view/U Boot/Patches#Attributing_Code_Copyrights_Sign > and note # 1 at http://www.denx.de/wiki/view/U-Boot/Patches#Notes > > Best regards, > > Wolfgang Denk I have encountered some requests of porting Google's Fastboot protocol to u-boot from customers. As your comment about supporting fastboot in uboot in http://lists.linaro.org/pipermail/linaro-dev/2011-April/004136.html I think the problem of supporting fastboot in uboot might not only be the license problem. For clarifying the license issue, I think we may present some history as follows. The original BSD license (4-clause license) was indeed incompatible with GPLv2. However, this conflict has finally be resolved in "The new BSD license" (2-clause license). After revising, the 2-clause BSD license is almost exactly the same as MIT X license, which is also compatible with GPLv2. In detail, please check about the the page about the 3rd advertisement clause. http://www.gnu.org/philosophy/bsd.html And the content of the 4th clause which has been removed was "Neither the name of the University nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission." The license of Google's fastboot is exactly 2-clause BSD license. http://www.opensource.org/licenses/bsd-license.php I think the well-known event of merging BSD/GPL code in QEMU could be a reference. The well-known Open Source Licensing and Patent consultant of Redhat -- Richard Fontana has also helped on this problem. In order to merge SLiRP into QEMU, Richard has written e-mail to the author of SLiRP, which is "Danny Gasparovski" and the maintainer "Kelly Price" to get the agreement of removing the incompatible clauses. And after the revising of license, they've successfully merged SLiRP. http://lists.gnu.org/archive/html/qemu-devel/2009-01/msg01765.html Since the license of fastboot.c doesn't have the problem above, I think there is no compatible problem for merging "Google's fastboot". -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] Can anyone help me to solve the stack problem of U-boot? Urgent~
Hi Civic Wu, > Please see the README (section "U-Boot Porting Guide", but also > section "System Initialization"), and read doc/README.SPL and > http://catb.org/esr/faqs/smart-questions.html > > If this is urgent, and you spent many days on this, then the best > advice for you is to hire an expert. > > Best regards, > > Wolfgang Denk http://www.youtube.com/watch?v=XaetQBZB_E4 Hope this introduction "U-boot Porting Guide for NDS32 based SoC" may help you. The stack setup of NDS32 is similar as ARM. Please also read the document at first. :) -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request: u-boot-nds32
Dear Wolfgang, Please pull the following 4 patches into your tree. Thanks! Macpaul Lin. The following changes since commit 2790bf69dc12fb9aeb9836904e5f57c7f83d5552: Prepare v2012.04 (2012-04-21 18:55:26 +0200) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master Macpaul Lin (4): nds32/ag102: add header support of ag102 soc nds32/ag102: add ag102 soc support board/adp-ag102: add board specific files board/adp-ag102: add configuration of adp-ag102 MAINTAINERS|1 + arch/nds32/cpu/n1213/ag102/Makefile| 58 + arch/nds32/cpu/n1213/ag102/asm-offsets.c | 54 arch/nds32/cpu/n1213/ag102/cpu.c | 195 +++ arch/nds32/cpu/n1213/ag102/lowlevel_init.S | 297 ++ arch/nds32/cpu/n1213/ag102/timer.c | 205 +++ arch/nds32/cpu/n1213/ag102/watchdog.S | 49 arch/nds32/include/asm/arch-ag102/ag102.h | 97 +++ arch/nds32/include/asm/mach-types.h| 14 + board/AndesTech/adp-ag102/Makefile | 43 board/AndesTech/adp-ag102/adp-ag102.c | 107 boards.cfg |1 + doc/README.ag102 | 36 +++ include/configs/adp-ag102.h| 375 14 files changed, 1532 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/cpu/n1213/ag102/Makefile create mode 100644 arch/nds32/cpu/n1213/ag102/asm-offsets.c create mode 100644 arch/nds32/cpu/n1213/ag102/cpu.c create mode 100644 arch/nds32/cpu/n1213/ag102/lowlevel_init.S create mode 100644 arch/nds32/cpu/n1213/ag102/timer.c create mode 100644 arch/nds32/cpu/n1213/ag102/watchdog.S create mode 100644 arch/nds32/include/asm/arch-ag102/ag102.h create mode 100644 board/AndesTech/adp-ag102/Makefile create mode 100644 board/AndesTech/adp-ag102/adp-ag102.c create mode 100644 doc/README.ag102 create mode 100644 include/configs/adp-ag102.h -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 2/4] nds32/ag102: add ag102 soc support
Hi Macpaul, 2012/2/28 Macpaul Lin : > From: Macpaul Lin > > Add lowlevel ag102 soc support. > > Signed-off-by: Macpaul Lin > --- > Changes for v2: > - cpu.c: > - 1. Remove unused variables. > - 2. Replace while(1) in do_reset by hang(). > - 3. Clean up other coding styles. > - timer.c: remove unneccessary static declaration > Changes for v3: > - watchdog.S: add support macro in linkage.h > Applied to u-boot-nds32/master, Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 1/4] nds32/ag102: add header support of ag102 soc
Hi Macpaul, 2012/2/28 Macpaul Lin : > From: Macpaul Lin > > Add device address offsets header of ag102 soc. > Add ag102 into mach-types.h. > Add asm-offsets.c for helping convert C headers into asm. > > Signed-off-by: Macpaul Lin > --- > Changes for v2-v3: > - No change. Applied to u-boot-nds32/master, Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 3/4] board/adp-ag102: add board specific files
Hi Macpaul, 2012/2/28 Macpaul Lin > > From: Macpaul Lin > > Add board specific files. > > Signed-off-by: Macpaul Lin > --- > Changes for v2-v3: > - No change. > > board/AndesTech/adp-ag102/Makefile | 43 + > board/AndesTech/adp-ag102/adp-ag102.c | 107 > + > 2 files changed, 150 insertions(+), 0 deletions(-) > create mode 100644 board/AndesTech/adp-ag102/Makefile > create mode 100644 board/AndesTech/adp-ag102/adp-ag102.c > > diff --git a/board/AndesTech/adp-ag102/Makefile > b/board/AndesTech/adp-ag102/Makefile Applied to u-boot-nds32/master, Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v3 4/4] board/adp-ag102: add configuration of adp-ag102
Hi Macpaul, 2012/2/28 Macpaul Lin > From: Macpaul Lin > > board: > Add config file of board adp-ag102 > Add adp-ag102 into boards.cfg > Add adp-ag102 into MAINTAINERS > > doc: > add README of ag102 > > Signed-off-by: Macpaul Lin > Applied to u-boot-nds32/master, Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] Pull request for u-boot-nds32
Dear Wolfgang, Please pull the following 2 fix patches into your master branch. Thanks! The following changes since commit dbb87bbd8eff11cf974caa2b5cc397aea444bc5a: Armada100: gplugD: Add FAT & EXT2 command support (2012-03-19 00:08:26 +0100) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master Macpaul Lin (2): nds32: fix ptrace and interrupt register overflow nds32/n1213: correct vector table in start.S arch/nds32/cpu/n1213/start.S| 22 +++--- arch/nds32/include/asm/ptrace.h |2 ++ arch/nds32/lib/interrupts.c |2 +- 3 files changed, 22 insertions(+), 4 deletions(-) -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] nds32/n1213: correct vector table in start.S
Hi Macpaul, 2012/3/11 Macpaul Lin > Correct definition of vector table in start.S > > Signed-off-by: Macpaul Lin > --- > Changes for v2: > - fix symbol declaration error in start.S > Applied to u-boot-nds32/master Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] nds32: fix ptrace and interrupt register overflow
Hi Macpaul, 2012/3/11 Macpaul Lin > Fix ptrace and interrupt register overflow warning. > Add missing P0 and P1 (r26 and r27) into register lists. > These register are usually used in OS. > > Signed-off-by: Macpaul Lin > Applied to u-boot-nds32/master Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] DEVELOPER's MEETING
Hi all, 2012/3/16 Mike Frysinger > On Thursday 08 March 2012 07:16:10 Wolfgang Denk wrote: > > I was just thinking if this year's Libre Software Meeting (LSM - from > > 7th to 12th July in Geneva, Switzerland) would be a suitable event to > > arrange a meeting of some U-Boot developers? > > seems like this is a go ? i think i'll submit a paper/talk to cover > travel. > -mike > To have a meeting is really great, but I'm afraid I cannot attend at that time. By the way, just want to share you an information about the biggest open source conference in Taiwan, COSCUP. http://coscup.org/2011/en/ This conference is always held in August, but not sure which date will be held this year. Because there are so many users and many companies using u-boot in Taiwan, maybe we can hold a meeting here some day. Maybe Wolfgang could have a talk and contact these users and encourage them to contribute their work back. :) -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] nds32/n1213: correct vector table in start.S
Correct definition of vector table in start.S Signed-off-by: Macpaul Lin --- Changes for v2: - fix symbol declaration error in start.S arch/nds32/cpu/n1213/start.S | 22 +++--- 1 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 1d1fcf7..889bf8b 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -68,15 +68,17 @@ _start: j reset j tlb_not_present j tlb_misc j tlb_vlpt_miss - j cache_parity_error + j machine_error j debug j general_exception + j syscall j internal_interrupt ! H0I j internal_interrupt ! H1I j internal_interrupt ! H2I j internal_interrupt ! H3I j internal_interrupt ! H4I j internal_interrupt ! H5I + j software_interrupt ! S0I .balign 16 @@ -477,7 +479,7 @@ tlb_vlpt_miss: bal do_interruption .align 5 -cache_parity_error: +machine_error: SAVE_ALL move$r0, $sp! To get the kernel stack li $r1, 5 ! Determine interruption type @@ -498,13 +500,27 @@ general_exception: bal do_interruption .align 5 -internal_interrupt: +syscall: SAVE_ALL move$r0, $sp! To get the kernel stack li $r1, 8 ! Determine interruption type bal do_interruption .align 5 +internal_interrupt: + SAVE_ALL + move$r0, $sp! To get the kernel stack + li $r1, 9 ! Determine interruption type + bal do_interruption + + .align 5 +software_interrupt: + SAVE_ALL + move$r0, $sp! To get the kernel stack + li $r1, 10 ! Determine interruption type + bal do_interruption + + .align 5 /* * void reset_cpu(ulong addr); -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] nds32: fix ptrace and interrupt register overflow
Fix ptrace and interrupt register overflow warning.
Add missing P0 and P1 (r26 and r27) into register lists.
These register are usually used in OS.
Signed-off-by: Macpaul Lin
---
Change for V2:
- no change.
arch/nds32/include/asm/ptrace.h |2 ++
arch/nds32/lib/interrupts.c |2 +-
2 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
index 4336083..ee181b2 100644
--- a/arch/nds32/include/asm/ptrace.h
+++ b/arch/nds32/include/asm/ptrace.h
@@ -38,6 +38,8 @@ struct pt_regs {
NDS32_REG d1hi;
NDS32_REG d1lo;
NDS32_REG r[26];/* r0 - r25 */
+ NDS32_REG p0; /* r26 - used by OS */
+ NDS32_REG p1; /* r27 - used by OS */
NDS32_REG fp; /* r28 */
NDS32_REG gp; /* r29 */
NDS32_REG lp; /* r30 */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
index 974d52a..ca8c227 100644
--- a/arch/nds32/lib/interrupts.c
+++ b/arch/nds32/lib/interrupts.c
@@ -91,7 +91,7 @@ void show_regs(struct pt_regs *regs)
printf("D1H: %08lx D1L: %08lx D0H: %08lx D0L: %08lx\n",
regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
printf("r27: %08lx r26: %08lx r25: %08lx r24: %08lx\n",
- regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+ regs->p1, regs->p0, regs->r[25], regs->r[24]);
printf("r23: %08lx r22: %08lx r21: %08lx r20: %08lx\n",
regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
printf("r19: %08lx r18: %08lx r17: %08lx r16: %08lx\n",
--
1.7.5.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] nds32/n1213: correct vector table in start.S
Correct definition of vector table in start.S Signed-off-by: Macpaul Lin --- arch/nds32/cpu/n1213/start.S | 22 +++--- 1 files changed, 19 insertions(+), 3 deletions(-) diff --git a/arch/nds32/cpu/n1213/start.S b/arch/nds32/cpu/n1213/start.S index 1d1fcf7..518628a 100644 --- a/arch/nds32/cpu/n1213/start.S +++ b/arch/nds32/cpu/n1213/start.S @@ -68,15 +68,17 @@ _start: j reset j tlb_not_present j tlb_misc j tlb_vlpt_miss - j cache_parity_error + j machine_error j debug j general_exception + j syscall j internal_interrupt ! H0I j internal_interrupt ! H1I j internal_interrupt ! H2I j internal_interrupt ! H3I j internal_interrupt ! H4I j internal_interrupt ! H5I + j software_interrupt ! S0I .balign 16 @@ -477,7 +479,7 @@ tlb_vlpt_miss: bal do_interruption .align 5 -cache_parity_error: +machine_error: SAVE_ALL move$r0, $sp! To get the kernel stack li $r1, 5 ! Determine interruption type @@ -498,13 +500,27 @@ general_exception: bal do_interruption .align 5 -internal_interrupt: +syscall SAVE_ALL move$r0, $sp! To get the kernel stack li $r1, 8 ! Determine interruption type bal do_interruption .align 5 +internal_interrupt: + SAVE_ALL + move$r0, $sp! To get the kernel stack + li $r1, 9 ! Determine interruption type + bal do_interruption + + .align 5 +software_interrupt: + SAVE_ALL + move$r0, $sp! To get the kernel stack + li $r1, 10 ! Determine interruption type + bal do_interruption + + .align 5 /* * void reset_cpu(ulong addr); -- 1.7.5.4 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] nds32: fix ptrace and interrupt register overflow
Fix ptrace and interrupt register overflow warning.
Add missing P0 and P1 (r26 and r27) into register lists.
These register are usually used in OS.
Signed-off-by: Macpaul Lin
---
arch/nds32/include/asm/ptrace.h |2 ++
arch/nds32/lib/interrupts.c |2 +-
2 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/arch/nds32/include/asm/ptrace.h b/arch/nds32/include/asm/ptrace.h
index 4336083..ee181b2 100644
--- a/arch/nds32/include/asm/ptrace.h
+++ b/arch/nds32/include/asm/ptrace.h
@@ -38,6 +38,8 @@ struct pt_regs {
NDS32_REG d1hi;
NDS32_REG d1lo;
NDS32_REG r[26];/* r0 - r25 */
+ NDS32_REG p0; /* r26 - used by OS */
+ NDS32_REG p1; /* r27 - used by OS */
NDS32_REG fp; /* r28 */
NDS32_REG gp; /* r29 */
NDS32_REG lp; /* r30 */
diff --git a/arch/nds32/lib/interrupts.c b/arch/nds32/lib/interrupts.c
index 974d52a..ca8c227 100644
--- a/arch/nds32/lib/interrupts.c
+++ b/arch/nds32/lib/interrupts.c
@@ -91,7 +91,7 @@ void show_regs(struct pt_regs *regs)
printf("D1H: %08lx D1L: %08lx D0H: %08lx D0L: %08lx\n",
regs->d1hi, regs->d1lo, regs->d0hi, regs->d0lo);
printf("r27: %08lx r26: %08lx r25: %08lx r24: %08lx\n",
- regs->r[27], regs->r[26], regs->r[25], regs->r[24]);
+ regs->p1, regs->p0, regs->r[25], regs->r[24]);
printf("r23: %08lx r22: %08lx r21: %08lx r20: %08lx\n",
regs->r[23], regs->r[22], regs->r[21], regs->r[20]);
printf("r19: %08lx r18: %08lx r17: %08lx r16: %08lx\n",
--
1.7.5.4
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] nds32 ptrace register overflow
Hi Mike,
2012/3/6 Mike Frysinger :
> building for adp-ag101p showed this warning:
> interrupts.c: In function 'show_regs':
> interrupts.c:93: warning: array subscript is above array bounds
> interrupts.c:93: warning: array subscript is above array bounds
Thanks for reporting this.
> but regs->r only has 26 members ...
> arch/nds32/include/asm/ptrace.h:
> struct pt_regs {
It looks like r26 and r27 are missing here.
Registers r26 and r27 are named P0 and P1.
They are used for OS specifically.
But since all registers are general purposed and the usage between
will affected by toolchain.
Maybe that's why there is no problem when used wrong registers.
> NDS32_REG r[26]; /* r0 - r25 */
> NDS32_REG fp; /* r28 */
> NDS32_REG gp; /* r29 */
I'll fix this later.
Thanks!
--
Best regards,
Macpaul Lin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3 4/4] board/adp-ag102: add configuration of adp-ag102
From: Macpaul Lin board: Add config file of board adp-ag102 Add adp-ag102 into boards.cfg Add adp-ag102 into MAINTAINERS doc: add README of ag102 Signed-off-by: Macpaul Lin --- Changes for v2: - add pci and usb support to board setting adp-ag102.h Changes for v3: - Fix patch because update of boards.cfg and MAINTAINERS MAINTAINERS |1 + boards.cfg |1 + doc/README.ag102| 36 include/configs/adp-ag102.h | 375 +++ 4 files changed, 413 insertions(+), 0 deletions(-) create mode 100644 doc/README.ag102 create mode 100644 include/configs/adp-ag102.h diff --git a/MAINTAINERS b/MAINTAINERS index 1e40af2..5b45978 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1199,6 +1199,7 @@ Macpaul Lin ADP-AG101 N1213 (AG101 SoC) ADP-AG101P N1213 (AG101P XC5 FPGA) + ADP-AG102 N1213f (AG102 SoC with FPU) # # OpenRISC Systems:# diff --git a/boards.cfg b/boards.cfg index 05ce1ae..38f0d34 100644 --- a/boards.cfg +++ b/boards.cfg @@ -376,6 +376,7 @@ incaip_150MHzmipsmips32 incaip - qi_lb60 mipsxburst qi_lb60 qi adp-ag101nds32 n1213 adp-ag101 AndesTech ag101 adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101 +adp-ag102nds32 n1213 adp-ag102 AndesTech ag102 nios2-genericnios2 nios2 nios2-generic altera PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent diff --git a/doc/README.ag102 b/doc/README.ag102 new file mode 100644 index 000..7d142a7 --- /dev/null +++ b/doc/README.ag102 @@ -0,0 +1,36 @@ +Andes Technology SoC AG102 +== + +AG102 is the second SoC produced by Andes Technology using N1213 CPU core +with FPU and DDR contoller support. +AG102 has integrated both AHB and APB bus and many periphals for application +and product development. + +ADP-AG102 += + +ADP-AG102 is the SoC with AG102 hardcore CPU. + +Configurations +== + +CONFIG_MEM_REMAP: + Doing memory remap is essential for preparing some non-OS or RTOS + applications. + +CONFIG_SKIP_LOWLEVEL_INIT: + If you want to boot this system from SPI ROM and bypass e-bios (the + other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT + in "include/configs/adp-ag102.h". + +Build and boot steps + + +build: +1. Prepare the toolchains and make sure the $PATH to toolchains is correct. +2. Use `make adp-ag102` in u-boot root to build the image. + +Burn u-boot to SPI ROM: + + +This section will be added later. diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h new file mode 100644 index 000..a4628e4 --- /dev/null +++ b/include/configs/adp-ag102.h @@ -0,0 +1,375 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_ADP_AG102 + +#define CONFIG_USE_INTERRUPT + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_MEM_REMAP +#endif + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0x0420 +#else +#define CONFIG_SYS_TEXT_BASE 0x +#endif + +/* + * Timer + */ + +/* + * According to the discussion in u-boot mailing list before, + * CONFIG_SYS_HZ at 1000 is mandatory. + */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK_FREQ(6600 * 2) +#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ + +/* + * Use Externel CLOCK or PCLK + */ +#undef CONFIG_FTRTC010_EXTCLK + +#ifndef CONFIG_FTRTC010_EXTCLK +#define CONFIG_FTRTC010_PCLK +#endif
[U-Boot] [PATCH v3 3/4] board/adp-ag102: add board specific files
From: Macpaul Lin
Add board specific files.
Signed-off-by: Macpaul Lin
---
Changes for v2-v3:
- No change.
board/AndesTech/adp-ag102/Makefile| 43 +
board/AndesTech/adp-ag102/adp-ag102.c | 107 +
2 files changed, 150 insertions(+), 0 deletions(-)
create mode 100644 board/AndesTech/adp-ag102/Makefile
create mode 100644 board/AndesTech/adp-ag102/adp-ag102.c
diff --git a/board/AndesTech/adp-ag102/Makefile
b/board/AndesTech/adp-ag102/Makefile
new file mode 100644
index 000..1cbf2d4
--- /dev/null
+++ b/board/AndesTech/adp-ag102/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Macpaul Lin, Andes Technology Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := adp-ag102.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/AndesTech/adp-ag102/adp-ag102.c
b/board/AndesTech/adp-ag102/adp-ag102.c
new file mode 100644
index 000..5a25632
--- /dev/null
+++ b/board/AndesTech/adp-ag102/adp-ag102.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include
+#include
+#include
+
+#include
+#ifdef CONFIG_FTSMC020
+#include
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+* refer to BOOT_PARAMETER_PA_BASE within
+* "linux/arch/nds32/include/asm/misc_spec.h"
+*/
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG102;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ ftsmc020_init();/* initialize Flash */
+#endif /* CONFIG_SYS_NO_FLASH */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftgmac100_initialize(bd);
+}
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+void pci_init_board(void)
+{
+ /* should be pci_ftpci100_init() */
+ extern void pci_ftpci_
[U-Boot] [PATCH v3 2/4] nds32/ag102: add ag102 soc support
From: Macpaul Lin
Add lowlevel ag102 soc support.
Signed-off-by: Macpaul Lin
---
Changes for v2:
- cpu.c:
- 1. Remove unused variables.
- 2. Replace while(1) in do_reset by hang().
- 3. Clean up other coding styles.
- timer.c: remove unneccessary static declaration
Changes for v3:
- watchdog.S: add support macro in linkage.h
arch/nds32/cpu/n1213/ag102/Makefile| 58 ++
arch/nds32/cpu/n1213/ag102/cpu.c | 195 ++
arch/nds32/cpu/n1213/ag102/lowlevel_init.S | 297
arch/nds32/cpu/n1213/ag102/timer.c | 205 +++
arch/nds32/cpu/n1213/ag102/watchdog.S | 49 +
5 files changed, 804 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/ag102/Makefile
create mode 100644 arch/nds32/cpu/n1213/ag102/cpu.c
create mode 100644 arch/nds32/cpu/n1213/ag102/lowlevel_init.S
create mode 100644 arch/nds32/cpu/n1213/ag102/timer.c
create mode 100644 arch/nds32/cpu/n1213/ag102/watchdog.S
diff --git a/arch/nds32/cpu/n1213/ag102/Makefile
b/arch/nds32/cpu/n1213/ag102/Makefile
new file mode 100644
index 000..8716c4e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor
+# Written-by: Prafulla Wadaskar
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation
+# Macpaul Lin, Andes Technology Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS-y:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS += watchdog.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c
new file mode 100644
index 000..ed88b52
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/cpu.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH
+ * Marius Groeger
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering,
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include
+#include
+#include
+#include
+
+#include
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+#ifdef CONFIG_MMU
+ /* turn off I/D-cache */
+ icache_disable();
+ dcache_disable();
+
+ /* flush I/D-cache */
+ invalidate_icac();
+ invalidate_dcac();
+#endif
+
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+
+ /*
+* reset to the base addr of andesboot.
+* currently no ROM loader at addr 0
[U-Boot] [PATCH v3 1/4] nds32/ag102: add header support of ag102 soc
From: Macpaul Lin
Add device address offsets header of ag102 soc.
Add ag102 into mach-types.h.
Add asm-offsets.c for helping convert C headers into asm.
Signed-off-by: Macpaul Lin
---
Changes for v2-v3:
- No change.
arch/nds32/cpu/n1213/ag102/asm-offsets.c | 54
arch/nds32/include/asm/arch-ag102/ag102.h | 97 +
arch/nds32/include/asm/mach-types.h | 14
3 files changed, 165 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/ag102/asm-offsets.c
create mode 100644 arch/nds32/include/asm/arch-ag102/ag102.h
diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c
b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
new file mode 100644
index 000..4769a95
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
@@ -0,0 +1,54 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include
+
+#include
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+ OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
+ OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
+#endif
+ BLANK();
+#ifdef CONFIG_FTAHBC020S
+ OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
+ OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
+#endif
+ BLANK();
+#ifdef CONFIG_ANDES_PCU
+ OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
+#endif
+ BLANK();
+#ifdef CONFIG_DWCDDR21MCTL
+ OFFSET(DWCDDR21MCTL_CCR,dwcddr21mctl, ccr); /* 0x04 */
+ OFFSET(DWCDDR21MCTL_DCR,dwcddr21mctl, dcr); /* 0x04 */
+ OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr);/* 0x08 */
+ OFFSET(DWCDDR21MCTL_CSR,dwcddr21mctl, csr); /* 0x0c */
+ OFFSET(DWCDDR21MCTL_DRR,dwcddr21mctl, drr); /* 0x10 */
+ OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
+ OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
+ OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
+ OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
+ OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
+ OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
+ OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
+ OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
+ OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
+ OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
+ OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
+ OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
+ OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar);/* 0xa4 */
+ OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
+#endif
+ return 0;
+}
diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h
b/arch/nds32/include/asm/arch-ag102/ag102.h
new file mode 100644
index 000..a12a8c5
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG102_H
+#define __AG102_H
+
+/*
+ * Hardware register bases
+ */
+
+/* PCI Controller */
+#define CONFIG_FTPCI100_BASE 0x9000
+/* LPC Controller */
+#define CONFIG_LPC_IO_BASE 0x9010
+/* LPC Controller */
+#define CONFIG_LPC_BASE0x9020
+
+/* NDS32 Data Local Memory 01 */
+#define CONFIG_NDS_DLM1_BASE 0x9030
+/* NDS32 Data Local Memory 02 */
+#define CONFIG_NDS_DLM2_BASE 0x9040
+
+/* Synopsys DWC DDR2/1 Controller */
+#define CONFIG_DWCDDR21MCTL_BASE 0x9050
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE 0x9060
+/* FTIDE020_S IDE (ATA
[U-Boot] Pull request: u-boot-nds32/master
Dear Wolfgang, Please pull the following change into u-boot/master, thanks!. The following changes since commit 54e96680cb96fb7a4b8f43fd949c62054004d3e5: Merge branch 'master' of git://git.denx.de/u-boot-microblaze (2012-02-26 22:17:40 +0100) are available in the git repository at: git://git.denx.de/u-boot-nds32.git master Macpaul Lin (3): nds32: add linkage support nds32/ag101/watchdog.S: add linkage support nds32/board.c: add PCI prompt at boot up arch/nds32/cpu/n1213/ag101/watchdog.S |5 +++-- arch/nds32/include/asm/linkage.h | 28 arch/nds32/lib/board.c|1 + 3 files changed, 32 insertions(+), 2 deletions(-) create mode 100644 arch/nds32/include/asm/linkage.h -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH] nds32/board.c: add PCI prompt at boot up
Hi Macpaul,
2011/11/29 Macpaul Lin
> add PCI prompt at boot up for probing PCI device
>
> Signed-off-by: Macpaul Lin
> ---
> arch/nds32/lib/board.c |1 +
> 1 files changed, 1 insertions(+), 0 deletions(-)
>
> diff --git a/arch/nds32/lib/board.c b/arch/nds32/lib/board.c
> index 66e4537..074aabf 100644
> --- a/arch/nds32/lib/board.c
> +++ b/arch/nds32/lib/board.c
> @@ -365,6 +365,7 @@ void board_init_r(gd_t *id, ulong dest_addr)
>env_relocate();
>
> #if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
> + puts("PCI: ");
>nds32_pci_init();
> #endif
>
> --
> 1.7.3.5
>
>
Applied to u-boot-nds32.git/master
Thanks!
--
Best regards,
Macpaul Lin
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/2] nds32/ag101/watchdog.S: add linkage support
Hi Macpaul 2011/12/1 Macpaul Lin > Add linkage support to watchdog.S. > > Signed-off-by: Macpaul Lin > --- > Changes for v2: > - No change. > > arch/nds32/cpu/n1213/ag101/watchdog.S |5 +++-- > 1 files changed, 3 insertions(+), 2 deletions(-) > > Applied, thanks, -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2] linkage.h: move from blackfin to common includes
Hi Mike, 2012/1/11 Mike Frysinger > > FYI, i'll be including it as part of my Blackfin merge when the window > closes > -mike > > Thanks for your information, I'll do other fix based on this commit. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH] ftintc010.h: add header of ftintc010 interrupt controller
add header definition of faraday interrupt controller
Signed-off-by: Macpaul Lin
---
include/faraday/ftintc010.h | 101 +++
1 files changed, 101 insertions(+), 0 deletions(-)
create mode 100644 include/faraday/ftintc010.h
diff --git a/include/faraday/ftintc010.h b/include/faraday/ftintc010.h
new file mode 100644
index 000..f2e004b
--- /dev/null
+++ b/include/faraday/ftintc010.h
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2012 Andes Technology Corp
+ * Macpaul Lin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * FTINTC010 - Faraday Interrupt Controller
+ */
+#ifndef __FTINTC010_H
+#define __FTINTC010_H
+
+#ifndef __ASSEMBLY__
+
+struct ftintc010 {
+ unsigned intirqsrc; /* 0x00 - IRQ Source */
+ unsigned intirqen; /* 0x04 - IRQ Enable */
+ unsigned intirqclr; /* 0x08 - IRQ Interrupt Clear */
+ unsigned intirqtrigmode;/* 0x0C - IRQ Trigger Mode */
+ unsigned intirqtriglevel; /* 0x10 - IRQ Trigger Level */
+ unsigned intstatus; /* 0x14 - IRQ Status */
+ unsigned intrsvd0[2]; /* 0x18-0x1C */
+ unsigned intfiqsrc; /* 0x20 - FIQ Source */
+ unsigned intfiqen; /* 0x24 - FIQ Enable */
+ unsigned intfiqclr; /* 0x28 - FIQ Interrupt Clear */
+ unsigned intfiqtrigmode;/* 0x2C - FIQ Trigger Mode */
+ unsigned intfiqtriglevel; /* 0x30 - FIQ Trigger Level */
+ unsigned intfiqstatus; /* 0x34 - FIQ Status */
+ unsigned intrsvd1[6]; /* 0x38-0x4C */
+ unsigned intrev;/* 0x50 - Revision */
+
+ /* The following are Feature Registers */
+ unsigned intfrin; /* 0x54 - Input Number */
+ unsigned intfrirqdl;/* 0x58 - IRQ De-bounce Location */
+ unsigned intfrfiqdl;/* 0x5C - FIQ De-bounce Location */
+};
+#endif /* __ASSEMBLY__ */
+
+/* 0x00 - IRQ Source Register */
+#define FTINTC010_IRQ_SRC(x) (1 << x)
+
+/* 0x04 - IRQ Enable Register */
+#define FTINTC010_IRQ_EN(x)(1 << x)
+
+/* 0x08 - IRQ Interrupt Clear Register */
+#define FTINTC010_IRQ_CLR(x) (1 << x)
+
+/* 0x0C - IRQ Trigger Mode Register */
+#define FTINTC010_IRQ_TRIGMODE(x) (1 << x)
+
+/* 0x10 - IRQ Trigger Level Register */
+#define FTINTC010_IRQ_TRIGLEVEL(x) (1 << x)
+
+/* 0x14 - IRQ Status Register */
+#define FTINTC010_IRQ_ST(x)(1 << x)
+
+/* 0x20 - FIQ Source Register */
+#define FTINTC010_FIQ_SRC(x) (1 << x)
+
+/* 0x24 - FIQ Enable Register */
+#define FTINTC010_FIQ_EN(x)(1 << x)
+
+/* 0x28 - FIQ Interrupt Clear Register */
+#define FTINTC010_FIQ_CLR(x) (1 << x)
+
+/* 0x2C - FIQ Trigger Mode Register */
+#define FTINTC010_FIQ_TRIGMODE(x) (1 << x)
+
+/* 0x30 - FIQ Trigger Level Register */
+#define FTINTC010_FIQ_TRIGLEVEL(x) (1 << x)
+
+/* 0x34 - FIQ Status Register */
+#define FTINTC010_FIQ_ST(x)(1 << x)
+
+/* 0x50 - Revision Register */
+#define FTINTC010_REV(x) (((x) > 0) & 0xFF)
+
+/* 0x54 - Feature Register for Input Number */
+#define FTINTC010_FRIN_IRQNO(x)(((x) > 8) & 0xFF)
+#define FTINTC010_FRIN_FIQNO(x)(((x) > 0) & 0xFF)
+
+/* 0x58 - Feature Register for IRQ De-bounce Location */
+#define FTINTC010_IRQDL(x) (1 << x)
+
+/* 0x5C - Feature Register for FIQ De-bounce Location */
+#define FTINTC010_FIQDL(x) (1 << x)
+
+#endif /* __FTINTC010_H */
--
1.7.3.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v3] nds32: add header of amic multicore interrupt controller.
Add header file support of amic multicore interrupt controller.
Signed-off-by: Macpaul Lin
---
Changes for v2:
- rename the subject to avoid misleading.
Changes for v3:
- correct the patch format of v2.
include/andestech/amic.h | 195 ++
1 files changed, 195 insertions(+), 0 deletions(-)
create mode 100644 include/andestech/amic.h
diff --git a/include/andestech/amic.h b/include/andestech/amic.h
new file mode 100644
index 000..52d95ca
--- /dev/null
+++ b/include/andestech/amic.h
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2012 Andes Technology Corp
+ * Macpaul Lin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Andes Multi-Core Interrupt Controller
+ */
+#ifndef __ANDES_AMIC_H
+#define __ANDES_AMIC_H
+
+#ifndef __ASSEMBLY__
+
+struct amic {
+ unsigned intintconfig; /* 0x00 - Hardware Configuration */
+ unsigned intcpudc; /* 0x04 - CPU owner DC reg */
+ unsigned intcpuid1; /* 0x08 - CPU owner ID reg 1 */
+ unsigned intcpuid2; /* 0x0c - CPU owner ID reg 2 */
+ unsigned intrsvd0[4]; /* 0x10-0x1c - Reserved */
+ unsigned intintrigmode; /* 0x20 - Interrupt Trigger Mode */
+ unsigned intintriglevel;/* 0x24 - Interrupt Trigger Level */
+ unsigned intintsrc; /* 0x28 - Interrupt Source reg */
+ unsigned intrsvd1[5]; /* 0x2c-0x3c - Reserved */
+ unsigned intipitrg; /* 0x40 - IPI trigger reg */
+ unsigned intipista; /* 0x44 - IPI status/clear reg */
+ unsigned intipipl; /* 0x48 - IPI priority level reg */
+ unsigned intipigsta;/* 0x4c - IPI global status/clear reg */
+ unsigned intipigpt; /* 0x50 - IPI global priority reg */
+ unsigned intrsvd2[11]; /* 0x54-0x7c - Reserved */
+ unsigned intinten; /* 0x80 - Interrupt enable reg */
+ unsigned intintgsta;/* 0x84 - Interrupt status/clear reg */
+ unsigned intinthw0sta; /* 0x88 - IVIC HW0 int status/clear */
+ unsigned intinthw1sta; /* 0x8c - IVIC HW1 int status/clear */
+ unsigned intinthw2sta; /* 0x90 - IVIC HW2 int status/clear */
+ unsigned intinthw3sta; /* 0x94 - IVIC HW3 int status/clear */
+ unsigned intinthw4sta; /* 0x98 - IVIC HW4 int status/clear */
+ unsigned intinthw5sta; /* 0x9c - IVIC HW5 int status/clear */
+ unsigned intiplcr0; /* 0xa0 - Int priority level0 0-7) */
+ unsigned intiplcr1; /* 0xa4 - Int priority level1 8-15 */
+ unsigned intiplcr2; /* 0xa8 - Int priority level2 16-23 */
+ unsigned intiplcr3; /* 0xac - Int priority level3 24-31 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * 0x00 - Configuration Register (ro)
+ */
+#define ANDES_AMIC_CPU_CNT(x) (((x) & 0x7) > 0)
+#define ANDES_AMIC_PLVL(1 << 4)
+#define ANDES_AMIC_IPI32 (1 << 5)
+#define ANDES_AMIC_EM0 (1 << 8)
+#define ANDES_AMIC_EM1 (1 << 9)
+#define ANDES_AMIC_EM2 (1 << 10)
+#define ANDES_AMIC_EM3 (1 << 11)
+#define ANDES_AMIC_VER(x) (((x) & 0x) > 16)
+
+/*
+ * 0x04 - CPU owner DC register
+ */
+#define ANDES_AMIC_CPUDC(x)((x) & 0x)
+
+/*
+ * 0x08 - CPU owner ID register 1
+ */
+#define ANDES_AMIC_CPUID1(x) (((x) & 0x) > 0)
+
+/*
+ * 0x0c - CPU owner ID register 2
+ */
+#define ANDES_AMIC_CPUID2(x) (((x) & 0x) > 16)
+
+/*
+ * 0x20 - Interrupt Trigger Mode Register
+ * 0: level trigger, 1: edge trigger
+ */
+#define ANDES_AMIC_INTRIGMODE(x) (1 << (x))
+
+/*
+ * 0x24 - Interrupt Trigger Level Register
+ * 0: Active-high/rising edge, 1: Active-low/falling edge
+ */
+#define ANDES_AMIC_INTRIGLEVEL(x) (1 << (x))
+
+/*
+ * 0x28 - Interrupt Source Register
+ */
+#define ANDES_AMIC_INTRSRC(x) (1 << (x))
+
+/*
+ * 0x040 - IPI Trigger Register
+ */
+#define ANDES_AMIC_IPITRG_CX0 (1 << 0)
+#define ANDES_AMIC_IPITRG_CX1
[U-Boot] [PATCH v2] nds32: add header of amic multicore interrupt controller.
Add header file support of amic multicore interrupt controller.
Signed-off-by: Macpaul Lin
Changes for v2:
- rename the subject to avoid misleading.
---
include/andestech/amic.h | 195 ++
1 files changed, 195 insertions(+), 0 deletions(-)
create mode 100644 include/andestech/amic.h
diff --git a/include/andestech/amic.h b/include/andestech/amic.h
new file mode 100644
index 000..52d95ca
--- /dev/null
+++ b/include/andestech/amic.h
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2012 Andes Technology Corp
+ * Macpaul Lin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Andes Multi-Core Interrupt Controller
+ */
+#ifndef __ANDES_AMIC_H
+#define __ANDES_AMIC_H
+
+#ifndef __ASSEMBLY__
+
+struct amic {
+ unsigned intintconfig; /* 0x00 - Hardware Configuration */
+ unsigned intcpudc; /* 0x04 - CPU owner DC reg */
+ unsigned intcpuid1; /* 0x08 - CPU owner ID reg 1 */
+ unsigned intcpuid2; /* 0x0c - CPU owner ID reg 2 */
+ unsigned intrsvd0[4]; /* 0x10-0x1c - Reserved */
+ unsigned intintrigmode; /* 0x20 - Interrupt Trigger Mode */
+ unsigned intintriglevel;/* 0x24 - Interrupt Trigger Level */
+ unsigned intintsrc; /* 0x28 - Interrupt Source reg */
+ unsigned intrsvd1[5]; /* 0x2c-0x3c - Reserved */
+ unsigned intipitrg; /* 0x40 - IPI trigger reg */
+ unsigned intipista; /* 0x44 - IPI status/clear reg */
+ unsigned intipipl; /* 0x48 - IPI priority level reg */
+ unsigned intipigsta;/* 0x4c - IPI global status/clear reg */
+ unsigned intipigpt; /* 0x50 - IPI global priority reg */
+ unsigned intrsvd2[11]; /* 0x54-0x7c - Reserved */
+ unsigned intinten; /* 0x80 - Interrupt enable reg */
+ unsigned intintgsta;/* 0x84 - Interrupt status/clear reg */
+ unsigned intinthw0sta; /* 0x88 - IVIC HW0 int status/clear */
+ unsigned intinthw1sta; /* 0x8c - IVIC HW1 int status/clear */
+ unsigned intinthw2sta; /* 0x90 - IVIC HW2 int status/clear */
+ unsigned intinthw3sta; /* 0x94 - IVIC HW3 int status/clear */
+ unsigned intinthw4sta; /* 0x98 - IVIC HW4 int status/clear */
+ unsigned intinthw5sta; /* 0x9c - IVIC HW5 int status/clear */
+ unsigned intiplcr0; /* 0xa0 - Int priority level0 0-7) */
+ unsigned intiplcr1; /* 0xa4 - Int priority level1 8-15 */
+ unsigned intiplcr2; /* 0xa8 - Int priority level2 16-23 */
+ unsigned intiplcr3; /* 0xac - Int priority level3 24-31 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * 0x00 - Configuration Register (ro)
+ */
+#define ANDES_AMIC_CPU_CNT(x) (((x) & 0x7) > 0)
+#define ANDES_AMIC_PLVL(1 << 4)
+#define ANDES_AMIC_IPI32 (1 << 5)
+#define ANDES_AMIC_EM0 (1 << 8)
+#define ANDES_AMIC_EM1 (1 << 9)
+#define ANDES_AMIC_EM2 (1 << 10)
+#define ANDES_AMIC_EM3 (1 << 11)
+#define ANDES_AMIC_VER(x) (((x) & 0x) > 16)
+
+/*
+ * 0x04 - CPU owner DC register
+ */
+#define ANDES_AMIC_CPUDC(x)((x) & 0x)
+
+/*
+ * 0x08 - CPU owner ID register 1
+ */
+#define ANDES_AMIC_CPUID1(x) (((x) & 0x) > 0)
+
+/*
+ * 0x0c - CPU owner ID register 2
+ */
+#define ANDES_AMIC_CPUID2(x) (((x) & 0x) > 16)
+
+/*
+ * 0x20 - Interrupt Trigger Mode Register
+ * 0: level trigger, 1: edge trigger
+ */
+#define ANDES_AMIC_INTRIGMODE(x) (1 << (x))
+
+/*
+ * 0x24 - Interrupt Trigger Level Register
+ * 0: Active-high/rising edge, 1: Active-low/falling edge
+ */
+#define ANDES_AMIC_INTRIGLEVEL(x) (1 << (x))
+
+/*
+ * 0x28 - Interrupt Source Register
+ */
+#define ANDES_AMIC_INTRSRC(x) (1 << (x))
+
+/*
+ * 0x040 - IPI Trigger Register
+ */
+#define ANDES_AMIC_IPITRG_CX0 (1 << 0)
+#define ANDES_AMIC_IPITRG_CX1 (1 << 1)
+#define ANDES_AMIC_IPITRG_CX2 (1
[U-Boot] [PATCH] nds32: add amic multicore interrupt controller support
Add header file support of amic multicore interrupt controller.
Signed-off-by: Macpaul Lin
---
include/andestech/amic.h | 195 ++
1 files changed, 195 insertions(+), 0 deletions(-)
create mode 100644 include/andestech/amic.h
diff --git a/include/andestech/amic.h b/include/andestech/amic.h
new file mode 100644
index 000..52d95ca
--- /dev/null
+++ b/include/andestech/amic.h
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2012 Andes Technology Corp
+ * Macpaul Lin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+/*
+ * Andes Multi-Core Interrupt Controller
+ */
+#ifndef __ANDES_AMIC_H
+#define __ANDES_AMIC_H
+
+#ifndef __ASSEMBLY__
+
+struct amic {
+ unsigned intintconfig; /* 0x00 - Hardware Configuration */
+ unsigned intcpudc; /* 0x04 - CPU owner DC reg */
+ unsigned intcpuid1; /* 0x08 - CPU owner ID reg 1 */
+ unsigned intcpuid2; /* 0x0c - CPU owner ID reg 2 */
+ unsigned intrsvd0[4]; /* 0x10-0x1c - Reserved */
+ unsigned intintrigmode; /* 0x20 - Interrupt Trigger Mode */
+ unsigned intintriglevel;/* 0x24 - Interrupt Trigger Level */
+ unsigned intintsrc; /* 0x28 - Interrupt Source reg */
+ unsigned intrsvd1[5]; /* 0x2c-0x3c - Reserved */
+ unsigned intipitrg; /* 0x40 - IPI trigger reg */
+ unsigned intipista; /* 0x44 - IPI status/clear reg */
+ unsigned intipipl; /* 0x48 - IPI priority level reg */
+ unsigned intipigsta;/* 0x4c - IPI global status/clear reg */
+ unsigned intipigpt; /* 0x50 - IPI global priority reg */
+ unsigned intrsvd2[11]; /* 0x54-0x7c - Reserved */
+ unsigned intinten; /* 0x80 - Interrupt enable reg */
+ unsigned intintgsta;/* 0x84 - Interrupt status/clear reg */
+ unsigned intinthw0sta; /* 0x88 - IVIC HW0 int status/clear */
+ unsigned intinthw1sta; /* 0x8c - IVIC HW1 int status/clear */
+ unsigned intinthw2sta; /* 0x90 - IVIC HW2 int status/clear */
+ unsigned intinthw3sta; /* 0x94 - IVIC HW3 int status/clear */
+ unsigned intinthw4sta; /* 0x98 - IVIC HW4 int status/clear */
+ unsigned intinthw5sta; /* 0x9c - IVIC HW5 int status/clear */
+ unsigned intiplcr0; /* 0xa0 - Int priority level0 0-7) */
+ unsigned intiplcr1; /* 0xa4 - Int priority level1 8-15 */
+ unsigned intiplcr2; /* 0xa8 - Int priority level2 16-23 */
+ unsigned intiplcr3; /* 0xac - Int priority level3 24-31 */
+};
+#endif /* __ASSEMBLY__ */
+
+/*
+ * 0x00 - Configuration Register (ro)
+ */
+#define ANDES_AMIC_CPU_CNT(x) (((x) & 0x7) > 0)
+#define ANDES_AMIC_PLVL(1 << 4)
+#define ANDES_AMIC_IPI32 (1 << 5)
+#define ANDES_AMIC_EM0 (1 << 8)
+#define ANDES_AMIC_EM1 (1 << 9)
+#define ANDES_AMIC_EM2 (1 << 10)
+#define ANDES_AMIC_EM3 (1 << 11)
+#define ANDES_AMIC_VER(x) (((x) & 0x) > 16)
+
+/*
+ * 0x04 - CPU owner DC register
+ */
+#define ANDES_AMIC_CPUDC(x)((x) & 0x)
+
+/*
+ * 0x08 - CPU owner ID register 1
+ */
+#define ANDES_AMIC_CPUID1(x) (((x) & 0x) > 0)
+
+/*
+ * 0x0c - CPU owner ID register 2
+ */
+#define ANDES_AMIC_CPUID2(x) (((x) & 0x) > 16)
+
+/*
+ * 0x20 - Interrupt Trigger Mode Register
+ * 0: level trigger, 1: edge trigger
+ */
+#define ANDES_AMIC_INTRIGMODE(x) (1 << (x))
+
+/*
+ * 0x24 - Interrupt Trigger Level Register
+ * 0: Active-high/rising edge, 1: Active-low/falling edge
+ */
+#define ANDES_AMIC_INTRIGLEVEL(x) (1 << (x))
+
+/*
+ * 0x28 - Interrupt Source Register
+ */
+#define ANDES_AMIC_INTRSRC(x) (1 << (x))
+
+/*
+ * 0x040 - IPI Trigger Register
+ */
+#define ANDES_AMIC_IPITRG_CX0 (1 << 0)
+#define ANDES_AMIC_IPITRG_CX1 (1 << 1)
+#define ANDES_AMIC_IPITRG_CX2 (1 << 2)
+#define ANDES_AMIC_IPITRG_CX3 (
Re: [U-Boot] [STATUS] v2011.12-rc1 is out - release date Dec 23
Hi Mike, 2011/12/12 Wolfgang Denk > Hi everybody, > > after long struggeling we finally have a -rc1. > > Please help testing, so we can fix the remaining issues before the > release, which I decided to shift to December 23. > > I have some patches depends on linkage.h issue. http://patchwork.ozlabs.org/patch/128640/ Would you please help testing on blackfin and see if there is any problem? Testing for NDS32 architecture for 2011.12-rc1 is done. Thanks! -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [STATUS] Getting ready for -rc1
Hi Mike, 2011/12/6 Wolfgang Denk > Hi all, > > Second, I would like to get ready for the -rc1 pre-release. > I'll wait for the next ARM pull request from Albert, and then I will > push -rc1 out. > > If anybody has any unmerged patches pending that are supposed to go > in, please speak up now. > > Would you please test linkage.h related change before rc2? I guess we cannot done this before rc1 is out. If we can done this before rc2, then other people could be able to refine their code if they want just after the official release. Thanks. :) Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 2/2] nds32/ag101/watchdog.S: add linkage support
Add linkage support to watchdog.S. Signed-off-by: Macpaul Lin --- Changes for v2: - No change. arch/nds32/cpu/n1213/ag101/watchdog.S |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S index fc39f3f..18f0b66 100644 --- a/arch/nds32/cpu/n1213/ag101/watchdog.S +++ b/arch/nds32/cpu/n1213/ag101/watchdog.S @@ -22,12 +22,12 @@ */ #include +#include .text #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG -.globl turnoff_watchdog -turnoff_watchdog: +ENTRY(turnoff_watchdog) #define WD_CR 0xC #define WD_ENABLE 0x1 @@ -45,4 +45,5 @@ turnoff_watchdog: ret +ENDPROC(turnoff_watchdog) #endif -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 1/2] nds32: add linkage support
Add linkage support. Signed-off-by: Macpaul Lin --- Changes for v2: - remove architecture related define of align. - remain this empty file for the compilation necessary. arch/nds32/include/asm/linkage.h | 28 1 files changed, 28 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/include/asm/linkage.h diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h new file mode 100644 index 000..6d4493a --- /dev/null +++ b/arch/nds32/include/asm/linkage.h @@ -0,0 +1,28 @@ +/* + * U-boot - linkage.h + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#endif -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2] linkage.h: move from blackfin to common includes
1. Add linkage.h support from blackfin to common include,
which is a reduced version from Linux.
2. Add architecture part support of linkage.h into blackfin
3. Fix include path of in blackfin related to linkage.h
due to header file movement.
Signed-off-by: Macpaul Lin
---
Changes for v2:
- add default value of align is 4.
- remove architecture related define of align.
- remain this empty file for the compilation necessary.
- squash 3 patches into one to avoid bisect problem.
arch/blackfin/cpu/cache.S |2 +-
arch/blackfin/include/asm/blackfin_local.h |2 +-
arch/blackfin/include/asm/cache.h |2 +-
arch/blackfin/include/asm/linkage.h| 50 +---
arch/blackfin/lib/__kgdb.S |2 +-
arch/blackfin/lib/outs.S |2 +-
.../include/asm => include/linux}/linkage.h|1 +
7 files changed, 8 insertions(+), 53 deletions(-)
copy {arch/blackfin/include/asm => include/linux}/linkage.h (98%)
diff --git a/arch/blackfin/cpu/cache.S b/arch/blackfin/cpu/cache.S
index 6ed655a..1e468ee 100644
--- a/arch/blackfin/cpu/cache.S
+++ b/arch/blackfin/cpu/cache.S
@@ -8,9 +8,9 @@
* Licensed under the GPL-2 or later.
*/
-#include
#include
#include
+#include
.text
/* Since all L1 caches work the same way, we use the same method for flushing
diff --git a/arch/blackfin/include/asm/blackfin_local.h
b/arch/blackfin/include/asm/blackfin_local.h
index 71207b6..9d27f31 100644
--- a/arch/blackfin/include/asm/blackfin_local.h
+++ b/arch/blackfin/include/asm/blackfin_local.h
@@ -48,8 +48,8 @@
#define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-#include
#include
+#include
#ifndef __ASSEMBLY__
# ifdef SHARED_RESOURCES
diff --git a/arch/blackfin/include/asm/cache.h
b/arch/blackfin/include/asm/cache.h
index 482e4b5..568885a 100644
--- a/arch/blackfin/include/asm/cache.h
+++ b/arch/blackfin/include/asm/cache.h
@@ -7,7 +7,7 @@
#ifndef __ARCH_BLACKFIN_CACHE_H
#define __ARCH_BLACKFIN_CACHE_H
-#include/* for asmlinkage */
+#include /* for asmlinkage */
/*
* Bytes per L1 cache line
diff --git a/arch/blackfin/include/asm/linkage.h
b/arch/blackfin/include/asm/linkage.h
index fbb497c..6d4493a 100644
--- a/arch/blackfin/include/asm/linkage.h
+++ b/arch/blackfin/include/asm/linkage.h
@@ -22,53 +22,7 @@
* MA 02110-1301 USA
*/
-#ifndef _LINUX_LINKAGE_H
-#define _LINUX_LINKAGE_H
-
-#include
-
-#ifdef __cplusplus
-#define CPP_ASMLINKAGE extern "C"
-#else
-#define CPP_ASMLINKAGE
-#endif
-
-#define asmlinkage CPP_ASMLINKAGE
-
-#define SYMBOL_NAME_STR(X) #X
-#define SYMBOL_NAME(X) X
-#ifdef __STDC__
-#define SYMBOL_NAME_LABEL(X) X##:
-#else
-#define SYMBOL_NAME_LABEL(X) X:
-#endif
-
-#define __ALIGN .align 4
-#define __ALIGN_STR".align 4"
-
-#ifdef __ASSEMBLY__
-
-#define ALIGN __ALIGN
-#define ALIGN_STR __ALIGN_STR
-
-#define LENTRY(name) \
- ALIGN; \
- SYMBOL_NAME_LABEL(name)
-
-#define ENTRY(name) \
- .globl SYMBOL_NAME(name); \
- LENTRY(name)
-#endif
-
-#ifndef END
-#define END(name) \
- .size name, .-name
-#endif
-
-#ifndef ENDPROC
-#define ENDPROC(name) \
- .type name, @function; \
- END(name)
-#endif
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
#endif
diff --git a/arch/blackfin/lib/__kgdb.S b/arch/blackfin/lib/__kgdb.S
index cba4179..4ccde8f 100644
--- a/arch/blackfin/lib/__kgdb.S
+++ b/arch/blackfin/lib/__kgdb.S
@@ -1,5 +1,5 @@
-#include
+#include
/* save stack context for non-local goto
* int kgdb_setjmp(long *buf)
diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S
index 253d4c3..39d5332 100644
--- a/arch/blackfin/lib/outs.S
+++ b/arch/blackfin/lib/outs.S
@@ -8,7 +8,7 @@
* Licensed under the GPL-2.
*/
-#include
+#include
.align 2
diff --git a/arch/blackfin/include/asm/linkage.h b/include/linux/linkage.h
similarity index 98%
copy from arch/blackfin/include/asm/linkage.h
copy to include/linux/linkage.h
index fbb497c..b8a7067 100644
--- a/arch/blackfin/include/asm/linkage.h
+++ b/include/linux/linkage.h
@@ -25,6 +25,7 @@
#ifndef _LINUX_LINKAGE_H
#define _LINUX_LINKAGE_H
+#include
#include
#ifdef __cplusplus
--
1.7.3.5
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] nds32: add linkage support
Hi Mike, > more than half will use ".align 4". for the few that do not, they can > still > define __ALIGN themselves, and thus the "#ifndef __ALIGN" i quoted above > will > keep it from executing. > -mike > Good! I will fix this up ASAP. :-) -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH 1/2] nds32: add linkage support
Hi Mike, 2011/12/1 Mike Frysinger > On Wednesday 30 November 2011 03:06:42 Macpaul Lin wrote: > > Add linkage support. > > let's add this to our linux/linkage.h: > #ifndef __ALIGN > #define __ALIGN .align 4 > #define __ALIGN_STR ".align 4" > #endif > > i think most arches will be this way > -mike > I'm not sure for this because I've found there exists different configurations for other architectures in Linux. For example, ../../../arch/arm/include/asm/linkage.h:4:#define __ALIGN .align 0 ../../../arch/arm/include/asm/linkage.h:5:#define __ALIGN_STR ".align 0" ../../../arch/avr32/include/asm/linkage.h:4:#define __ALIGN .balign 2 ../../../arch/avr32/include/asm/linkage.h:5:#define __ALIGN_STR ".balign 2" ../../../arch/score/include/asm/linkage.h:4:#define __ALIGN .align 2 ../../../arch/score/include/asm/linkage.h:5:#define __ALIGN_STR ".align 2" -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/2] nds32/ag101/watchdog.S: add linkage support
Add linkage support to watchdog.S. Signed-off-by: Macpaul Lin --- arch/nds32/cpu/n1213/ag101/watchdog.S |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/nds32/cpu/n1213/ag101/watchdog.S b/arch/nds32/cpu/n1213/ag101/watchdog.S index fc39f3f..18f0b66 100644 --- a/arch/nds32/cpu/n1213/ag101/watchdog.S +++ b/arch/nds32/cpu/n1213/ag101/watchdog.S @@ -22,12 +22,12 @@ */ #include +#include .text #ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG -.globl turnoff_watchdog -turnoff_watchdog: +ENTRY(turnoff_watchdog) #define WD_CR 0xC #define WD_ENABLE 0x1 @@ -45,4 +45,5 @@ turnoff_watchdog: ret +ENDPROC(turnoff_watchdog) #endif -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/2] nds32: add linkage support
Add linkage support. Signed-off-by: Macpaul Lin --- arch/nds32/include/asm/linkage.h | 31 +++ 1 files changed, 31 insertions(+), 0 deletions(-) create mode 100644 arch/nds32/include/asm/linkage.h diff --git a/arch/nds32/include/asm/linkage.h b/arch/nds32/include/asm/linkage.h new file mode 100644 index 000..9d6edd9 --- /dev/null +++ b/arch/nds32/include/asm/linkage.h @@ -0,0 +1,31 @@ +/* + * U-boot - linkage.h + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#define __ALIGN .align 4 +#define __ALIGN_STR".align 4" + +#endif -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 1/3] linkage.h: move from blackfin to common includes
Add linkage.h support from blackfin to common include, which is a reduced version from Linux. Signed-off-by: Macpaul Lin --- arch/blackfin/include/asm/linkage.h | 74 --- include/linux/linkage.h | 72 ++ 2 files changed, 72 insertions(+), 74 deletions(-) delete mode 100644 arch/blackfin/include/asm/linkage.h create mode 100644 include/linux/linkage.h diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h deleted file mode 100644 index fbb497c..000 --- a/arch/blackfin/include/asm/linkage.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * U-boot - linkage.h - * - * Copyright (c) 2005-2007 Analog Devices Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#ifndef _LINUX_LINKAGE_H -#define _LINUX_LINKAGE_H - -#include - -#ifdef __cplusplus -#define CPP_ASMLINKAGE extern "C" -#else -#define CPP_ASMLINKAGE -#endif - -#define asmlinkage CPP_ASMLINKAGE - -#define SYMBOL_NAME_STR(X) #X -#define SYMBOL_NAME(X) X -#ifdef __STDC__ -#define SYMBOL_NAME_LABEL(X) X##: -#else -#define SYMBOL_NAME_LABEL(X) X: -#endif - -#define __ALIGN .align 4 -#define __ALIGN_STR".align 4" - -#ifdef __ASSEMBLY__ - -#define ALIGN __ALIGN -#define ALIGN_STR __ALIGN_STR - -#define LENTRY(name) \ - ALIGN; \ - SYMBOL_NAME_LABEL(name) - -#define ENTRY(name) \ - .globl SYMBOL_NAME(name); \ - LENTRY(name) -#endif - -#ifndef END -#define END(name) \ - .size name, .-name -#endif - -#ifndef ENDPROC -#define ENDPROC(name) \ - .type name, @function; \ - END(name) -#endif - -#endif diff --git a/include/linux/linkage.h b/include/linux/linkage.h new file mode 100644 index 000..1081dad --- /dev/null +++ b/include/linux/linkage.h @@ -0,0 +1,72 @@ +/* + * U-boot - linkage.h + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef _LINUX_LINKAGE_H +#define _LINUX_LINKAGE_H + +#include +#include + +#ifdef __cplusplus +#define CPP_ASMLINKAGE extern "C" +#else +#define CPP_ASMLINKAGE +#endif + +#define asmlinkage CPP_ASMLINKAGE + +#define SYMBOL_NAME_STR(X) #X +#define SYMBOL_NAME(X) X +#ifdef __STDC__ +#define SYMBOL_NAME_LABEL(X) X##: +#else +#define SYMBOL_NAME_LABEL(X) X: +#endif + +#ifdef __ASSEMBLY__ + +#define ALIGN __ALIGN +#define ALIGN_STR __ALIGN_STR + +#define LENTRY(name) \ + ALIGN; \ + SYMBOL_NAME_LABEL(name) + +#define ENTRY(name) \ + .globl SYMBOL_NAME(name); \ + LENTRY(name) +#endif + +#ifndef END +#define END(name) \ + .size name, .-name +#endif + +#ifndef ENDPROC +#define ENDPROC(name) \ + .type name, @function; \ + END(name) +#endif + +#endif -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 3/3] blackfin: fix linkage support due to header movement
Fix include path of linkage.h due to header file movement. Signed-off-by: Macpaul Lin --- arch/blackfin/cpu/cache.S |2 +- arch/blackfin/include/asm/blackfin_local.h |2 +- arch/blackfin/include/asm/cache.h |2 +- arch/blackfin/lib/__kgdb.S |2 +- arch/blackfin/lib/outs.S |2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/blackfin/cpu/cache.S b/arch/blackfin/cpu/cache.S index 6ed655a..1e468ee 100644 --- a/arch/blackfin/cpu/cache.S +++ b/arch/blackfin/cpu/cache.S @@ -8,9 +8,9 @@ * Licensed under the GPL-2 or later. */ -#include #include #include +#include .text /* Since all L1 caches work the same way, we use the same method for flushing diff --git a/arch/blackfin/include/asm/blackfin_local.h b/arch/blackfin/include/asm/blackfin_local.h index 71207b6..9d27f31 100644 --- a/arch/blackfin/include/asm/blackfin_local.h +++ b/arch/blackfin/include/asm/blackfin_local.h @@ -48,8 +48,8 @@ #define L1_CACHE_SHIFT 5 #define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT) -#include #include +#include #ifndef __ASSEMBLY__ # ifdef SHARED_RESOURCES diff --git a/arch/blackfin/include/asm/cache.h b/arch/blackfin/include/asm/cache.h index 482e4b5..568885a 100644 --- a/arch/blackfin/include/asm/cache.h +++ b/arch/blackfin/include/asm/cache.h @@ -7,7 +7,7 @@ #ifndef __ARCH_BLACKFIN_CACHE_H #define __ARCH_BLACKFIN_CACHE_H -#include/* for asmlinkage */ +#include /* for asmlinkage */ /* * Bytes per L1 cache line diff --git a/arch/blackfin/lib/__kgdb.S b/arch/blackfin/lib/__kgdb.S index cba4179..4ccde8f 100644 --- a/arch/blackfin/lib/__kgdb.S +++ b/arch/blackfin/lib/__kgdb.S @@ -1,5 +1,5 @@ -#include +#include /* save stack context for non-local goto * int kgdb_setjmp(long *buf) diff --git a/arch/blackfin/lib/outs.S b/arch/blackfin/lib/outs.S index 253d4c3..39d5332 100644 --- a/arch/blackfin/lib/outs.S +++ b/arch/blackfin/lib/outs.S @@ -8,7 +8,7 @@ * Licensed under the GPL-2. */ -#include +#include .align 2 -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH 2/3] blackfin: add architecture part support of linkage.h
add architecture part support of linkage.h Signed-off-by: Macpaul Lin --- arch/blackfin/include/asm/linkage.h | 31 +++ 1 files changed, 31 insertions(+), 0 deletions(-) create mode 100644 arch/blackfin/include/asm/linkage.h diff --git a/arch/blackfin/include/asm/linkage.h b/arch/blackfin/include/asm/linkage.h new file mode 100644 index 000..9d6edd9 --- /dev/null +++ b/arch/blackfin/include/asm/linkage.h @@ -0,0 +1,31 @@ +/* + * U-boot - linkage.h + * + * Copyright (c) 2005-2007 Analog Devices Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_LINKAGE_H +#define __ASM_LINKAGE_H + +#define __ALIGN .align 4 +#define __ALIGN_STR".align 4" + +#endif -- 1.7.3.5 ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/4] nds32/ag102: add ag102 soc support
Hi Mike, 2011/11/30 Macpaul Lin > Hi Mike, > > err, i thought i saw u-boot had this in common code. seems it is not (i >>> must >>> have been looking in the Linux tree). don't worry about it until we get >>> that >>> addressed. >>> -mike >>> >> >> >> > It seems the only architecture related part in this header are the > following codes. > #define __ALIGN .align 4 > #define __ALIGN_STR ".align 4" > > In Linux, the common linkage.h will include only this part from > architectures' local linkage.h. > > I think we can put the common linkage.h in "include/linux" folder is okay. > > I have done this for blackfin also, but when I ran checkpatch to these patches, I've got several warnings and it looks those warnings should not be problem at all. So I'll send these patches to you and hope you can run checkpatch, too and see if there are something need to be fixed. Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/4] nds32/ag102: add ag102 soc support
Hi Mike, 2011/11/30 Macpaul Lin > Hi Mike and Wolfgang, > > 2011/11/30 Mike Frysinger > >> > For supporting this kind of implementation, I must to put header support >> > like linkage.h >> >> err, i thought i saw u-boot had this in common code. seems it is not (i >> must >> have been looking in the Linux tree). don't worry about it until we get >> that >> addressed. >> -mike >> > > > It seems the only architecture related part in this header are the following codes. #define __ALIGN .align 4 #define __ALIGN_STR ".align 4" In Linux, the common linkage.h will include only this part from architectures' local linkage.h. I think we can put the common linkage.h in "include/linux" folder is okay. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/4] nds32/ag102: add ag102 soc support
Hi Mike and Wolfgang, 2011/11/30 Mike Frysinger > > For supporting this kind of implementation, I must to put header support > > like linkage.h > > err, i thought i saw u-boot had this in common code. seems it is not (i > must > have been looking in the Linux tree). don't worry about it until we get > that > addressed. > -mike > I think you can send a patch to move linkage.h to common headers at first, than we can move to this step by step. I'll also fix this in these series of patches with manually added linkage.h to NDS32 architecture. Hope your can do this move sooner hence I do not need to send a commit of adding linkage.h into NDS32. :-) Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Re: [U-Boot] [PATCH v2 2/4] nds32/ag102: add ag102 soc support
Hi Mike, 2011/11/30 Mike Frysinger > On Tuesday 29 November 2011 04:15:05 Macpaul Lin wrote: > > +.globl turnoff_watchdog > > +turnoff_watchdog: > > should be: > ENTRY(turnoff_watchdog) > > > + ret > > and at the end, add: > ENDPROC(turnoff_watchdog) > > seems a lot of the nds32 code could use this fixup ... > -mike > Thanks for your suggestion, however, I'd like to confirm what is the benefits of these kind of implementation? I know there are such code in Linux. One benefits might be alignment (marco ENDPROC), and the other looks like for coding style. For supporting this kind of implementation, I must to put header support like linkage.h from blackfin into nds32's common includes. Currently I don't see other architecture support these kind of code. Would you like to make some comment in more detail and also suggest other custodians? I think if this kind of implementation is good then it is worthy to be adopt to other architectures as well just like Linux. Thanks. -- Best regards, Macpaul Lin ___ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
[U-Boot] [PATCH v2 4/4] board/adp-ag102: add configuration of adp-ag102
board: Add config file of board adp-ag102 Add adp-ag102 into boards.cfg Add adp-ag102 into MAINTAINERS doc: add README of ag102 Signed-off-by: Macpaul Lin --- Changes for v2: - add pci and usb support to board setting adp-ag102.h MAINTAINERS |1 + boards.cfg |1 + doc/README.ag102| 36 include/configs/adp-ag102.h | 375 +++ 4 files changed, 413 insertions(+), 0 deletions(-) create mode 100644 doc/README.ag102 create mode 100644 include/configs/adp-ag102.h diff --git a/MAINTAINERS b/MAINTAINERS index f6f6b72..892829c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1145,6 +1145,7 @@ Macpaul Lin ADP-AG101 N1213 (AG101 SoC) ADP-AG101P N1213 (AG101P XC5 FPGA) + ADP-AG102 N1213f (AG102 SoC with FPU) # # End of MAINTAINERS list # diff --git a/boards.cfg b/boards.cfg index c83d861..13ddbcb 100644 --- a/boards.cfg +++ b/boards.cfg @@ -349,6 +349,7 @@ qi_lb60 mipsxburst qi_lb60 qi nios2-genericnios2 nios2 nios2-generic altera adp-ag101nds32 n1213 adp-ag101 AndesTech ag101 adp-ag101p nds32 n1213 adp-ag101p AndesTech ag101 +adp-ag102nds32 n1213 adp-ag102 AndesTech ag102 PCI5441 nios2 nios2 pci5441 psyent PK1C20 nios2 nios2 pk1c20 psyent EVB64260 powerpc 74xx_7xxevb64260- - EVB64260 diff --git a/doc/README.ag102 b/doc/README.ag102 new file mode 100644 index 000..7d142a7 --- /dev/null +++ b/doc/README.ag102 @@ -0,0 +1,36 @@ +Andes Technology SoC AG102 +== + +AG102 is the second SoC produced by Andes Technology using N1213 CPU core +with FPU and DDR contoller support. +AG102 has integrated both AHB and APB bus and many periphals for application +and product development. + +ADP-AG102 += + +ADP-AG102 is the SoC with AG102 hardcore CPU. + +Configurations +== + +CONFIG_MEM_REMAP: + Doing memory remap is essential for preparing some non-OS or RTOS + applications. + +CONFIG_SKIP_LOWLEVEL_INIT: + If you want to boot this system from SPI ROM and bypass e-bios (the + other boot loader on ROM). You should undefine CONFIG_SKIP_LOWLEVEL_INIT + in "include/configs/adp-ag102.h". + +Build and boot steps + + +build: +1. Prepare the toolchains and make sure the $PATH to toolchains is correct. +2. Use `make adp-ag102` in u-boot root to build the image. + +Burn u-boot to SPI ROM: + + +This section will be added later. diff --git a/include/configs/adp-ag102.h b/include/configs/adp-ag102.h new file mode 100644 index 000..a4628e4 --- /dev/null +++ b/include/configs/adp-ag102.h @@ -0,0 +1,375 @@ +/* + * Copyright (C) 2011 Andes Technology Corporation + * Macpaul Lin, Andes Technology Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include + +/* + * CPU and Board Configuration Options + */ +#define CONFIG_ADP_AG102 + +#define CONFIG_USE_INTERRUPT + +#define CONFIG_SKIP_LOWLEVEL_INIT + +#ifndef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_MEM_REMAP +#endif + +#ifdef CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_TEXT_BASE 0x0420 +#else +#define CONFIG_SYS_TEXT_BASE 0x +#endif + +/* + * Timer + */ + +/* + * According to the discussion in u-boot mailing list before, + * CONFIG_SYS_HZ at 1000 is mandatory. + */ +#define CONFIG_SYS_HZ 1000 +#define CONFIG_SYS_CLK_FREQ(6600 * 2) +#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ + +/* + * Use Externel CLOCK or PCLK + */ +#undef CONFIG_FTRTC010_EXTCLK + +#ifndef CONFIG_FTRTC010_EXTCLK +#define CONFIG_FTRTC010_PCLK +#endif + +#ifdef CONFIG_FTRTC010_EXTCLK +#define TIMER_CLOC
[U-Boot] [PATCH v2 2/4] nds32/ag102: add ag102 soc support
Add lowlevel ag102 soc support.
Signed-off-by: Macpaul Lin
---
Changes for v2:
- cpu.c:
- 1. Remove unused variables.
- 2. Replace while(1) in do_reset by hang().
- 3. Clean up other coding styles.
- timer.c: remove unneccessary static declaration
arch/nds32/cpu/n1213/ag102/Makefile| 58 ++
arch/nds32/cpu/n1213/ag102/cpu.c | 195 ++
arch/nds32/cpu/n1213/ag102/lowlevel_init.S | 297
arch/nds32/cpu/n1213/ag102/timer.c | 205 +++
arch/nds32/cpu/n1213/ag102/watchdog.S | 48 +
5 files changed, 803 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/ag102/Makefile
create mode 100644 arch/nds32/cpu/n1213/ag102/cpu.c
create mode 100644 arch/nds32/cpu/n1213/ag102/lowlevel_init.S
create mode 100644 arch/nds32/cpu/n1213/ag102/timer.c
create mode 100644 arch/nds32/cpu/n1213/ag102/watchdog.S
diff --git a/arch/nds32/cpu/n1213/ag102/Makefile
b/arch/nds32/cpu/n1213/ag102/Makefile
new file mode 100644
index 000..8716c4e
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/Makefile
@@ -0,0 +1,58 @@
+#
+# (C) Copyright 2009
+# Marvell Semiconductor
+# Written-by: Prafulla Wadaskar
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Shawn Lin, Andes Technology Corporation
+# Macpaul Lin, Andes Technology Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(SOC).o
+
+COBJS-y:= cpu.o timer.o
+
+ifndef CONFIG_SKIP_LOWLEVEL_INIT
+SOBJS := lowlevel_init.o
+endif
+
+ifndef CONFIG_SKIP_TRUNOFF_WATCHDOG
+SOBJS += watchdog.o
+endif
+
+SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+
+all: $(obj).depend $(LIB)
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/arch/nds32/cpu/n1213/ag102/cpu.c b/arch/nds32/cpu/n1213/ag102/cpu.c
new file mode 100644
index 000..ed88b52
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/cpu.c
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2002
+ * Sysgo Real-Time Solutions, GmbH
+ * Marius Groeger
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering,
+ *
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* CPU specific code */
+#include
+#include
+#include
+#include
+
+#include
+
+/*
+ * cleanup_before_linux() is called just before we call linux
+ * it prepares the processor for linux
+ *
+ * we disable interrupt and caches.
+ */
+int cleanup_before_linux(void)
+{
+ disable_interrupts();
+
+#ifdef CONFIG_MMU
+ /* turn off I/D-cache */
+ icache_disable();
+ dcache_disable();
+
+ /* flush I/D-cache */
+ invalidate_icac();
+ invalidate_dcac();
+#endif
+
+ return 0;
+}
+
+int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ disable_interrupts();
+
+ /*
+* reset to the base addr of andesboot.
+* currently no ROM loader at addr 0.
+* do not use reset_cpu(0);
+*/
+#ifdef CONFIG_FTWDT010_WATCHDOG
[U-Boot] [PATCH v2 3/4] board/adp-ag102: add board specific files
Add board specific files.
Signed-off-by: Macpaul Lin
---
Changes for v2:
- No change.
board/AndesTech/adp-ag102/Makefile| 43 +
board/AndesTech/adp-ag102/adp-ag102.c | 107 +
2 files changed, 150 insertions(+), 0 deletions(-)
create mode 100644 board/AndesTech/adp-ag102/Makefile
create mode 100644 board/AndesTech/adp-ag102/adp-ag102.c
diff --git a/board/AndesTech/adp-ag102/Makefile
b/board/AndesTech/adp-ag102/Makefile
new file mode 100644
index 000..1cbf2d4
--- /dev/null
+++ b/board/AndesTech/adp-ag102/Makefile
@@ -0,0 +1,43 @@
+#
+# Copyright (C) 2011 Andes Technology Corporation
+# Macpaul Lin, Andes Technology Corporation
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB= $(obj)lib$(BOARD).o
+
+COBJS := adp-ag102.o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+$(LIB):$(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#
diff --git a/board/AndesTech/adp-ag102/adp-ag102.c
b/board/AndesTech/adp-ag102/adp-ag102.c
new file mode 100644
index 000..5a25632
--- /dev/null
+++ b/board/AndesTech/adp-ag102/adp-ag102.c
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Shawn Lin, Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include
+#include
+#include
+
+#include
+#ifdef CONFIG_FTSMC020
+#include
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Miscellaneous platform dependent initializations
+ */
+
+int board_init(void)
+{
+ /*
+* refer to BOOT_PARAMETER_PA_BASE within
+* "linux/arch/nds32/include/asm/misc_spec.h"
+*/
+ gd->bd->bi_arch_number = MACH_TYPE_ADPAG102;
+ gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400;
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ ftsmc020_init();/* initialize Flash */
+#endif /* CONFIG_SYS_NO_FLASH */
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned long sdram_base = PHYS_SDRAM_0;
+ unsigned long expected_size = PHYS_SDRAM_0_SIZE;
+ unsigned long actual_size;
+
+ actual_size = get_ram_size((void *)sdram_base, expected_size);
+
+ gd->ram_size = actual_size;
+
+ if (expected_size != actual_size) {
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+ }
+
+ return 0;
+}
+
+int board_eth_init(bd_t *bd)
+{
+ return ftgmac100_initialize(bd);
+}
+
+#if !defined(CONFIG_SYS_NO_FLASH)
+ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+{
+ if (banknum == 0) { /* non-CFI boot flash */
+ info->portwidth = FLASH_CFI_8BIT;
+ info->chipwidth = FLASH_CFI_BY8;
+ info->interface = FLASH_CFI_X8;
+ return 1;
+ } else {
+ return 0;
+ }
+}
+#endif /* CONFIG_SYS_NO_FLASH */
+
+#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI)
+void pci_init_board(void)
+{
+ /* should be pci_ftpci100_init() */
+ extern void pci_ftpci_init();
+
+ pci_ft
[U-Boot] [PATCH v2 1/4] nds32/ag102: add header support of ag102 soc
Add device address offsets header of ag102 soc.
Add ag102 into mach-types.h.
Add asm-offsets.c for helping convert C headers into asm.
Signed-off-by: Macpaul Lin
---
Changes for v2:
- No change.
arch/nds32/cpu/n1213/ag102/asm-offsets.c | 54
arch/nds32/include/asm/arch-ag102/ag102.h | 97 +
arch/nds32/include/asm/mach-types.h | 14
3 files changed, 165 insertions(+), 0 deletions(-)
create mode 100644 arch/nds32/cpu/n1213/ag102/asm-offsets.c
create mode 100644 arch/nds32/include/asm/arch-ag102/ag102.h
diff --git a/arch/nds32/cpu/n1213/ag102/asm-offsets.c
b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
new file mode 100644
index 000..4769a95
--- /dev/null
+++ b/arch/nds32/cpu/n1213/ag102/asm-offsets.c
@@ -0,0 +1,54 @@
+/*
+ * Adapted from Linux v2.6.36 kernel: arch/powerpc/kernel/asm-offsets.c
+ *
+ * Generate definitions needed by assembly language modules.
+ * This code generates raw asm output which is post-processed to extract
+ * and format the required data.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include
+
+#include
+
+int main(void)
+{
+#ifdef CONFIG_FTSMC020
+ OFFSET(FTSMC020_BANK0_CR, ftsmc020, bank[0].cr);
+ OFFSET(FTSMC020_BANK0_TPR, ftsmc020, bank[0].tpr);
+#endif
+ BLANK();
+#ifdef CONFIG_FTAHBC020S
+ OFFSET(FTAHBC020S_SLAVE_BSR_6, ftahbc02s, s_bsr[6]);
+ OFFSET(FTAHBC020S_CR, ftahbc02s, cr);
+#endif
+ BLANK();
+#ifdef CONFIG_ANDES_PCU
+ OFFSET(ANDES_PCU_PCS4, andes_pcu, pcs4.parm); /* 0x104 */
+#endif
+ BLANK();
+#ifdef CONFIG_DWCDDR21MCTL
+ OFFSET(DWCDDR21MCTL_CCR,dwcddr21mctl, ccr); /* 0x04 */
+ OFFSET(DWCDDR21MCTL_DCR,dwcddr21mctl, dcr); /* 0x04 */
+ OFFSET(DWCDDR21MCTL_IOCR, dwcddr21mctl, iocr);/* 0x08 */
+ OFFSET(DWCDDR21MCTL_CSR,dwcddr21mctl, csr); /* 0x0c */
+ OFFSET(DWCDDR21MCTL_DRR,dwcddr21mctl, drr); /* 0x10 */
+ OFFSET(DWCDDR21MCTL_DLLCR0, dwcddr21mctl, dllcr[0]); /* 0x24 */
+ OFFSET(DWCDDR21MCTL_DLLCR1, dwcddr21mctl, dllcr[1]); /* 0x28 */
+ OFFSET(DWCDDR21MCTL_DLLCR2, dwcddr21mctl, dllcr[2]); /* 0x2c */
+ OFFSET(DWCDDR21MCTL_DLLCR3, dwcddr21mctl, dllcr[3]); /* 0x30 */
+ OFFSET(DWCDDR21MCTL_DLLCR4, dwcddr21mctl, dllcr[4]); /* 0x34 */
+ OFFSET(DWCDDR21MCTL_DLLCR5, dwcddr21mctl, dllcr[5]); /* 0x38 */
+ OFFSET(DWCDDR21MCTL_DLLCR6, dwcddr21mctl, dllcr[6]); /* 0x3c */
+ OFFSET(DWCDDR21MCTL_DLLCR7, dwcddr21mctl, dllcr[7]); /* 0x40 */
+ OFFSET(DWCDDR21MCTL_DLLCR8, dwcddr21mctl, dllcr[8]); /* 0x44 */
+ OFFSET(DWCDDR21MCTL_DLLCR9, dwcddr21mctl, dllcr[9]); /* 0x48 */
+ OFFSET(DWCDDR21MCTL_RSLR0, dwcddr21mctl, rslr[0]); /* 0x4c */
+ OFFSET(DWCDDR21MCTL_RDGR0, dwcddr21mctl, rdgr[0]); /* 0x5c */
+ OFFSET(DWCDDR21MCTL_DTAR, dwcddr21mctl, dtar);/* 0xa4 */
+ OFFSET(DWCDDR21MCTL_MR, dwcddr21mctl, mr); /* 0x1f0 */
+#endif
+ return 0;
+}
diff --git a/arch/nds32/include/asm/arch-ag102/ag102.h
b/arch/nds32/include/asm/arch-ag102/ag102.h
new file mode 100644
index 000..a12a8c5
--- /dev/null
+++ b/arch/nds32/include/asm/arch-ag102/ag102.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2011 Andes Technology Corporation
+ * Macpaul Lin, Andes Technology Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __AG102_H
+#define __AG102_H
+
+/*
+ * Hardware register bases
+ */
+
+/* PCI Controller */
+#define CONFIG_FTPCI100_BASE 0x9000
+/* LPC Controller */
+#define CONFIG_LPC_IO_BASE 0x9010
+/* LPC Controller */
+#define CONFIG_LPC_BASE0x9020
+
+/* NDS32 Data Local Memory 01 */
+#define CONFIG_NDS_DLM1_BASE 0x9030
+/* NDS32 Data Local Memory 02 */
+#define CONFIG_NDS_DLM2_BASE 0x9040
+
+/* Synopsys DWC DDR2/1 Controller */
+#define CONFIG_DWCDDR21MCTL_BASE 0x9050
+/* DMA Controller */
+#define CONFIG_FTDMAC020_BASE 0x9060
+/* FTIDE020_S IDE (ATA) Controller */
+#define
