[PATCH 8/8] video: rockchip: dw_mipi_dsi: Fix GRF access

2023-05-22 Thread megi
From: Ondrej Jirman 

Use proper register base and access method to access GRF registers.
GRF registers start at a completely different base, and need special
access method, that sets the change mask in the 16 MSBs.

Signed-off-by: Ondrej Jirman 
---
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 16 ++--
 1 file changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c 
b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index fd885ac8ccb6..117c3db21ac1 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -18,6 +18,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -30,6 +31,9 @@
 #include 
 #include 
 
+#include 
+#include 
+
 #define USEC_PER_SEC   100L
 
 /*
@@ -197,6 +201,7 @@ struct dw_rockchip_dsi_priv {
struct mipi_dsi_device device;
void __iomem *base;
struct udevice *panel;
+   void __iomem *grf;
 
/* Optional external dphy */
struct phy phy;
@@ -752,16 +757,13 @@ static int dw_mipi_dsi_rockchip_set_bl(struct udevice 
*dev, int percent)
 static void dw_mipi_dsi_rockchip_config(struct dw_rockchip_dsi_priv *dsi)
 {
if (dsi->cdata->lanecfg1_grf_reg)
-   dsi_write(dsi, dsi->cdata->lanecfg1_grf_reg,
- dsi->cdata->lanecfg1);
+   rk_setreg(dsi->grf + dsi->cdata->lanecfg1_grf_reg, 
dsi->cdata->lanecfg1);
 
if (dsi->cdata->lanecfg2_grf_reg)
-   dsi_write(dsi, dsi->cdata->lanecfg2_grf_reg,
- dsi->cdata->lanecfg2);
+   rk_setreg(dsi->grf + dsi->cdata->lanecfg2_grf_reg, 
dsi->cdata->lanecfg2);
 
if (dsi->cdata->enable_grf_reg)
-   dsi_write(dsi, dsi->cdata->enable_grf_reg,
- dsi->cdata->enable);
+   rk_setreg(dsi->grf + dsi->cdata->enable_grf_reg, 
dsi->cdata->enable);
 }
 
 static int dw_mipi_dsi_rockchip_bind(struct udevice *dev)
@@ -794,6 +796,8 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
return -EINVAL;
}
 
+   priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+
i = 0;
while (cdata[i].reg) {
if (cdata[i].reg == (fdt_addr_t)priv->base) {
-- 
2.40.1



[PATCH 7/8] video: rockchip: dw_mipi_dsi: Correct check for lacking phy phandle

2023-05-22 Thread megi
From: Ondrej Jirman 

If phy is not defined in DT (eg. on rk3399), generic_phy_get_by_name
will return -ENODATA. Handle that case correctly.

Signed-off-by: Ondrej Jirman 
---
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c 
b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index 6d8b1e6f541a..fd885ac8ccb6 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -814,9 +814,9 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
 * NULL if it's not initialized.
 */
ret = generic_phy_get_by_name(dev, "dphy", >phy);
-   if ((ret) && (ret != -ENODEV)) {
+   if (ret && ret != -ENODATA) {
dev_err(dev, "failed to get mipi dphy: %d\n", ret);
-   return -EINVAL;
+   return ret;
}
 
priv->pclk = devm_clk_get(dev, "pclk");
-- 
2.40.1



[PATCH 6/8] video: rockchip: dw_mipi_dsi: Fix best_rate calculation

2023-05-22 Thread megi
From: Ondrej Jirman 

pllref_clk is unused after being retrieved. fin needs to be set
to dsi->ref clock's rate for the following calculation to work.
Otherwise fin is undefined, and calculation return bogus number
based on undefined variable.

Signed-off-by: Ondrej Jirman 
---
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c 
b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index 5e8db6bd2e63..6d8b1e6f541a 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -505,7 +505,6 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct 
display_timing *timings,
unsigned int _prediv, best_prediv;
unsigned long _fbdiv, best_fbdiv;
unsigned long min_delta = ULONG_MAX;
-   unsigned int pllref_clk;
 
bpp = mipi_dsi_pixel_format_to_bpp(format);
if (bpp < 0) {
@@ -537,7 +536,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct 
display_timing *timings,
return 0;
}
 
-   pllref_clk = clk_get_rate(dsi->ref);
+   fin = clk_get_rate(dsi->ref);
fout = target_mbps * USEC_PER_SEC;
 
/* constraint: 5Mhz <= Fref / N <= 40MHz */
-- 
2.40.1



[PATCH 4/8] video: rockchip: dw_mipi_dsi: Fix error path checks in probe function

2023-05-22 Thread megi
From: Ondrej Jirman 

Wrong return codes were checked in several places. Check the proper ones.

Signed-off-by: Ondrej Jirman 
---
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c 
b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index b1b5328595e0..b7d6b51703c0 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -822,6 +822,7 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
 
priv->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(priv->pclk)) {
+   ret = PTR_ERR(priv->pclk);
dev_err(dev, "peripheral clock get error %d\n", ret);
return ret;
}
@@ -833,7 +834,8 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
 
} else {
priv->ref = devm_clk_get(dev, "ref");
-   if (ret) {
+   if (IS_ERR(priv->ref)) {
+   ret = PTR_ERR(priv->ref);
dev_err(dev, "pll reference clock get error %d\n", ret);
return ret;
}
@@ -841,7 +843,8 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
 
priv->rst = devm_reset_control_get_by_index(device->dev, 0);
if (IS_ERR(priv->rst)) {
-   dev_err(dev, "missing dsi hardware reset\n");
+   ret = PTR_ERR(priv->rst);
+   dev_err(dev, "missing dsi hardware reset %d\n", ret);
return ret;
}
 
-- 
2.40.1



[PATCH 5/8] video: rockchip: dw_mipi_dsi: Return 0 from dsi_phy_init on success

2023-05-22 Thread megi
From: Ondrej Jirman 

ret is undefined if external phy is not used resulting in bogus
error being returned in that scenario.

Signed-off-by: Ondrej Jirman 
---
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c 
b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index b7d6b51703c0..5e8db6bd2e63 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -460,7 +460,7 @@ static int dsi_phy_init(void *priv_data)
dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL,
  BIT(5) | ns2bc(dsi, 100));
 
-   return ret;
+   return 0;
 }
 
 static void dsi_phy_post_set_mode(void *priv_data, unsigned long mode_flags)
-- 
2.40.1



[PATCH 3/8] video: rockchip: dw_mipi_dsi: Fix external phy existnece check

2023-05-22 Thread megi
From: Ondrej Jirman 

>phy is always true. Compiler warns about this loudly.

Use a propper check for phy device allocation. Without this fix
using this driver with SoC that doesn't use external phy (eg. RK3399)
doesn't work.

Signed-off-by: Ondrej Jirman 
---
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c 
b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
index ca548a60b750..b1b5328595e0 100644
--- a/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
+++ b/drivers/video/rockchip/dw_mipi_dsi_rockchip.c
@@ -344,7 +344,7 @@ static int dsi_phy_init(void *priv_data)
struct dw_rockchip_dsi_priv *dsi = dev_get_priv(dev);
int ret, i, vco;
 
-   if (>phy) {
+   if (dsi->phy.dev) {
ret = generic_phy_configure(>phy, >phy_opts);
if (ret) {
dev_err(dsi->dsi_host,
@@ -527,7 +527,7 @@ dw_mipi_dsi_get_lane_mbps(void *priv_data, struct 
display_timing *timings,
}
 
/* for external phy only the mipi_dphy_config is necessary */
-   if (>phy) {
+   if (dsi->phy.dev) {
phy_mipi_dphy_get_default_config(timings->pixelclock.typ  * 10 
/ 8,
 bpp, lanes,
 >phy_opts);
@@ -827,7 +827,7 @@ static int dw_mipi_dsi_rockchip_probe(struct udevice *dev)
}
 
/* Get a ref clock only if not using an external phy. */
-   if (>phy) {
+   if (priv->phy.dev) {
dev_dbg(dev, "setting priv->ref to NULL\n");
priv->ref = NULL;
 
-- 
2.40.1



[PATCH 1/8] video: rockchip: vop: Fix whitespace

2023-05-22 Thread megi
From: Ondrej Jirman 

Fix confusing use of indentation.

Signed-off-by: Ondrej Jirman 
---
 drivers/video/rockchip/rk_vop.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/video/rockchip/rk_vop.c b/drivers/video/rockchip/rk_vop.c
index dab9902fda73..c514e2a0e449 100644
--- a/drivers/video/rockchip/rk_vop.c
+++ b/drivers/video/rockchip/rk_vop.c
@@ -432,7 +432,7 @@ int rk_vop_probe(struct udevice *dev)
ret = reset_assert(_rst);
if (ret) {
dev_err(dev, "failed to assert ahb reset (ret=%d)\n", ret);
-   return ret;
+   return ret;
}
udelay(20);
 
-- 
2.40.1



[PATCH 2/8] video: dw_mipi_dsi: Fix hsync/vsync settings

2023-05-22 Thread megi
From: Ondrej Jirman 

These must be read from timings->flags, like other DSI HOST drivers do.

And they must not be inverted either. Low means low.

Without this fix, panel drivers that set *SYNC_LOW produce corrupted
output on screen (shifted horizobnntally and vertivally by back porch
distance).

Signed-off-by: Ondrej Jirman 
---
 drivers/video/dw_mipi_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/video/dw_mipi_dsi.c b/drivers/video/dw_mipi_dsi.c
index 92e388ac1e42..22fef7e8825f 100644
--- a/drivers/video/dw_mipi_dsi.c
+++ b/drivers/video/dw_mipi_dsi.c
@@ -538,9 +538,9 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
break;
}
 
-   if (device->mode_flags & DISPLAY_FLAGS_VSYNC_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_VSYNC_LOW)
val |= VSYNC_ACTIVE_LOW;
-   if (device->mode_flags & DISPLAY_FLAGS_HSYNC_HIGH)
+   if (timings->flags & DISPLAY_FLAGS_HSYNC_LOW)
val |= HSYNC_ACTIVE_LOW;
 
dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
-- 
2.40.1



[PATCH 0/8] Some fixes for the rockchip dw_mipi_dsi driver

2023-05-22 Thread megi
From: Ondrej Jirman 

These are just random fixes for bugs I found while eyeballing the code and 
porting
it to work with RK3399.

Please take a look.

Thank you and regards,
Ondrej Jirman

Ondrej Jirman (8):
  video: rockchip: vop: Fix whitespace
  video: dw_mipi_dsi: Fix hsync/vsync settings
  video: rockchip: dw_mipi_dsi: Fix external phy existnece check
  video: rockchip: dw_mipi_dsi: Fix error path checks in probe function
  video: rockchip: dw_mipi_dsi: Return 0 from dsi_phy_init on success
  video: rockchip: dw_mipi_dsi: Fix best_rate calculation
  video: rockchip: dw_mipi_dsi: Correct check for lacking phy phandle
  video: rockchip: dw_mipi_dsi: Fix GRF access

 drivers/video/dw_mipi_dsi.c   |  4 +-
 drivers/video/rockchip/dw_mipi_dsi_rockchip.c | 38 +++
 drivers/video/rockchip/rk_vop.c   |  2 +-
 3 files changed, 25 insertions(+), 19 deletions(-)

-- 
2.40.1