On Thursday, March 9, 2017 at 12:36:31 AM UTC+1, Jernej Škrabec wrote:
>
> Designware HDMI controller and phy are used in other SoCs as well. Split
> out platform independent code.
>
> DW HDMI has 8 bit registers but they can be represented as 32 bit
> registers as well. Add support to select access mode.
>
> EDID reading code use reading by blocks which is not supported by other
> SoCs in general. Make it more general using byte by byte approach, which
> is also used in Linux driver.
>
> Finally, not all DW HDMI controllers are accompanied with DW HDMI phy.
> Support custom phys by making controller code independent from phy code.
>
> Signed-off-by: Jernej Skrabec >
> ---
>
> arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h | 456 --
> drivers/video/dw_hdmi.c | 764
> +++
> drivers/video/rockchip/Makefile | 2 +-
> drivers/video/rockchip/rk_hdmi.c | 757
> +-
> drivers/video/rockchip/rk_vop.c | 1 -
> include/dw_hdmi.h| 486 ++
> 6 files changed, 1275 insertions(+), 1191 deletions(-)
> delete mode 100644 arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
> create mode 100644 drivers/video/dw_hdmi.c
> create mode 100644 include/dw_hdmi.h
>
> diff --git a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
> b/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
> deleted file mode 100644
> index 0b51d40882..00
> --- a/arch/arm/include/asm/arch-rockchip/hdmi_rk3288.h
> +++ /dev/null
> @@ -1,456 +0,0 @@
> -/*
> - * Copyright (c) 2015 Google, Inc
> - * Copyright 2014 Rockchip Inc.
> - * Copyright (C) 2011 Freescale Semiconductor, Inc.
> - *
> - * SPDX-License-Identifier:GPL-2.0+
> - */
> -
> -#ifndef _ASM_ARCH_HDMI_H
> -#define _ASM_ARCH_HDMI_H
> -
> -
> -#define HDMI_EDID_BLOCK_SIZE128
> -
> -struct rk3288_hdmi {
> -u32 reserved0[0x100];
> -u32 ih_fc_stat0;
> -u32 ih_fc_stat1;
> -u32 ih_fc_stat2;
> -u32 ih_as_stat0;
> -u32 ih_phy_stat0;
> -u32 ih_i2cm_stat0;
> -u32 ih_cec_stat0;
> -u32 ih_vp_stat0;
> -u32 ih_i2cmphy_stat0;
> -u32 ih_ahbdmaaud_stat0;
> -u32 reserved1[0x17f-0x109];
> -u32 ih_mute_fc_stat0;
> -u32 ih_mute_fc_stat1;
> -u32 ih_mute_fc_stat2;
> -u32 ih_mute_as_stat0;
> -u32 ih_mute_phy_stat0;
> -u32 ih_mute_i2cm_stat0;
> -u32 ih_mute_cec_stat0;
> -u32 ih_mute_vp_stat0;
> -u32 ih_mute_i2cmphy_stat0;
> -u32 ih_mute_ahbdmaaud_stat0;
> -u32 reserved2[0x1fe - 0x189];
> -u32 ih_mute;
> -u32 tx_invid0;
> -u32 tx_instuffing;
> -u32 tx_gydata0;
> -u32 tx_gydata1;
> -u32 tx_rcrdata0;
> -u32 tx_rcrdata1;
> -u32 tx_bcbdata0;
> -u32 tx_bcbdata1;
> -u32 reserved3[0x7ff-0x207];
> -u32 vp_status;
> -u32 vp_pr_cd;
> -u32 vp_stuff;
> -u32 vp_remap;
> -u32 vp_conf;
> -u32 vp_stat;
> -u32 vp_int;
> -u32 vp_mask;
> -u32 vp_pol;
> -u32 reserved4[0xfff-0x808];
> -u32 fc_invidconf;
> -u32 fc_inhactv0;
> -u32 fc_inhactv1;
> -u32 fc_inhblank0;
> -u32 fc_inhblank1;
> -u32 fc_invactv0;
> -u32 fc_invactv1;
> -u32 fc_invblank;
> -u32 fc_hsyncindelay0;
> -u32 fc_hsyncindelay1;
> -u32 fc_hsyncinwidth0;
> -u32 fc_hsyncinwidth1;
> -u32 fc_vsyncindelay;
> -u32 fc_vsyncinwidth;
> -u32 fc_infreq0;
> -u32 fc_infreq1;
> -u32 fc_infreq2;
> -u32 fc_ctrldur;
> -u32 fc_exctrldur;
> -u32 fc_exctrlspac;
> -u32 fc_ch0pream;
> -u32 fc_ch1pream;
> -u32 fc_ch2pream;
> -u32 fc_aviconf3;
> -u32 fc_gcp;
> -u32 fc_aviconf0;
> -u32 fc_aviconf1;
> -u32 fc_aviconf2;
> -u32 fc_avivid;
> -u32 fc_avietb0;
> -u32 fc_avietb1;
> -u32 fc_avisbb0;
> -u32 fc_avisbb1;
> -u32 fc_avielb0;
> -u32 fc_avielb1;
> -u32 fc_avisrb0;
> -u32 fc_avisrb1;
> -u32 fc_audiconf0;
> -u32 fc_audiconf1;
> -u32 fc_audiconf2;
> -u32 fc_audiconf3;
> -u32 fc_vsdieeeid0;
> -u32 fc_vsdsize;
> -u32 reserved7[0x2fff-0x102a];
> -u32 phy_conf0;
> -u32 phy_tst0;
> -u32 phy_tst1;
> -u32 phy_tst2;
> -u32 phy_stat0;
> -u32 phy_int0;
> -u32 phy_mask0;
> -u32 phy_pol0;
> -u32 reserved8[0x301f-0x3007];
> -u32 phy_i2cm_slave_addr;
> -u32 phy_i2cm_address_addr;
> -u32 phy_i2cm_datao_1_ad
