[Agilex7 M-series Platform Enablement v1 16/16] configs: Add defconfig for Agilex7 M-series
From: Wan Yee Lau
Add defconfig for Agilex7 M-series.
Signed-off-by: Wan Yee Lau
Signed-off-by: Teik Heng Chong
Signed-off-by: Tingting Meng
---
...onfig => socfpga_agilex7m_sdmmc_defconfig} | 110 +-
1 file changed, 54 insertions(+), 56 deletions(-)
copy configs/{socfpga_agilex5_defconfig => socfpga_agilex7m_sdmmc_defconfig}
(56%)
diff --git a/configs/socfpga_agilex5_defconfig
b/configs/socfpga_agilex7m_sdmmc_defconfig
similarity index 56%
copy from configs/socfpga_agilex5_defconfig
copy to configs/socfpga_agilex7m_sdmmc_defconfig
index f39954aea8..12414e2e5f 100644
--- a/configs/socfpga_agilex5_defconfig
+++ b/configs/socfpga_agilex7m_sdmmc_defconfig
@@ -1,50 +1,69 @@
CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=4
CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds"
-CONFIG_SYS_SPI_U_BOOT_OFFS=0x0400
CONFIG_ARCH_SOCFPGA=y
-CONFIG_TEXT_BASE=0x8020
+CONFIG_TEXT_BASE=0x20
CONFIG_SYS_MALLOC_F_LEN=0x2000
-CONFIG_NR_DRAM_BANKS=2
+CONFIG_NR_DRAM_BANKS=1
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0x0410
+CONFIG_ENV_SECT_SIZE=0x2
+CONFIG_SYS_SPI_U_BOOT_OFFS=0x0400
CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex5_socdk"
-CONFIG_TARGET_SOCFPGA_AGILEX5_SOCDK=y
-CONFIG_IDENT_STRING="socfpga_agilex5"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex7m_socdk"
+CONFIG_SPL_TEXT_BASE=0xFFE0
+CONFIG_TARGET_SOCFPGA_AGILEX7M_SOCDK=y
+CONFIG_IDENT_STRING="socfpga_agilex7m"
CONFIG_SPL_FS_FAT=y
CONFIG_DISTRO_DEFAULTS=y
CONFIG_FIT=y
CONFIG_SPL_FIT_SIGNATURE=y
CONFIG_SPL_LOAD_FIT=y
-CONFIG_SPL_LOAD_FIT_ADDRESS=0x8200
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x0200
+CONFIG_SYS_LOAD_ADDR=0x0200
# CONFIG_USE_SPL_FIT_GENERATOR is not set
-CONFIG_QSPI_BOOT=y
+# CONFIG_NAND_BOOT is not set
+# CONFIG_QSPI_BOOT is not set
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttyS0,115200 initrd=0x9000 root=/dev/ram0 rw
init=/sbin/init ramdisk_size=1000 earlycon panic=-1 nosmp kvm-arm.mode=nvhe"
-CONFIG_LEGACY_IMAGE_FORMAT=y
+CONFIG_BOOTARGS="earlycon panic=-1"
# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x30
+CONFIG_SPL_MAX_SIZE=0x4
+CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
+CONFIG_SPL_BSS_START_ADDR=0x3ff0
+# CONFIG_SPL_SHARES_INIT_SP_ADDR is not set
+CONFIG_SPL_STACK=0xffe3f000
+CONFIG_SPL_SYS_MALLOC=y
+CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
+CONFIG_CUSTOM_SPL_SYS_MALLOC_ADDR=0x3fa0
+CONFIG_SPL_SYS_MALLOC_SIZE=0x50
+CONFIG_SPL_BSS_MAX_SIZE=0x10
CONFIG_SPL_CRC32=y
+CONFIG_SPL_MTD_SUPPORT=y
+# CONFIG_SPL_NAND_SUPPORT is not set
CONFIG_SPL_CACHE=y
+CONFIG_SPL_SPI_LOAD=y
CONFIG_SPL_ATF=y
CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
-CONFIG_SYS_PROMPT="SOCFPGA_AGILEX5 # "
+CONFIG_SYS_PROMPT="SOCFPGA_AGILEX7M # "
CONFIG_CMD_NVEDIT_SELECT=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_I2C=y
-CONFIG_CMD_SF=y
-CONFIG_DOS_PARTITION=y
-CONFIG_SPL_DOS_PARTITION=y
-CONFIG_SPL_SYS_DISABLE_DCACHE_OPS=y
+CONFIG_CMD_MMC=y
CONFIG_CMD_MTD=y
-# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+# CONFIG_CMD_NAND_TRIMFFS is not set
+# CONFIG_CMD_NAND_LOCK_UNLOCK is not set
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
CONFIG_CMD_CACHE=y
CONFIG_SPL_SPI_FLASH_MTD=y
CONFIG_SPI_FLASH_MTD=y
-CONFIG_SPL_MTD_SUPPORT=y
+CONFIG_MTDIDS_DEFAULT="nand0=ffb9.nand.0"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb9.nand.0:2m(u-boot),-(root)"
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
CONFIG_CMD_UBI=y
CONFIG_CMD_UBIFS=y
CONFIG_MTD_UBI=y
@@ -53,9 +72,8 @@ CONFIG_MTD_UBI_BEB_LIMIT=20
# CONFIG_ISO_PARTITION is not set
# CONFIG_EFI_PARTITION is not set
CONFIG_OF_LIST=""
-CONFIG_ENV_IS_IN_UBI=y
-CONFIG_ENV_UBI_PART="root"
-CONFIG_ENV_UBI_VOLUME="env"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="0:1"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM_SEQ_ALIAS=y
@@ -65,52 +83,32 @@ CONFIG_DWAPB_GPIO=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y
CONFIG_MISC=y
+CONFIG_MMC_DW=y
+CONFIG_SYS_MMC_MAX_BLK_COUNT=256
CONFIG_MTD=y
CONFIG_DM_MTD=y
+# CONFIG_NAND_DENALI_DT is not set
+# CONFIG_SYS_NAND_U_BOOT_LOCATIONS is not set
+CONFIG_SYS_NAND_U_BOOT_OFFS=0x0
+CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x10
+CONFIG_SPL_NAND_FRAMEWORK=y
CONFIG_SF_DEFAULT_MODE=0x2003
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_UBI_SILENCE_MSG=y
+CONFIG_PHY_MICREL=y
+CONFIG_PHY_MICREL_KSZ90X1=y
CONFIG_DM_ETH=y
-CONFIG_RGMII=y
+CONFIG_ETH_DESIGNWARE=y
+CONFIG_MII=y
CONFIG_DM_RESET=y
CONFIG_SYS_NS16550_MEM32=y
CONFIG_SPI=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
+# CONFIG_CADENCE_QSPI is not set
+# CONFIG_DESIGNWARE_SPI is not set
CONFIG_USB=y
+CONFIG_DM_USB=y
CONFIG_USB_DWC2=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_UBIFS_SILENCE_MSG=y
+CONFIG_DESIGNWARE_WATCHDOG=y
+CONFIG_WDT=y
# CONFIG_SPL_USE_TINY_
[Agilex7 M-series Platform Enablement v1 15/16] arch: arm: dts: Update Makefile for new platform Agilex7 M-series
From: Wan Yee Lau Update Makefile to support Agilex7 M-series platform enablement. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/dts/Makefile | 1 + arch/arm/mach-socfpga/Makefile | 18 ++ board/intel/agilex7m-socdk/Makefile | 7 +++ 3 files changed, 26 insertions(+) create mode 100644 board/intel/agilex7m-socdk/Makefile diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 7b7788f755..c056e0e78e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -547,6 +547,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_agilex_socdk.dtb\ socfpga_agilex5_socdk.dtb \ + socfpga_agilex7m_socdk.dtb \ socfpga_arria5_secu1.dtb\ socfpga_arria5_socdk.dtb\ socfpga_arria10_chameleonv3_270_2.dtb \ diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile index 67c6a8dfec..856fd597f6 100644 --- a/arch/arm/mach-socfpga/Makefile +++ b/arch/arm/mach-socfpga/Makefile @@ -65,6 +65,21 @@ obj-y+= reset_manager_s10.o obj-y += wrap_pll_config_soc64.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +obj-y += clock_manager_agilex.o +obj-y += lowlevel_init_soc64.o +obj-y += mailbox_s10.o +obj-y += misc_soc64.o +obj-y += mmu-arm64_s10.o +obj-y += reset_manager_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += secure_vab.o +obj-y += system_manager_soc64.o +obj-y += timer_s10.o +obj-$(CONFIG_SOCFPGA_SECURE_VAB_AUTH) += vab.o +obj-y += wrap_handoff_soc64.o +obj-y += wrap_pll_config_soc64.o +endif + ifdef CONFIG_TARGET_SOCFPGA_N5X obj-y += clock_manager_n5x.o obj-y += lowlevel_init_soc64.o @@ -107,6 +122,9 @@ endif ifdef CONFIG_TARGET_SOCFPGA_AGILEX5 obj-y += spl_soc64.o endif +ifdef CONFIG_TARGET_SOCFPGA_AGILEX7M +obj-y += spl_agilex7m.o +endif else obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o obj-$(CONFIG_SPL_ATF) += smc_api.o diff --git a/board/intel/agilex7m-socdk/Makefile b/board/intel/agilex7m-socdk/Makefile new file mode 100644 index 00..ff5d9dde3b --- /dev/null +++ b/board/intel/agilex7m-socdk/Makefile @@ -0,0 +1,7 @@ + +# Copyright (C) 2024 Intel Corporation +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := socfpga.o -- 2.25.1
[Agilex7 M-series Platform Enablement v1 14/16] arch: arm: mach-socfpga: Update kconfig for new platform Agilex7 M-series
From: Wan Yee Lau Update Kconfig for new platform Agilex7 M-series. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/Kconfig | 4 +++- arch/arm/mach-socfpga/Kconfig | 19 +++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 56e190adf6..f68b680d82 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -32,7 +32,9 @@ config COUNTER_FREQUENCY ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036 default 2500 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A default 1 if ARCH_ZYNQMP - default 2 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 + default 4 if ARCH_SOCFPGA && ARM64 && !TARGET_SOCFPGA_AGILEX7M + default 2 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5 && \ + TARGET_SOCFPGA_AGILEX7M default 0 help For platforms with ARMv8-A and ARMv7-A which features a system diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig index 1008232cac..2ca6336f21 100644 --- a/arch/arm/mach-socfpga/Kconfig +++ b/arch/arm/mach-socfpga/Kconfig @@ -59,6 +59,18 @@ config TARGET_SOCFPGA_AGILEX select SPL_CLK if SPL select TARGET_SOCFPGA_SOC64 +config TARGET_SOCFPGA_AGILEX7M + bool + select ARMV8_MULTIENTRY + select ARMV8_SET_SMPEN + select BINMAN if SPL_ATF + select CLK + select FPGA_INTEL_SDM_MAILBOX + select GICV2 + select NCORE_CACHE + select SPL_CLK if SPL + select TARGET_SOCFPGA_SOC64 + config TARGET_SOCFPGA_AGILEX5 bool select BINMAN if SPL_ATF @@ -139,6 +151,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK bool "Intel SOCFPGA SoCDK (Agilex)" select TARGET_SOCFPGA_AGILEX +config TARGET_SOCFPGA_AGILEX7M_SOCDK + bool "Intel SOCFPGA SoCDK (Agilex7 M-series)" + select TARGET_SOCFPGA_AGILEX7M + config TARGET_SOCFPGA_AGILEX5_SOCDK bool "Intel SOCFPGA SoCDK (Agilex5)" select TARGET_SOCFPGA_AGILEX5 @@ -216,6 +232,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT endchoice config SYS_BOARD + default "agilex7m-socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK @@ -238,6 +255,7 @@ config SYS_BOARD default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA config SYS_VENDOR + default "intel" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK default "intel" if TARGET_SOCFPGA_N5X_SOCDK @@ -261,6 +279,7 @@ config SYS_SOC default "socfpga" config SYS_CONFIG_NAME + default "socfpga_agilex7m_socdk" if TARGET_SOCFPGA_AGILEX7M_SOCDK default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1 -- 2.25.1
[Agilex7 M-series Platform Enablement v1 13/16] ddr: altera: soc64: Fix dram size calculation in clamshell mode
From: Teik Heng Chong
This patch is to fix wrong memory size calculation in clamshell mode
Signed-off-by: Teik Heng Chong
Signed-off-by: Tingting Meng
---
drivers/ddr/altera/sdram_soc64.c | 16 +++-
drivers/ddr/altera/sdram_soc64.h | 5 +
2 files changed, 20 insertions(+), 1 deletion(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index 8f2085f3a0..27580cce2f 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -27,6 +27,9 @@
#define PGTABLE_OFF0x4000
+#define SINGLE_RANK_CLAMSHELL 0xC3C3
+#define DUAL_RANK_CLAMSHELL0xA5A5
+
#if !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
u32 hmc_readl(struct altera_sdram_plat *plat, u32 reg)
{
@@ -240,8 +243,19 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat
*plat)
{
u32 dramaddrw = hmc_readl(plat, DRAMADDRW);
+ u32 reg_ctrlcfg6_value = hmc_readl(plat, CTRLCFG6);
+ u32 cs_rank = CTRLCFG6_CFG_CS_CHIP(reg_ctrlcfg6_value);
+ u32 cs_addr_width;
+
+ if (cs_rank == SINGLE_RANK_CLAMSHELL)
+ cs_addr_width = 0;
+ else if (cs_rank == DUAL_RANK_CLAMSHELL)
+ cs_addr_width = 1;
+ else
+ cs_addr_width = DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw);
+
phys_size_t size = (phys_size_t)1 <<
- (DRAMADDRW_CFG_CS_ADDR_WIDTH(dramaddrw) +
+ (cs_addr_width +
DRAMADDRW_CFG_BANK_GRP_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_BANK_ADDR_WIDTH(dramaddrw) +
DRAMADDRW_CFG_ROW_ADDR_WIDTH(dramaddrw) +
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index add7df01a5..8b3b53cf5d 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -78,6 +78,8 @@ struct altera_sdram_plat {
#define CTRLCFG0 0x28
#define CTRLCFG1 0x2c
#define CTRLCFG30x34
+#define CTRLCFG50x3c
+#define CTRLCFG60x40
#define DRAMTIMING00x50
#define CALTIMING0 0x7c
#define CALTIMING1 0x80
@@ -118,6 +120,9 @@ struct altera_sdram_plat {
#define CTRLCFG1_CFG_CTRL_EN_ECC(x)\
(((x) >> 7) & 0x1)
+#define CTRLCFG6_CFG_CS_CHIP(x)\
+ ((x) & 0x)
+
#define DRAMTIMING0_CFG_TCL(x) \
((x) & 0x7F)
--
2.25.1
[Agilex7 M-series Platform Enablement v1 12/16] ddr: altera: soc64: Clean up bit-shift by zero bit
From: Teik Heng Chong
Clean up bit-shift by zero bit
Signed-off-by: Teik Heng Chong
Signed-off-by: Tingting Meng
---
drivers/ddr/altera/sdram_soc64.h | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.h b/drivers/ddr/altera/sdram_soc64.h
index 02019ac9e5..add7df01a5 100644
--- a/drivers/ddr/altera/sdram_soc64.h
+++ b/drivers/ddr/altera/sdram_soc64.h
@@ -92,7 +92,7 @@ struct altera_sdram_plat {
#define NIOSRESERVED2 0x118
#define DRAMADDRW_CFG_COL_ADDR_WIDTH(x)\
- (((x) >> 0) & 0x1F)
+ ((x) & 0x1F)
#define DRAMADDRW_CFG_ROW_ADDR_WIDTH(x)\
(((x) >> 5) & 0x1F)
#define DRAMADDRW_CFG_BANK_ADDR_WIDTH(x) \
@@ -103,7 +103,7 @@ struct altera_sdram_plat {
(((x) >> 16) & 0x7)
#define CTRLCFG0_CFG_MEMTYPE(x)\
- (((x) >> 0) & 0xF)
+ ((x) & 0xF)
#define CTRLCFG0_CFG_DIMM_TYPE(x) \
(((x) >> 4) & 0x7)
#define CTRLCFG0_CFG_AC_POS(x) \
@@ -112,17 +112,17 @@ struct altera_sdram_plat {
(((x) >> 9) & 0x1F)
#define CTRLCFG1_CFG_DBC3_BURST_LEN(x) \
- (((x) >> 0) & 0x1F)
+ ((x) & 0x1F)
#define CTRLCFG1_CFG_ADDR_ORDER(x) \
(((x) >> 5) & 0x3)
#define CTRLCFG1_CFG_CTRL_EN_ECC(x)\
(((x) >> 7) & 0x1)
#define DRAMTIMING0_CFG_TCL(x) \
- (((x) >> 0) & 0x7F)
+ ((x) & 0x7F)
#define CALTIMING0_CFG_ACT_TO_RDWR(x) \
- (((x) >> 0) & 0x3F)
+ ((x) & 0x3F)
#define CALTIMING0_CFG_ACT_TO_PCH(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING0_CFG_ACT_TO_ACT(x) \
@@ -131,7 +131,7 @@ struct altera_sdram_plat {
(((x) >> 18) & 0x3F)
#define CALTIMING1_CFG_RD_TO_RD(x) \
- (((x) >> 0) & 0x3F)
+ ((x) & 0x3F)
#define CALTIMING1_CFG_RD_TO_RD_DC(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING1_CFG_RD_TO_RD_DB(x) \
@@ -142,7 +142,7 @@ struct altera_sdram_plat {
(((x) >> 24) & 0x3F)
#define CALTIMING2_CFG_RD_TO_WR_DB(x) \
- (((x) >> 0) & 0x3F)
+ ((x) & 0x3F)
#define CALTIMING2_CFG_RD_TO_WR_PCH(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING2_CFG_RD_AP_TO_VALID(x) \
@@ -153,7 +153,7 @@ struct altera_sdram_plat {
(((x) >> 24) & 0x3F)
#define CALTIMING3_CFG_WR_TO_WR_DB(x) \
- (((x) >> 0) & 0x3F)
+ ((x) & 0x3F)
#define CALTIMING3_CFG_WR_TO_RD(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING3_CFG_WR_TO_RD_DC(x) \
@@ -164,7 +164,7 @@ struct altera_sdram_plat {
(((x) >> 24) & 0x3F)
#define CALTIMING4_CFG_WR_AP_TO_VALID(x) \
- (((x) >> 0) & 0x3F)
+ ((x) & 0x3F)
#define CALTIMING4_CFG_PCH_TO_VALID(x) \
(((x) >> 6) & 0x3F)
#define CALTIMING4_CFG_PCH_ALL_TO_VALID(x) \
@@ -175,7 +175,7 @@ struct altera_sdram_plat {
(((x) >> 26) & 0x3F)
#define CALTIMING9_CFG_4_ACT_TO_ACT(x) \
- (((x) >> 0) & 0xFF)
+ ((x) & 0xFF)
/* Firewall DDR scheduler MPFE */
#define FW_HMC_ADAPTOR_REG_ADDR0xf8020004
--
2.25.1
[Agilex7 M-series Platform Enablement v1 11/16] ddr: altera: soc64: Restructure SDRAM firewall function
From: Sin Hui Kho
Restructure SDRAM firewall function. Move the non-F2SDRAM firewall
configuration to an individual function, in preparation to support
F2SDRAM firewall configuration.
Signed-off-by: Sin Hui Kho
Signed-off-by: Tingting Meng
---
drivers/ddr/altera/sdram_soc64.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/ddr/altera/sdram_soc64.c b/drivers/ddr/altera/sdram_soc64.c
index a0cc9be25e..8f2085f3a0 100644
--- a/drivers/ddr/altera/sdram_soc64.c
+++ b/drivers/ddr/altera/sdram_soc64.c
@@ -253,7 +253,7 @@ phys_size_t sdram_calculate_size(struct altera_sdram_plat
*plat)
return size;
}
-void sdram_set_firewall(struct bd_info *bd)
+static void sdram_set_firewall_non_f2sdram(struct bd_info *bd)
{
u32 i;
phys_size_t value;
@@ -289,7 +289,7 @@ void sdram_set_firewall(struct bd_info *bd)
FW_MPU_DDR_SCR_NONMPUREGION0ADDR_BASEEXT +
(i * 4 * sizeof(u32)));
- /* Setting non-secure MPU limit and limit extexded */
+ /* Setting non-secure MPU limit and limit extended */
value = bd->bi_dram[i].start + bd->bi_dram[i].size - 1;
lower = lower_32_bits(value);
@@ -302,7 +302,7 @@ void sdram_set_firewall(struct bd_info *bd)
FW_MPU_DDR_SCR_MPUREGION0ADDR_LIMITEXT +
(i * 4 * sizeof(u32)));
- /* Setting non-secure Non-MPU limit and limit extexded */
+ /* Setting non-secure Non-MPU limit and limit extended */
FW_MPU_DDR_SCR_WRITEL(lower,
FW_MPU_DDR_SCR_NONMPUREGION0ADDR_LIMIT +
(i * 4 * sizeof(u32)));
@@ -315,6 +315,11 @@ void sdram_set_firewall(struct bd_info *bd)
}
}
+void sdram_set_firewall(struct bd_info *bd)
+{
+ sdram_set_firewall_non_f2sdram(bd);
+}
+
static int altera_sdram_of_to_plat(struct udevice *dev)
{
struct altera_sdram_plat *plat = dev_get_plat(dev);
--
2.25.1
[Agilex7 M-series Platform Enablement v1 10/16] ddr: altera: Add DDR driver for Agilex7 M-series
From: Wan Yee Lau This is for new platform enablement for Agilex7 M-series. Add DDR driver for Agilex7 M-series. This driver is designed to support DDR and HBM memory. The official HBM handoff is not ready yet, therefore hardcoded handoff is used for HBM driver validation on mUDV board. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- .../include/mach/base_addr_soc64.h| 6 +- .../include/mach/system_manager_soc64.h | 7 +- drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/sdram_agilex7m.c | 527 ++ drivers/ddr/altera/sdram_soc64.c | 15 +- drivers/ddr/altera/sdram_soc64.h | 15 +- 6 files changed, 565 insertions(+), 8 deletions(-) create mode 100644 drivers/ddr/altera/sdram_agilex7m.c diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 65721098b2..1f935fcdec 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -45,12 +45,15 @@ #define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400 #define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf801 #define SOCFPGA_SDR_ADDRESS0xf8011000 +#define SOCFPGA_FW_MPFE_SCR_ADDRESS0xf802 #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) + IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020200 #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa00 #define SOCFPGA_MAILBOX_ADDRESS0xffa3 #define SOCFPGA_UART0_ADDRESS 0xffc02000 @@ -74,6 +77,7 @@ #define SOCFPGA_FIREWALL_SOC2FPGA 0xffd21200 #define SOCFPGA_FIREWALL_LWSOC2FPGA0xffd21300 #define SOCFPGA_FIREWALL_TCU 0xffd21400 +#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0xffd24800 #define SOCFPGA_DMANONSECURE_ADDRESS 0xffda #define SOCFPGA_DMASECURE_ADDRESS 0xffda1000 #define SOCFPGA_OCRAM_ADDRESS 0xffe0 diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index a8009664fe..815bdf8ce1 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019-2021 Intel Corporation + * Copyright (C) 2019-2024 Intel Corporation */ #ifndef _SYSTEM_MANAGER_SOC64_H_ @@ -103,6 +103,11 @@ void populate_sysmgr_pinmux(void); #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_MASK (BIT(29) | BIT(28)) #define ALT_SYSMGR_SCRATCH_REG_0_DDR_RESET_TYPE_SHIFT 28 +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) +#define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define ALT_SYSMGR_SCRATCH_REG_8_OCRAM_DBE_MASKBIT(29) +#define ALT_SYSMGR_SCRATCH_REG_8_IO96B_HPS_MASKGENMASK(28, 27) + #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC #define SYSMGR_ROMCODEGRP_CTRL_WARMRSTCFGPINMUXBIT(0) diff --git a/drivers/ddr/altera/Makefile b/drivers/ddr/altera/Makefile index 9fa5d85a27..1dac088b39 100644 --- a/drivers/ddr/altera/Makefile +++ b/drivers/ddr/altera/Makefile @@ -4,7 +4,7 @@ # Wolfgang Denk, DENX Software Engineering, w...@denx.de. # # (C) Copyright 2010, Thomas Chou -# Copyright (C) 2014-2021 Altera Corporation +# Copyright (C) 2014-2024 Altera Corporation ifdef CONFIG_$(SPL_)ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o @@ -12,4 +12,5 @@ obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o obj-$(CONFIG_TARGET_SOCFPGA_STRATIX10) += sdram_soc64.o sdram_s10.o obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += sdram_soc64.o sdram_agilex.o obj-$(CONFIG_TARGET_SOCFPGA_N5X) += sdram_soc64.o sdram_n5x.o +obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += sdram_soc64.o sdram_agilex7m.o iossm_mailbox.o uibssm_mailbox.o endif diff --git a/drivers/ddr/altera/sdram_agilex7m.c b/drivers/ddr/altera/sdram_agilex7m.c new file mode 100644 index 00..4d585501e6 --- /dev/null +++ b/drivers/ddr/altera/sdram_agilex7m.c @@ -0,0 +1,527 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2024 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include "iossm_mailbox.h" +#include "uibssm_mailbox.h" +#include "sdram_soc64.h" + +/* NOCPLL register */ +#define SYSMGR_HMC_CLK 0xB4 +#define SYSMGR_HMC_CLK_NOCPLL BIT(8) + +/* MPFE NOC registers */ +#defin
[Agilex7 M-series Platform Enablement v1 09/16] ddr: altera: Add uibssm mailbox for Agilex7 M-series
From: Teik Heng Chong
Add uibssm mailbox driver for Agilex7 M-series. HPS will interact with UIB
and HBM subsystem through software defined mailbox interface.
HPS can retrieve memory interface calibration status, UIB configuration,
memory interfae configuration, trigger calibration and etc with the list of
supported mailbox command type and opcode.
Signed-off-by: Teik Heng Chong
Signed-off-by: Tingting Meng
---
drivers/ddr/altera/uibssm_mailbox.c | 311
drivers/ddr/altera/uibssm_mailbox.h | 117 +++
2 files changed, 428 insertions(+)
create mode 100644 drivers/ddr/altera/uibssm_mailbox.c
create mode 100644 drivers/ddr/altera/uibssm_mailbox.h
diff --git a/drivers/ddr/altera/uibssm_mailbox.c
b/drivers/ddr/altera/uibssm_mailbox.c
new file mode 100644
index 00..a6e2a5f44b
--- /dev/null
+++ b/drivers/ddr/altera/uibssm_mailbox.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation
+ */
+#include
+#include
+#include
+#include
+#include "uibssm_mailbox.h"
+
+#define MAX_RETRIES 3
+
+int uib_bist_mem_init_start(struct uib_info *uib_ctrl)
+{
+ struct uib_mb_resp usr_resp;
+ bool bist_start = false;
+ bool bist_success = false;
+ u32 start;
+
+ /*
+* Full memory initialization BIST performed on all UIB channels
+* start memory initialization BIST on full memory address
+*/
+ uib_mb_req(uib_ctrl->uib[0].uib_csr_addr,
+ UIB_CMD_TRIG_CONTROLLER_OP,
+ UIB_BIST_MEM_INIT_START,
+ UIB_BIST_FULL_MEM, _resp);
+
+ bist_start = UIBSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) &
+ UIB_BIST_INITIATE_PASS;
+ if (!bist_start) {
+ printf("%s: Failed to initialized memory on UIB\n", __func__);
+
+ return -EINVAL;
+ }
+
+ /* Polling for the initiated memory initialization BIST status */
+ start = get_timer(0);
+ while (!bist_success) {
+ /*
+* cmd_param_0 is not used in BIST status request,
+* hence set the value to 0
+*/
+ uib_mb_req(uib_ctrl->uib[0].uib_csr_addr,
+ UIB_CMD_TRIG_CONTROLLER_OP,
+ UIB_BIST_MEM_INIT_STATUS,
+ 0, _resp);
+
+ bist_success =
UIBSSM_CMD_RESPONSE_DATA_SHORT(usr_resp.cmd_resp_status) & BIT(0);
+ if (!bist_success && (get_timer(start) > TIMEOUT)) {
+ printf("%s: Timeout initialize memory on UIB\n",
__func__);
+
+ return -ETIMEDOUT;
+ }
+
+ udelay(1);
+ }
+
+ debug("%s: Memory initialized successfully on UIB\n", __func__);
+
+ return 0;
+}
+
+int uib_cal_status(phys_addr_t addr)
+{
+ int ret = 0;
+ phys_addr_t status_addr = addr + UIB_R_INITSTS_OFFSET;
+
+ /* Ensure calibration completed */
+ ret = wait_for_bit_le32((const void *)status_addr,
UIB_R_INITSTS_INITSTS_PASS, true,
+ TIMEOUT, false);
+ if (ret)
+ printf("%s: HBM calibration UIB instance 0x%llx timeout\n",
__func__, status_addr);
+
+ return ret;
+}
+
+void uib_init_mem_cal(struct uib_info *uib_ctrl)
+{
+ int i, ret;
+
+ if (!uib_ctrl->num_instance) {
+ uib_ctrl->overall_cal_status = false;
+ } else {
+ uib_ctrl->overall_cal_status = true;
+
+ /* Check initial calibration status for the assigned UIB */
+ for (i = 0; i < uib_ctrl->num_instance; i++) {
+ ret = uib_cal_status(uib_ctrl->uib[i].uib_csr_addr);
+ if (ret) {
+ uib_ctrl->uib[i].cal_status = false;
+ uib_ctrl->overall_cal_status = false;
+
+ printf("%s: Initial HBM calibration UIB_%d
failed\n", __func__, i);
+ break;
+ }
+
+ uib_ctrl->uib[i].cal_status = true;
+
+ debug("%s: Initial HBM calibration UIB_%d succeed\n",
__func__, i);
+ }
+ }
+}
+
+/* Trying 3 times re-calibration if initial calibration failed */
+void uib_trig_mem_cal(struct uib_info *uib_ctrl)
+{
+ int i, j, cal_stat;
+
+ if (!uib_ctrl->num_instance) {
+ uib_ctrl->overall_cal_status = false;
+ } else {
+ uib_ctrl->overall_cal_status = true;
+
+ for (i = 0; i < uib_ctrl->num_instance; i++) {
+ uib_ctrl->uib[i].cal_status = false;
+
+ /* Initiate Re-calibration
[Agilex7 M-series Platform Enablement v1 08/16] ddr: altera: Add iossm mailbox for Agilex7 M-series
From: Wan Yee Lau
Add iossm mailbox driver for Agilex7 M-series. HPS will interact with IO96B
and DDR subsystem through software defined mailbox interface.
HPS can retrieve memory interface calibration status, IO96B configuration,
memory interfae configuration, trigger calibration and etc with the list of
supported mailbox command type and opcode.
Signed-off-by: Wan Yee Lau
Signed-off-by: Teik Heng Chong
Signed-off-by: Tingting Meng
---
drivers/ddr/altera/iossm_mailbox.c | 637 +
drivers/ddr/altera/iossm_mailbox.h | 182 +
2 files changed, 819 insertions(+)
create mode 100644 drivers/ddr/altera/iossm_mailbox.c
create mode 100644 drivers/ddr/altera/iossm_mailbox.h
diff --git a/drivers/ddr/altera/iossm_mailbox.c
b/drivers/ddr/altera/iossm_mailbox.c
new file mode 100644
index 00..f84a3a070d
--- /dev/null
+++ b/drivers/ddr/altera/iossm_mailbox.c
@@ -0,0 +1,637 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "iossm_mailbox.h"
+
+#define ECC_INTSTATUS_SERR SOCFPGA_SYSMGR_ADDRESS + 0x9C
+#define ECC_INISTATUS_DERR SOCFPGA_SYSMGR_ADDRESS + 0xA0
+#define DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK BIT(16)
+#define DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK BIT(17)
+
+#define DDR_CSR_CLKGEN_LOCKED_IO96B_MASK(x)(i == 0 ?
DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK : \
+
DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK)
+
+#define IO96B_MB_REQ_SETUP(v, w, x, y, z) usr_req.ip_type = v; \
+ usr_req.ip_id = w; \
+ usr_req.usr_cmd_type = x; \
+ usr_req.usr_cmd_opcode = y; \
+ usr_req.cmd_param[0] = z; \
+ for (n = 1; n < NUM_CMD_PARAM;
n++) \
+ usr_req.cmd_param[n] = 0
+#define MAX_RETRY_COUNT3
+
+#define IO96B0_PLL_A_MASK BIT(0)
+#define IO96B0_PLL_B_MASK BIT(1)
+#define IO96B1_PLL_A_MASK BIT(2)
+#define IO96B1_PLL_B_MASK BIT(3)
+
+/* supported DDR type list */
+static const char *ddr_type_list[7] = {
+ "DDR4", "DDR5", "DDR5_RDIMM", "LPDDR4", "LPDDR5", "QDRIV",
"UNKNOWN"
+};
+
+static int is_ddr_csr_clkgen_locked(u8 io96b_pll)
+{
+ int ret = 0;
+
+ if (FIELD_GET(IO96B0_PLL_A_MASK, io96b_pll)) {
+ ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR),
+ DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK,
true, TIMEOUT, false);
+
+ if (ret) {
+ debug("%s: ddr csr io96b_0 clkgenA locked is
timeout\n", __func__);
+ goto err;
+ }
+ }
+
+ if (FIELD_GET(IO96B0_PLL_B_MASK, io96b_pll)) {
+ ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR),
+ DDR_CSR_CLKGEN_LOCKED_IO96B0_MASK,
true, TIMEOUT, false);
+
+ if (ret) {
+ debug("%s: ddr csr io96b_0 clkgenB locked is
timeout\n", __func__);
+ goto err;
+ }
+ }
+
+ if (FIELD_GET(IO96B1_PLL_A_MASK, io96b_pll)) {
+ ret = wait_for_bit_le32((const void *)(ECC_INTSTATUS_SERR),
+ DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK,
true, TIMEOUT, false);
+
+ if (ret) {
+ debug("%s: ddr csr io96b_1 clkgenA locked is
timeout\n", __func__);
+ goto err;
+ }
+ }
+
+ if (FIELD_GET(IO96B1_PLL_B_MASK, io96b_pll)) {
+ ret = wait_for_bit_le32((const void *)(ECC_INISTATUS_DERR),
+ DDR_CSR_CLKGEN_LOCKED_IO96B1_MASK,
true, TIMEOUT, false);
+
+ if (ret) {
+ debug("%s: ddr csr io96b_1 clkgenB locked is
timeout\n", __func__);
+ goto err;
+ }
+ }
+
+err:
+ return ret;
+}
+
+/* Mailbox request function
+ * This function will send the request to IOSSM mailbox and wait for response
return
+ *
+ * @io96b_csr_addr: CSR address for the target IO96B
+ * @req:Structure contain command request for IOSSM mailbox command
+ * @resp_data_len: User desire extra response data fields other than
+ * CMD_RESPONSE_DATA_SHORT field on
CMD_RESPONSE_STATUS
+ * @resp: Structure contain responses returned from the requested
IOSSM
+ * mailbox command
+ */
+int io96b_mb_req(phys_addr_t io96b_csr_addr, struct io96b_mb_req req,
+u32 resp_data_len, str
[Agilex7 M-series Platform Enablement v1 07/16] clk: altera: Add clock support for Agilex7 M-series
From: Teik Heng Chong
Agilex7 M-series reuse the clock driver from Agilex.
Signed-off-by: Wan Yee Lau
Signed-off-by: Teik Heng Chong
Signed-off-by: Tingting Meng
---
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 +-
arch/arm/mach-socfpga/misc.c | 2 +-
drivers/clk/altera/Makefile| 1 +
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index 6c9d32b9dd..77d97193f5 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -26,7 +26,7 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#include
#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
#include
-#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) ||
IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
#include
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
#include
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 79f7887519..5537445e10 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -252,7 +252,7 @@ void socfpga_get_managers_addr(void)
if (ret)
hang();
-#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) ||
IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
ret = socfpga_get_base_addr("intel,agilex-clkmgr",
_clkmgr_base);
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile
index 61ffa4179a..858f828e53 100644
--- a/drivers/clk/altera/Makefile
+++ b/drivers/clk/altera/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
+obj-$(CONFIG_TARGET_SOCFPGA_AGILEX7M) += clk-agilex.o
obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
--
2.25.1
[Agilex7 M-series Platform Enablement v1 06/16] include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile
From: Siew Chin Lim ATF boot flow (SPL->ATF->U-Boot Proper->OS) boot to OS via kernel.itb file using bootm command. Change to use CONFIG_SPL_ATF to differentiate the bootfile of default environment variable. We shouldn't use CONFIG_FIT because it is enabled by default for U-Boot Proper. Signed-off-by: Siew Chin Lim Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index a0842e1933..56e190adf6 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -21,6 +21,9 @@ config ARM64_CRC32 not be present on all ARMv8.0, but is always present on ARMv8.1 and newer. +config BOOTFILE + default kernel.itb if SPL_ATF && TARGET_SOCFPGA_SOC64 + config COUNTER_FREQUENCY int "Timer clock frequency" depends on ARM64 || CPU_V7A -- 2.25.1
[Agilex7 M-series Platform Enablement v1 05/16] include: configs: Add config header file for Agilex7 M-series
From: Wan Yee Lau
Add config header file for new platform Agilex7 M-series.
Signed-off-by: Wan Yee Lau
Signed-off-by: Teik Heng Chong
Signed-off-by: Tingting Meng
---
.../{socfpga_agilex5_socdk.h => socfpga_agilex7m_socdk.h} | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
copy include/configs/{socfpga_agilex5_socdk.h => socfpga_agilex7m_socdk.h}
(55%)
diff --git a/include/configs/socfpga_agilex5_socdk.h
b/include/configs/socfpga_agilex7m_socdk.h
similarity index 55%
copy from include/configs/socfpga_agilex5_socdk.h
copy to include/configs/socfpga_agilex7m_socdk.h
index b5b5bd767f..433556804e 100644
--- a/include/configs/socfpga_agilex5_socdk.h
+++ b/include/configs/socfpga_agilex7m_socdk.h
@@ -4,9 +4,9 @@
*
*/
-#ifndef __CONFIG_SOCFGPA_AGILEX5_H__
-#define __CONFIG_SOCFGPA_AGILEX5_H__
+#ifndef __CONFIG_SOCFGPA_AGILEX7M_H__
+#define __CONFIG_SOCFGPA_AGILEX7M_H__
#include
-#endif /* __CONFIG_SOCFGPA_AGILEX5_H__ */
+#endif /* __CONFIG_SOCFGPA_AGILEX7M_H__ */
--
2.25.1
[Agilex7 M-series Platform Enablement v1 04/16] arch: arm: mach-socfpga: Update handoff settings for Agilex7 M-series
From: Wan Yee Lau Handoff settings updated for new platform Agilex7 M-series. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 14 -- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h index d839f28841..747016b436 100644 --- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h @@ -28,10 +28,20 @@ #define SOC64_HANDOFF_OFFSET_DATA 0x10 #define SOC64_HANDOFF_SIZE 4096 -#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \ - IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64) || \ + IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) #define SOC64_HANDOFF_BASE 0xFFE3F000 +#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) +#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x62C) +/* DDR handoff */ +#define SOC64_HANDOFF_MAGIC_DDR0x5344524D +#define SOC64_HANDOFF_DDR_BASE (SOC64_HANDOFF_BASE + 0x610) +#define SOC64_HANDOFF_DDR_LEN 2 +#define SOC64_HANDOFF_DDR_INTERLEAVING_MODE_MASK BIT(0) +#define SOC64_HANDOFF_DDR_MEMORY_TYPE_MASK BIT(0) +#else #define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610) +#endif #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) #define SOC64_HANDOFF_BASE 0x0007F000 #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) -- 2.25.1
[Agilex7 M-series Platform Enablement v1 03/16] arch: arm: mach-socfpga: Improve help info.
From: Teik Heng Chong To improve help info for bridge enable/disable command. Signed-off-by: Wan Yee Lau Signed-off-by: Teik Heng Chong Signed-off-by: Tingting Meng --- arch/arm/mach-socfpga/misc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index 80ad087034..79f7887519 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -210,8 +210,8 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc, U_BOOT_CMD(bridge, 3, 1, do_bridge, "SoCFPGA HPS FPGA bridge control", - "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" - "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n" + "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges \n" + "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n" "" ); -- 2.25.1
[Agilex7 M-series Platform Enablement v1 02/16] arch: arm: mach-socfpga: Add Agilex7 M-series mach-socfgpa enablement
From: Wan Yee Lau
Add platform related files for new platform Agilex7 M-series.
Signed-off-by: Wan Yee Lau
Signed-off-by: Teik Heng Chong
Signed-off-by: Tingting Meng
---
arch/arm/mach-socfpga/include/mach/misc.h | 3 +-
.../{spl_agilex.c => spl_agilex7m.c} | 45 ---
arch/arm/mach-socfpga/wrap_handoff_soc64.c| 4 ++
board/intel/agilex7m-socdk/MAINTAINERS| 7 +++
board/intel/agilex7m-socdk/socfpga.c | 4 ++
5 files changed, 45 insertions(+), 18 deletions(-)
copy arch/arm/mach-socfpga/{spl_agilex.c => spl_agilex7m.c} (68%)
create mode 100644 board/intel/agilex7m-socdk/MAINTAINERS
create mode 100644 board/intel/agilex7m-socdk/socfpga.c
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index 8460acb00d..e271d2855f 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -40,7 +40,8 @@ void socfpga_sdram_remap_zero(void);
#endif
#if defined(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
- defined(CONFIG_TARGET_SOCFPGA_AGILEX)
+ defined(CONFIG_TARGET_SOCFPGA_AGILEX) || \
+ defined(CONFIG_TARGET_SOCFPGA_AGILEX7M)
int is_fpga_config_ready(void);
#endif
diff --git a/arch/arm/mach-socfpga/spl_agilex.c
b/arch/arm/mach-socfpga/spl_agilex7m.c
similarity index 68%
copy from arch/arm/mach-socfpga/spl_agilex.c
copy to arch/arm/mach-socfpga/spl_agilex7m.c
index ee5a9dc1e2..ee41db8884 100644
--- a/arch/arm/mach-socfpga/spl_agilex.c
+++ b/arch/arm/mach-socfpga/spl_agilex7m.c
@@ -1,26 +1,25 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019 Intel Corporation
- *
+ * Copyright (C) 2024 Intel Corporation
*/
-#include
-#include
-#include
-#include
-#include
-#include
#include
#include
#include
+#include
+#include
#include
+#include
#include
#include
#include
#include
#include
#include
-#include
+#include
+#include
+#include
+#include
#include
DECLARE_GLOBAL_DATA_PTR;
@@ -40,13 +39,6 @@ void board_init_f(ulong dummy)
writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
-#ifdef CONFIG_HW_WATCHDOG
- /* Enable watchdog before initializing the HW */
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
- socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
- hw_watchdog_init();
-#endif
-
/* ensure all processors are not released prior Linux boot */
writeq(0, CPU_RELEASE_ADDR);
@@ -60,11 +52,30 @@ void board_init_f(ulong dummy)
hang();
}
+ /*
+* Enable watchdog as early as possible before initializing other
+* component. Watchdog need to be enabled after clock driver because
+* it will retrieve the clock frequency from clock driver.
+*/
+ if (CONFIG_IS_ENABLED(WDT))
+ initr_watchdog();
+
preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
- firewall_setup();
+ ret = uclass_get_device_by_name(UCLASS_NOP,
"socfpga-system-mgr-firewall", );
+ if (ret) {
+ printf("System manager firewall configuration failed: %d\n",
ret);
+ hang();
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_NOP,
"socfpga-l3interconnect-firewall", );
+ if (ret) {
+ printf("L3 interconnect firewall configuration failed: %d\n",
ret);
+ hang();
+ }
+
ret = uclass_get_device(UCLASS_CACHE, 0, );
if (ret) {
debug("CCU init failed: %d\n", ret);
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index 6aa9bb26b4..8c06b3d59e 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -39,6 +39,10 @@ static enum endianness check_endianness(u32 handoff)
case SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC:
debug("%s: PHY engine handoff data\n", __func__);
return LITTLE_ENDIAN;
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M)
+ case SOC64_HANDOFF_MAGIC_DDR:
+ debug("%s: SOC64_HANDOFF_MAGIC_DDR\n", __func__);
+ return BIG_ENDIAN;
#endif
default:
debug("%s: Unknown endianness!!\n", __func__);
diff --git a/board/intel/agilex7m-socdk/MAINTAINERS
b/board/intel/agilex7m-socdk/MAINTAINERS
new file mode 100644
index 00..feb2916488
--- /dev/null
+++ b/board/intel/agilex7m-socdk/MAINTAINERS
@@ -0,0 +1,7 @@
+SOCFPGA BOARD
+M: Tien Fong Chee
+M: Teik Heng Chong
+S: Maintained
+F: board/intel/agilex7m-socdk/
+F: include/configs/socfpga_agilex7m_socdk.h
+F: configs/socfpga_agilex7m_sdmmc_defconfig
diff --git a/board/intel/agilex7m-socdk/socfpga.c
b/board/intel/agilex7m-socdk/socfpga.c
new file mode 100644
[Agilex7 M-series Platform Enablement v1 01/16] arch: arm: dts: Add dts and dtsi for new platform Agilex7 M-series
From: Wan Yee Lau
Add Agilex7 M-series dtsi and dts for new platform Agilex7 M-series.
Signed-off-by: Wan Yee Lau
Signed-off-by: Teik Heng Chong
Signed-off-by: Tingting Meng
---
...tsi => socfpga_agilex7m_socdk-u-boot.dtsi} | 37 -
...x_socdk.dts => socfpga_agilex7m_socdk.dts} | 66 +++--
arch/arm/dts/socfpga_soc64_u-boot.dtsi| 127 ++
3 files changed, 213 insertions(+), 17 deletions(-)
copy arch/arm/dts/{socfpga_agilex_socdk-u-boot.dtsi =>
socfpga_agilex7m_socdk-u-boot.dtsi} (50%)
copy arch/arm/dts/{socfpga_agilex_socdk.dts => socfpga_agilex7m_socdk.dts}
(63%)
create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
similarity index 50%
copy from arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
copy to arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
index 63df28e836..4369f0b545 100644
--- a/arch/arm/dts/socfpga_agilex_socdk-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi
@@ -2,12 +2,18 @@
/*
* U-Boot additions
*
- * Copyright (C) 2019-2022 Intel Corporation
+ * Copyright (C) 2024 Intel Corporation
*/
#include "socfpga_agilex-u-boot.dtsi"
+#include "socfpga_soc64_u-boot.dtsi"
/{
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order =
+ };
+
aliases {
spi0 =
i2c0 =
@@ -23,9 +29,7 @@
};
memory {
- /* 8GB */
- reg = <0 0x 0 0x8000>,
- <2 0x8000 1 0x8000>;
+ reg = <0 0x 0 0x8000>;
};
};
@@ -34,22 +38,43 @@
spi-tx-bus-width = <4>;
spi-rx-bus-width = <4>;
bootph-all;
+ /delete-property/ cdns,read-delay;
};
{
status = "okay";
};
+ {
+ status = "okay";
+ nand-bus-width = <16>;
+ bootph-all;
+};
+
{
drvsel = <3>;
smplsel = <0>;
bootph-all;
};
- {
- status = "okay";
+ {
+ compatible = "intel,sdr-ctl-agilex7m";
+
+ reg = <0xf802 0x100>;
+};
+
+_l3interconnect_firewall {
+ soc_noc_fw_mpfe_csr_inst_0_mpfe_scr@f802 {
+ intel,offset-settings =
+ /* Disable MPFE firewall for SMMU */
+ <0x 0x00010101 0x00010101>;
+ };
};
{
bootph-all;
};
+
+ {
+ /delete-node/ kernel;
+};
diff --git a/arch/arm/dts/socfpga_agilex_socdk.dts
b/arch/arm/dts/socfpga_agilex7m_socdk.dts
similarity index 63%
copy from arch/arm/dts/socfpga_agilex_socdk.dts
copy to arch/arm/dts/socfpga_agilex7m_socdk.dts
index bcdeecc0e0..ba929b9c74 100644
--- a/arch/arm/dts/socfpga_agilex_socdk.dts
+++ b/arch/arm/dts/socfpga_agilex7m_socdk.dts
@@ -1,11 +1,11 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2019, Intel Corporation
+ * Copyright (C) 2024, Intel Corporation
*/
#include "socfpga_agilex.dtsi"
/ {
- model = "SoCFPGA Agilex SoCDK";
+ model = "SoCFPGA Agilex7-M SoCDK";
aliases {
serial0 =
@@ -14,10 +14,6 @@
ethernet2 =
};
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
leds {
compatible = "gpio-leds";
hps0 {
@@ -85,6 +81,36 @@
};
};
+ {
+ status = "okay";
+ phy-mode = "rgmii";
+ phy-handle = <>;
+
+ max-frame-size = <3800>;
+
+ mdio2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy2: ethernet-phy@2 {
+ reg = <4>;
+
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <1860>; /* 960ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+
{
status = "okay";
cap-sd-highspeed;
@@ -128,13 +154,31 @@
#size-cells = <1>;
qspi_boot: partition@0 {
-
[Agilex7 M-series Platform Enablement v1 00/16]
From: Tingting Meng Intel Agilex7 M-Series is the highest peformance FPGA targeted for compute and memory-intensive application,this series is built using intel 7 process technology and expands upon I-Series device feature, offering in-package high bandwidth memory (HBM), memory interfaces for DDR5 SDRAM, and a hard memory Network-on-Chip (NoC) to maximize memory bandwidth. The series of patches include adding clock driver, IOSSM mailbox driver, UIBSSM mailbox driver, DDR driver and HBM driver needed for Agilex 7 M-Series platform enablement and supports linux boot from SD card. This series patches based on master branch https://source.denx.de/u-boot/u-boot Complete compilation check on different devices, ran checkpatch and tested on board Siew Chin Lim (1): include: configs: soc64: Use CONFIG_SPL_ATF to differentiate bootfile Sin Hui Kho (1): ddr: altera: soc64: Restructure SDRAM firewall function Teik Heng Chong (5): arch: arm: mach-socfpga: Improve help info. clk: altera: Add clock support for Agilex7 M-series ddr: altera: Add uibssm mailbox for Agilex7 M-series ddr: altera: soc64: Clean up bit-shift by zero bit ddr: altera: soc64: Fix dram size calculation in clamshell mode Wan Yee Lau (9): arch: arm: dts: Add dts and dtsi for new platform Agilex7 M-series arch: arm: mach-socfpga: Add Agilex7 M-series mach-socfgpa enablement arch: arm: mach-socfpga: Update handoff settings for Agilex7 M-series include: configs: Add config header file for Agilex7 M-series ddr: altera: Add iossm mailbox for Agilex7 M-series ddr: altera: Add DDR driver for Agilex7 M-series arch: arm: mach-socfpga: Update kconfig for new platform Agilex7 M-series arch: arm: dts: Update Makefile for new platform Agilex7 M-series configs: Add defconfig for Agilex7 M-series arch/arm/Kconfig | 7 +- arch/arm/dts/Makefile | 1 + .../dts/socfpga_agilex7m_socdk-u-boot.dtsi| 80 +++ arch/arm/dts/socfpga_agilex7m_socdk.dts | 185 + arch/arm/dts/socfpga_soc64_u-boot.dtsi| 127 arch/arm/mach-socfpga/Kconfig | 19 + arch/arm/mach-socfpga/Makefile| 18 + .../include/mach/base_addr_soc64.h| 6 +- .../mach-socfpga/include/mach/clock_manager.h | 2 +- .../mach-socfpga/include/mach/handoff_soc64.h | 14 +- arch/arm/mach-socfpga/include/mach/misc.h | 3 +- .../include/mach/system_manager_soc64.h | 7 +- arch/arm/mach-socfpga/misc.c | 6 +- arch/arm/mach-socfpga/spl_agilex7m.c | 98 +++ arch/arm/mach-socfpga/wrap_handoff_soc64.c| 4 + board/intel/agilex7m-socdk/MAINTAINERS| 7 + board/intel/agilex7m-socdk/Makefile | 7 + board/intel/agilex7m-socdk/socfpga.c | 4 + configs/socfpga_agilex7m_sdmmc_defconfig | 114 drivers/clk/altera/Makefile | 1 + drivers/ddr/altera/Makefile | 3 +- drivers/ddr/altera/iossm_mailbox.c| 637 ++ drivers/ddr/altera/iossm_mailbox.h| 182 + drivers/ddr/altera/sdram_agilex7m.c | 527 +++ drivers/ddr/altera/sdram_soc64.c | 42 +- drivers/ddr/altera/sdram_soc64.h | 40 +- drivers/ddr/altera/uibssm_mailbox.c | 311 + drivers/ddr/altera/uibssm_mailbox.h | 117 include/configs/socfpga_agilex7m_socdk.h | 12 + 29 files changed, 2551 insertions(+), 30 deletions(-) create mode 100644 arch/arm/dts/socfpga_agilex7m_socdk-u-boot.dtsi create mode 100644 arch/arm/dts/socfpga_agilex7m_socdk.dts create mode 100644 arch/arm/dts/socfpga_soc64_u-boot.dtsi create mode 100644 arch/arm/mach-socfpga/spl_agilex7m.c create mode 100644 board/intel/agilex7m-socdk/MAINTAINERS create mode 100644 board/intel/agilex7m-socdk/Makefile create mode 100644 board/intel/agilex7m-socdk/socfpga.c create mode 100644 configs/socfpga_agilex7m_sdmmc_defconfig create mode 100644 drivers/ddr/altera/iossm_mailbox.c create mode 100644 drivers/ddr/altera/iossm_mailbox.h create mode 100644 drivers/ddr/altera/sdram_agilex7m.c create mode 100644 drivers/ddr/altera/uibssm_mailbox.c create mode 100644 drivers/ddr/altera/uibssm_mailbox.h create mode 100644 include/configs/socfpga_agilex7m_socdk.h -- 2.25.1
