Re: [PATCH] ARM: zynq: Add Z-turn board V5
st 23. 9. 2020 v 19:33 odesÃlatel napsal: > > From: Alexandre GRIVEAUX > > Adding Z-turn board V5 to resolve the change between: > > "Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035 > "Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel > KSZ9031 > > At this time the S25FL128SAGNFI003 doesn't work because of bug: > > *** Warning - spi_flash_probe_bus_cs() failed, using default environment > > zynq-zturn was checked on V5 board, same error. > > Maybe Z-turn board have the same problem (board with W25Q128BVFIG). > > Signed-off-by: Alexandre GRIVEAUX please send this as v2 version with changelog. M
[PATCH] ARM: zynq: Add Z-turn board V5
From: Alexandre GRIVEAUX
Adding Z-turn board V5 to resolve the change between:
"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel
KSZ9031
At this time the S25FL128SAGNFI003 doesn't work because of bug:
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
zynq-zturn was checked on V5 board, same error.
Maybe Z-turn board have the same problem (board with W25Q128BVFIG).
Signed-off-by: Alexandre GRIVEAUX
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-zturn-common.dtsi | 120
arch/arm/dts/zynq-zturn-v5.dts| 15 +
arch/arm/dts/zynq-zturn.dts | 109 +--
.../xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c | 273 ++
configs/xilinx_zynq_virt_defconfig| 4 +-
6 files changed, 413 insertions(+), 109 deletions(-)
create mode 100644 arch/arm/dts/zynq-zturn-common.dtsi
create mode 100644 arch/arm/dts/zynq-zturn-v5.dts
create mode 100644 board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f8f529435b..0f8973b1c8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -277,6 +277,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
+ zynq-zturn-v5.dtb \
zynq-zybo.dtb \
zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
diff --git a/arch/arm/dts/zynq-zturn-common.dtsi
b/arch/arm/dts/zynq-zturn-common.dtsi
new file mode 100644
index 00..1d7af02893
--- /dev/null
+++ b/arch/arm/dts/zynq-zturn-common.dtsi
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2015 Andrea Merello
+ * Copyright (C) 2017 Alexander Graf
+ *
+ * Based on zynq-zed.dts which is:
+ * Copyright (C) 2011 - 2014 Xilinx
+ * Copyright (C) 2012 National Instruments Corp.
+ *
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ compatible = "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ serial1 =
+ mmc0 =
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x4000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ usr-led1 {
+ label = "usr-led1";
+ gpios = < 0x0 0x1>;
+ default-state = "off";
+ };
+
+ usr-led2 {
+ label = "usr-led2";
+ gpios = < 0x9 0x1>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ K1 {
+ label = "K1";
+ gpios = < 0x32 0x1>;
+ linux,code = <0x66>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+};
+
+ {
+ ps-clk-frequency = <>;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ dr_mode = "host";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ clock-frequency = <40>;
+
+ stlm75@49 {
+ status = "okay";
+ compatible = "lm75";
+ reg = <0x49>;
+ };
+
+ accelerometer@53 {
+ compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
+ reg = <0x53>;
+ interrupt-parent = <>;
+ interrupts = <0x0 0x1e 0x4>;
+ };
+};
diff --git a/arch/arm/dts/zynq-zturn-v5.dts b/arch/arm/dts/zynq-zturn-v5.dts
new file mode 100644
index 00..536632a09a
--- /dev/null
+++ b/arch/arm/dts/zynq-zturn-v5.dts
@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/dts-v1/;
+/include/ "zynq-zturn-common.dtsi"
+
+/ {
+ model = "Zynq Z-Turn MYIR Board V5";
+ compatible = "myir,zynq-zturn-v5", "xlnx,zynq-7000";
+};
+
+ {
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0x3>;
+ };
+};
diff --git a/arch/arm/dts/zynq-zturn.dts b/arch/arm/dts/zynq-zturn.dts
index 600e8ee025..620b24a25e 100644
--- a/arch/arm/dts/zynq-zturn.dts
+++ b/arch/arm/dts/zynq-zturn.dts
@@ -1,122 +1,15 @@
// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2015 Andrea Merello
- * Copyright (C) 2017 Alexander Graf
- *
- *
Re: [PATCH] ARM: zynq: Add Z-turn board V5
On 07. 09. 20 18:11, agrive...@deutnet.info wrote:
> From: Alexandre GRIVEAUX
>
> Adding Z-turn board V5 to resolve the change between:
>
> "Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
> "Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel
> KSZ9031
>
> At this time the S25FL128SAGNFI003 doesn't work because of bug:
>
> *** Warning - spi_flash_probe_bus_cs() failed, using default environment
>
> Signed-off-by: Alexandre GRIVEAUX
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/zynq-zturn-v5.dts| 121
> .../xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c | 273 ++
> configs/xilinx_zynq_virt_defconfig| 4 +-
> 4 files changed, 398 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/zynq-zturn-v5.dts
> create mode 100644 board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index f8f529435b..0f8973b1c8 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -277,6 +277,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
> zynq-zc770-xm013.dtb \
> zynq-zed.dtb \
> zynq-zturn.dtb \
> + zynq-zturn-v5.dtb \
> zynq-zybo.dtb \
> zynq-zybo-z7.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP) += \
> diff --git a/arch/arm/dts/zynq-zturn-v5.dts b/arch/arm/dts/zynq-zturn-v5.dts
> new file mode 100644
> index 00..eebeec800f
> --- /dev/null
> +++ b/arch/arm/dts/zynq-zturn-v5.dts
> @@ -0,0 +1,121 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Alexandre Griveaux
> + *
> + * Based on zynq-zturn.dts which is:
> + * Copyright (C) 2015 Andrea Merello
> + * Copyright (C) 2017 Alexander Graf
> + *
> + */
> +
> +/dts-v1/;
> +/include/ "zynq-7000.dtsi"
> +
> +/ {
> + model = "Zynq Z-Turn MYIR Board V5";
> + compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
I prefer to make this simpler because the most of that stuff is just c
What about this?
#include "zynq-zturn.dts";
/ {
model = "Zynq Z-Turn MYIR Board V5";
compatible = "myir,zynq-zturn-v5", "myir,zynq-zturn", "xlnx,zynq-7000";
};
_phy {
reg = <3>;
};
Thanks,
Michal
[PATCH] ARM: zynq: Add Z-turn board V5
From: Alexandre GRIVEAUX
Adding Z-turn board V5 to resolve the change between:
"Z-TURNBOARD_schematic.pdf" schematics state version 1 to 4 has Atheros AR8035
"Z-Turn_Board_sch_V15_20160303.pdf" schematics state version 5 has Micrel
KSZ9031
At this time the S25FL128SAGNFI003 doesn't work because of bug:
*** Warning - spi_flash_probe_bus_cs() failed, using default environment
Signed-off-by: Alexandre GRIVEAUX
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/zynq-zturn-v5.dts| 121
.../xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c | 273 ++
configs/xilinx_zynq_virt_defconfig| 4 +-
4 files changed, 398 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/dts/zynq-zturn-v5.dts
create mode 100644 board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index f8f529435b..0f8973b1c8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -277,6 +277,7 @@ dtb-$(CONFIG_ARCH_ZYNQ) += \
zynq-zc770-xm013.dtb \
zynq-zed.dtb \
zynq-zturn.dtb \
+ zynq-zturn-v5.dtb \
zynq-zybo.dtb \
zynq-zybo-z7.dtb
dtb-$(CONFIG_ARCH_ZYNQMP) += \
diff --git a/arch/arm/dts/zynq-zturn-v5.dts b/arch/arm/dts/zynq-zturn-v5.dts
new file mode 100644
index 00..eebeec800f
--- /dev/null
+++ b/arch/arm/dts/zynq-zturn-v5.dts
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Alexandre Griveaux
+ *
+ * Based on zynq-zturn.dts which is:
+ * Copyright (C) 2015 Andrea Merello
+ * Copyright (C) 2017 Alexander Graf
+ *
+ */
+
+/dts-v1/;
+/include/ "zynq-7000.dtsi"
+
+/ {
+ model = "Zynq Z-Turn MYIR Board V5";
+ compatible = "myir,zynq-zturn", "xlnx,zynq-7000";
+
+ aliases {
+ ethernet0 =
+ serial0 =
+ serial1 =
+ mmc0 =
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x4000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+ usr-led1 {
+ label = "usr-led1";
+ gpios = < 0x0 0x1>;
+ default-state = "off";
+ };
+
+ usr-led2 {
+ label = "usr-led2";
+ gpios = < 0x9 0x1>;
+ default-state = "off";
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ autorepeat;
+ K1 {
+ label = "K1";
+ gpios = < 0x32 0x1>;
+ linux,code = <0x66>;
+ wakeup-source;
+ autorepeat;
+ };
+ };
+};
+
+ {
+ ps-clk-frequency = <>;
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <_phy>;
+
+ ethernet_phy: ethernet-phy@0 {
+ reg = <0x3>;
+ };
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+ {
+ u-boot,dm-pre-reloc;
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ dr_mode = "host";
+};
+
+ {
+ status = "okay";
+};
+
+ {
+ status = "okay";
+ clock-frequency = <40>;
+
+ stlm75@49 {
+ status = "okay";
+ compatible = "lm75";
+ reg = <0x49>;
+ };
+
+ accelerometer@53 {
+ compatible = "adi,adxl345", "adxl345", "adi,adxl34x", "adxl34x";
+ reg = <0x53>;
+ interrupt-parent = <>;
+ interrupts = <0x0 0x1e 0x4>;
+ };
+};
diff --git a/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
b/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
new file mode 100644
index 00..5d573868cb
--- /dev/null
+++ b/board/xilinx/zynq/zynq-zturn-v5/ps7_init_gpl.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) Xilinx, Inc.
+ */
+
+#include
+
+static unsigned long ps7_pll_init_data[] = {
+ EMIT_WRITE(0xF808, 0xDF0DU),
+ EMIT_MASKWRITE(0xF8000110, 0x0030U, 0x000FA220U),
+ EMIT_MASKWRITE(0xF8000100, 0x0007F000U, 0x00028000U),
+ EMIT_MASKWRITE(0xF8000100, 0x0010U, 0x0010U),
+ EMIT_MASKWRITE(0xF8000100, 0x0001U, 0x0001U),
+ EMIT_MASKWRITE(0xF8000100, 0x0001U, 0xU),
+ EMIT_MASKPOLL(0xF800010C, 0x0001U),
+ EMIT_MASKWRITE(0xF8000100, 0x0010U, 0xU),
+ EMIT_MASKWRITE(0xF8000120, 0x1F003F30U, 0x1F000200U),
+ EMIT_MASKWRITE(0xF8000114, 0x0030U, 0x0012C220U),
+ EMIT_MASKWRITE(0xF8000104, 0x0007F000U, 0x0002U),
+ EMIT_MASKWRITE(0xF8000104,
