Modify "CONFIG_AE350" to "CONFIG_ANDES_AE350"
Unify the memory layout for u-boot SPL.
Signed-off-by: Randolph
---
arch/riscv/Kconfig | 4 +-
arch/riscv/dts/Makefile | 2 +-
arch/riscv/dts/ae350-u-boot.dtsi | 1 +
arch/riscv/dts/ae350_32.dts | 61 ++--
arch/riscv/dts/ae350_64.dts | 1 -
board/AndesTech/ae350/Kconfig| 28 -
configs/ae350_rv32_defconfig | 3 +-
configs/ae350_rv32_spl_defconfig | 21 --
configs/ae350_rv32_spl_xip_defconfig | 18
configs/ae350_rv32_xip_defconfig | 3 +-
configs/ae350_rv64_defconfig | 3 +-
configs/ae350_rv64_spl_defconfig | 19 -
configs/ae350_rv64_spl_xip_defconfig | 16
configs/ae350_rv64_xip_defconfig | 3 +-
14 files changed, 101 insertions(+), 82 deletions(-)
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6771d8d919..aff1f33665 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -8,8 +8,8 @@ choice
prompt "Target select"
optional
-config TARGET_AE350
- bool "Support ae350"
+config TARGET_ANDES_AE350
+ bool "Support Andes ae350"
config TARGET_MICROCHIP_ICICLE
bool "Support Microchip PolarFire-SoC Icicle Board"
diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
index f1525cb668..be6c8a4227 100644
--- a/arch/riscv/dts/Makefile
+++ b/arch/riscv/dts/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0+
-dtb-$(CONFIG_TARGET_AE350) += ae350_32.dtb ae350_64.dtb
+dtb-$(CONFIG_TARGET_ANDES_AE350) += ae350_32.dtb ae350_64.dtb
dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
diff --git a/arch/riscv/dts/ae350-u-boot.dtsi b/arch/riscv/dts/ae350-u-boot.dtsi
index aef9159b7a..ff5725501f 100644
--- a/arch/riscv/dts/ae350-u-boot.dtsi
+++ b/arch/riscv/dts/ae350-u-boot.dtsi
@@ -1,4 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+#include CONFIG_SPL_LOAD_FIT_CONFIG
/ {
cpus {
diff --git a/arch/riscv/dts/ae350_32.dts b/arch/riscv/dts/ae350_32.dts
index 61af6d5465..3dde0e1dfa 100644
--- a/arch/riscv/dts/ae350_32.dts
+++ b/arch/riscv/dts/ae350_32.dts
@@ -2,12 +2,11 @@
/dts-v1/;
-#include "binman.dtsi"
#include "ae350-u-boot.dtsi"
/ {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "andestech,a25";
model = "andestech,a25";
@@ -115,7 +114,7 @@
compatible = "cache";
cache-level = <2>;
cache-size = <0x4>;
- reg = <0xe050 0x4>;
+ reg = <0x0 0xe050 0x0 0x4>;
andes,inst-prefetch = <3>;
andes,data-prefetch = <3>;
/* The value format is */
@@ -125,12 +124,12 @@
memory@0 {
device_type = "memory";
- reg = <0x 0x4000>;
+ reg = <0x0 0x 0x0 0x4000>;
};
soc {
- #address-cells = <1>;
- #size-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
compatible = "simple-bus";
ranges;
@@ -138,7 +137,7 @@
compatible = "riscv,plic0";
#interrupt-cells = <2>;
interrupt-controller;
- reg = <0xe400 0x200>;
+ reg = <0x0 0xe400 0x0 0x200>;
riscv,ndev=<71>;
interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9
&CPU1_intc 11 &CPU1_intc 9
@@ -148,9 +147,9 @@
plicsw: interrupt-controller@e640 {
compatible = "andestech,plicsw";
- #interrupt-cells = <1>;
+ #interrupt-cells = <2>;
interrupt-controller;
- reg = <0xe640 0x40>;
+ reg = <0x0 0xe640 0x0 0x40>;
riscv,ndev=<2>;
interrupts-extended = <&CPU0_intc 3
&CPU1_intc 3
@@ -164,7 +163,7 @@
&CPU1_intc 7
&CPU2_intc 7
&CPU3_intc 7>;
- reg = <0xe600 0x10>;
+ reg = <0x0 0xe600 0x0 0x10>;
};
};
@@ -176,7 +175,7 @@
timer0: timer@f040 {
compatible = "andestech,atcpit100";
- reg = <0xf040 0x1000>;
+ reg = <0x0 0xf040 0x0 0x1000>;
clock-frequency = <6000>;
interrupts = <3 4>;
interrupt-parent = <&plic