BCM63138 is an ARM A9 based DSL Broadband SoC. It is part of the BCA
(Broadband Carrier Access origin) chipset family so it's added under
ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory, peripheral timer and
Broadcom uart.
This SoC is supported in the linux-next git repository so the dts and
dtsi files are stripped down version of linux copies with mininum blocks
needed by u-boot.
The u-boot image can be loaded from flash or network to the entry
point address in the memory and boot from there.
This patch applies on top of the my previous patch [1] and depends
on the timer support from patch [2].
[1] https://lists.denx.de/pipermail/u-boot/2022-August/490597.html
[2] https://lists.denx.de/pipermail/u-boot/2022-August/490570.html
Signed-off-by: William Zhang
---
MAINTAINERS| 1 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/bcm63138.dtsi | 102 +
arch/arm/dts/bcm963138.dts | 30
arch/arm/mach-bcmbca/Kconfig | 9 +++
arch/arm/mach-bcmbca/Makefile | 1 +
arch/arm/mach-bcmbca/bcm63138/Kconfig | 17 +
arch/arm/mach-bcmbca/bcm63138/Makefile | 5 ++
board/broadcom/bcmbca/Kconfig | 7 ++
configs/bcm963138_defconfig| 22 ++
include/configs/bcm963138.h| 11 +++
11 files changed, 207 insertions(+)
create mode 100644 arch/arm/dts/bcm63138.dtsi
create mode 100644 arch/arm/dts/bcm963138.dts
create mode 100644 arch/arm/mach-bcmbca/bcm63138/Kconfig
create mode 100644 arch/arm/mach-bcmbca/bcm63138/Makefile
create mode 100644 configs/bcm963138_defconfig
create mode 100644 include/configs/bcm963138.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 8c3a7d77f17d..2a27d15705cb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -219,6 +219,7 @@ F: board/broadcom/bcmbca/
F: drivers/timer/bcmbca-timer.c
N: bcmbca
N: bcm[9]?47622
+N: bcm[9]?63138
N: bcm[9]?63148
N: bcm[9]?63178
N: bcm[9]?6756
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b8d136bd129b..f4fa6f517744 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1165,6 +1165,8 @@ dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
dtb-$(CONFIG_BCM47622) += \
bcm947622.dtb
+dtb-$(CONFIG_BCM63138) += \
+ bcm963138.dtb
dtb-$(CONFIG_BCM63148) += \
bcm963148.dtb
dtb-$(CONFIG_BCM63178) += \
diff --git a/arch/arm/dts/bcm63138.dtsi b/arch/arm/dts/bcm63138.dtsi
new file mode 100644
index ..0665f24e8308
--- /dev/null
+++ b/arch/arm/dts/bcm63138.dtsi
@@ -0,0 +1,102 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Broadcom BCM63138 DSL SoCs Device Tree
+ */
+
+#include
+#include
+
+/ {
+ compatible = "brcm,bcm63138", "brcm,bcmbca";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ interrupt-parent = <>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <0>;
+ enable-method = "brcm,bcm63138";
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ next-level-cache = <>;
+ reg = <1>;
+ enable-method = "brcm,bcm63138";
+ };
+ };
+
+ clocks {
+ /* UBUS peripheral clock */
+ periph_clk: periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <5000>;
+ clock-output-names = "periph";
+ };
+ };
+
+ /* ARM bus */
+ axi@8000 {
+ compatible = "simple-bus";
+ ranges = <0 0x8000 0x784000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ L2: cache-controller@1d000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x1d000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
+ cache-size = <524288>;
+ cache-sets = <1024>;
+ cache-line-size = <32>;
+ interrupts = ;
+ };
+
+ scu: scu@1e000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x1e000 0x100>;
+ };
+
+ gic: interrupt-controller@1f000 {
+ compatible = "arm,cortex-a9-gic";
+ reg = <0x1f000 0x1000
+ 0x1e100 0x100>;
+ #interrupt-cells = <3>;
+
