Re: [PATCH] arm: dts: stm32mp15: alignment with v5.11-rc2
Hi, On 1/11/21 12:33 PM, Patrick Delaunay wrote: Device tree alignment with Linux kernel v5.11-rc2 - fix DCMI DMA features on stm32mp15 family - Add alternate pinmux for FMC EBI bus - Harmonize EHCI/OHCI DT nodes name on stm32mp15 - update sdmmc IP version for STM32MP15 - Add LP timer irqs on stm32mp151 - Add LP timer wakeup-source on stm32mp151 - enable HASH by default on stm32mp15 - enable CRC1 by default on stm32mp15 - enable CRYP by default on stm32mp15 - set bus-type in DCMI endpoint for stm32mp157c-ev1 board - reorder spi4 within stm32mp15-pinctrl - add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx - fix mdma1 clients channel priority level on stm32mp151 - fix dmamux reg property on stm32mp151 - adjust USB OTG gadget fifo sizes in stm32mp151 - update stm32mp151 for remote proc synchronization support - support child mfd cells for the stm32mp1 TAMP syscon Signed-off-by: Patrick Delaunay Signed-off-by: Patrick Delaunay --- arch/arm/dts/stm32mp15-pinctrl.dtsi| 87 +- arch/arm/dts/stm32mp151.dtsi | 48 +--- arch/arm/dts/stm32mp153.dtsi | 6 ++ arch/arm/dts/stm32mp157c-dk2.dts | 4 + arch/arm/dts/stm32mp157c-ed1.dts | 27 +++ arch/arm/dts/stm32mp157c-ev1.dts | 1 + arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 55 -- arch/arm/dts/stm32mp15xx-dkx.dtsi | 47 ++-- 8 files changed, 200 insertions(+), 75 deletions(-) Applied to u-boot-stm/master, thanks! Regards Patrick
Re: [PATCH] arm: dts: stm32mp15: alignment with v5.11-rc2
On 1/13/21 10:48 AM, Patrick DELAUNAY wrote:
Hi Marek,
Hi,
On 1/11/21 1:15 PM, Marek Vasut wrote:
On 1/11/21 12:33 PM, Patrick Delaunay wrote:
Device tree alignment with Linux kernel v5.11-rc2
- fix DCMI DMA features on stm32mp15 family
- Add alternate pinmux for FMC EBI bus
- Harmonize EHCI/OHCI DT nodes name on stm32mp15
- update sdmmc IP version for STM32MP15
- Add LP timer irqs on stm32mp151
- Add LP timer wakeup-source on stm32mp151
- enable HASH by default on stm32mp15
- enable CRC1 by default on stm32mp15
- enable CRYP by default on stm32mp15
- set bus-type in DCMI endpoint for stm32mp157c-ev1 board
- reorder spi4 within stm32mp15-pinctrl
- add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx
- fix mdma1 clients channel priority level on stm32mp151
- fix dmamux reg property on stm32mp151
- adjust USB OTG gadget fifo sizes in stm32mp151
- update stm32mp151 for remote proc synchronization support
- support child mfd cells for the stm32mp1 TAMP syscon
Are you completely sure the dhcom based boards generate the same DT
after the sync ?
I would rather prefer sync with Linux 5.10 (LTS), or is that not an
option due to some extra DT patches ?
Either way, if you have an upstream queue for this DT sync somewhere,
please give me a link, I plan to sync the dhcom boards after 2021.01
is out, so I would build on top of that.
I am sure the DT is not the same, sorry.
At least for the SOC part (new nodes, updates value).
I compare the dhcom device tree (dts file form dtb) and I don't found
modifications except the phandle changes and the expected modifications.
But it is not a exhaustive check.
There is dtdiff, you can run it on the generated SPL and U-Boot DTBs
before and after your changes. That should be a thorough check.
For ST boards, the U-Boot device trees are aligned with Linux 5.9 since
the commit 62f95af92a3fc21a72f5f3198f0d065cbd773f03 ("ARM: dts:
stm32mp1: DT alignment with Linux kernel v5.9-rc4")
I skip the Linux 5.10 (LTS) as it comes after v2020.10 merge windows and
the 5.11 device tree are already updated (pull request from Alexandre
Torgue =
https://kernel.googlesource.com/pub/scm/linux/kernel/git/atorgue/stm32)
But if you prefer I can split it in 2 steps
1/ Device tree alignment with Linux kernel v5.10 (LTS)
2/ Device tree alignment with Linux kernel v5.11-rc2
Today the patch is present in next branch of stm custodians
(https://gitlab.denx.de/u-boot/custodians/u-boot-stm/-/tree/next)
And I am preparing a pull request for the master branch.
Keep it as-is, I just wanted to know why you didn't pick the LTS option,
now it's clear, thanks.
Re: [PATCH] arm: dts: stm32mp15: alignment with v5.11-rc2
Hi Marek,
On 1/11/21 1:15 PM, Marek Vasut wrote:
On 1/11/21 12:33 PM, Patrick Delaunay wrote:
Device tree alignment with Linux kernel v5.11-rc2
- fix DCMI DMA features on stm32mp15 family
- Add alternate pinmux for FMC EBI bus
- Harmonize EHCI/OHCI DT nodes name on stm32mp15
- update sdmmc IP version for STM32MP15
- Add LP timer irqs on stm32mp151
- Add LP timer wakeup-source on stm32mp151
- enable HASH by default on stm32mp15
- enable CRC1 by default on stm32mp15
- enable CRYP by default on stm32mp15
- set bus-type in DCMI endpoint for stm32mp157c-ev1 board
- reorder spi4 within stm32mp15-pinctrl
- add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx
- fix mdma1 clients channel priority level on stm32mp151
- fix dmamux reg property on stm32mp151
- adjust USB OTG gadget fifo sizes in stm32mp151
- update stm32mp151 for remote proc synchronization support
- support child mfd cells for the stm32mp1 TAMP syscon
Are you completely sure the dhcom based boards generate the same DT
after the sync ?
I would rather prefer sync with Linux 5.10 (LTS), or is that not an
option due to some extra DT patches ?
Either way, if you have an upstream queue for this DT sync somewhere,
please give me a link, I plan to sync the dhcom boards after 2021.01
is out, so I would build on top of that.
I am sure the DT is not the same, sorry.
At least for the SOC part (new nodes, updates value).
I compare the dhcom device tree (dts file form dtb) and I don't found
modifications except the phandle changes and the expected modifications.
But it is not a exhaustive check.
For ST boards, the U-Boot device trees are aligned with Linux 5.9 since
the commit 62f95af92a3fc21a72f5f3198f0d065cbd773f03 ("ARM: dts:
stm32mp1: DT alignment with Linux kernel v5.9-rc4")
I skip the Linux 5.10 (LTS) as it comes after v2020.10 merge windows and
the 5.11 device tree are already updated (pull request from Alexandre
Torgue =
https://kernel.googlesource.com/pub/scm/linux/kernel/git/atorgue/stm32)
But if you prefer I can split it in 2 steps
1/ Device tree alignment with Linux kernel v5.10 (LTS)
2/ Device tree alignment with Linux kernel v5.11-rc2
Today the patch is present in next branch of stm custodians
(https://gitlab.denx.de/u-boot/custodians/u-boot-stm/-/tree/next)
And I am preparing a pull request for the master branch.
Patrick
Re: [PATCH] arm: dts: stm32mp15: alignment with v5.11-rc2
On 1/11/21 12:33 PM, Patrick Delaunay wrote: Device tree alignment with Linux kernel v5.11-rc2 - fix DCMI DMA features on stm32mp15 family - Add alternate pinmux for FMC EBI bus - Harmonize EHCI/OHCI DT nodes name on stm32mp15 - update sdmmc IP version for STM32MP15 - Add LP timer irqs on stm32mp151 - Add LP timer wakeup-source on stm32mp151 - enable HASH by default on stm32mp15 - enable CRC1 by default on stm32mp15 - enable CRYP by default on stm32mp15 - set bus-type in DCMI endpoint for stm32mp157c-ev1 board - reorder spi4 within stm32mp15-pinctrl - add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx - fix mdma1 clients channel priority level on stm32mp151 - fix dmamux reg property on stm32mp151 - adjust USB OTG gadget fifo sizes in stm32mp151 - update stm32mp151 for remote proc synchronization support - support child mfd cells for the stm32mp1 TAMP syscon Are you completely sure the dhcom based boards generate the same DT after the sync ? I would rather prefer sync with Linux 5.10 (LTS), or is that not an option due to some extra DT patches ? Either way, if you have an upstream queue for this DT sync somewhere, please give me a link, I plan to sync the dhcom boards after 2021.01 is out, so I would build on top of that.
[PATCH] arm: dts: stm32mp15: alignment with v5.11-rc2
Device tree alignment with Linux kernel v5.11-rc2
- fix DCMI DMA features on stm32mp15 family
- Add alternate pinmux for FMC EBI bus
- Harmonize EHCI/OHCI DT nodes name on stm32mp15
- update sdmmc IP version for STM32MP15
- Add LP timer irqs on stm32mp151
- Add LP timer wakeup-source on stm32mp151
- enable HASH by default on stm32mp15
- enable CRC1 by default on stm32mp15
- enable CRYP by default on stm32mp15
- set bus-type in DCMI endpoint for stm32mp157c-ev1 board
- reorder spi4 within stm32mp15-pinctrl
- add STUSB1600 Type-C using I2C4 on stm32mp15xx-dkx
- fix mdma1 clients channel priority level on stm32mp151
- fix dmamux reg property on stm32mp151
- adjust USB OTG gadget fifo sizes in stm32mp151
- update stm32mp151 for remote proc synchronization support
- support child mfd cells for the stm32mp1 TAMP syscon
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrick Delaunay
---
arch/arm/dts/stm32mp15-pinctrl.dtsi| 87 +-
arch/arm/dts/stm32mp151.dtsi | 48 +---
arch/arm/dts/stm32mp153.dtsi | 6 ++
arch/arm/dts/stm32mp157c-dk2.dts | 4 +
arch/arm/dts/stm32mp157c-ed1.dts | 27 +++
arch/arm/dts/stm32mp157c-ev1.dts | 1 +
arch/arm/dts/stm32mp15xx-dhcom-u-boot.dtsi | 55 --
arch/arm/dts/stm32mp15xx-dkx.dtsi | 47 ++--
8 files changed, 200 insertions(+), 75 deletions(-)
diff --git a/arch/arm/dts/stm32mp15-pinctrl.dtsi
b/arch/arm/dts/stm32mp15-pinctrl.dtsi
index 154832983c..dd4bd1e554 100644
--- a/arch/arm/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/dts/stm32mp15-pinctrl.dtsi
@@ -349,6 +349,61 @@
};
};
+ fmc_pins_b: fmc-1 {
+ pins {
+ pinmux = , /* FMC_NOE */
+, /* FMC_NWE */
+, /* FMC_NL */
+, /* FMC_D0 */
+, /* FMC_D1 */
+, /* FMC_D2 */
+, /* FMC_D3 */
+, /* FMC_D4 */
+, /* FMC_D5 */
+, /* FMC_D6 */
+, /* FMC_D7 */
+, /* FMC_D8 */
+, /* FMC_D9 */
+, /* FMC_D10 */
+, /* FMC_D11 */
+, /* FMC_D12 */
+, /* FMC_D13 */
+, /* FMC_D14 */
+, /* FMC_D15 */
+, /*
FMC_NE2_FMC_NCE */
+; /* FMC_NE4 */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <3>;
+ };
+ };
+
+ fmc_sleep_pins_b: fmc-sleep-1 {
+ pins {
+ pinmux = , /* FMC_NOE */
+, /* FMC_NWE */
+, /* FMC_NL */
+, /* FMC_D0 */
+, /* FMC_D1 */
+, /* FMC_D2 */
+, /* FMC_D3 */
+, /* FMC_D4 */
+, /* FMC_D5 */
+, /* FMC_D6 */
+, /* FMC_D7 */
+, /* FMC_D8 */
+, /* FMC_D9 */
+, /* FMC_D10 */
+, /* FMC_D11 */
+, /* FMC_D12 */
+, /* FMC_D13 */
+, /* FMC_D14 */
+, /* FMC_D15 */
+, /*
FMC_NE2_FMC_NCE */
+; /* FMC_NE4 */
+ };
+ };
+
i2c1_pins_a: i2c1-0 {
pins {
pinmux = , /* I2C1_SCL */
@@ -1437,6 +1492,24 @@
};
};
+ sdmmc2_d47_pins_d: sdmmc2-d47-3 {
+ pins {
+ pinmux = , /* SDMMC2_D4 */
+, /* SDMMC2_D5 */
+, /* SDMMC2_D6 */
+; /* SDMMC2_D7 */
+ };
+ };
+
+ sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 {
+ pins {
+ pinmux = , /* SDMMC2_D4 */
+, /* SDMMC2_D5 */
+, /* SDMMC2_D6 */
+; /* SDMMC2_D7 */
+ };
+ };
+
sdmmc3_b4_pins_a: sdmmc3-b4-0 {
pins1 {
pinmux = , /* SDMMC3_D0 */
@@ -1588,9 +1661,9 @@
};
stusb1600_pins_a: stusb1600-0 {
-
