Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to 8.
The C7x and VPAC have been overwhelming the DSS's access to the DDR
(when it was accessing via the Non Real-Time (NRT) Queue), primarily
because their functional frequencies, and hence DDR accesses, were
significantly higher than that of DSS. This led the display to flicker
when certain edgeAI models were being run.
With the DSS traffic serviced from the RT queue, the flickering issue
has been found to be mitigated.
The am62a qos files are auto generated from the k3 resource partitioning
tool.
Section-3.1.12, "QoS Programming Guide", in the AM62A TRM[1], provides
more information about the QoS, and section-14.1, "System Interconnect
Registers", provides the register descriptions.
[1] AM62A Tech Ref Manual: https://www.ti.com/lit/pdf/spruj16
Signed-off-by: Aradhya Bhatia
---
arch/arm/mach-k3/am62a7_init.c| 16 +++
arch/arm/mach-k3/am62ax/Makefile | 1 +
arch/arm/mach-k3/am62ax/am62a_qos_data.c | 47 +
arch/arm/mach-k3/include/mach/am62a_qos.h | 114 ++
arch/arm/mach-k3/include/mach/hardware.h | 9 ++
5 files changed, 187 insertions(+)
create mode 100644 arch/arm/mach-k3/am62ax/am62a_qos_data.c
create mode 100644 arch/arm/mach-k3/include/mach/am62a_qos.h
diff --git a/arch/arm/mach-k3/am62a7_init.c b/arch/arm/mach-k3/am62a7_init.c
index 02da24a3d6f0..2a827a31cf19 100644
--- a/arch/arm/mach-k3/am62a7_init.c
+++ b/arch/arm/mach-k3/am62a7_init.c
@@ -65,6 +65,20 @@ static void ctrl_mmr_unlock(void)
mmr_unlock(PADCFG_MMR1_BASE, 1);
}
+#if (IS_ENABLED(CONFIG_CPU_V7R))
+static void setup_qos(void)
+{
+ u32 i;
+
+ for (i = 0; i < am62a_qos_count; i++)
+ writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg);
+}
+#else
+static void setup_qos(void)
+{
+}
+#endif
+
void board_init_f(ulong dummy)
{
struct udevice *dev;
@@ -158,6 +172,8 @@ void board_init_f(ulong dummy)
panic("DRAM init failed: %d\n", ret);
#endif
+ setup_qos();
+
printf("am62a_init: %s done\n", __func__);
}
diff --git a/arch/arm/mach-k3/am62ax/Makefile b/arch/arm/mach-k3/am62ax/Makefile
index c58e52df1fa2..02a941805e9a 100644
--- a/arch/arm/mach-k3/am62ax/Makefile
+++ b/arch/arm/mach-k3/am62ax/Makefile
@@ -4,3 +4,4 @@
obj-y += clk-data.o
obj-y += dev-data.o
+obj-y += am62a_qos_data.o
diff --git a/arch/arm/mach-k3/am62ax/am62a_qos_data.c
b/arch/arm/mach-k3/am62ax/am62a_qos_data.c
new file mode 100644
index ..01b76f7493c3
--- /dev/null
+++ b/arch/arm/mach-k3/am62ax/am62a_qos_data.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am62a Quality of Service (QoS) Configuration Data
+ * Auto generated from K3 Resource Partitioning tool
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#include
+#include
+#include "common.h"
+
+struct k3_qos_data am62a_qos_data[] = {
+ /* modules_qosConfig0 - 1 endpoints, 4 channels */
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
+ .val = ORDERID_8,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1,
+ .val = ORDERID_8,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2,
+ .val = ORDERID_8,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3,
+ .val = ORDERID_8,
+ },
+
+ /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+* remap registers. orderID x is remapped to orderID x again
+* This is to ensure orderID from MAP register is unchanged
+*/
+
+ /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0,
+ .val = 0x76543210,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4,
+ .val = 0xfedcba98,
+ },
+};
+
+uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]);
diff --git a/arch/arm/mach-k3/include/mach/am62a_qos.h
b/arch/arm/mach-k3/include/mach/am62a_qos.h
new file mode 100644
index ..c74d69a28f8c
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am62a_qos.h
@@ -0,0 +1,114 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define QOS_0 (0 << 0)
+#define QOS_1 (1 << 0)
+#define QOS_2 (2 << 0)
+#define QOS_3 (3 << 0)
+#define QOS_4 (4 << 0)
+#define QOS_5 (5 << 0)
+#define QOS_6 (6 << 0)
+#define QOS_7 (7 << 0)
+
+#define ORDERID_0 (0 << 4)
+#define ORDERID_1 (1 << 4)
+#define ORDERID_2 (2 << 4)
+#define ORDERID
