Re: [PATCH] phy: zynqmp: Add serdes/psgtr driver
On 11/29/21 16:12, Sean Anderson wrote: On 11/24/21 9:52 AM, Michal Simek wrote: On 11/22/21 22:53, Sean Anderson wrote: On 11/18/21 7:30 AM, Michal Simek wrote: Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Are USB3 and SGMII all that's been tested? I noticed that the kernel driver has DP- and SATA-specific stuff which has been left out. Presumably they are not supported? I have tested USB3 and SGMII. I didn't test DP/SATA and there is missing some code for it. DP will be tested with u-boot driver which we will develop. Perhaps also note that the termination fix is not implemented. Terminanation fix was for v1 silicon which none is really using now that's why this code is not needed for newly written SW. Signed-off-by: Michal Simek --- MAINTAINERS | 1 + drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-zynqmp.c | 690 +++ 4 files changed, 699 insertions(+) create mode 100644 drivers/phy/phy-zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index 1eb71cbdad12..d1e9fbd4a279 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -611,6 +611,7 @@ F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c +F: drivers/phy/phy-zynqmp.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 4767d215f337..d79798429b18 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -281,6 +281,13 @@ config PHY_IMX8MQ_USB help Support the USB3.0 PHY in NXP i.MX8MQ SoC +config PHY_XILINX_ZYNQMP + tristate "Xilinx ZynqMP PHY driver" + depends on PHY && ARCH_ZYNQMP + help + Enable this to support ZynqMP High Speed Gigabit Transceiver + that is part of ZynqMP SoC. + source "drivers/phy/rockchip/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 13a8ade8919f..bf9b40932fe3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -38,5 +38,6 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o +obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ obj-y += ti/ diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c new file mode 100644 index ..d6fe8dcef74e --- /dev/null +++ b/drivers/phy/phy-zynqmp.c @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. + * + * Copyright (C) 2018-2021 Xilinx Inc. + * + * Author: Anurag Kumar Vulisha + * Author: Subbaraya Sundeep + * Author: Laurent Pinchart + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +/* + * Lane Registers + */ + +/* TX De-emphasis parameters */ +#define L0_TX_ANA_TM_18 0x0048 +#define L0_TX_ANA_TM_118 0x01d8 +#define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0) + +/* DN Resistor calibration code parameters */ +#define L0_TXPMA_ST_3 0x0b0c +#define L0_DN_CALIB_CODE 0x3f + +/* PMA control parameters */ +#define L0_TXPMD_TM_45 0x0cb4 +#define L0_TXPMD_TM_48 0x0cc0 +#define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0) +#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1) +#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2) +#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3) +#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4) +#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5) + +/* PCS control parameters */ +#define L0_TM_DIG_6 0x106c +#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f +#define L0_TX_DIG_61 0x00f4 +#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f + +/* PLL Test Mode register parameters */ +#define L0_TM_PLL_DIG_37 0x2094 +#define L0_TM_COARSE_CODE_LIMIT 0x10 + +/* PLL SSC step size offsets */ +#define L0_PLL_SS_STEPS_0_LSB 0x2368 +#define L0_PLL_SS_STEPS_1_MSB 0x236c +#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370 +#define L0_PLL_SS_STEP_SIZE_1 0x2374 +#define L0_PLL_SS_STEP_SIZE_2 0x2378 +#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c +#define L0_PLL_STATUS_READ_1 0x23e4 + +/* SSC step size parameters */ +#define STEP_SIZE_0_MASK 0xff +#define STEP_SIZE_1_MASK 0xff +#define STEP_SIZE_2_MASK 0xff +#define STEP_SIZE_3_MASK 0x3 +#define STEP_SIZE_SHIFT 8 +#define
Re: [PATCH] phy: zynqmp: Add serdes/psgtr driver
On 11/24/21 9:52 AM, Michal Simek wrote: On 11/22/21 22:53, Sean Anderson wrote: On 11/18/21 7:30 AM, Michal Simek wrote: Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Are USB3 and SGMII all that's been tested? I noticed that the kernel driver has DP- and SATA-specific stuff which has been left out. Presumably they are not supported? I have tested USB3 and SGMII. I didn't test DP/SATA and there is missing some code for it. DP will be tested with u-boot driver which we will develop. Perhaps also note that the termination fix is not implemented. Terminanation fix was for v1 silicon which none is really using now that's why this code is not needed for newly written SW. Signed-off-by: Michal Simek --- MAINTAINERS | 1 + drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-zynqmp.c | 690 +++ 4 files changed, 699 insertions(+) create mode 100644 drivers/phy/phy-zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index 1eb71cbdad12..d1e9fbd4a279 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -611,6 +611,7 @@ F:drivers/mmc/zynq_sdhci.c F:drivers/mtd/nand/raw/zynq_nand.c F:drivers/net/phy/xilinx_phy.c F:drivers/net/zynq_gem.c +F:drivers/phy/phy-zynqmp.c F:drivers/serial/serial_zynq.c F:drivers/reset/reset-zynqmp.c F:drivers/rtc/zynqmp_rtc.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 4767d215f337..d79798429b18 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -281,6 +281,13 @@ config PHY_IMX8MQ_USB help Support the USB3.0 PHY in NXP i.MX8MQ SoC +config PHY_XILINX_ZYNQMP +tristate "Xilinx ZynqMP PHY driver" +depends on PHY && ARCH_ZYNQMP +help + Enable this to support ZynqMP High Speed Gigabit Transceiver + that is part of ZynqMP SoC. + source "drivers/phy/rockchip/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 13a8ade8919f..bf9b40932fe3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -38,5 +38,6 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o +obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ obj-y += ti/ diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c new file mode 100644 index ..d6fe8dcef74e --- /dev/null +++ b/drivers/phy/phy-zynqmp.c @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. + * + * Copyright (C) 2018-2021 Xilinx Inc. + * + * Author: Anurag Kumar Vulisha + * Author: Subbaraya Sundeep + * Author: Laurent Pinchart + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +/* + * Lane Registers + */ + +/* TX De-emphasis parameters */ +#define L0_TX_ANA_TM_180x0048 +#define L0_TX_ANA_TM_1180x01d8 +#define L0_TX_ANA_TM_118_FORCE_17_0BIT(0) + +/* DN Resistor calibration code parameters */ +#define L0_TXPMA_ST_30x0b0c +#define L0_DN_CALIB_CODE0x3f + +/* PMA control parameters */ +#define L0_TXPMD_TM_450x0cb4 +#define L0_TXPMD_TM_480x0cc0 +#define L0_TXPMD_TM_45_OVER_DP_MAINBIT(0) +#define L0_TXPMD_TM_45_ENABLE_DP_MAINBIT(1) +#define L0_TXPMD_TM_45_OVER_DP_POST1BIT(2) +#define L0_TXPMD_TM_45_ENABLE_DP_POST1BIT(3) +#define L0_TXPMD_TM_45_OVER_DP_POST2BIT(4) +#define L0_TXPMD_TM_45_ENABLE_DP_POST2BIT(5) + +/* PCS control parameters */ +#define L0_TM_DIG_60x106c +#define L0_TM_DIS_DESCRAMBLE_DECODER0x0f +#define L0_TX_DIG_610x00f4 +#define L0_TM_DISABLE_SCRAMBLE_ENCODER0x0f + +/* PLL Test Mode register parameters */ +#define L0_TM_PLL_DIG_370x2094 +#define L0_TM_COARSE_CODE_LIMIT0x10 + +/* PLL SSC step size offsets */ +#define L0_PLL_SS_STEPS_0_LSB0x2368 +#define L0_PLL_SS_STEPS_1_MSB0x236c +#define L0_PLL_SS_STEP_SIZE_0_LSB0x2370 +#define L0_PLL_SS_STEP_SIZE_10x2374 +#define L0_PLL_SS_STEP_SIZE_20x2378 +#define L0_PLL_SS_STEP_SIZE_3_MSB0x237c +#define L0_PLL_STATUS_READ_10x23e4 + +/* SSC step size parameters */ +#define STEP_SIZE_0_MASK0xff +#define STEP_SIZE_1_MASK0xff +#define STEP_SIZE_2_MASK0xff +#define STEP_SIZE_3_MASK0x3 +#define STEP_SIZE_SHIFT8 +#define FORCE_STEP_SIZE0x10 +#define FORCE_STEPS
Re: [PATCH] phy: zynqmp: Add serdes/psgtr driver
On 11/22/21 22:53, Sean Anderson wrote: On 11/18/21 7:30 AM, Michal Simek wrote: Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Are USB3 and SGMII all that's been tested? I noticed that the kernel driver has DP- and SATA-specific stuff which has been left out. Presumably they are not supported? I have tested USB3 and SGMII. I didn't test DP/SATA and there is missing some code for it. DP will be tested with u-boot driver which we will develop. Perhaps also note that the termination fix is not implemented. Terminanation fix was for v1 silicon which none is really using now that's why this code is not needed for newly written SW. Signed-off-by: Michal Simek --- MAINTAINERS | 1 + drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-zynqmp.c | 690 +++ 4 files changed, 699 insertions(+) create mode 100644 drivers/phy/phy-zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index 1eb71cbdad12..d1e9fbd4a279 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -611,6 +611,7 @@ F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c +F: drivers/phy/phy-zynqmp.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 4767d215f337..d79798429b18 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -281,6 +281,13 @@ config PHY_IMX8MQ_USB help Support the USB3.0 PHY in NXP i.MX8MQ SoC +config PHY_XILINX_ZYNQMP + tristate "Xilinx ZynqMP PHY driver" + depends on PHY && ARCH_ZYNQMP + help + Enable this to support ZynqMP High Speed Gigabit Transceiver + that is part of ZynqMP SoC. + source "drivers/phy/rockchip/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 13a8ade8919f..bf9b40932fe3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -38,5 +38,6 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o +obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ obj-y += ti/ diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c new file mode 100644 index ..d6fe8dcef74e --- /dev/null +++ b/drivers/phy/phy-zynqmp.c @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. + * + * Copyright (C) 2018-2021 Xilinx Inc. + * + * Author: Anurag Kumar Vulisha + * Author: Subbaraya Sundeep + * Author: Laurent Pinchart + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +/* + * Lane Registers + */ + +/* TX De-emphasis parameters */ +#define L0_TX_ANA_TM_18 0x0048 +#define L0_TX_ANA_TM_118 0x01d8 +#define L0_TX_ANA_TM_118_FORCE_17_0 BIT(0) + +/* DN Resistor calibration code parameters */ +#define L0_TXPMA_ST_3 0x0b0c +#define L0_DN_CALIB_CODE 0x3f + +/* PMA control parameters */ +#define L0_TXPMD_TM_45 0x0cb4 +#define L0_TXPMD_TM_48 0x0cc0 +#define L0_TXPMD_TM_45_OVER_DP_MAIN BIT(0) +#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1) +#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2) +#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3) +#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4) +#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5) + +/* PCS control parameters */ +#define L0_TM_DIG_6 0x106c +#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f +#define L0_TX_DIG_61 0x00f4 +#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f + +/* PLL Test Mode register parameters */ +#define L0_TM_PLL_DIG_37 0x2094 +#define L0_TM_COARSE_CODE_LIMIT 0x10 + +/* PLL SSC step size offsets */ +#define L0_PLL_SS_STEPS_0_LSB 0x2368 +#define L0_PLL_SS_STEPS_1_MSB 0x236c +#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370 +#define L0_PLL_SS_STEP_SIZE_1 0x2374 +#define L0_PLL_SS_STEP_SIZE_2 0x2378 +#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c +#define L0_PLL_STATUS_READ_1 0x23e4 + +/* SSC step size parameters */ +#define STEP_SIZE_0_MASK 0xff +#define STEP_SIZE_1_MASK 0xff +#define STEP_SIZE_2_MASK 0xff +#define STEP_SIZE_3_MASK 0x3 +#define STEP_SIZE_SHIFT 8 +#define FORCE_STEP_SIZE 0x10 +#define FORCE_STEPS 0x20 +#define STEPS_0_MASK
Re: [PATCH] phy: zynqmp: Add serdes/psgtr driver
On 11/18/21 7:30 AM, Michal Simek wrote: Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Are USB3 and SGMII all that's been tested? I noticed that the kernel driver has DP- and SATA-specific stuff which has been left out. Presumably they are not supported? Perhaps also note that the termination fix is not implemented. Signed-off-by: Michal Simek --- MAINTAINERS | 1 + drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-zynqmp.c | 690 +++ 4 files changed, 699 insertions(+) create mode 100644 drivers/phy/phy-zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index 1eb71cbdad12..d1e9fbd4a279 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -611,6 +611,7 @@ F: drivers/mmc/zynq_sdhci.c F:drivers/mtd/nand/raw/zynq_nand.c F:drivers/net/phy/xilinx_phy.c F:drivers/net/zynq_gem.c +F: drivers/phy/phy-zynqmp.c F:drivers/serial/serial_zynq.c F:drivers/reset/reset-zynqmp.c F:drivers/rtc/zynqmp_rtc.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 4767d215f337..d79798429b18 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -281,6 +281,13 @@ config PHY_IMX8MQ_USB help Support the USB3.0 PHY in NXP i.MX8MQ SoC +config PHY_XILINX_ZYNQMP + tristate "Xilinx ZynqMP PHY driver" + depends on PHY && ARCH_ZYNQMP + help + Enable this to support ZynqMP High Speed Gigabit Transceiver + that is part of ZynqMP SoC. + source "drivers/phy/rockchip/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 13a8ade8919f..bf9b40932fe3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -38,5 +38,6 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o +obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ obj-y += ti/ diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c new file mode 100644 index ..d6fe8dcef74e --- /dev/null +++ b/drivers/phy/phy-zynqmp.c @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. + * + * Copyright (C) 2018-2021 Xilinx Inc. + * + * Author: Anurag Kumar Vulisha + * Author: Subbaraya Sundeep + * Author: Laurent Pinchart + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +/* + * Lane Registers + */ + +/* TX De-emphasis parameters */ +#define L0_TX_ANA_TM_180x0048 +#define L0_TX_ANA_TM_118 0x01d8 +#define L0_TX_ANA_TM_118_FORCE_17_0BIT(0) + +/* DN Resistor calibration code parameters */ +#define L0_TXPMA_ST_3 0x0b0c +#define L0_DN_CALIB_CODE 0x3f + +/* PMA control parameters */ +#define L0_TXPMD_TM_45 0x0cb4 +#define L0_TXPMD_TM_48 0x0cc0 +#define L0_TXPMD_TM_45_OVER_DP_MAINBIT(0) +#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1) +#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2) +#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3) +#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4) +#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5) + +/* PCS control parameters */ +#define L0_TM_DIG_60x106c +#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f +#define L0_TX_DIG_61 0x00f4 +#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f + +/* PLL Test Mode register parameters */ +#define L0_TM_PLL_DIG_37 0x2094 +#define L0_TM_COARSE_CODE_LIMIT0x10 + +/* PLL SSC step size offsets */ +#define L0_PLL_SS_STEPS_0_LSB 0x2368 +#define L0_PLL_SS_STEPS_1_MSB 0x236c +#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370 +#define L0_PLL_SS_STEP_SIZE_1 0x2374 +#define L0_PLL_SS_STEP_SIZE_2 0x2378 +#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c +#define L0_PLL_STATUS_READ_1 0x23e4 + +/* SSC step size parameters */ +#define STEP_SIZE_0_MASK 0xff +#define STEP_SIZE_1_MASK 0xff +#define STEP_SIZE_2_MASK 0xff +#define STEP_SIZE_3_MASK 0x3 +#define STEP_SIZE_SHIFT8 +#define FORCE_STEP_SIZE0x10 +#define FORCE_STEPS0x20 +#define STEPS_0_MASK 0xff +#define STEPS_1_MASK 0x07 + +/* Reference clock selection parameters */ +#define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4) +#define
[PATCH] phy: zynqmp: Add serdes/psgtr driver
Add PSGTR driver for Xilinx ZynqMP. The most of configurations are taken from Linux kernel psgtr driver. USB3.0 and SGMII configurations are tested on SOM. In SGMII case also IOU_SLCR reg is updated to get proper clock setup and signal detection configuration. Signed-off-by: Michal Simek --- MAINTAINERS | 1 + drivers/phy/Kconfig | 7 + drivers/phy/Makefile | 1 + drivers/phy/phy-zynqmp.c | 690 +++ 4 files changed, 699 insertions(+) create mode 100644 drivers/phy/phy-zynqmp.c diff --git a/MAINTAINERS b/MAINTAINERS index 1eb71cbdad12..d1e9fbd4a279 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -611,6 +611,7 @@ F: drivers/mmc/zynq_sdhci.c F: drivers/mtd/nand/raw/zynq_nand.c F: drivers/net/phy/xilinx_phy.c F: drivers/net/zynq_gem.c +F: drivers/phy/phy-zynqmp.c F: drivers/serial/serial_zynq.c F: drivers/reset/reset-zynqmp.c F: drivers/rtc/zynqmp_rtc.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 4767d215f337..d79798429b18 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -281,6 +281,13 @@ config PHY_IMX8MQ_USB help Support the USB3.0 PHY in NXP i.MX8MQ SoC +config PHY_XILINX_ZYNQMP + tristate "Xilinx ZynqMP PHY driver" + depends on PHY && ARCH_ZYNQMP + help + Enable this to support ZynqMP High Speed Gigabit Transceiver + that is part of ZynqMP SoC. + source "drivers/phy/rockchip/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/ti/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 13a8ade8919f..bf9b40932fe3 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -38,5 +38,6 @@ obj-$(CONFIG_MT76X8_USB_PHY) += mt76x8-usb-phy.o obj-$(CONFIG_PHY_DA8XX_USB) += phy-da8xx-usb.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_IMX8MQ_USB) += phy-imx8mq-usb.o +obj-$(CONFIG_PHY_XILINX_ZYNQMP) += phy-zynqmp.o obj-y += cadence/ obj-y += ti/ diff --git a/drivers/phy/phy-zynqmp.c b/drivers/phy/phy-zynqmp.c new file mode 100644 index ..d6fe8dcef74e --- /dev/null +++ b/drivers/phy/phy-zynqmp.c @@ -0,0 +1,690 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT. + * + * Copyright (C) 2018-2021 Xilinx Inc. + * + * Author: Anurag Kumar Vulisha + * Author: Subbaraya Sundeep + * Author: Laurent Pinchart + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +/* + * Lane Registers + */ + +/* TX De-emphasis parameters */ +#define L0_TX_ANA_TM_180x0048 +#define L0_TX_ANA_TM_118 0x01d8 +#define L0_TX_ANA_TM_118_FORCE_17_0BIT(0) + +/* DN Resistor calibration code parameters */ +#define L0_TXPMA_ST_3 0x0b0c +#define L0_DN_CALIB_CODE 0x3f + +/* PMA control parameters */ +#define L0_TXPMD_TM_45 0x0cb4 +#define L0_TXPMD_TM_48 0x0cc0 +#define L0_TXPMD_TM_45_OVER_DP_MAINBIT(0) +#define L0_TXPMD_TM_45_ENABLE_DP_MAIN BIT(1) +#define L0_TXPMD_TM_45_OVER_DP_POST1 BIT(2) +#define L0_TXPMD_TM_45_ENABLE_DP_POST1 BIT(3) +#define L0_TXPMD_TM_45_OVER_DP_POST2 BIT(4) +#define L0_TXPMD_TM_45_ENABLE_DP_POST2 BIT(5) + +/* PCS control parameters */ +#define L0_TM_DIG_60x106c +#define L0_TM_DIS_DESCRAMBLE_DECODER 0x0f +#define L0_TX_DIG_61 0x00f4 +#define L0_TM_DISABLE_SCRAMBLE_ENCODER 0x0f + +/* PLL Test Mode register parameters */ +#define L0_TM_PLL_DIG_37 0x2094 +#define L0_TM_COARSE_CODE_LIMIT0x10 + +/* PLL SSC step size offsets */ +#define L0_PLL_SS_STEPS_0_LSB 0x2368 +#define L0_PLL_SS_STEPS_1_MSB 0x236c +#define L0_PLL_SS_STEP_SIZE_0_LSB 0x2370 +#define L0_PLL_SS_STEP_SIZE_1 0x2374 +#define L0_PLL_SS_STEP_SIZE_2 0x2378 +#define L0_PLL_SS_STEP_SIZE_3_MSB 0x237c +#define L0_PLL_STATUS_READ_1 0x23e4 + +/* SSC step size parameters */ +#define STEP_SIZE_0_MASK 0xff +#define STEP_SIZE_1_MASK 0xff +#define STEP_SIZE_2_MASK 0xff +#define STEP_SIZE_3_MASK 0x3 +#define STEP_SIZE_SHIFT8 +#define FORCE_STEP_SIZE0x10 +#define FORCE_STEPS0x20 +#define STEPS_0_MASK 0xff +#define STEPS_1_MASK 0x07 + +/* Reference clock selection parameters */ +#define L0_Ln_REF_CLK_SEL(n) (0x2860 + (n) * 4) +#define L0_REF_CLK_SEL_MASK0x8f + +/* Calibration digital logic parameters */ +#define L3_TM_CALIB_DIG19 0xec4c +#define L3_CALIB_DONE_STATUS 0xef14 +#define L3_TM_CALIB_DIG18 0xec48 +#define L3_TM_CALIB_DIG19_NSW 0x07 +#define L3_TM_CALIB_DIG18_NSW
