Re: [PATCH] riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy

[Leo Liang]

On Thu, Oct 12, 2023 at 01:35:34PM +0800, Randolph wrote:
> Source hart information is not necessary in IPI, so we could
> use single-bit-per-hart strategy to rearrange PLICSW mapping.
> 
> Bit 0 of Interrupt Pending Bits is hardwired to 0.
> Therefore, we use bit 1 to send IPI to hart 0,
> bit 2 to hart 1, ..., and so on.
> 
> Signed-off-by: Randolph 
> ---
>  arch/riscv/lib/andes_plicsw.c | 24 +++-
>  1 file changed, 11 insertions(+), 13 deletions(-)

Reviewed-by: Leo Yu-Chi Liang 

[PATCH] riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy

[Randolph]

Source hart information is not necessary in IPI, so we could
use single-bit-per-hart strategy to rearrange PLICSW mapping.

Bit 0 of Interrupt Pending Bits is hardwired to 0.
Therefore, we use bit 1 to send IPI to hart 0,
bit 2 to hart 1, ..., and so on.

Signed-off-by: Randolph 
---
 arch/riscv/lib/andes_plicsw.c | 24 +++-
 1 file changed, 11 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/lib/andes_plicsw.c b/arch/riscv/lib/andes_plicsw.c
index 7518408089..6fd49e873b 100644
--- a/arch/riscv/lib/andes_plicsw.c
+++ b/arch/riscv/lib/andes_plicsw.c
@@ -22,7 +22,7 @@
 #include 
 
 /* pending register */
-#define PENDING_REG(base, hart)((ulong)(base) + 0x1000 + ((hart) / 4) 
* 4)
+#define PENDING_REG(base)  ((ulong)(base) + 0x1000)
 /* enable register */
 #define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
 /* claim register */
@@ -30,10 +30,11 @@
 /* priority register */
 #define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE)
 
-#define ENABLE_HART_IPI (0x01010101)
-#define SEND_IPI_TO_HART(hart)  (0x1 << (hart))
+/* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 
*/
+#define FIRST_AVAILABLE_BIT0x2
+#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart))
 #define PLICSW_PRIORITY_BASE0x4
-#define PLICSW_INTERRUPT_PER_HART   0x8
+#define PLICSW_INTERRUPT_PER_HART   0x1
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -41,9 +42,8 @@ static int enable_ipi(int hart)
 {
unsigned int en;
 
-   en = ENABLE_HART_IPI << hart;
+   en = FIRST_AVAILABLE_BIT << hart;
writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
-   writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw + 0x4, hart));
 
return 0;
 }
@@ -75,7 +75,7 @@ int riscv_init_ipi(void)
ret = uclass_find_first_device(UCLASS_CPU, );
if (ret)
return ret;
-   else if (!dev)
+   if (!dev)
return -ENODEV;
 
ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
@@ -105,10 +105,9 @@ int riscv_init_ipi(void)
 
 int riscv_send_ipi(int hart)
 {
-   unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+   unsigned int ipi = SEND_IPI_TO_HART(hart);
 
-   writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw,
-   gd->arch.boot_hart));
+   writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw));
 
return 0;
 }
@@ -125,10 +124,9 @@ int riscv_clear_ipi(int hart)
 
 int riscv_get_ipi(int hart, int *pending)
 {
-   unsigned int ipi = (SEND_IPI_TO_HART(hart) << (8 * gd->arch.boot_hart));
+   unsigned int ipi = SEND_IPI_TO_HART(hart);
 
-   *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw,
-gd->arch.boot_hart));
+   *pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw));
*pending = !!(*pending & ipi);
 
return 0;
-- 
2.34.1