Re: [PATCH 08/14] net: dwc_eth_qos: Add Qcom ethernet driver glue layer
On Fri, Jan 20, 2023 at 9:18 AM Sumit Garg wrote:
>
> The Qualcom ETHQOS hardware supports an RGMII macro which needs to be
> configured according to following link speeds:
> - SPEED_1000
> - SPEED_100
> - SPEED_10
>
> So add a corresponding glue driver to configure RGMII macro.
>
> Signed-off-by: Sumit Garg
> ---
> drivers/net/Kconfig| 7 +
> drivers/net/Makefile | 1 +
> drivers/net/dwc_eth_qos.c | 7 +
> drivers/net/dwc_eth_qos.h | 3 +
> drivers/net/dwc_eth_qos_qcom.c | 612 +
> 5 files changed, 630 insertions(+)
> create mode 100644 drivers/net/dwc_eth_qos_qcom.c
>
> diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
> index 7873538cc2..815e1f9248 100644
> --- a/drivers/net/Kconfig
> +++ b/drivers/net/Kconfig
> @@ -242,6 +242,13 @@ config DWC_ETH_QOS_TEGRA186
> The Synopsys Designware Ethernet QOS IP block with specific
> configuration used in NVIDIA's Tegra186 chip.
>
> +config DWC_ETH_QOS_QCOM
> + bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs"
> + depends on DWC_ETH_QOS
> + help
> + The Synopsys Designware Ethernet QOS IP block with specific
> + configuration used in Qcom QCS404 SoC.
> +
> config E1000
> bool "Intel PRO/1000 Gigabit Ethernet support"
> depends on PCI
> diff --git a/drivers/net/Makefile b/drivers/net/Makefile
> index 5b4e60eea3..b009b10aca 100644
> --- a/drivers/net/Makefile
> +++ b/drivers/net/Makefile
> @@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
> obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
> obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
> obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
> +obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
> obj-$(CONFIG_E1000) += e1000.o
> obj-$(CONFIG_E1000_SPI) += e1000_spi.o
> obj-$(CONFIG_EEPRO100) += eepro100.o
> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
> index 65b8556be2..112deb546d 100644
> --- a/drivers/net/dwc_eth_qos.c
> +++ b/drivers/net/dwc_eth_qos.c
> @@ -1712,6 +1712,13 @@ static const struct udevice_id eqos_ids[] = {
> },
> #endif
>
> +#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM)
> + {
> + .compatible = "qcom,qcs404-ethqos",
> + .data = (ulong)_qcom_config
> + },
> +#endif
> +
> { }
> };
>
> diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
> index 466a792de7..fddbe9336c 100644
> --- a/drivers/net/dwc_eth_qos.h
> +++ b/drivers/net/dwc_eth_qos.h
> @@ -253,6 +253,7 @@ struct eqos_priv {
> struct eqos_mtl_regs *mtl_regs;
> struct eqos_dma_regs *dma_regs;
> struct eqos_tegra186_regs *tegra186_regs;
> + void *eqos_qcom_rgmii_regs;
> struct reset_ctl reset_ctl;
> struct gpio_desc phy_reset_gpio;
> struct clk clk_master_bus;
> @@ -277,6 +278,7 @@ struct eqos_priv {
> bool reg_access_ok;
> bool clk_ck_enabled;
> unsigned int tx_fifo_sz, rx_fifo_sz;
> + u32 reset_delays[3];
> };
>
> void eqos_inval_desc_generic(void *desc);
> @@ -286,3 +288,4 @@ void eqos_flush_buffer_generic(void *buf, size_t size);
> int eqos_null_ops(struct udevice *dev);
>
> extern struct eqos_config eqos_imx_config;
> +extern struct eqos_config eqos_qcom_config;
> diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c
> new file mode 100644
> index 00..df83f1c5f9
> --- /dev/null
> +++ b/drivers/net/dwc_eth_qos_qcom.c
> @@ -0,0 +1,612 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2022-2023 Sumit Garg
> + *
> + * Qcom DWMAC specific glue layer
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "dwc_eth_qos.h"
> +
> +/* RGMII_IO_MACRO_CONFIG fields */
> +#define RGMII_CONFIG_FUNC_CLK_EN BIT(30)
> +#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23)
> +#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20)
> +#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17)
> +#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8)
> +#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6)
> +#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4)
> +#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3)
> +#define RGMII_CONFIG_LOOPBACK_EN BIT(2)
> +#define RGMII_CONFIG_PROG_SWAP BIT(1)
> +#define RGMII_CONFIG_DDR_MODE BIT(0)
> +
> +/* SDCC_HC_REG_DLL_CONFIG fields */
> +#define SDCC_DLL_CONFIG_DLL_RSTBIT(30)
> +#define SDCC_DLL_CONFIG_PDNBIT(29)
> +#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24)
> +#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20)
> +#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19)
> +#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18)
>
[PATCH 08/14] net: dwc_eth_qos: Add Qcom ethernet driver glue layer
The Qualcom ETHQOS hardware supports an RGMII macro which needs to be
configured according to following link speeds:
- SPEED_1000
- SPEED_100
- SPEED_10
So add a corresponding glue driver to configure RGMII macro.
Signed-off-by: Sumit Garg
---
drivers/net/Kconfig| 7 +
drivers/net/Makefile | 1 +
drivers/net/dwc_eth_qos.c | 7 +
drivers/net/dwc_eth_qos.h | 3 +
drivers/net/dwc_eth_qos_qcom.c | 612 +
5 files changed, 630 insertions(+)
create mode 100644 drivers/net/dwc_eth_qos_qcom.c
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 7873538cc2..815e1f9248 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -242,6 +242,13 @@ config DWC_ETH_QOS_TEGRA186
The Synopsys Designware Ethernet QOS IP block with specific
configuration used in NVIDIA's Tegra186 chip.
+config DWC_ETH_QOS_QCOM
+ bool "Synopsys DWC Ethernet QOS device support for Qcom SoCs"
+ depends on DWC_ETH_QOS
+ help
+ The Synopsys Designware Ethernet QOS IP block with specific
+ configuration used in Qcom QCS404 SoC.
+
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on PCI
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 5b4e60eea3..b009b10aca 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -20,6 +20,7 @@ obj-$(CONFIG_DRIVER_DM9000) += dm9000x.o
obj-$(CONFIG_DSA_SANDBOX) += dsa_sandbox.o
obj-$(CONFIG_DWC_ETH_QOS) += dwc_eth_qos.o
obj-$(CONFIG_DWC_ETH_QOS_IMX) += dwc_eth_qos_imx.o
+obj-$(CONFIG_DWC_ETH_QOS_QCOM) += dwc_eth_qos_qcom.o
obj-$(CONFIG_E1000) += e1000.o
obj-$(CONFIG_E1000_SPI) += e1000_spi.o
obj-$(CONFIG_EEPRO100) += eepro100.o
diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 65b8556be2..112deb546d 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -1712,6 +1712,13 @@ static const struct udevice_id eqos_ids[] = {
},
#endif
+#if IS_ENABLED(CONFIG_DWC_ETH_QOS_QCOM)
+ {
+ .compatible = "qcom,qcs404-ethqos",
+ .data = (ulong)_qcom_config
+ },
+#endif
+
{ }
};
diff --git a/drivers/net/dwc_eth_qos.h b/drivers/net/dwc_eth_qos.h
index 466a792de7..fddbe9336c 100644
--- a/drivers/net/dwc_eth_qos.h
+++ b/drivers/net/dwc_eth_qos.h
@@ -253,6 +253,7 @@ struct eqos_priv {
struct eqos_mtl_regs *mtl_regs;
struct eqos_dma_regs *dma_regs;
struct eqos_tegra186_regs *tegra186_regs;
+ void *eqos_qcom_rgmii_regs;
struct reset_ctl reset_ctl;
struct gpio_desc phy_reset_gpio;
struct clk clk_master_bus;
@@ -277,6 +278,7 @@ struct eqos_priv {
bool reg_access_ok;
bool clk_ck_enabled;
unsigned int tx_fifo_sz, rx_fifo_sz;
+ u32 reset_delays[3];
};
void eqos_inval_desc_generic(void *desc);
@@ -286,3 +288,4 @@ void eqos_flush_buffer_generic(void *buf, size_t size);
int eqos_null_ops(struct udevice *dev);
extern struct eqos_config eqos_imx_config;
+extern struct eqos_config eqos_qcom_config;
diff --git a/drivers/net/dwc_eth_qos_qcom.c b/drivers/net/dwc_eth_qos_qcom.c
new file mode 100644
index 00..df83f1c5f9
--- /dev/null
+++ b/drivers/net/dwc_eth_qos_qcom.c
@@ -0,0 +1,612 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2022-2023 Sumit Garg
+ *
+ * Qcom DWMAC specific glue layer
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "dwc_eth_qos.h"
+
+/* RGMII_IO_MACRO_CONFIG fields */
+#define RGMII_CONFIG_FUNC_CLK_EN BIT(30)
+#define RGMII_CONFIG_POS_NEG_DATA_SEL BIT(23)
+#define RGMII_CONFIG_GPIO_CFG_RX_INT GENMASK(21, 20)
+#define RGMII_CONFIG_GPIO_CFG_TX_INT GENMASK(19, 17)
+#define RGMII_CONFIG_MAX_SPD_PRG_9 GENMASK(16, 8)
+#define RGMII_CONFIG_MAX_SPD_PRG_2 GENMASK(7, 6)
+#define RGMII_CONFIG_INTF_SEL GENMASK(5, 4)
+#define RGMII_CONFIG_BYPASS_TX_ID_EN BIT(3)
+#define RGMII_CONFIG_LOOPBACK_EN BIT(2)
+#define RGMII_CONFIG_PROG_SWAP BIT(1)
+#define RGMII_CONFIG_DDR_MODE BIT(0)
+
+/* SDCC_HC_REG_DLL_CONFIG fields */
+#define SDCC_DLL_CONFIG_DLL_RSTBIT(30)
+#define SDCC_DLL_CONFIG_PDNBIT(29)
+#define SDCC_DLL_CONFIG_MCLK_FREQ GENMASK(26, 24)
+#define SDCC_DLL_CONFIG_CDR_SELEXT GENMASK(23, 20)
+#define SDCC_DLL_CONFIG_CDR_EXT_EN BIT(19)
+#define SDCC_DLL_CONFIG_CK_OUT_EN BIT(18)
+#define SDCC_DLL_CONFIG_CDR_EN BIT(17)
+#define SDCC_DLL_CONFIG_DLL_EN BIT(16)
+#define SDCC_DLL_MCLK_GATING_ENBIT(5)
+#define SDCC_DLL_CDR_FINE_PHASEGENMASK(3, 2)
+
+/* SDCC_HC_REG_DDR_CONFIG fields */
+#define SDCC_DDR_CONFIG_PRG_DLY_EN
