Re: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372
On Tue, Nov 30, 2021 at 01:06:56AM +0100, Stefan Mätje wrote: > On AM4372 the SPI_GCLK input gets its clock from the PRCM module which > divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4. > See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration. > > The QSPI_FCLK therefore needs to take this factor into account and > becomes (19200 / 4). > > Signed-off-by: Stefan Mätje Applied to u-boot/master, thanks! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372
Am Montag, den 29.11.2021, 22:58 -0500 schrieb Tom Rini: > On Tue, Nov 30, 2021 at 01:06:56AM +0100, Stefan Mätje wrote: > > > On AM4372 the SPI_GCLK input gets its clock from the PRCM module which > > divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4. > > See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration. > > > > The QSPI_FCLK therefore needs to take this factor into account and > > becomes (19200 / 4). > > > > Signed-off-by: Stefan Mätje > > --- > > drivers/spi/ti_qspi.c | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c > > index 664b9cad79..bccdeeaf82 100644 > > --- a/drivers/spi/ti_qspi.c > > +++ b/drivers/spi/ti_qspi.c > > @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; > > > > /* ti qpsi register bit masks */ > > #define QSPI_TIMEOUT200 > > -#define QSPI_FCLK 19200 > > +/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. > > */ > > +#define QSPI_FCLK (19200 / 4) > > #define QSPI_DRA7XX_FCLK7680 > > #define QSPI_WLEN_MAX_BITS 128 > > #define QSPI_WLEN_MAX_BYTES(QSPI_WLEN_MAX_BITS >> 3) > > How is this treated in the kernel? Thanks. > The current driver in mainline Linux @drivers/spi/spi-ti-qspi.c still has the wrong QSPI_FCLK define, but it seems to be used nowhere any more. The driver gets its "fclk" from the device tree. But the device tree (arch/arm/boot/dts/am4372.dtsi) was broken till this patch on the mainline kernel: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm/boot/dts/am4372.dtsi?id=f60c41257fa06d496c9653d3f77d34b7426d9274 It seems to me that there the first time a valid "fclk" property was provided to the qspi module. Best regards, Stefan Mätje
[PATCH 1/1] Fix wrong QSPI clock calculation for AM4372
On AM4372 the SPI_GCLK input gets its clock from the PRCM module which divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4. See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration. The QSPI_FCLK therefore needs to take this factor into account and becomes (19200 / 4). Signed-off-by: Stefan Mätje --- drivers/spi/ti_qspi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index 664b9cad79..bccdeeaf82 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; /* ti qpsi register bit masks */ #define QSPI_TIMEOUT200 -#define QSPI_FCLK 19200 +/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. */ +#define QSPI_FCLK (19200 / 4) #define QSPI_DRA7XX_FCLK7680 #define QSPI_WLEN_MAX_BITS 128 #define QSPI_WLEN_MAX_BYTES(QSPI_WLEN_MAX_BITS >> 3) -- 2.25.1
Re: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372
On Tue, Nov 30, 2021 at 12:14:12PM +, Stefan Mätje wrote: > Am Montag, den 29.11.2021, 22:58 -0500 schrieb Tom Rini: > > On Tue, Nov 30, 2021 at 01:06:56AM +0100, Stefan Mätje wrote: > > > > > On AM4372 the SPI_GCLK input gets its clock from the PRCM module which > > > divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4. > > > See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration. > > > > > > The QSPI_FCLK therefore needs to take this factor into account and > > > becomes (19200 / 4). > > > > > > Signed-off-by: Stefan Mätje > > > --- > > > drivers/spi/ti_qspi.c | 3 ++- > > > 1 file changed, 2 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c > > > index 664b9cad79..bccdeeaf82 100644 > > > --- a/drivers/spi/ti_qspi.c > > > +++ b/drivers/spi/ti_qspi.c > > > @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; > > > > > > /* ti qpsi register bit masks */ > > > #define QSPI_TIMEOUT200 > > > -#define QSPI_FCLK19200 > > > +/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by > > > 4. > > > */ > > > +#define QSPI_FCLK (19200 / 4) > > > #define QSPI_DRA7XX_FCLK7680 > > > #define QSPI_WLEN_MAX_BITS 128 > > > #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3) > > > > How is this treated in the kernel? Thanks. > > > The current driver in mainline Linux @drivers/spi/spi-ti-qspi.c still has > the wrong QSPI_FCLK define, but it seems to be used nowhere any more. > > The driver gets its "fclk" from the device tree. But the device tree > (arch/arm/boot/dts/am4372.dtsi) was broken till this patch on the > mainline kernel: > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/arch/arm/boot/dts/am4372.dtsi?id=f60c41257fa06d496c9653d3f77d34b7426d9274 > > It seems to me that there the first time a valid "fclk" property > was provided to the qspi module. OK, thanks for checking! -- Tom signature.asc Description: PGP signature
Re: [PATCH 1/1] Fix wrong QSPI clock calculation for AM4372
On Tue, Nov 30, 2021 at 01:06:56AM +0100, Stefan Mätje wrote: > On AM4372 the SPI_GCLK input gets its clock from the PRCM module which > divides the PER_CLKOUTM2 frequency (192MHz) by a fixed factor of 4. > See AM437x Reference Manual in section 27 QSPI >> 27.2 Integration. > > The QSPI_FCLK therefore needs to take this factor into account and > becomes (19200 / 4). > > Signed-off-by: Stefan Mätje > --- > drivers/spi/ti_qspi.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c > index 664b9cad79..bccdeeaf82 100644 > --- a/drivers/spi/ti_qspi.c > +++ b/drivers/spi/ti_qspi.c > @@ -25,7 +25,8 @@ DECLARE_GLOBAL_DATA_PTR; > > /* ti qpsi register bit masks */ > #define QSPI_TIMEOUT200 > -#define QSPI_FCLK19200 > +/* AM4372: QSPI gets SPI_GCLK from PRCM unit as PER_CLKOUTM2 divided by 4. */ > +#define QSPI_FCLK (19200 / 4) > #define QSPI_DRA7XX_FCLK7680 > #define QSPI_WLEN_MAX_BITS 128 > #define QSPI_WLEN_MAX_BYTES (QSPI_WLEN_MAX_BITS >> 3) How is this treated in the kernel? Thanks. -- Tom signature.asc Description: PGP signature
