subject:"\[PATCH 1\/3\] phy\: marvell\: cp110\: let the firmware configure the comphy"

Re: [PATCH 1/3] phy: marvell: cp110: let the firmware configure the comphy

2020-10-20 Thread Stefan Roese


On 18.10.20 21:43, Marek Behun wrote:

On Sun, 18 Oct 2020 17:11:11 +0300
Baruch Siach  wrote:


From: Grzegorz Jaszczyk 

Replace all comphy initialization with appropriate smc calls. It will
result with triggering synchronous exception that is handled by Secure
Monitor code in EL3. Then the Secure Monitor code will dispatch each smc
call (by parsing the smc function identifier) and triggers appropriate
comphy initialization.

This patch reworks serdes handling for: SATA, SGMII, HS-SGMII and SFI
interfaces.

Signed-off-by: Grzegorz Jaszczyk 
Reviewed-by: Igal Liberman 
Signed-off-by: Baruch Siach 
---
  drivers/phy/marvell/comphy_cp110.c | 816 -
  1 file changed, 89 insertions(+), 727 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c 
b/drivers/phy/marvell/comphy_cp110.c
index 15e80049def6..31baa0bb3700 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -7,6 +7,7 @@
  #include 
  #include 
  #include 
+#include 
  #include 
  #include 
  #include 
@@ -22,6 +23,32 @@ DECLARE_GLOBAL_DATA_PTR;
  #define HPIPE_ADDR(base, lane)(SD_ADDR(base, lane) + 
0x800)
  #define COMPHY_ADDR(base, lane)   (base + 0x28 * lane)
  
+/* Firmware related definitions used for SMC calls */

+#define MV_SIP_COMPHY_POWER_ON 0x8201
+#define MV_SIP_COMPHY_POWER_OFF0x8202
+#define MV_SIP_COMPHY_PLL_LOCK 0x8203
+
+#define COMPHY_FW_MODE_FORMAT(mode)((mode) << 12)
+#define COMPHY_FW_FORMAT(mode, idx, speeds)\
+   (((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
+#define COMPHY_SATA_MODE   0x1
+#define COMPHY_SGMII_MODE  0x2 /* SGMII 1G */
+#define COMPHY_HS_SGMII_MODE   0x3 /* SGMII 2.5G */
+#define COMPHY_USB3H_MODE  0x4
+#define COMPHY_USB3D_MODE  0x5
+#define COMPHY_PCIE_MODE   0x6
+#define COMPHY_RXAUI_MODE  0x7
+#define COMPHY_XFI_MODE0x8
+#define COMPHY_SFI_MODE0x9
+#define COMPHY_USB3_MODE   0xa
+#define COMPHY_AP_MODE 0xb


These same constants can be used for Armada 3720, btw... And maybe even
the code itself. So if this works, after it is applied I will try to
make this driver support Armada 3720 as well.


Good.


BTW, my opinion on using firmware calls in kernel for this changed
recently, when encountering problems on EspressoBIN which were result
of many people simply not upgrading the firmware... I now think kernel
should not depend on the firmware for this and implement this on its
own... But I think U-Boot is ok.


I'm okay with these patches in general as well, but I would like to see
some users testing them on their Armada 7k/8k boards. Marek?

Thanks,
Stefan

Re: [PATCH 1/3] phy: marvell: cp110: let the firmware configure the comphy

2020-10-18 Thread Marek Behun

On Sun, 18 Oct 2020 17:11:11 +0300
Baruch Siach  wrote:

> From: Grzegorz Jaszczyk 
> 
> Replace all comphy initialization with appropriate smc calls. It will
> result with triggering synchronous exception that is handled by Secure
> Monitor code in EL3. Then the Secure Monitor code will dispatch each smc
> call (by parsing the smc function identifier) and triggers appropriate
> comphy initialization.
> 
> This patch reworks serdes handling for: SATA, SGMII, HS-SGMII and SFI
> interfaces.
> 
> Signed-off-by: Grzegorz Jaszczyk 
> Reviewed-by: Igal Liberman 
> Signed-off-by: Baruch Siach 
> ---
>  drivers/phy/marvell/comphy_cp110.c | 816 -
>  1 file changed, 89 insertions(+), 727 deletions(-)
> 
> diff --git a/drivers/phy/marvell/comphy_cp110.c 
> b/drivers/phy/marvell/comphy_cp110.c
> index 15e80049def6..31baa0bb3700 100644
> --- a/drivers/phy/marvell/comphy_cp110.c
> +++ b/drivers/phy/marvell/comphy_cp110.c
> @@ -7,6 +7,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  #include 
>  #include 
>  #include 
> @@ -22,6 +23,32 @@ DECLARE_GLOBAL_DATA_PTR;
>  #define HPIPE_ADDR(base, lane)   (SD_ADDR(base, lane) + 
> 0x800)
>  #define COMPHY_ADDR(base, lane)  (base + 0x28 * lane)
>  
> +/* Firmware related definitions used for SMC calls */
> +#define MV_SIP_COMPHY_POWER_ON   0x8201
> +#define MV_SIP_COMPHY_POWER_OFF  0x8202
> +#define MV_SIP_COMPHY_PLL_LOCK   0x8203
> +
> +#define COMPHY_FW_MODE_FORMAT(mode)  ((mode) << 12)
> +#define COMPHY_FW_FORMAT(mode, idx, speeds)  \
> + (((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
> +#define COMPHY_SATA_MODE 0x1
> +#define COMPHY_SGMII_MODE0x2 /* SGMII 1G */
> +#define COMPHY_HS_SGMII_MODE 0x3 /* SGMII 2.5G */
> +#define COMPHY_USB3H_MODE0x4
> +#define COMPHY_USB3D_MODE0x5
> +#define COMPHY_PCIE_MODE 0x6
> +#define COMPHY_RXAUI_MODE0x7
> +#define COMPHY_XFI_MODE  0x8
> +#define COMPHY_SFI_MODE  0x9
> +#define COMPHY_USB3_MODE 0xa
> +#define COMPHY_AP_MODE   0xb

These same constants can be used for Armada 3720, btw... And maybe even
the code itself. So if this works, after it is applied I will try to
make this driver support Armada 3720 as well.

BTW, my opinion on using firmware calls in kernel for this changed
recently, when encountering problems on EspressoBIN which were result
of many people simply not upgrading the firmware... I now think kernel
should not depend on the firmware for this and implement this on its
own... But I think U-Boot is ok.

Marek

[PATCH 1/3] phy: marvell: cp110: let the firmware configure the comphy

2020-10-18 Thread Baruch Siach

From: Grzegorz Jaszczyk 

Replace all comphy initialization with appropriate smc calls. It will
result with triggering synchronous exception that is handled by Secure
Monitor code in EL3. Then the Secure Monitor code will dispatch each smc
call (by parsing the smc function identifier) and triggers appropriate
comphy initialization.

This patch reworks serdes handling for: SATA, SGMII, HS-SGMII and SFI
interfaces.

Signed-off-by: Grzegorz Jaszczyk 
Reviewed-by: Igal Liberman 
Signed-off-by: Baruch Siach 
---
 drivers/phy/marvell/comphy_cp110.c | 816 -
 1 file changed, 89 insertions(+), 727 deletions(-)

diff --git a/drivers/phy/marvell/comphy_cp110.c 
b/drivers/phy/marvell/comphy_cp110.c
index 15e80049def6..31baa0bb3700 100644
--- a/drivers/phy/marvell/comphy_cp110.c
+++ b/drivers/phy/marvell/comphy_cp110.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -22,6 +23,32 @@ DECLARE_GLOBAL_DATA_PTR;
 #define HPIPE_ADDR(base, lane) (SD_ADDR(base, lane) + 0x800)
 #define COMPHY_ADDR(base, lane)(base + 0x28 * lane)
 
+/* Firmware related definitions used for SMC calls */
+#define MV_SIP_COMPHY_POWER_ON 0x8201
+#define MV_SIP_COMPHY_POWER_OFF0x8202
+#define MV_SIP_COMPHY_PLL_LOCK 0x8203
+
+#define COMPHY_FW_MODE_FORMAT(mode)((mode) << 12)
+#define COMPHY_FW_FORMAT(mode, idx, speeds)\
+   (((mode) << 12) | ((idx) << 8) | ((speeds) << 2))
+#define COMPHY_SATA_MODE   0x1
+#define COMPHY_SGMII_MODE  0x2 /* SGMII 1G */
+#define COMPHY_HS_SGMII_MODE   0x3 /* SGMII 2.5G */
+#define COMPHY_USB3H_MODE  0x4
+#define COMPHY_USB3D_MODE  0x5
+#define COMPHY_PCIE_MODE   0x6
+#define COMPHY_RXAUI_MODE  0x7
+#define COMPHY_XFI_MODE0x8
+#define COMPHY_SFI_MODE0x9
+#define COMPHY_USB3_MODE   0xa
+#define COMPHY_AP_MODE 0xb
+
+/* Comphy unit index macro */
+#define COMPHY_UNIT_ID00
+#define COMPHY_UNIT_ID11
+#define COMPHY_UNIT_ID22
+#define COMPHY_UNIT_ID33
+
 struct utmi_phy_data {
void __iomem *utmi_base_addr;
void __iomem *usb_cfg_addr;
@@ -642,15 +669,31 @@ static int comphy_usb3_power_up(u32 lane, void __iomem 
*hpipe_base,
return ret;
 }
 
+static int comphy_smc(u32 function_id, void __iomem *comphy_base_addr,
+ u32 lane, u32 mode)
+{
+   struct pt_regs pregs = {0};
+
+   pregs.regs[0] = function_id;
+   pregs.regs[1] = (unsigned long)comphy_base_addr;
+   pregs.regs[2] = lane;
+   pregs.regs[3] = mode;
+
+   smc_call(&pregs);
+
+   /*
+* TODO: Firmware return 0 on success, temporary map it to u-boot
+* convention, but after all comphy will be reworked the convention in
+* u-boot should be change and this conversion removed
+*/
+   return pregs.regs[0] ? 0 : 1;
+}
+
 static int comphy_sata_power_up(u32 lane, void __iomem *hpipe_base,
-   void __iomem *comphy_base, int cp_index,
-   u32 invert)
+   void __iomem *comphy_base_addr, int cp_index,
+   u32 type)
 {
u32 mask, data, i, ret = 1;
-   void __iomem *hpipe_addr = HPIPE_ADDR(hpipe_base, lane);
-   void __iomem *sd_ip_addr = SD_ADDR(hpipe_base, lane);
-   void __iomem *comphy_addr = COMPHY_ADDR(comphy_base, lane);
-   void __iomem *addr;
void __iomem *sata_base = NULL;
int sata_node = -1; /* Set to -1 in order to read the first sata node */
 
@@ -703,255 +746,8 @@ static int comphy_sata_power_up(u32 lane, void __iomem 
*hpipe_base,
data |= 0x0 << SATA3_CTRL_SATA_SSU_OFFSET;
reg_set(sata_base + SATA3_VENDOR_DATA, data, mask);
 
-   debug("stage: RFU configurations - hard reset comphy\n");
-   /* RFU configurations - hard reset comphy */
-   mask = COMMON_PHY_CFG1_PWR_UP_MASK;
-   data = 0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET;
-   mask |= COMMON_PHY_CFG1_PIPE_SELECT_MASK;
-   data |= 0x0 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET;
-   mask |= COMMON_PHY_CFG1_PWR_ON_RESET_MASK;
-   data |= 0x0 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET;
-   mask |= COMMON_PHY_CFG1_CORE_RSTN_MASK;
-   data |= 0x0 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET;
-   reg_set(comphy_addr + COMMON_PHY_CFG1_REG, data, mask);
-
-   /* Set select data  width 40Bit - SATA mode only */
-   reg_set(comphy_addr + COMMON_PHY_CFG6_REG,
-   0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET,
-   COMMON_PHY_CFG6_IF_40_SEL_MASK);
-
-   /* release from hard reset in SD external */
-   mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK;
-   data = 0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET;
-   mask |= SD_EXTERNAL_CONFIG1_RESET_CORE_MASK;
-   data |= 0x1 << SD_EXTERNAL_CONFIG1_RESET_COR

Re: [PATCH 1/3] phy: marvell: cp110: let the firmware configure the comphy

Re: [PATCH 1/3] phy: marvell: cp110: let the firmware configure the comphy

[PATCH 1/3] phy: marvell: cp110: let the firmware configure the comphy

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