Re: [PATCH 1/4] phy: rockchip: add usbdp combo phy driver
On 2023/5/29 18:01, Eugen Hristev wrote:
From: Frank Wang
This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.
Signed-off-by: Frank Wang
[eugen.hris...@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev
Reviewed-by: Kever Yang
Thanks,
- Kever
---
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile | 1 +
drivers/phy/rockchip/phy-rockchip-usbdp.c | 880 ++
include/linux/usb/phy-rockchip-usbdp.h| 70 ++
4 files changed, 958 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
create mode 100644 include/linux/usb/phy-rockchip-usbdp.h
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index f87ca8c31060..0247d93ab401 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -41,6 +41,13 @@ config PHY_ROCKCHIP_SNPS_PCIE3
It could support PCIe Gen3 single root complex, and could
also be able splited into multiple combinations of lanes.
+config PHY_ROCKCHIP_USBDP
+ tristate "Rockchip USBDP COMBO PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Enable this to support the Rockchip USB3.0/DP
+ combo PHY with Samsung IP block.
config PHY_ROCKCHIP_TYPEC
bool "Rockchip TYPEC PHY Driver"
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 25a803a8a86f..7fdbd107976d 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY) += phy-rockchip-inno-dsidphy.o
+obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c
b/drivers/phy/rockchip/phy-rockchip-usbdp.c
new file mode 100644
index ..baf92529348c
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Rockchip USBDP Combo PHY with Samsung IP block driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define BIT_WRITEABLE_SHIFT16
+
+enum {
+ UDPHY_MODE_NONE = 0,
+ UDPHY_MODE_USB = BIT(0),
+ UDPHY_MODE_DP = BIT(1),
+ UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
+};
+
+struct udphy_grf_reg {
+ unsigned intoffset;
+ unsigned intbitend;
+ unsigned intbitstart;
+ unsigned intdisable;
+ unsigned intenable;
+};
+
+/**
+ * struct reg_sequence - An individual write from a sequence of writes.
+ *
+ * @reg: Register address.
+ * @def: Register value.
+ * @delay_us: Delay to be applied after the register write in microseconds
+ *
+ * Register/value pairs for sequences of writes with an optional delay in
+ * microseconds to be applied after each write.
+ */
+struct reg_sequence {
+ unsigned int reg;
+ unsigned int def;
+ unsigned int delay_us;
+};
+
+struct udphy_grf_cfg {
+ /* u2phy-grf */
+ struct udphy_grf_regbvalid_phy_con;
+ struct udphy_grf_regbvalid_grf_con;
+
+ /* usb-grf */
+ struct udphy_grf_regusb3otg0_cfg;
+ struct udphy_grf_regusb3otg1_cfg;
+
+ /* usbdpphy-grf */
+ struct udphy_grf_reglow_pwrn;
+ struct udphy_grf_regrx_lfps;
+};
+
+struct rockchip_udphy;
+
+struct rockchip_udphy_cfg {
+ /* resets to be requested */
+ const char * const *rst_list;
+ int num_rsts;
+
+ struct udphy_grf_cfg grfcfg;
+ int (*combophy_init)(struct rockchip_udphy *udphy);
+};
+
+struct rockchip_udphy {
+ struct udevice *dev;
+ struct regmap *pma_regmap;
+ struct regmap *u2phygrf;
+ struct regmap *udphygrf;
+ struct regmap *usbgrf;
+ struct regmap *vogrf;
+
+ /* clocks and rests */
+ struct reset_ctl *rsts;
+
+ /* PHY status management */
+ bool flip;
+ bool mode_change;
+ u8 mode;
+ u8 status;
+
+ /* utilized for USB */
+ bool hs; /* flag for high-speed */
+
+ /* utilized for DP */
+ struct gpio_desc *sbu1_dc_gpio;
+ struct gpio_desc *sbu2_dc_gpio;
+ u32 lane_mux_sel[4];
+ u32 dp_lane_sel[4];
+ u32 dp_aux_dout_sel;
+ u32 dp_aux_din_sel;
+ int id;
+
+ /* PHY const config */
+ const struct rockchip_udphy_cfg *cfgs;
+};
+
+static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
+ {0x0090, 0x68}, {0x0094, 0x68},
+
[PATCH 1/4] phy: rockchip: add usbdp combo phy driver
From: Frank Wang
This adds a new USBDP combo PHY with Samsung IP block driver.
The PHY is a combo between USB 3.0 and DisplayPort alt mode.
Signed-off-by: Frank Wang
[eugen.hris...@collabora.com: ported to 2023.07, clean-up]
Signed-off-by: Eugen Hristev
---
drivers/phy/rockchip/Kconfig | 7 +
drivers/phy/rockchip/Makefile | 1 +
drivers/phy/rockchip/phy-rockchip-usbdp.c | 880 ++
include/linux/usb/phy-rockchip-usbdp.h| 70 ++
4 files changed, 958 insertions(+)
create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
create mode 100644 include/linux/usb/phy-rockchip-usbdp.h
diff --git a/drivers/phy/rockchip/Kconfig b/drivers/phy/rockchip/Kconfig
index f87ca8c31060..0247d93ab401 100644
--- a/drivers/phy/rockchip/Kconfig
+++ b/drivers/phy/rockchip/Kconfig
@@ -41,6 +41,13 @@ config PHY_ROCKCHIP_SNPS_PCIE3
It could support PCIe Gen3 single root complex, and could
also be able splited into multiple combinations of lanes.
+config PHY_ROCKCHIP_USBDP
+ tristate "Rockchip USBDP COMBO PHY Driver"
+ depends on ARCH_ROCKCHIP
+ select PHY
+ help
+ Enable this to support the Rockchip USB3.0/DP
+ combo PHY with Samsung IP block.
config PHY_ROCKCHIP_TYPEC
bool "Rockchip TYPEC PHY Driver"
diff --git a/drivers/phy/rockchip/Makefile b/drivers/phy/rockchip/Makefile
index 25a803a8a86f..7fdbd107976d 100644
--- a/drivers/phy/rockchip/Makefile
+++ b/drivers/phy/rockchip/Makefile
@@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE) += phy-rockchip-pcie.o
obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3) += phy-rockchip-snps-pcie3.o
obj-$(CONFIG_PHY_ROCKCHIP_TYPEC) += phy-rockchip-typec.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY)+= phy-rockchip-inno-dsidphy.o
+obj-$(CONFIG_PHY_ROCKCHIP_USBDP) += phy-rockchip-usbdp.o
diff --git a/drivers/phy/rockchip/phy-rockchip-usbdp.c
b/drivers/phy/rockchip/phy-rockchip-usbdp.c
new file mode 100644
index ..baf92529348c
--- /dev/null
+++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
@@ -0,0 +1,880 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Rockchip USBDP Combo PHY with Samsung IP block driver
+ *
+ * Copyright (C) 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#define BIT_WRITEABLE_SHIFT16
+
+enum {
+ UDPHY_MODE_NONE = 0,
+ UDPHY_MODE_USB = BIT(0),
+ UDPHY_MODE_DP = BIT(1),
+ UDPHY_MODE_DP_USB = BIT(1) | BIT(0),
+};
+
+struct udphy_grf_reg {
+ unsigned intoffset;
+ unsigned intbitend;
+ unsigned intbitstart;
+ unsigned intdisable;
+ unsigned intenable;
+};
+
+/**
+ * struct reg_sequence - An individual write from a sequence of writes.
+ *
+ * @reg: Register address.
+ * @def: Register value.
+ * @delay_us: Delay to be applied after the register write in microseconds
+ *
+ * Register/value pairs for sequences of writes with an optional delay in
+ * microseconds to be applied after each write.
+ */
+struct reg_sequence {
+ unsigned int reg;
+ unsigned int def;
+ unsigned int delay_us;
+};
+
+struct udphy_grf_cfg {
+ /* u2phy-grf */
+ struct udphy_grf_regbvalid_phy_con;
+ struct udphy_grf_regbvalid_grf_con;
+
+ /* usb-grf */
+ struct udphy_grf_regusb3otg0_cfg;
+ struct udphy_grf_regusb3otg1_cfg;
+
+ /* usbdpphy-grf */
+ struct udphy_grf_reglow_pwrn;
+ struct udphy_grf_regrx_lfps;
+};
+
+struct rockchip_udphy;
+
+struct rockchip_udphy_cfg {
+ /* resets to be requested */
+ const char * const *rst_list;
+ int num_rsts;
+
+ struct udphy_grf_cfg grfcfg;
+ int (*combophy_init)(struct rockchip_udphy *udphy);
+};
+
+struct rockchip_udphy {
+ struct udevice *dev;
+ struct regmap *pma_regmap;
+ struct regmap *u2phygrf;
+ struct regmap *udphygrf;
+ struct regmap *usbgrf;
+ struct regmap *vogrf;
+
+ /* clocks and rests */
+ struct reset_ctl *rsts;
+
+ /* PHY status management */
+ bool flip;
+ bool mode_change;
+ u8 mode;
+ u8 status;
+
+ /* utilized for USB */
+ bool hs; /* flag for high-speed */
+
+ /* utilized for DP */
+ struct gpio_desc *sbu1_dc_gpio;
+ struct gpio_desc *sbu2_dc_gpio;
+ u32 lane_mux_sel[4];
+ u32 dp_lane_sel[4];
+ u32 dp_aux_dout_sel;
+ u32 dp_aux_din_sel;
+ int id;
+
+ /* PHY const config */
+ const struct rockchip_udphy_cfg *cfgs;
+};
+
+static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
+ {0x0090, 0x68}, {0x0094, 0x68},
+ {0x0128, 0x24}, {0x012c, 0x44},
+ {0x0130, 0x3f}, {0x0134, 0x44},
+ {0x015c, 0xa9}, {0x0160,
