From: Tien Fong Chee
This patch triggers warm reset to recover the MPFE NoC from corruption
due to high frequency transient clock output from HPS EMIF IOPLL at
VCO startup after peripheral RBF is programmed.
Signed-off-by: Tien Fong Chee
Signed-off-by: Sin Hui Kho
---
arch/arm/mach-socfpga/include/mach/misc.h | 5 +-
.../include/mach/reset_manager_arria10.h | 6 +-
.../include/mach/system_manager_arria10.h | 4 +
arch/arm/mach-socfpga/misc_arria10.c | 90 -
arch/arm/mach-socfpga/spl_a10.c | 96 ++-
5 files changed, 195 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-socfpga/include/mach/misc.h
b/arch/arm/mach-socfpga/include/mach/misc.h
index 649d2f6ce2..74e8e2590f 100644
--- a/arch/arm/mach-socfpga/include/mach/misc.h
+++ b/arch/arm/mach-socfpga/include/mach/misc.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
#ifndef _SOCFPGA_MISC_H_
@@ -45,7 +45,10 @@ int is_fpga_config_ready(void);
#endif
void do_bridge_reset(int enable, unsigned int mask);
+bool is_regular_boot_valid(void);
+void set_regular_boot(unsigned int status);
void socfpga_pl310_clear(void);
void socfpga_get_managers_addr(void);
+int qspi_flash_software_reset(void);
#endif /* _SOCFPGA_MISC_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
index 19507c292d..26faa628a0 100644
--- a/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
#ifndef _RESET_MANAGER_ARRIA10_H_
@@ -22,6 +22,7 @@ int socfpga_bridges_reset(void);
#define RSTMGR_A10_PER1MODRST 0x28
#define RSTMGR_A10_BRGMODRST 0x2c
#define RSTMGR_A10_SYSMODRST 0x30
+#define RSTMGR_A10_SYSWARMMASK 0x50
#define RSTMGR_CTRLRSTMGR_A10_CTRL
@@ -115,4 +116,7 @@ int socfpga_bridges_reset(void);
#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
+#define ALT_RSTMGR_FPGAMGRWARMMASK_S2F_SET_MSK BIT(3)
+#define ALT_RSTMGR_SYSWARMMASK_S2F_SET_MSK BIT(4)
+
#endif /* _RESET_MANAGER_ARRIA10_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
index 75e1fcd80f..0afe63e647 100644
--- a/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/system_manager_arria10.h
@@ -31,7 +31,11 @@
#define SYSMGR_A10_NOC_IDLEACK 0xd0
#define SYSMGR_A10_NOC_IDLESTATUS 0xd4
#define SYSMGR_A10_FPGA2SOC_CTRL 0xd8
+#define SYSMGR_A10_ROMCODE_CTRL0x204
#define SYSMGR_A10_ROMCODE_INITSWSTATE 0x20C
+#define SYSMGR_A10_ROMCODE_QSPIRESETCOMMAND0x208
+#define SYSMGR_A10_ISW_HANDOFF_BASE0x230
+#define SYSMGR_A10_ISW_HANDOFF_7 0x1c
#define SYSMGR_SDMMC SYSMGR_A10_SDMMC
diff --git a/arch/arm/mach-socfpga/misc_arria10.c
b/arch/arm/mach-socfpga/misc_arria10.c
index bf978053ca..634e63ed42 100644
--- a/arch/arm/mach-socfpga/misc_arria10.c
+++ b/arch/arm/mach-socfpga/misc_arria10.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2017 Intel Corporation
+ * Copyright (C) 2016-2021 Intel Corporation
*/
#include
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -21,6 +22,7 @@
#include
#include
#include
+#include
#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q1_3 0x08
#define PINMUX_UART0_TX_SHARED_IO_OFFSET_Q2_11 0x58
@@ -29,6 +31,12 @@
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q3_7 0x78
#define PINMUX_UART1_TX_SHARED_IO_OFFSET_Q4_3 0x98
+#define REGULAR_BOOT_MAGIC 0xd15ea5e
+
+#define QSPI_S25FL_SOFT_RESET_COMMAND 0x00f0ff82
+#define QSPI_N25_SOFT_RESET_COMMAND0x0001
+#define QSPI_NO_SOFT_RESET 0x
+
/*
* FPGA programming support for SoC FPGA Arria 10
*/
@@ -122,3 +130,83 @@ void do_bridge_reset(int enable, unsigned int mask)
else
socfpga_bridges_reset();
}
+
+/*
+ * This function set/unset magic number "0xd15ea5e" to
+ * handoff register isw_handoff[7] - 0xffd0624c
+ * This magic number is part of boot progress tracking
+ * and it's required for warm reset workaround on MPFE hang issue.
+ */
+void set_regular_boot(unsigned int status)
+{
+ if (status)
+ writel(REGULAR_BOOT_MAGIC, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOFF_BASE + SYSMGR_A10_ISW_HANDOFF_7);
+ else
+ writel(0, socfpga_get_sysmgr_addr() +
+ SYSMGR_A10_ISW_HANDOF
