Re: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint

[Rick Chen]

> > From: Bin Meng 
> > Sent: Monday, June 12, 2023 3:36 PM
> > To: u-boot@lists.denx.de
> > Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志) 
> > 
> > Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to 
> > support aclint
> >
> > This RISC-V ACLINT specification [1] defines a set of memory mapped devices 
> > which provide inter-processor interrupts (IPI) and timer functionalities 
> > for each HART on a multi-HART RISC-V platform.
> >
> > The RISC-V ACLINT specification is defined to be backward compatible with 
> > the SiFive CLINT specification, however the device tree binding is a new 
> > one. This change updates the sifive clint ipi driver to support ACLINT mswi 
> > device, by checking the per-driver data field of the ACLINT mtimer driver 
> > to determine whether a syscon based approach needs to be taken to get the 
> > base address of the ACLINT mswi device.
> >
> > [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
> >
> > Signed-off-by: Bin Meng 
>
> LGTM.

Sorry, forgot the signed up.

Reviewed-by: Rick Chen 

>
> Thanks,
> Rick

Re: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint

[Rick Chen]

> From: Bin Meng 
> Sent: Monday, June 12, 2023 3:36 PM
> To: u-boot@lists.denx.de
> Cc: Leo Yu-Chi Liang(梁育齊) ; Rick Jian-Zhi Chen(陳建志) 
> 
> Subject: [PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to 
> support aclint
>
> This RISC-V ACLINT specification [1] defines a set of memory mapped devices 
> which provide inter-processor interrupts (IPI) and timer functionalities for 
> each HART on a multi-HART RISC-V platform.
>
> The RISC-V ACLINT specification is defined to be backward compatible with the 
> SiFive CLINT specification, however the device tree binding is a new one. 
> This change updates the sifive clint ipi driver to support ACLINT mswi 
> device, by checking the per-driver data field of the ACLINT mtimer driver to 
> determine whether a syscon based approach needs to be taken to get the base 
> address of the ACLINT mswi device.
>
> [1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
>
> Signed-off-by: Bin Meng 

LGTM.

Thanks,
Rick

[PATCH 2/3] riscv: clint: Update the sifive clint ipi driver to support aclint

[Bin Meng]

This RISC-V ACLINT specification [1] defines a set of memory mapped
devices which provide inter-processor interrupts (IPI) and timer
functionalities for each HART on a multi-HART RISC-V platform.

The RISC-V ACLINT specification is defined to be backward compatible
with the SiFive CLINT specification, however the device tree binding
is a new one. This change updates the sifive clint ipi driver to
support ACLINT mswi device, by checking the per-driver data field of
the ACLINT mtimer driver to determine whether a syscon based approach
needs to be taken to get the base address of the ACLINT mswi device.

[1] https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc

Signed-off-by: Bin Meng 
---

 arch/riscv/Kconfig|  4 
 arch/riscv/lib/sifive_clint.c | 21 -
 2 files changed, 24 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index f6ed05906a..9fcdd8c451 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -188,6 +188,8 @@ config DMA_ADDR_T_64BIT
 config SIFIVE_CLINT
bool
depends on RISCV_MMODE
+   select REGMAP
+   select SYSCON
help
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
@@ -195,6 +197,8 @@ config SIFIVE_CLINT
 config SPL_SIFIVE_CLINT
bool
depends on SPL_RISCV_MMODE
+   select SPL_REGMAP
+   select SPL_SYSCON
help
  The SiFive CLINT block holds memory-mapped control and status 
registers
  associated with software and timer interrupts.
diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
index ab22395c55..f242168381 100644
--- a/arch/riscv/lib/sifive_clint.c
+++ b/arch/riscv/lib/sifive_clint.c
@@ -10,9 +10,12 @@
 
 #include 
 #include 
+#include 
+#include 
 #include 
 #include 
 #include 
+#include 
 #include 
 
 /* MSIP registers */
@@ -30,7 +33,11 @@ int riscv_init_ipi(void)
if (ret)
return ret;
 
-   gd->arch.clint = dev_read_addr_ptr(dev);
+   if (dev_get_driver_data(dev) != 0)
+   gd->arch.clint = dev_read_addr_ptr(dev);
+   else
+   gd->arch.clint = syscon_get_first_range(RISCV_SYSCON_CLINT);
+
if (!gd->arch.clint)
return -EINVAL;
 
@@ -57,3 +64,15 @@ int riscv_get_ipi(int hart, int *pending)
 
return 0;
 }
+
+static const struct udevice_id riscv_aclint_swi_ids[] = {
+   { .compatible = "riscv,aclint-mswi", .data = RISCV_SYSCON_CLINT },
+   { }
+};
+
+U_BOOT_DRIVER(riscv_aclint_swi) = {
+   .name   = "riscv_aclint_swi",
+   .id = UCLASS_SYSCON,
+   .of_match   = riscv_aclint_swi_ids,
+   .flags  = DM_FLAG_PRE_RELOC,
+};
-- 
2.25.1