Re: [PATCH 2/7] arm: mach-k3: j721e: Enable QoS for DSS

2024-05-30 Thread Jayesh Choudhary 

Hello Andrew,

On 22/05/24 21:14, Andrew Davis wrote:

On 5/22/24 6:37 AM, Jayesh Choudhary wrote:

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
ATYPE 3 is selected so that the traffic takes non-coherent path and does


So this is the part I'm not sure about, this change is not just a 
performance
adjustment, it can and does break things. The ORDERID setting is fine 
with me,
but changing ATYPE should be done in a separate patch so it can be 
debated on

its own.


not have a conflict with coherent traffic from C7x (deep-learning
applications).
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM 
sources

using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])

Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruil1

Signed-off-by: Jayesh Choudhary 
---
  arch/arm/mach-k3/j721e/j721e_init.c |  28 +
  arch/arm/mach-k3/r5/j721e/Makefile  |   1 +
  arch/arm/mach-k3/r5/j721e/j721e_qos.h   |  96 +++
  arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 125 
  4 files changed, 250 insertions(+)
  create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h
  create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c

diff --git a/arch/arm/mach-k3/j721e/j721e_init.c 
b/arch/arm/mach-k3/j721e/j721e_init.c

index c2024f2500..e9ed8cb267 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c



[...]

diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c 
b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c

new file mode 100644
index 00..c829057200
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * j721e Quality of Service (QoS) Configuration Data
+ * Auto generated from K3 Resource Partitioning tool
+ */
+
+#include 
+#include "j721e_qos.h"
+
+struct k3_qos_data qos_data[] = {
+    /* DSS_PIPE_VID1 - 2 endpoints, 2 channels */
+    {
+    .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 0,


0x100 being the instance, and 0x4 * x being the specific device register 
right?

That could be encoded in a macro (the "Resource Partitioning tool" would
be updated to generate that too).

Andrew



Okay both val and reg could be updated.


+    .val = ATYPE_3 | ORDERID_15,
+    },
+    {
+    .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0x100 + 0x4 * 1,
+    .val = ATYPE_3 | ORDERID_15,
+    },


[...]


+
+    /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers. orderID x is remapped to orderID x again
+ * This is to ensure orderID from MAP register is unchanged
+ */
+
+    /* K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA - 2 groups */
+    {
+    .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 0,
+    .val = 0x76543210,
+    },
+    {
+    .reg = K3_DSS_MAIN_0_DSS_INST0_VBUSM_DMA + 4,
+    .val = 0xfedcba98,
+    },


From the looks of it, these register and val can also be encoded as
K3_QOS_GROUP_REG and K3_QOS_GROUP_VAL_HIGH (0xfedcba98) and
K3_QOS_GROUP_VAL_LOW (0x76543210)

[...]


+
+u32 qos_count = ARRAY_SIZE(qos_data);

Re: [PATCH 2/7] arm: mach-k3: j721e: Enable QoS for DSS

2024-05-22 Thread Andrew Davis 

On 5/22/24 6:37 AM, Jayesh Choudhary wrote:

Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
ATYPE 3 is selected so that the traffic takes non-coherent path and does


So this is the part I'm not sure about, this change is not just a performance
adjustment, it can and does break things. The ORDERID setting is fine with me,
but changing ATYPE should be done in a separate patch so it can be debated on
its own.


not have a conflict with coherent traffic from C7x (deep-learning
applications).
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])

Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruil1

Signed-off-by: Jayesh Choudhary 
---
  arch/arm/mach-k3/j721e/j721e_init.c |  28 +
  arch/arm/mach-k3/r5/j721e/Makefile  |   1 +
  arch/arm/mach-k3/r5/j721e/j721e_qos.h   |  96 +++
  arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 125 
  4 files changed, 250 insertions(+)
  create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h
  create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c

diff --git a/arch/arm/mach-k3/j721e/j721e_init.c 
b/arch/arm/mach-k3/j721e/j721e_init.c
index c2024f2500..e9ed8cb267 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -23,6 +23,22 @@
  #include "../sysfw-loader.h"
  #include "../common.h"
  
+/* NAVSS North Bridge (NB) registers */

+#define NAVSS0_NBSS_NB0_CFG_MMRS   0x03802000
+#define NAVSS0_NBSS_NB1_CFG_MMRS   0x03803000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB0_CFG_MMRS + 
0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB1_CFG_MMRS + 
0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-7 to VBUSM.C thread number
+ * Bit[1] maps orderID 8-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0  BIT(0)
+#define NB_THREADMAP_BIT1  BIT(1)
+
  #ifdef CONFIG_K3_LOAD_SYSFW
  struct fwl_data cbass_hc_cfg0_fwls[] = {
  #if defined(CONFIG_TARGET_J721E_R5_EVM)
@@ -124,6 +140,13 @@ void k3_mmc_restart_clock(void)
  }
  #endif
  
+/* Setup North Bridge registers to map ORDERID 8-15 to RT traffic */

+static void setup_navss_nb(void)
+{
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
  /*
   * This uninitialized global variable would normal end up in the .bss section,
   * but the .bss is cleared between writing and reading this variable, so move
@@ -288,6 +311,11 @@ void board_init_f(ulong dummy)
panic("DRAM init failed: %d\n", ret);
  #endif
spl_enable_cache();
+
+   if (IS_ENABLED(CONFIG_CPU_V7R))
+   setup_navss_nb();
+
+   setup_qos();
  }
  
  u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)

diff --git a/arch/arm/mach-k3/r5/j721e/Makefile 
b/arch/arm/mach-k3/r5/j721e/Makefile
index 78325db402..07bfb0dd93 100644
--- a/arch/arm/mach-k3/r5/j721e/Makefile
+++ b/arch/arm/mach-k3/r5/j721e/Makefile
@@ -3,3 +3,4 @@
  # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
  obj-y += clk-data.o
  obj-y += dev-data.o
+obj-y += j721e_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos.h 
b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
new file mode 100644
index 00..9ec0b7c630
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_SL_MCU_0_MEMBDG_RMST0   0x45D1
+#define PULSAR_SL_MCU_0_MEMBDG_WMST0   0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST  0x45D10800
+#define PULSAR_SL_MCU_0_MEMBDG_RMST1   0x45D11000
+#define PULSAR_SL_MCU_0_MEMBDG_WMST1   0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST  0x45D11800
+#define SA2_UL_MCU_0_CTXCACH_EXT_DMA   0x45D13000
+#define ICSS_G_MAIN_0_PR1_EXT_VBUSM0x45D8
+#define ICSS_G_MAIN_1_PR1_EXT_VBUSM0x45D80400
+#define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000
+#define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D82000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D82400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD   0x45D82800
+#define EMMCSD4SS_MAIN_1_EMMCSDS

[PATCH 2/7] arm: mach-k3: j721e: Enable QoS for DSS

2024-05-22 Thread Jayesh Choudhary 
Enable Quality of Service (QoS) blocks for Display SubSystem (DSS), by
servicing the DSS - DDR traffic from the Real-Time (RT) queue. This is
done by setting the DSS DMA orderID to greater than 7.
ATYPE 3 is selected so that the traffic takes non-coherent path and does
not have a conflict with coherent traffic from C7x (deep-learning
applications).
Before setting up the QoS, the ORDERID needs to be mapped to VBUSM sources
using setup_navss_nb() function call that sets the threadmap for NBSS
registers. (Section 10.2.10.1.2 "NB Parameters" in TRM[0])

Section 3.3.2 "Quality of Service (QoS)" in the TRM[0] provide more
details.

[0]: https://www.ti.com/lit/zip/spruil1

Signed-off-by: Jayesh Choudhary 
---
 arch/arm/mach-k3/j721e/j721e_init.c |  28 +
 arch/arm/mach-k3/r5/j721e/Makefile  |   1 +
 arch/arm/mach-k3/r5/j721e/j721e_qos.h   |  96 +++
 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c | 125 
 4 files changed, 250 insertions(+)
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos.h
 create mode 100644 arch/arm/mach-k3/r5/j721e/j721e_qos_uboot.c

diff --git a/arch/arm/mach-k3/j721e/j721e_init.c 
b/arch/arm/mach-k3/j721e/j721e_init.c
index c2024f2500..e9ed8cb267 100644
--- a/arch/arm/mach-k3/j721e/j721e_init.c
+++ b/arch/arm/mach-k3/j721e/j721e_init.c
@@ -23,6 +23,22 @@
 #include "../sysfw-loader.h"
 #include "../common.h"
 
+/* NAVSS North Bridge (NB) registers */
+#define NAVSS0_NBSS_NB0_CFG_MMRS   0x03802000
+#define NAVSS0_NBSS_NB1_CFG_MMRS   0x03803000
+#define NAVSS0_NBSS_NB0_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB0_CFG_MMRS + 
0x10)
+#define NAVSS0_NBSS_NB1_CFG_NB_THREADMAP   (NAVSS0_NBSS_NB1_CFG_MMRS + 
0x10)
+/*
+ * Thread Map for North Bridge Configuration
+ * Each bit is for each VBUSM source.
+ * Bit[0] maps orderID 0-7 to VBUSM.C thread number
+ * Bit[1] maps orderID 8-15 to VBUSM.C thread number
+ * When bit has value 0: VBUSM.C thread 0 (non-real time traffic)
+ * When bit has value 1: VBUSM.C thread 2 (real time traffic)
+ */
+#define NB_THREADMAP_BIT0  BIT(0)
+#define NB_THREADMAP_BIT1  BIT(1)
+
 #ifdef CONFIG_K3_LOAD_SYSFW
 struct fwl_data cbass_hc_cfg0_fwls[] = {
 #if defined(CONFIG_TARGET_J721E_R5_EVM)
@@ -124,6 +140,13 @@ void k3_mmc_restart_clock(void)
 }
 #endif
 
+/* Setup North Bridge registers to map ORDERID 8-15 to RT traffic */
+static void setup_navss_nb(void)
+{
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB0_CFG_NB_THREADMAP);
+   writel(NB_THREADMAP_BIT1, (uintptr_t)NAVSS0_NBSS_NB1_CFG_NB_THREADMAP);
+}
+
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -288,6 +311,11 @@ void board_init_f(ulong dummy)
panic("DRAM init failed: %d\n", ret);
 #endif
spl_enable_cache();
+
+   if (IS_ENABLED(CONFIG_CPU_V7R))
+   setup_navss_nb();
+
+   setup_qos();
 }
 
 u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device)
diff --git a/arch/arm/mach-k3/r5/j721e/Makefile 
b/arch/arm/mach-k3/r5/j721e/Makefile
index 78325db402..07bfb0dd93 100644
--- a/arch/arm/mach-k3/r5/j721e/Makefile
+++ b/arch/arm/mach-k3/r5/j721e/Makefile
@@ -3,3 +3,4 @@
 # Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
 obj-y += clk-data.o
 obj-y += dev-data.o
+obj-y += j721e_qos_uboot.o
diff --git a/arch/arm/mach-k3/r5/j721e/j721e_qos.h 
b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
new file mode 100644
index 00..9ec0b7c630
--- /dev/null
+++ b/arch/arm/mach-k3/r5/j721e/j721e_qos.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define PULSAR_SL_MCU_0_MEMBDG_RMST0   0x45D1
+#define PULSAR_SL_MCU_0_MEMBDG_WMST0   0x45D10400
+#define PULSAR_SL_MCU_0_CPU0_PMST  0x45D10800
+#define PULSAR_SL_MCU_0_MEMBDG_RMST1   0x45D11000
+#define PULSAR_SL_MCU_0_MEMBDG_WMST1   0x45D11400
+#define PULSAR_SL_MCU_0_CPU1_PMST  0x45D11800
+#define SA2_UL_MCU_0_CTXCACH_EXT_DMA   0x45D13000
+#define ICSS_G_MAIN_0_PR1_EXT_VBUSM0x45D8
+#define ICSS_G_MAIN_1_PR1_EXT_VBUSM0x45D80400
+#define K3_C66_COREPAC_MAIN_0_C66_MDMA 0x45D81000
+#define K3_C66_COREPAC_MAIN_1_C66_MDMA 0x45D81400
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD   0x45D82000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR   0x45D82400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD   0x45D82800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR   0x45D82C00
+#define PULSAR_SL_MAIN_0_MEMBDG_RMST0  0x45D84000
+#define PULSAR_SL_MAIN_0_MEMBDG_RMST1  0x45D84400
+#define PULSAR_SL_MAIN_0_MEMBDG_WMST0  0x45D84800
+#define PULSAR_SL_MAIN_0_MEMBDG_WMST1  0x45D84C00
+#define PULSAR_SL_MAIN_1_MEMBDG_RMST0  0x45D85000
+#define PULSAR_SL_MAIN_1_MEMBDG_RMST1  0x45D85400