Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Fabio Estevam]

On Tue, May 30, 2023 at 7:35 PM Adam Ford  wrote:

> I have it working now.  I need some time to clean my stuff and re-base
> the imx8mp.dtsi file, but I can submit a patch which fixes the clocks
> and re-sync's the device tree with the current stuff from kernel.org.
> I should be able to get a patch series out tonight.

Great work, Adam!

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Adam Ford]

On Tue, May 30, 2023 at 1:40 PM Tim Harvey  wrote:
>
> On Tue, May 30, 2023 at 10:28 AM Adam Ford  wrote:
> >
> > On Tue, May 30, 2023 at 12:23 PM Tim Harvey  wrote:
> > >
> > > On Mon, May 29, 2023 at 10:45 AM Adam Ford  wrote:
> > > >
> > > > On Wed, May 24, 2023 at 9:02 PM Fabio Estevam  
> > > > wrote:
> > > > >
> > > > > Hi Tim,
> > > > >
> > > > > On Fri, May 19, 2023 at 8:00 PM Tim Harvey  
> > > > > wrote:
> > > > >
> > > > > > Fabio,
> > > >
> > > > + Marek
> > > > I am adding Marek since he did the HSIO power domain driver.
> > > >
> > > > > >
> > > > > > There's more to be done here also. With this patch, and with the
> > > > > > spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> > > > > > you get:
> > > > > > starting USB...
> > > > > > Bus usb@3820:
> > > > > > Enable clock-controller@3038 failed
> > > > > > probe failed, error -2
> > > > > > No working controllers found
> > > > >
> > > > > Does this help?
> > > >
> > > > A bit.  I finally got some time to try to troubleshoot USB on my 8MP.
> > > >
> > > > >
> > > > > --- a/drivers/clk/imx/clk-imx8mp.c
> > > > > +++ b/drivers/clk/imx/clk-imx8mp.c
> > > > > @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
> > > > > clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk",
> > > > > "uart2", base + 0x44a0, 0));
> > > > > clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk",
> > > > > "uart3", base + 0x44b0, 0));
> > > > > clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk",
> > > > > "uart4", base + 0x44c0, 0));
> > > > > -   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > > > > "usb_core_ref", base + 0x44d0, 0));
> > > > > -   clk_dm(IMX8MP_CLK_USB_PHY_ROOT,
> > > >
> > > > IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I
> > > > don't think we can delete it. I had  keep IMX8MP_CLK_USB_ROOT, and
> > > > IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
> > > >
> > > > > imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
> > > > > +   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > > > > "hsio_axi", base + 0x44d0, 0));
> > > > > +   clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk",
> > > > > "osc_32k", base + 0x44d0, 0));
> > > > > clk_dm(IMX8MP_CLK_USDHC1_ROOT,
> > > > > imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> > > > > clk_dm(IMX8MP_CLK_USDHC2_ROOT,
> > > > > imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> > > > > clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk",
> > > > > "wdog", base + 0x4530, 0));
> > > >
> > > > At this point, the missing clock errors go away, but it hangs.  I
> > > > updated my 8MP USB clocks based on the latest Linux kernel so my
> > > > clocks looks like:
> > > >
> > > > clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi",
> > > > base + 0x44d0, 0));
> > > > clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk",
> > > > "clock-osc-24m", base + 0x44d0, 0));
> > > > clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk",
> > > > "usb_phy_ref", base + 0x44f0, 0));
> > > >
> > > > The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is
> > > > used for IMX8MP_CLK_USB_PHY_ROOT.  I didn't verify this against the
> > > > reference manual.
> > > >
> > > > With some debugging enabled, it looks to me like it might be
> > > > power-domain related, but I am not 100% certain.
> > > > When I start the USB, it appears to go through some clocks, and start
> > > > one power domain, but I think we have a power-domain chain where one
> > > > power domain starts another.  I saw a patch on another thread for
> > > > enabling parent power-domains, but it didn't seem to help me.
> > > >
> > > > u-boot=> usb start
> > > > starting USB...
> > > > Bus usb@3820: ofnode_read_prop: maximum-speed: 
> > > > ofnode_read_prop: dr_mode: host
> > > > dev_power_domain_on usb@32f10108
> > > > ofnode_read_prop: assigned-clock-rates: 
> > > > Looking for clock-controller@3038
> > > > Looking for clock-controller@3038
> > > >- result for clock-controller@3038: clock-controller@3038 
> > > > (ret=0)
> > > >- result for clock-controller@3038: clock-controller@3038 
> > > > (ret=0)
> > > > Looking for clock-controller@3038
> > > > Looking for clock-controller@3038
> > > >- result for clock-controller@3038: clock-controller@3038 
> > > > (ret=0)
> > > >- result for clock-controller@3038: clock-controller@3038 
> > > > (ret=0)
> > > > ofnode_read_prop: dr_mode: host
> > > >
> > > > 
> > > >
> > > > I added some debug code to the imx8mp_hsiomix_on in HSIOmix power
> > > > domain driver, and it doesn't appear to be getting called, yet
> > > > dev_power_domain_on usb@32f10108 should be invoking it.
> > > >
> > > > I am not positive it's a power domain issue, that's my first guess.
> > > 

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Tim Harvey]

On Tue, May 30, 2023 at 10:28 AM Adam Ford  wrote:
>
> On Tue, May 30, 2023 at 12:23 PM Tim Harvey  wrote:
> >
> > On Mon, May 29, 2023 at 10:45 AM Adam Ford  wrote:
> > >
> > > On Wed, May 24, 2023 at 9:02 PM Fabio Estevam  wrote:
> > > >
> > > > Hi Tim,
> > > >
> > > > On Fri, May 19, 2023 at 8:00 PM Tim Harvey  
> > > > wrote:
> > > >
> > > > > Fabio,
> > >
> > > + Marek
> > > I am adding Marek since he did the HSIO power domain driver.
> > >
> > > > >
> > > > > There's more to be done here also. With this patch, and with the
> > > > > spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> > > > > you get:
> > > > > starting USB...
> > > > > Bus usb@3820:
> > > > > Enable clock-controller@3038 failed
> > > > > probe failed, error -2
> > > > > No working controllers found
> > > >
> > > > Does this help?
> > >
> > > A bit.  I finally got some time to try to troubleshoot USB on my 8MP.
> > >
> > > >
> > > > --- a/drivers/clk/imx/clk-imx8mp.c
> > > > +++ b/drivers/clk/imx/clk-imx8mp.c
> > > > @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
> > > > clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk",
> > > > "uart2", base + 0x44a0, 0));
> > > > clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk",
> > > > "uart3", base + 0x44b0, 0));
> > > > clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk",
> > > > "uart4", base + 0x44c0, 0));
> > > > -   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > > > "usb_core_ref", base + 0x44d0, 0));
> > > > -   clk_dm(IMX8MP_CLK_USB_PHY_ROOT,
> > >
> > > IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I
> > > don't think we can delete it. I had  keep IMX8MP_CLK_USB_ROOT, and
> > > IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
> > >
> > > > imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
> > > > +   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > > > "hsio_axi", base + 0x44d0, 0));
> > > > +   clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk",
> > > > "osc_32k", base + 0x44d0, 0));
> > > > clk_dm(IMX8MP_CLK_USDHC1_ROOT,
> > > > imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> > > > clk_dm(IMX8MP_CLK_USDHC2_ROOT,
> > > > imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> > > > clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk",
> > > > "wdog", base + 0x4530, 0));
> > >
> > > At this point, the missing clock errors go away, but it hangs.  I
> > > updated my 8MP USB clocks based on the latest Linux kernel so my
> > > clocks looks like:
> > >
> > > clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi",
> > > base + 0x44d0, 0));
> > > clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk",
> > > "clock-osc-24m", base + 0x44d0, 0));
> > > clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk",
> > > "usb_phy_ref", base + 0x44f0, 0));
> > >
> > > The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is
> > > used for IMX8MP_CLK_USB_PHY_ROOT.  I didn't verify this against the
> > > reference manual.
> > >
> > > With some debugging enabled, it looks to me like it might be
> > > power-domain related, but I am not 100% certain.
> > > When I start the USB, it appears to go through some clocks, and start
> > > one power domain, but I think we have a power-domain chain where one
> > > power domain starts another.  I saw a patch on another thread for
> > > enabling parent power-domains, but it didn't seem to help me.
> > >
> > > u-boot=> usb start
> > > starting USB...
> > > Bus usb@3820: ofnode_read_prop: maximum-speed: 
> > > ofnode_read_prop: dr_mode: host
> > > dev_power_domain_on usb@32f10108
> > > ofnode_read_prop: assigned-clock-rates: 
> > > Looking for clock-controller@3038
> > > Looking for clock-controller@3038
> > >- result for clock-controller@3038: clock-controller@3038 
> > > (ret=0)
> > >- result for clock-controller@3038: clock-controller@3038 
> > > (ret=0)
> > > Looking for clock-controller@3038
> > > Looking for clock-controller@3038
> > >- result for clock-controller@3038: clock-controller@3038 
> > > (ret=0)
> > >- result for clock-controller@3038: clock-controller@3038 
> > > (ret=0)
> > > ofnode_read_prop: dr_mode: host
> > >
> > > 
> > >
> > > I added some debug code to the imx8mp_hsiomix_on in HSIOmix power
> > > domain driver, and it doesn't appear to be getting called, yet
> > > dev_power_domain_on usb@32f10108 should be invoking it.
> > >
> > > I am not positive it's a power domain issue, that's my first guess.
> > >
> > >
> > > Tim - have you had any success?
> > >
> >
> > Adam,
> >
> > No success here yet but I don't have any time to work on it for at
> > least another week.
>
> No worries. I'll try to spend some more time this week, and keep you
> informed of any progress.  I'd like to see 

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Adam Ford]

On Tue, May 30, 2023 at 12:23 PM Tim Harvey  wrote:
>
> On Mon, May 29, 2023 at 10:45 AM Adam Ford  wrote:
> >
> > On Wed, May 24, 2023 at 9:02 PM Fabio Estevam  wrote:
> > >
> > > Hi Tim,
> > >
> > > On Fri, May 19, 2023 at 8:00 PM Tim Harvey  wrote:
> > >
> > > > Fabio,
> >
> > + Marek
> > I am adding Marek since he did the HSIO power domain driver.
> >
> > > >
> > > > There's more to be done here also. With this patch, and with the
> > > > spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> > > > you get:
> > > > starting USB...
> > > > Bus usb@3820:
> > > > Enable clock-controller@3038 failed
> > > > probe failed, error -2
> > > > No working controllers found
> > >
> > > Does this help?
> >
> > A bit.  I finally got some time to try to troubleshoot USB on my 8MP.
> >
> > >
> > > --- a/drivers/clk/imx/clk-imx8mp.c
> > > +++ b/drivers/clk/imx/clk-imx8mp.c
> > > @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
> > > clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk",
> > > "uart2", base + 0x44a0, 0));
> > > clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk",
> > > "uart3", base + 0x44b0, 0));
> > > clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk",
> > > "uart4", base + 0x44c0, 0));
> > > -   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > > "usb_core_ref", base + 0x44d0, 0));
> > > -   clk_dm(IMX8MP_CLK_USB_PHY_ROOT,
> >
> > IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I
> > don't think we can delete it. I had  keep IMX8MP_CLK_USB_ROOT, and
> > IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
> >
> > > imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
> > > +   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > > "hsio_axi", base + 0x44d0, 0));
> > > +   clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk",
> > > "osc_32k", base + 0x44d0, 0));
> > > clk_dm(IMX8MP_CLK_USDHC1_ROOT,
> > > imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> > > clk_dm(IMX8MP_CLK_USDHC2_ROOT,
> > > imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> > > clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk",
> > > "wdog", base + 0x4530, 0));
> >
> > At this point, the missing clock errors go away, but it hangs.  I
> > updated my 8MP USB clocks based on the latest Linux kernel so my
> > clocks looks like:
> >
> > clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi",
> > base + 0x44d0, 0));
> > clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk",
> > "clock-osc-24m", base + 0x44d0, 0));
> > clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk",
> > "usb_phy_ref", base + 0x44f0, 0));
> >
> > The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is
> > used for IMX8MP_CLK_USB_PHY_ROOT.  I didn't verify this against the
> > reference manual.
> >
> > With some debugging enabled, it looks to me like it might be
> > power-domain related, but I am not 100% certain.
> > When I start the USB, it appears to go through some clocks, and start
> > one power domain, but I think we have a power-domain chain where one
> > power domain starts another.  I saw a patch on another thread for
> > enabling parent power-domains, but it didn't seem to help me.
> >
> > u-boot=> usb start
> > starting USB...
> > Bus usb@3820: ofnode_read_prop: maximum-speed: 
> > ofnode_read_prop: dr_mode: host
> > dev_power_domain_on usb@32f10108
> > ofnode_read_prop: assigned-clock-rates: 
> > Looking for clock-controller@3038
> > Looking for clock-controller@3038
> >- result for clock-controller@3038: clock-controller@3038 (ret=0)
> >- result for clock-controller@3038: clock-controller@3038 (ret=0)
> > Looking for clock-controller@3038
> > Looking for clock-controller@3038
> >- result for clock-controller@3038: clock-controller@3038 (ret=0)
> >- result for clock-controller@3038: clock-controller@3038 (ret=0)
> > ofnode_read_prop: dr_mode: host
> >
> > 
> >
> > I added some debug code to the imx8mp_hsiomix_on in HSIOmix power
> > domain driver, and it doesn't appear to be getting called, yet
> > dev_power_domain_on usb@32f10108 should be invoking it.
> >
> > I am not positive it's a power domain issue, that's my first guess.
> >
> >
> > Tim - have you had any success?
> >
>
> Adam,
>
> No success here yet but I don't have any time to work on it for at
> least another week.

No worries. I'll try to spend some more time this week, and keep you
informed of any progress.  I'd like to see the USB working too.

adam
>
> Best Regards,
>
> Tim

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Tim Harvey]

On Mon, May 29, 2023 at 10:45 AM Adam Ford  wrote:
>
> On Wed, May 24, 2023 at 9:02 PM Fabio Estevam  wrote:
> >
> > Hi Tim,
> >
> > On Fri, May 19, 2023 at 8:00 PM Tim Harvey  wrote:
> >
> > > Fabio,
>
> + Marek
> I am adding Marek since he did the HSIO power domain driver.
>
> > >
> > > There's more to be done here also. With this patch, and with the
> > > spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> > > you get:
> > > starting USB...
> > > Bus usb@3820:
> > > Enable clock-controller@3038 failed
> > > probe failed, error -2
> > > No working controllers found
> >
> > Does this help?
>
> A bit.  I finally got some time to try to troubleshoot USB on my 8MP.
>
> >
> > --- a/drivers/clk/imx/clk-imx8mp.c
> > +++ b/drivers/clk/imx/clk-imx8mp.c
> > @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
> > clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk",
> > "uart2", base + 0x44a0, 0));
> > clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk",
> > "uart3", base + 0x44b0, 0));
> > clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk",
> > "uart4", base + 0x44c0, 0));
> > -   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > "usb_core_ref", base + 0x44d0, 0));
> > -   clk_dm(IMX8MP_CLK_USB_PHY_ROOT,
>
> IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I
> don't think we can delete it. I had  keep IMX8MP_CLK_USB_ROOT, and
> IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.
>
> > imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
> > +   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> > "hsio_axi", base + 0x44d0, 0));
> > +   clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk",
> > "osc_32k", base + 0x44d0, 0));
> > clk_dm(IMX8MP_CLK_USDHC1_ROOT,
> > imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> > clk_dm(IMX8MP_CLK_USDHC2_ROOT,
> > imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> > clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk",
> > "wdog", base + 0x4530, 0));
>
> At this point, the missing clock errors go away, but it hangs.  I
> updated my 8MP USB clocks based on the latest Linux kernel so my
> clocks looks like:
>
> clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi",
> base + 0x44d0, 0));
> clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk",
> "clock-osc-24m", base + 0x44d0, 0));
> clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk",
> "usb_phy_ref", base + 0x44f0, 0));
>
> The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is
> used for IMX8MP_CLK_USB_PHY_ROOT.  I didn't verify this against the
> reference manual.
>
> With some debugging enabled, it looks to me like it might be
> power-domain related, but I am not 100% certain.
> When I start the USB, it appears to go through some clocks, and start
> one power domain, but I think we have a power-domain chain where one
> power domain starts another.  I saw a patch on another thread for
> enabling parent power-domains, but it didn't seem to help me.
>
> u-boot=> usb start
> starting USB...
> Bus usb@3820: ofnode_read_prop: maximum-speed: 
> ofnode_read_prop: dr_mode: host
> dev_power_domain_on usb@32f10108
> ofnode_read_prop: assigned-clock-rates: 
> Looking for clock-controller@3038
> Looking for clock-controller@3038
>- result for clock-controller@3038: clock-controller@3038 (ret=0)
>- result for clock-controller@3038: clock-controller@3038 (ret=0)
> Looking for clock-controller@3038
> Looking for clock-controller@3038
>- result for clock-controller@3038: clock-controller@3038 (ret=0)
>- result for clock-controller@3038: clock-controller@3038 (ret=0)
> ofnode_read_prop: dr_mode: host
>
> 
>
> I added some debug code to the imx8mp_hsiomix_on in HSIOmix power
> domain driver, and it doesn't appear to be getting called, yet
> dev_power_domain_on usb@32f10108 should be invoking it.
>
> I am not positive it's a power domain issue, that's my first guess.
>
>
> Tim - have you had any success?
>

Adam,

No success here yet but I don't have any time to work on it for at
least another week.

Best Regards,

Tim

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Adam Ford]

On Wed, May 24, 2023 at 9:02 PM Fabio Estevam  wrote:
>
> Hi Tim,
>
> On Fri, May 19, 2023 at 8:00 PM Tim Harvey  wrote:
>
> > Fabio,

+ Marek
I am adding Marek since he did the HSIO power domain driver.

> >
> > There's more to be done here also. With this patch, and with the
> > spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> > you get:
> > starting USB...
> > Bus usb@3820:
> > Enable clock-controller@3038 failed
> > probe failed, error -2
> > No working controllers found
>
> Does this help?

A bit.  I finally got some time to try to troubleshoot USB on my 8MP.

>
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
> clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk",
> "uart2", base + 0x44a0, 0));
> clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk",
> "uart3", base + 0x44b0, 0));
> clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk",
> "uart4", base + 0x44c0, 0));
> -   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> "usb_core_ref", base + 0x44d0, 0));
> -   clk_dm(IMX8MP_CLK_USB_PHY_ROOT,

IMX8MP_CLK_USB_PHY_ROOT is also referenced in the device tree, so I
don't think we can delete it. I had  keep IMX8MP_CLK_USB_ROOT, and
IMX8MP_CLK_USB_PHY_ROOT while also adding IMX8MP_CLK_USB_SUSP.

> imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
> +   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
> "hsio_axi", base + 0x44d0, 0));
> +   clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk",
> "osc_32k", base + 0x44d0, 0));
> clk_dm(IMX8MP_CLK_USDHC1_ROOT,
> imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
> clk_dm(IMX8MP_CLK_USDHC2_ROOT,
> imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
> clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk",
> "wdog", base + 0x4530, 0));

At this point, the missing clock errors go away, but it hangs.  I
updated my 8MP USB clocks based on the latest Linux kernel so my
clocks looks like:

clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate2("usb_root_clk", "hsio_axi",
base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate2("usb_suspend_clk",
"clock-osc-24m", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USB_PHY_ROOT, imx_clk_gate4("usb_phy_root_clk",
"usb_phy_ref", base + 0x44f0, 0));

The linux kernel uses gate2 for USB_ROOT and USB_SUSP while gate4 is
used for IMX8MP_CLK_USB_PHY_ROOT.  I didn't verify this against the
reference manual.

With some debugging enabled, it looks to me like it might be
power-domain related, but I am not 100% certain.
When I start the USB, it appears to go through some clocks, and start
one power domain, but I think we have a power-domain chain where one
power domain starts another.  I saw a patch on another thread for
enabling parent power-domains, but it didn't seem to help me.

u-boot=> usb start
starting USB...
Bus usb@3820: ofnode_read_prop: maximum-speed: 
ofnode_read_prop: dr_mode: host
dev_power_domain_on usb@32f10108
ofnode_read_prop: assigned-clock-rates: 
Looking for clock-controller@3038
Looking for clock-controller@3038
   - result for clock-controller@3038: clock-controller@3038 (ret=0)
   - result for clock-controller@3038: clock-controller@3038 (ret=0)
Looking for clock-controller@3038
Looking for clock-controller@3038
   - result for clock-controller@3038: clock-controller@3038 (ret=0)
   - result for clock-controller@3038: clock-controller@3038 (ret=0)
ofnode_read_prop: dr_mode: host



I added some debug code to the imx8mp_hsiomix_on in HSIOmix power
domain driver, and it doesn't appear to be getting called, yet
dev_power_domain_on usb@32f10108 should be invoking it.

I am not positive it's a power domain issue, that's my first guess.


Tim - have you had any success?

adam

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Fabio Estevam]

Hi Tim,

On Fri, May 19, 2023 at 8:00 PM Tim Harvey  wrote:

> Fabio,
>
> There's more to be done here also. With this patch, and with the
> spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> you get:
> starting USB...
> Bus usb@3820:
> Enable clock-controller@3038 failed
> probe failed, error -2
> No working controllers found

Does this help?

--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -337,8 +337,8 @@ static int imx8mp_clk_probe(struct udevice *dev)
clk_dm(IMX8MP_CLK_UART2_ROOT, imx_clk_gate4("uart2_root_clk",
"uart2", base + 0x44a0, 0));
clk_dm(IMX8MP_CLK_UART3_ROOT, imx_clk_gate4("uart3_root_clk",
"uart3", base + 0x44b0, 0));
clk_dm(IMX8MP_CLK_UART4_ROOT, imx_clk_gate4("uart4_root_clk",
"uart4", base + 0x44c0, 0));
-   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
"usb_core_ref", base + 0x44d0, 0));
-   clk_dm(IMX8MP_CLK_USB_PHY_ROOT,
imx_clk_gate4("usb_phy_root_clk", "usb_phy_ref", base + 0x44f0, 0));
+   clk_dm(IMX8MP_CLK_USB_ROOT, imx_clk_gate4("usb_root_clk",
"hsio_axi", base + 0x44d0, 0));
+   clk_dm(IMX8MP_CLK_USB_SUSP, imx_clk_gate4("usb_suspend_clk",
"osc_32k", base + 0x44d0, 0));
clk_dm(IMX8MP_CLK_USDHC1_ROOT,
imx_clk_gate4("usdhc1_root_clk", "usdhc1", base + 0x4510, 0));
clk_dm(IMX8MP_CLK_USDHC2_ROOT,
imx_clk_gate4("usdhc2_root_clk", "usdhc2", base + 0x4520, 0));
clk_dm(IMX8MP_CLK_WDOG1_ROOT, imx_clk_gate4("wdog1_root_clk",
"wdog", base + 0x4530, 0));

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Adam Ford]

On Mon, May 22, 2023 at 3:49 PM Fabio Estevam  wrote:
>
> Hi Tim,
>
> On Fri, May 19, 2023 at 8:00 PM Tim Harvey  wrote:
>
> > Fabio,
> >
> > There's more to be done here also. With this patch, and with the
> > spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> > you get:
> > starting USB...
> > Bus usb@3820:
> > Enable clock-controller@3038 failed
> > probe failed, error -2
> > No working controllers found
> >
> > So until we get this figured out please don't apply this.
>
> I don't have any imx8mp-based board here to debug this problem, so it
> would be nice
> if someone else could investigate this.

I can do some testing on the imx8mp-beacon board, but it will likely
be a few days before I can get to it.

adam
>
> Thanks

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Fabio Estevam]

Hi Tim,

On Fri, May 19, 2023 at 8:00 PM Tim Harvey  wrote:

> Fabio,
>
> There's more to be done here also. With this patch, and with the
> spba-bus added to u-boot.dtsi, if you try to enable usb (usb start)
> you get:
> starting USB...
> Bus usb@3820:
> Enable clock-controller@3038 failed
> probe failed, error -2
> No working controllers found
>
> So until we get this figured out please don't apply this.

I don't have any imx8mp-based board here to debug this problem, so it
would be nice
if someone else could investigate this.

Thanks

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Rasmus Villemoes]

On 20/05/2023 00.26, Adam Ford wrote:
> On Fri, May 19, 2023 at 5:19 PM Tim Harvey  wrote:
>>
>> On Wed, May 3, 2023 at 9:11 AM Tim Harvey  wrote:
>>>
>> Fabio,
>>
>> Apparently I didn't do a very good job of testing this. This patch is
>> causing imx8mp-venice-* and imx8mp-evk boards to no longer boot with
>> no SPL banner. The specific change that causes breakage is the one
>> that encapsulates the spi/uart/flexcan children with
>> spba-bus@3080.
> 
> The SPI, UART, and Flexcan are part of the spba-bus.
> 
> We'll need to add the spba bus to imx8mp-u-boot.dtsi. Since it had no
> node name, it'll have to fall under aip3.
> 
> Try this:
> 
> diff --git a/arch/arm/dts/imx8mp-u-boot.dtsi b/arch/arm/dts/imx8mp-u-boot.dtsi
> index 18d1728e1d..0e6811b129 100644
> --- a/arch/arm/dts/imx8mp-u-boot.dtsi
> +++ b/arch/arm/dts/imx8mp-u-boot.dtsi
> @@ -44,6 +44,10 @@
> 
>   {
> bootph-pre-ram;
> +
> +   spba-bus@3080 {
> +   bootph-pre-ram;
> +   };
>  };
> 
>   {

This begs the question: Why don't these tags just implicitly propagate
to parent nodes? It's a U-Boot specific tool (fdtgrep) that makes use of
them, no? So making the rule be "keep this node if it _or any
descendant_ has that tag" should be possible.

This has probably been answered somewhere before.

Rasmus

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Tim Harvey]

On Fri, May 19, 2023 at 3:35 PM Adam Ford  wrote:
>
> On Fri, May 19, 2023 at 5:34 PM Tim Harvey  wrote:
> >
> > On Fri, May 19, 2023 at 3:31 PM Tim Harvey  wrote:
> > >
> > > On Fri, May 19, 2023 at 3:27 PM Adam Ford  wrote:
> > > >
> > > > On Fri, May 19, 2023 at 5:19 PM Tim Harvey  
> > > > wrote:
> > > > >
> > > > > On Wed, May 3, 2023 at 9:11 AM Tim Harvey  
> > > > > wrote:
> > > > > >
> > > > > > On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam  
> > > > > > wrote:
> > > > > > >
> > > > > > > From: Fabio Estevam 
> > > > > > >
> > > > > > > Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
> > > > > > >
> > > > > > > Signed-off-by: Fabio Estevam 
> > > > > > > ---
> > > > > > >  arch/arm/dts/imx8mp.dtsi | 374 
> > > > > > > ---
> > > > > > >  include/dt-bindings/clock/imx8mp-clock.h |  14 +-
> > > > > > >  2 files changed, 270 insertions(+), 118 deletions(-)
> > > > > > >
> > > > > > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> > > > > > > index bb916a0948a8..a237275ee017 100644
> > > > > > > --- a/arch/arm/dts/imx8mp.dtsi
> > > > > > > +++ b/arch/arm/dts/imx8mp.dtsi
> > > > > > > @@ -123,6 +123,7 @@
> > > > > > >
> > > > > > > A53_L2: l2-cache0 {
> > > > > > > compatible = "cache";
> > > > > > > +   cache-unified;
> > > > > > > cache-level = <2>;
> > > > > > > cache-size = <0x8>;
> > > > > > > cache-line-size = <64>;
> > > > > > > @@ -379,6 +380,8 @@
> > > > > > > compatible = "fsl,imx8mp-tmu";
> > > > > > > reg = <0x3026 0x1>;
> > > > > > > clocks = < 
> > > > > > > IMX8MP_CLK_TSENSOR_ROOT>;
> > > > > > > +   nvmem-cells = <_calib>;
> > > > > > > +   nvmem-cell-names = "calib";
> > > > > > > #thermal-sensor-cells = <1>;
> > > > > > > };
> > > > > > >
> > > > > > > @@ -411,7 +414,7 @@
> > > > > > > reg = <0x3033 0x1>;
> > > > > > > };
> > > > > > >
> > > > > > > -   gpr: iomuxc-gpr@3034 {
> > > > > > > +   gpr: syscon@3034 {
> > > > > > > compatible = 
> > > > > > > "fsl,imx8mp-iomuxc-gpr", "syscon";
> > > > > > > reg = <0x3034 0x1>;
> > > > > > > };
> > > > > > > @@ -424,27 +427,44 @@
> > > > > > > #address-cells = <1>;
> > > > > > > #size-cells = <1>;
> > > > > > >
> > > > > > > -   imx8mp_uid: unique-id@420 {
> > > > > > > +   /*
> > > > > > > +* The register address below 
> > > > > > > maps to the MX8M
> > > > > > > +* Fusemap Description Table 
> > > > > > > entries this way.
> > > > > > > +* Assuming
> > > > > > > +*   reg = ;
> > > > > > > +* then
> > > > > > > +*   Fuse Address = (ADDR * 4) + 
> > > > > > > 0x400
> > > > > > > +* Note that if SIZE is greater 
> > > > > > > than 4, then
> > > > > > > +* each subsequent fuse is 
> > > > > > > located at offset
> > > > > > > +* +0x10 in Fusemap Description 
> > > > > > > Table (e.g.
> > > > > > > +* reg = <0x8 0x8> describes 
> > > > > > > fuses 0x420 and
> > > > > > > +* 0x430).
> > > > > > > +*/
> > > > > > > +   imx8mp_uid: unique-id@8 { /* 
> > > > > > > 0x420-0x430 */
> > > > > > > reg = <0x8 0x8>;
> > > > > > > };
> > > > > > >
> > > > > > > -   cpu_speed_grade: speed-grade@10 {
> > > > > > > +   cpu_speed_grade: speed-grade@10 { 
> > > > > > > /* 0x440 */
> > > > > > > reg = <0x10 4>;
> > > > > > > };
> > > > > > >
> > > > > > > -   eth_mac1: mac-address@90 {
> > > > > > > +   eth_mac1: mac-address@90 { /* 
> > > > > > > 0x640 */
> > > > > > > reg = <0x90 6>;
> > > > > > > };
> > > > > > >
> > > > > > > -   eth_mac2: mac-address@96 {
> > > > > > > +   eth_mac2: mac-address@96 { /* 
> > > > > > > 0x658 */
> > > > > > >

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Adam Ford]

On Fri, May 19, 2023 at 5:34 PM Tim Harvey  wrote:
>
> On Fri, May 19, 2023 at 3:31 PM Tim Harvey  wrote:
> >
> > On Fri, May 19, 2023 at 3:27 PM Adam Ford  wrote:
> > >
> > > On Fri, May 19, 2023 at 5:19 PM Tim Harvey  wrote:
> > > >
> > > > On Wed, May 3, 2023 at 9:11 AM Tim Harvey  wrote:
> > > > >
> > > > > On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam  
> > > > > wrote:
> > > > > >
> > > > > > From: Fabio Estevam 
> > > > > >
> > > > > > Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
> > > > > >
> > > > > > Signed-off-by: Fabio Estevam 
> > > > > > ---
> > > > > >  arch/arm/dts/imx8mp.dtsi | 374 
> > > > > > ---
> > > > > >  include/dt-bindings/clock/imx8mp-clock.h |  14 +-
> > > > > >  2 files changed, 270 insertions(+), 118 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> > > > > > index bb916a0948a8..a237275ee017 100644
> > > > > > --- a/arch/arm/dts/imx8mp.dtsi
> > > > > > +++ b/arch/arm/dts/imx8mp.dtsi
> > > > > > @@ -123,6 +123,7 @@
> > > > > >
> > > > > > A53_L2: l2-cache0 {
> > > > > > compatible = "cache";
> > > > > > +   cache-unified;
> > > > > > cache-level = <2>;
> > > > > > cache-size = <0x8>;
> > > > > > cache-line-size = <64>;
> > > > > > @@ -379,6 +380,8 @@
> > > > > > compatible = "fsl,imx8mp-tmu";
> > > > > > reg = <0x3026 0x1>;
> > > > > > clocks = < 
> > > > > > IMX8MP_CLK_TSENSOR_ROOT>;
> > > > > > +   nvmem-cells = <_calib>;
> > > > > > +   nvmem-cell-names = "calib";
> > > > > > #thermal-sensor-cells = <1>;
> > > > > > };
> > > > > >
> > > > > > @@ -411,7 +414,7 @@
> > > > > > reg = <0x3033 0x1>;
> > > > > > };
> > > > > >
> > > > > > -   gpr: iomuxc-gpr@3034 {
> > > > > > +   gpr: syscon@3034 {
> > > > > > compatible = 
> > > > > > "fsl,imx8mp-iomuxc-gpr", "syscon";
> > > > > > reg = <0x3034 0x1>;
> > > > > > };
> > > > > > @@ -424,27 +427,44 @@
> > > > > > #address-cells = <1>;
> > > > > > #size-cells = <1>;
> > > > > >
> > > > > > -   imx8mp_uid: unique-id@420 {
> > > > > > +   /*
> > > > > > +* The register address below maps 
> > > > > > to the MX8M
> > > > > > +* Fusemap Description Table 
> > > > > > entries this way.
> > > > > > +* Assuming
> > > > > > +*   reg = ;
> > > > > > +* then
> > > > > > +*   Fuse Address = (ADDR * 4) + 
> > > > > > 0x400
> > > > > > +* Note that if SIZE is greater 
> > > > > > than 4, then
> > > > > > +* each subsequent fuse is located 
> > > > > > at offset
> > > > > > +* +0x10 in Fusemap Description 
> > > > > > Table (e.g.
> > > > > > +* reg = <0x8 0x8> describes fuses 
> > > > > > 0x420 and
> > > > > > +* 0x430).
> > > > > > +*/
> > > > > > +   imx8mp_uid: unique-id@8 { /* 
> > > > > > 0x420-0x430 */
> > > > > > reg = <0x8 0x8>;
> > > > > > };
> > > > > >
> > > > > > -   cpu_speed_grade: speed-grade@10 {
> > > > > > +   cpu_speed_grade: speed-grade@10 { 
> > > > > > /* 0x440 */
> > > > > > reg = <0x10 4>;
> > > > > > };
> > > > > >
> > > > > > -   eth_mac1: mac-address@90 {
> > > > > > +   eth_mac1: mac-address@90 { /* 0x640 
> > > > > > */
> > > > > > reg = <0x90 6>;
> > > > > > };
> > > > > >
> > > > > > -   eth_mac2: mac-address@96 {
> > > > > > +   eth_mac2: mac-address@96 { /* 0x658 
> > > > > > */
> > > > > > reg = <0x96 6>;
> > > > > > };
> > > > > > +
> > > > > > +   tmu_calib: calib@264 { /* 
> > > > > > 0xd90-0xdc0 */
> > > > > > +   reg = <0x264 0x10>;

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Tim Harvey]

On Fri, May 19, 2023 at 3:31 PM Tim Harvey  wrote:
>
> On Fri, May 19, 2023 at 3:27 PM Adam Ford  wrote:
> >
> > On Fri, May 19, 2023 at 5:19 PM Tim Harvey  wrote:
> > >
> > > On Wed, May 3, 2023 at 9:11 AM Tim Harvey  wrote:
> > > >
> > > > On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam  
> > > > wrote:
> > > > >
> > > > > From: Fabio Estevam 
> > > > >
> > > > > Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
> > > > >
> > > > > Signed-off-by: Fabio Estevam 
> > > > > ---
> > > > >  arch/arm/dts/imx8mp.dtsi | 374 
> > > > > ---
> > > > >  include/dt-bindings/clock/imx8mp-clock.h |  14 +-
> > > > >  2 files changed, 270 insertions(+), 118 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> > > > > index bb916a0948a8..a237275ee017 100644
> > > > > --- a/arch/arm/dts/imx8mp.dtsi
> > > > > +++ b/arch/arm/dts/imx8mp.dtsi
> > > > > @@ -123,6 +123,7 @@
> > > > >
> > > > > A53_L2: l2-cache0 {
> > > > > compatible = "cache";
> > > > > +   cache-unified;
> > > > > cache-level = <2>;
> > > > > cache-size = <0x8>;
> > > > > cache-line-size = <64>;
> > > > > @@ -379,6 +380,8 @@
> > > > > compatible = "fsl,imx8mp-tmu";
> > > > > reg = <0x3026 0x1>;
> > > > > clocks = < 
> > > > > IMX8MP_CLK_TSENSOR_ROOT>;
> > > > > +   nvmem-cells = <_calib>;
> > > > > +   nvmem-cell-names = "calib";
> > > > > #thermal-sensor-cells = <1>;
> > > > > };
> > > > >
> > > > > @@ -411,7 +414,7 @@
> > > > > reg = <0x3033 0x1>;
> > > > > };
> > > > >
> > > > > -   gpr: iomuxc-gpr@3034 {
> > > > > +   gpr: syscon@3034 {
> > > > > compatible = "fsl,imx8mp-iomuxc-gpr", 
> > > > > "syscon";
> > > > > reg = <0x3034 0x1>;
> > > > > };
> > > > > @@ -424,27 +427,44 @@
> > > > > #address-cells = <1>;
> > > > > #size-cells = <1>;
> > > > >
> > > > > -   imx8mp_uid: unique-id@420 {
> > > > > +   /*
> > > > > +* The register address below maps to 
> > > > > the MX8M
> > > > > +* Fusemap Description Table entries 
> > > > > this way.
> > > > > +* Assuming
> > > > > +*   reg = ;
> > > > > +* then
> > > > > +*   Fuse Address = (ADDR * 4) + 0x400
> > > > > +* Note that if SIZE is greater than 
> > > > > 4, then
> > > > > +* each subsequent fuse is located at 
> > > > > offset
> > > > > +* +0x10 in Fusemap Description Table 
> > > > > (e.g.
> > > > > +* reg = <0x8 0x8> describes fuses 
> > > > > 0x420 and
> > > > > +* 0x430).
> > > > > +*/
> > > > > +   imx8mp_uid: unique-id@8 { /* 
> > > > > 0x420-0x430 */
> > > > > reg = <0x8 0x8>;
> > > > > };
> > > > >
> > > > > -   cpu_speed_grade: speed-grade@10 {
> > > > > +   cpu_speed_grade: speed-grade@10 { /* 
> > > > > 0x440 */
> > > > > reg = <0x10 4>;
> > > > > };
> > > > >
> > > > > -   eth_mac1: mac-address@90 {
> > > > > +   eth_mac1: mac-address@90 { /* 0x640 */
> > > > > reg = <0x90 6>;
> > > > > };
> > > > >
> > > > > -   eth_mac2: mac-address@96 {
> > > > > +   eth_mac2: mac-address@96 { /* 0x658 */
> > > > > reg = <0x96 6>;
> > > > > };
> > > > > +
> > > > > +   tmu_calib: calib@264 { /* 0xd90-0xdc0 
> > > > > */
> > > > > +   reg = <0x264 0x10>;
> > > > > +   };
> > > > > };
> > > > >
> > > > > -   anatop: anatop@3036 {
> > > > > -   compatible = "fsl,imx8mp-anatop", 
> > > > > "fsl,imx8mm-anatop",
> > > > > - 

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Tim Harvey]

On Fri, May 19, 2023 at 3:27 PM Adam Ford  wrote:
>
> On Fri, May 19, 2023 at 5:19 PM Tim Harvey  wrote:
> >
> > On Wed, May 3, 2023 at 9:11 AM Tim Harvey  wrote:
> > >
> > > On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam  wrote:
> > > >
> > > > From: Fabio Estevam 
> > > >
> > > > Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
> > > >
> > > > Signed-off-by: Fabio Estevam 
> > > > ---
> > > >  arch/arm/dts/imx8mp.dtsi | 374 ---
> > > >  include/dt-bindings/clock/imx8mp-clock.h |  14 +-
> > > >  2 files changed, 270 insertions(+), 118 deletions(-)
> > > >
> > > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> > > > index bb916a0948a8..a237275ee017 100644
> > > > --- a/arch/arm/dts/imx8mp.dtsi
> > > > +++ b/arch/arm/dts/imx8mp.dtsi
> > > > @@ -123,6 +123,7 @@
> > > >
> > > > A53_L2: l2-cache0 {
> > > > compatible = "cache";
> > > > +   cache-unified;
> > > > cache-level = <2>;
> > > > cache-size = <0x8>;
> > > > cache-line-size = <64>;
> > > > @@ -379,6 +380,8 @@
> > > > compatible = "fsl,imx8mp-tmu";
> > > > reg = <0x3026 0x1>;
> > > > clocks = < IMX8MP_CLK_TSENSOR_ROOT>;
> > > > +   nvmem-cells = <_calib>;
> > > > +   nvmem-cell-names = "calib";
> > > > #thermal-sensor-cells = <1>;
> > > > };
> > > >
> > > > @@ -411,7 +414,7 @@
> > > > reg = <0x3033 0x1>;
> > > > };
> > > >
> > > > -   gpr: iomuxc-gpr@3034 {
> > > > +   gpr: syscon@3034 {
> > > > compatible = "fsl,imx8mp-iomuxc-gpr", 
> > > > "syscon";
> > > > reg = <0x3034 0x1>;
> > > > };
> > > > @@ -424,27 +427,44 @@
> > > > #address-cells = <1>;
> > > > #size-cells = <1>;
> > > >
> > > > -   imx8mp_uid: unique-id@420 {
> > > > +   /*
> > > > +* The register address below maps to 
> > > > the MX8M
> > > > +* Fusemap Description Table entries 
> > > > this way.
> > > > +* Assuming
> > > > +*   reg = ;
> > > > +* then
> > > > +*   Fuse Address = (ADDR * 4) + 0x400
> > > > +* Note that if SIZE is greater than 4, 
> > > > then
> > > > +* each subsequent fuse is located at 
> > > > offset
> > > > +* +0x10 in Fusemap Description Table 
> > > > (e.g.
> > > > +* reg = <0x8 0x8> describes fuses 
> > > > 0x420 and
> > > > +* 0x430).
> > > > +*/
> > > > +   imx8mp_uid: unique-id@8 { /* 
> > > > 0x420-0x430 */
> > > > reg = <0x8 0x8>;
> > > > };
> > > >
> > > > -   cpu_speed_grade: speed-grade@10 {
> > > > +   cpu_speed_grade: speed-grade@10 { /* 
> > > > 0x440 */
> > > > reg = <0x10 4>;
> > > > };
> > > >
> > > > -   eth_mac1: mac-address@90 {
> > > > +   eth_mac1: mac-address@90 { /* 0x640 */
> > > > reg = <0x90 6>;
> > > > };
> > > >
> > > > -   eth_mac2: mac-address@96 {
> > > > +   eth_mac2: mac-address@96 { /* 0x658 */
> > > > reg = <0x96 6>;
> > > > };
> > > > +
> > > > +   tmu_calib: calib@264 { /* 0xd90-0xdc0 */
> > > > +   reg = <0x264 0x10>;
> > > > +   };
> > > > };
> > > >
> > > > -   anatop: anatop@3036 {
> > > > -   compatible = "fsl,imx8mp-anatop", 
> > > > "fsl,imx8mm-anatop",
> > > > -"syscon";
> > > > +   anatop: clock-controller@3036 {
> > > > +   compatible = "fsl,imx8mp-anatop", 
> > > > "fsl,imx8mm-anatop";
> > > > reg = <0x3036 0x1>;
> > > > +   

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Adam Ford]

On Fri, May 19, 2023 at 5:19 PM Tim Harvey  wrote:
>
> On Wed, May 3, 2023 at 9:11 AM Tim Harvey  wrote:
> >
> > On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam  wrote:
> > >
> > > From: Fabio Estevam 
> > >
> > > Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
> > >
> > > Signed-off-by: Fabio Estevam 
> > > ---
> > >  arch/arm/dts/imx8mp.dtsi | 374 ---
> > >  include/dt-bindings/clock/imx8mp-clock.h |  14 +-
> > >  2 files changed, 270 insertions(+), 118 deletions(-)
> > >
> > > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> > > index bb916a0948a8..a237275ee017 100644
> > > --- a/arch/arm/dts/imx8mp.dtsi
> > > +++ b/arch/arm/dts/imx8mp.dtsi
> > > @@ -123,6 +123,7 @@
> > >
> > > A53_L2: l2-cache0 {
> > > compatible = "cache";
> > > +   cache-unified;
> > > cache-level = <2>;
> > > cache-size = <0x8>;
> > > cache-line-size = <64>;
> > > @@ -379,6 +380,8 @@
> > > compatible = "fsl,imx8mp-tmu";
> > > reg = <0x3026 0x1>;
> > > clocks = < IMX8MP_CLK_TSENSOR_ROOT>;
> > > +   nvmem-cells = <_calib>;
> > > +   nvmem-cell-names = "calib";
> > > #thermal-sensor-cells = <1>;
> > > };
> > >
> > > @@ -411,7 +414,7 @@
> > > reg = <0x3033 0x1>;
> > > };
> > >
> > > -   gpr: iomuxc-gpr@3034 {
> > > +   gpr: syscon@3034 {
> > > compatible = "fsl,imx8mp-iomuxc-gpr", 
> > > "syscon";
> > > reg = <0x3034 0x1>;
> > > };
> > > @@ -424,27 +427,44 @@
> > > #address-cells = <1>;
> > > #size-cells = <1>;
> > >
> > > -   imx8mp_uid: unique-id@420 {
> > > +   /*
> > > +* The register address below maps to the 
> > > MX8M
> > > +* Fusemap Description Table entries this 
> > > way.
> > > +* Assuming
> > > +*   reg = ;
> > > +* then
> > > +*   Fuse Address = (ADDR * 4) + 0x400
> > > +* Note that if SIZE is greater than 4, 
> > > then
> > > +* each subsequent fuse is located at 
> > > offset
> > > +* +0x10 in Fusemap Description Table 
> > > (e.g.
> > > +* reg = <0x8 0x8> describes fuses 0x420 
> > > and
> > > +* 0x430).
> > > +*/
> > > +   imx8mp_uid: unique-id@8 { /* 0x420-0x430 
> > > */
> > > reg = <0x8 0x8>;
> > > };
> > >
> > > -   cpu_speed_grade: speed-grade@10 {
> > > +   cpu_speed_grade: speed-grade@10 { /* 
> > > 0x440 */
> > > reg = <0x10 4>;
> > > };
> > >
> > > -   eth_mac1: mac-address@90 {
> > > +   eth_mac1: mac-address@90 { /* 0x640 */
> > > reg = <0x90 6>;
> > > };
> > >
> > > -   eth_mac2: mac-address@96 {
> > > +   eth_mac2: mac-address@96 { /* 0x658 */
> > > reg = <0x96 6>;
> > > };
> > > +
> > > +   tmu_calib: calib@264 { /* 0xd90-0xdc0 */
> > > +   reg = <0x264 0x10>;
> > > +   };
> > > };
> > >
> > > -   anatop: anatop@3036 {
> > > -   compatible = "fsl,imx8mp-anatop", 
> > > "fsl,imx8mm-anatop",
> > > -"syscon";
> > > +   anatop: clock-controller@3036 {
> > > +   compatible = "fsl,imx8mp-anatop", 
> > > "fsl,imx8mm-anatop";
> > > reg = <0x3036 0x1>;
> > > +   #clock-cells = <1>;
> > > };
> > >
> > > snvs: snvs@3037 {
> > > @@ -523,6 +543,7 @@
> > > compatible = "fsl,imx8mp-gpc";
> > > reg = 

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Tim Harvey]

On Wed, May 3, 2023 at 9:11 AM Tim Harvey  wrote:
>
> On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam  wrote:
> >
> > From: Fabio Estevam 
> >
> > Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
> >
> > Signed-off-by: Fabio Estevam 
> > ---
> >  arch/arm/dts/imx8mp.dtsi | 374 ---
> >  include/dt-bindings/clock/imx8mp-clock.h |  14 +-
> >  2 files changed, 270 insertions(+), 118 deletions(-)
> >
> > diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> > index bb916a0948a8..a237275ee017 100644
> > --- a/arch/arm/dts/imx8mp.dtsi
> > +++ b/arch/arm/dts/imx8mp.dtsi
> > @@ -123,6 +123,7 @@
> >
> > A53_L2: l2-cache0 {
> > compatible = "cache";
> > +   cache-unified;
> > cache-level = <2>;
> > cache-size = <0x8>;
> > cache-line-size = <64>;
> > @@ -379,6 +380,8 @@
> > compatible = "fsl,imx8mp-tmu";
> > reg = <0x3026 0x1>;
> > clocks = < IMX8MP_CLK_TSENSOR_ROOT>;
> > +   nvmem-cells = <_calib>;
> > +   nvmem-cell-names = "calib";
> > #thermal-sensor-cells = <1>;
> > };
> >
> > @@ -411,7 +414,7 @@
> > reg = <0x3033 0x1>;
> > };
> >
> > -   gpr: iomuxc-gpr@3034 {
> > +   gpr: syscon@3034 {
> > compatible = "fsl,imx8mp-iomuxc-gpr", 
> > "syscon";
> > reg = <0x3034 0x1>;
> > };
> > @@ -424,27 +427,44 @@
> > #address-cells = <1>;
> > #size-cells = <1>;
> >
> > -   imx8mp_uid: unique-id@420 {
> > +   /*
> > +* The register address below maps to the 
> > MX8M
> > +* Fusemap Description Table entries this 
> > way.
> > +* Assuming
> > +*   reg = ;
> > +* then
> > +*   Fuse Address = (ADDR * 4) + 0x400
> > +* Note that if SIZE is greater than 4, then
> > +* each subsequent fuse is located at offset
> > +* +0x10 in Fusemap Description Table (e.g.
> > +* reg = <0x8 0x8> describes fuses 0x420 and
> > +* 0x430).
> > +*/
> > +   imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
> > reg = <0x8 0x8>;
> > };
> >
> > -   cpu_speed_grade: speed-grade@10 {
> > +   cpu_speed_grade: speed-grade@10 { /* 0x440 
> > */
> > reg = <0x10 4>;
> > };
> >
> > -   eth_mac1: mac-address@90 {
> > +   eth_mac1: mac-address@90 { /* 0x640 */
> > reg = <0x90 6>;
> > };
> >
> > -   eth_mac2: mac-address@96 {
> > +   eth_mac2: mac-address@96 { /* 0x658 */
> > reg = <0x96 6>;
> > };
> > +
> > +   tmu_calib: calib@264 { /* 0xd90-0xdc0 */
> > +   reg = <0x264 0x10>;
> > +   };
> > };
> >
> > -   anatop: anatop@3036 {
> > -   compatible = "fsl,imx8mp-anatop", 
> > "fsl,imx8mm-anatop",
> > -"syscon";
> > +   anatop: clock-controller@3036 {
> > +   compatible = "fsl,imx8mp-anatop", 
> > "fsl,imx8mm-anatop";
> > reg = <0x3036 0x1>;
> > +   #clock-cells = <1>;
> > };
> >
> > snvs: snvs@3037 {
> > @@ -523,6 +543,7 @@
> > compatible = "fsl,imx8mp-gpc";
> > reg = <0x303a 0x1000>;
> > interrupt-parent = <>;
> > +   interrupts =  > IRQ_TYPE_LEVEL_HIGH>;
> > interrupt-controller;
> > #interrupt-cells = <3>;
> >
> > @@ -589,7 +610,7 @@
> > 

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Tim Harvey]

On Thu, Apr 27, 2023 at 11:09 AM Fabio Estevam  wrote:
>
> From: Fabio Estevam 
>
> Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
>
> Signed-off-by: Fabio Estevam 
> ---
>  arch/arm/dts/imx8mp.dtsi | 374 ---
>  include/dt-bindings/clock/imx8mp-clock.h |  14 +-
>  2 files changed, 270 insertions(+), 118 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> index bb916a0948a8..a237275ee017 100644
> --- a/arch/arm/dts/imx8mp.dtsi
> +++ b/arch/arm/dts/imx8mp.dtsi
> @@ -123,6 +123,7 @@
>
> A53_L2: l2-cache0 {
> compatible = "cache";
> +   cache-unified;
> cache-level = <2>;
> cache-size = <0x8>;
> cache-line-size = <64>;
> @@ -379,6 +380,8 @@
> compatible = "fsl,imx8mp-tmu";
> reg = <0x3026 0x1>;
> clocks = < IMX8MP_CLK_TSENSOR_ROOT>;
> +   nvmem-cells = <_calib>;
> +   nvmem-cell-names = "calib";
> #thermal-sensor-cells = <1>;
> };
>
> @@ -411,7 +414,7 @@
> reg = <0x3033 0x1>;
> };
>
> -   gpr: iomuxc-gpr@3034 {
> +   gpr: syscon@3034 {
> compatible = "fsl,imx8mp-iomuxc-gpr", 
> "syscon";
> reg = <0x3034 0x1>;
> };
> @@ -424,27 +427,44 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> -   imx8mp_uid: unique-id@420 {
> +   /*
> +* The register address below maps to the MX8M
> +* Fusemap Description Table entries this way.
> +* Assuming
> +*   reg = ;
> +* then
> +*   Fuse Address = (ADDR * 4) + 0x400
> +* Note that if SIZE is greater than 4, then
> +* each subsequent fuse is located at offset
> +* +0x10 in Fusemap Description Table (e.g.
> +* reg = <0x8 0x8> describes fuses 0x420 and
> +* 0x430).
> +*/
> +   imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
> reg = <0x8 0x8>;
> };
>
> -   cpu_speed_grade: speed-grade@10 {
> +   cpu_speed_grade: speed-grade@10 { /* 0x440 */
> reg = <0x10 4>;
> };
>
> -   eth_mac1: mac-address@90 {
> +   eth_mac1: mac-address@90 { /* 0x640 */
> reg = <0x90 6>;
> };
>
> -   eth_mac2: mac-address@96 {
> +   eth_mac2: mac-address@96 { /* 0x658 */
> reg = <0x96 6>;
> };
> +
> +   tmu_calib: calib@264 { /* 0xd90-0xdc0 */
> +   reg = <0x264 0x10>;
> +   };
> };
>
> -   anatop: anatop@3036 {
> -   compatible = "fsl,imx8mp-anatop", 
> "fsl,imx8mm-anatop",
> -"syscon";
> +   anatop: clock-controller@3036 {
> +   compatible = "fsl,imx8mp-anatop", 
> "fsl,imx8mm-anatop";
> reg = <0x3036 0x1>;
> +   #clock-cells = <1>;
> };
>
> snvs: snvs@3037 {
> @@ -523,6 +543,7 @@
> compatible = "fsl,imx8mp-gpc";
> reg = <0x303a 0x1000>;
> interrupt-parent = <>;
> +   interrupts = ;
> interrupt-controller;
> #interrupt-cells = <3>;
>
> @@ -589,7 +610,7 @@
> reg = 
> ;
> };
>
> -   pgc_hsiomix: power-domains@17 {
> +   pgc_hsiomix: power-domain@17 {
> 

Re: [PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Adam Ford]

On Thu, Apr 27, 2023 at 1:09 PM Fabio Estevam  wrote:
>
> From: Fabio Estevam 
>
> Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.
>
> Signed-off-by: Fabio Estevam 
Reviewed-by: Adam Ford 
> ---
>  arch/arm/dts/imx8mp.dtsi | 374 ---
>  include/dt-bindings/clock/imx8mp-clock.h |  14 +-
>  2 files changed, 270 insertions(+), 118 deletions(-)
>
> diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
> index bb916a0948a8..a237275ee017 100644
> --- a/arch/arm/dts/imx8mp.dtsi
> +++ b/arch/arm/dts/imx8mp.dtsi
> @@ -123,6 +123,7 @@
>
> A53_L2: l2-cache0 {
> compatible = "cache";
> +   cache-unified;
> cache-level = <2>;
> cache-size = <0x8>;
> cache-line-size = <64>;
> @@ -379,6 +380,8 @@
> compatible = "fsl,imx8mp-tmu";
> reg = <0x3026 0x1>;
> clocks = < IMX8MP_CLK_TSENSOR_ROOT>;
> +   nvmem-cells = <_calib>;
> +   nvmem-cell-names = "calib";
> #thermal-sensor-cells = <1>;
> };
>
> @@ -411,7 +414,7 @@
> reg = <0x3033 0x1>;
> };
>
> -   gpr: iomuxc-gpr@3034 {
> +   gpr: syscon@3034 {
> compatible = "fsl,imx8mp-iomuxc-gpr", 
> "syscon";
> reg = <0x3034 0x1>;
> };
> @@ -424,27 +427,44 @@
> #address-cells = <1>;
> #size-cells = <1>;
>
> -   imx8mp_uid: unique-id@420 {
> +   /*
> +* The register address below maps to the MX8M
> +* Fusemap Description Table entries this way.
> +* Assuming
> +*   reg = ;
> +* then
> +*   Fuse Address = (ADDR * 4) + 0x400
> +* Note that if SIZE is greater than 4, then
> +* each subsequent fuse is located at offset
> +* +0x10 in Fusemap Description Table (e.g.
> +* reg = <0x8 0x8> describes fuses 0x420 and
> +* 0x430).
> +*/
> +   imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
> reg = <0x8 0x8>;
> };
>
> -   cpu_speed_grade: speed-grade@10 {
> +   cpu_speed_grade: speed-grade@10 { /* 0x440 */
> reg = <0x10 4>;
> };
>
> -   eth_mac1: mac-address@90 {
> +   eth_mac1: mac-address@90 { /* 0x640 */
> reg = <0x90 6>;
> };
>
> -   eth_mac2: mac-address@96 {
> +   eth_mac2: mac-address@96 { /* 0x658 */
> reg = <0x96 6>;
> };
> +
> +   tmu_calib: calib@264 { /* 0xd90-0xdc0 */
> +   reg = <0x264 0x10>;
> +   };
> };
>
> -   anatop: anatop@3036 {
> -   compatible = "fsl,imx8mp-anatop", 
> "fsl,imx8mm-anatop",
> -"syscon";
> +   anatop: clock-controller@3036 {
> +   compatible = "fsl,imx8mp-anatop", 
> "fsl,imx8mm-anatop";
> reg = <0x3036 0x1>;
> +   #clock-cells = <1>;
> };
>
> snvs: snvs@3037 {
> @@ -523,6 +543,7 @@
> compatible = "fsl,imx8mp-gpc";
> reg = <0x303a 0x1000>;
> interrupt-parent = <>;
> +   interrupts = ;
> interrupt-controller;
> #interrupt-cells = <3>;
>
> @@ -589,7 +610,7 @@
> reg = 
> ;
> };
>
> -   pgc_hsiomix: power-domains@17 {
> +   pgc_hsiomix: power-domain@17 {
>   

[PATCH 3/3] arm: dts: imx8mp: Sync with Linux 6.3

[Fabio Estevam]

From: Fabio Estevam 

Sync imx8mp.dtsi and imx8mp-clock.h with Linux 6.3.

Signed-off-by: Fabio Estevam 
---
 arch/arm/dts/imx8mp.dtsi | 374 ---
 include/dt-bindings/clock/imx8mp-clock.h |  14 +-
 2 files changed, 270 insertions(+), 118 deletions(-)

diff --git a/arch/arm/dts/imx8mp.dtsi b/arch/arm/dts/imx8mp.dtsi
index bb916a0948a8..a237275ee017 100644
--- a/arch/arm/dts/imx8mp.dtsi
+++ b/arch/arm/dts/imx8mp.dtsi
@@ -123,6 +123,7 @@
 
A53_L2: l2-cache0 {
compatible = "cache";
+   cache-unified;
cache-level = <2>;
cache-size = <0x8>;
cache-line-size = <64>;
@@ -379,6 +380,8 @@
compatible = "fsl,imx8mp-tmu";
reg = <0x3026 0x1>;
clocks = < IMX8MP_CLK_TSENSOR_ROOT>;
+   nvmem-cells = <_calib>;
+   nvmem-cell-names = "calib";
#thermal-sensor-cells = <1>;
};
 
@@ -411,7 +414,7 @@
reg = <0x3033 0x1>;
};
 
-   gpr: iomuxc-gpr@3034 {
+   gpr: syscon@3034 {
compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
reg = <0x3034 0x1>;
};
@@ -424,27 +427,44 @@
#address-cells = <1>;
#size-cells = <1>;
 
-   imx8mp_uid: unique-id@420 {
+   /*
+* The register address below maps to the MX8M
+* Fusemap Description Table entries this way.
+* Assuming
+*   reg = ;
+* then
+*   Fuse Address = (ADDR * 4) + 0x400
+* Note that if SIZE is greater than 4, then
+* each subsequent fuse is located at offset
+* +0x10 in Fusemap Description Table (e.g.
+* reg = <0x8 0x8> describes fuses 0x420 and
+* 0x430).
+*/
+   imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
reg = <0x8 0x8>;
};
 
-   cpu_speed_grade: speed-grade@10 {
+   cpu_speed_grade: speed-grade@10 { /* 0x440 */
reg = <0x10 4>;
};
 
-   eth_mac1: mac-address@90 {
+   eth_mac1: mac-address@90 { /* 0x640 */
reg = <0x90 6>;
};
 
-   eth_mac2: mac-address@96 {
+   eth_mac2: mac-address@96 { /* 0x658 */
reg = <0x96 6>;
};
+
+   tmu_calib: calib@264 { /* 0xd90-0xdc0 */
+   reg = <0x264 0x10>;
+   };
};
 
-   anatop: anatop@3036 {
-   compatible = "fsl,imx8mp-anatop", 
"fsl,imx8mm-anatop",
-"syscon";
+   anatop: clock-controller@3036 {
+   compatible = "fsl,imx8mp-anatop", 
"fsl,imx8mm-anatop";
reg = <0x3036 0x1>;
+   #clock-cells = <1>;
};
 
snvs: snvs@3037 {
@@ -523,6 +543,7 @@
compatible = "fsl,imx8mp-gpc";
reg = <0x303a 0x1000>;
interrupt-parent = <>;
+   interrupts = ;
interrupt-controller;
#interrupt-cells = <3>;
 
@@ -589,7 +610,7 @@
reg = 
;
};
 
-   pgc_hsiomix: power-domains@17 {
+   pgc_hsiomix: power-domain@17 {
#power-domain-cells = <0>;
reg = 
;
clocks = < 
IMX8MP_CLK_HSIO_AXI>,
@@ -631,6 +652,14 @@
reg = 
;