Re: [PATCH 4/9] stm32mp1: clk: configure pll1 with OPP
Hi Patrick
On 4/21/20 5:11 PM, Patrick Delaunay wrote:
> The PLL1 node (st,pll1) is optional in device tree, the max supported
> frequency define in OPP node is used when the node is absent.
>
> Signed-off-by: Patrick Delaunay
> ---
>
> .../clock/st,stm32mp1.txt | 4 +
> drivers/clk/clk_stm32mp1.c| 290 --
> 2 files changed, 266 insertions(+), 28 deletions(-)
>
> diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt
> b/doc/device-tree-bindings/clock/st,stm32mp1.txt
> index a3d427911d..4d4136d2fc 100644
> --- a/doc/device-tree-bindings/clock/st,stm32mp1.txt
> +++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
> @@ -87,6 +87,10 @@ Optional Properties:
>are listed with associated reg 0 to 3.
>PLLx is off when the associated node is absent or deactivated.
>
> + For PLL1, when the node is absent, the frequency of the OPP node is used
> + to compute the PLL setting (see compatible "operating-points-v2" in
> + opp/opp.txt for details).
> +
>Here are the available properties for each PLL node:
> - compatible: should be "st,stm32mp1-pll"
>
> diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
> index 50df8425bf..baacc1abb5 100644
> --- a/drivers/clk/clk_stm32mp1.c
> +++ b/drivers/clk/clk_stm32mp1.c
> @@ -14,6 +14,7 @@
> #include
> #include
> #include
> +#include
> #include
> #include
>
> @@ -641,8 +642,18 @@ static const struct stm32mp1_clk_sel
> stm32mp1_clk_sel[_PARENT_SEL_NB] = {
> };
>
> #ifdef STM32MP1_CLOCK_TREE_INIT
> +
> /* define characteristic of PLL according type */
> +#define DIVM_MIN 0
> +#define DIVM_MAX 63
> #define DIVN_MIN 24
> +#define DIVP_MIN 0
> +#define DIVP_MAX 127
> +#define FRAC_MAX 8192
> +
> +#define PLL1600_VCO_MIN 8
> +#define PLL1600_VCO_MAX 16
> +
> static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
> [PLL_800] = {
> .refclk_min = 4,
> @@ -1186,6 +1197,208 @@ static ulong stm32mp1_clk_get_rate(struct clk *clk)
> }
>
> #ifdef STM32MP1_CLOCK_TREE_INIT
> +
> +bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
> +{
> + unsigned int id;
> +
> + switch (opp_id) {
> + case 1:
> + case 2:
> + id = opp_id;
> + break;
> + default:
> + id = 1; /* default value */
> + break;
> + }
> +
> + switch (cpu_type) {
> + case CPU_STM32MP157Fxx:
> + case CPU_STM32MP157Dxx:
> + case CPU_STM32MP153Fxx:
> + case CPU_STM32MP153Dxx:
> + case CPU_STM32MP151Fxx:
> + case CPU_STM32MP151Dxx:
> + return true;
> + default:
> + return id == 1;
> + }
> +}
> +
> +/*
> + * gets OPP parameters (frequency in KHz and voltage in mV) from
> + * an OPP table subnode. Platform HW support capabilities are also checked.
> + * Returns 0 on success and a negative FDT error code on failure.
> + */
> +static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
> + u32 *freq_khz, u32 *voltage_mv)
> +{
> + u32 opp_hw;
> + u64 read_freq_64;
> + u32 read_voltage_32;
> +
> + *freq_khz = 0;
> + *voltage_mv = 0;
> +
> + opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
> + if (opp_hw)
> + if (!stm32mp1_supports_opp(opp_hw, cpu_type))
> + return -FDT_ERR_BADVALUE;
> +
> + read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
> +1000ULL;
> + read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
> + 1000U;
> +
> + if (!read_voltage_32 || !read_freq_64)
> + return -FDT_ERR_NOTFOUND;
> +
> + /* Frequency value expressed in KHz must fit on 32 bits */
> + if (read_freq_64 > U32_MAX)
> + return -FDT_ERR_BADVALUE;
> +
> + /* Millivolt value must fit on 16 bits */
> + if (read_voltage_32 > U16_MAX)
> + return -FDT_ERR_BADVALUE;
> +
> + *freq_khz = (u32)read_freq_64;
> + *voltage_mv = read_voltage_32;
> +
> + return 0;
> +}
> +
> +/*
> + * parses OPP table in DT and finds the parameters for the
> + * highest frequency supported by the HW platform.
> + * Returns 0 on success and a negative FDT error code on failure.
> + */
> +int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
> +{
> + ofnode node, subnode;
> + int ret;
> + u32 freq = 0U, voltage = 0U;
> + u32 cpu_type = get_cpu_type();
> +
> + node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
> + if (!ofnode_valid(node))
> + return -FDT_ERR_NOTFOUND;
> +
> + ofnode_for_each_subnode(subnode, node) {
> + unsigned int read_freq;
> + unsigned int read_voltage;
> +
> + ret = stm32mp1_get_opp(cpu_type, subnode,
> +_freq, _voltage);
> + if (ret)
> +
[PATCH 4/9] stm32mp1: clk: configure pll1 with OPP
The PLL1 node (st,pll1) is optional in device tree, the max supported
frequency define in OPP node is used when the node is absent.
Signed-off-by: Patrick Delaunay
---
.../clock/st,stm32mp1.txt | 4 +
drivers/clk/clk_stm32mp1.c| 290 --
2 files changed, 266 insertions(+), 28 deletions(-)
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt
b/doc/device-tree-bindings/clock/st,stm32mp1.txt
index a3d427911d..4d4136d2fc 100644
--- a/doc/device-tree-bindings/clock/st,stm32mp1.txt
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -87,6 +87,10 @@ Optional Properties:
are listed with associated reg 0 to 3.
PLLx is off when the associated node is absent or deactivated.
+ For PLL1, when the node is absent, the frequency of the OPP node is used
+ to compute the PLL setting (see compatible "operating-points-v2" in
+ opp/opp.txt for details).
+
Here are the available properties for each PLL node:
- compatible: should be "st,stm32mp1-pll"
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 50df8425bf..baacc1abb5 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -14,6 +14,7 @@
#include
#include
#include
+#include
#include
#include
@@ -641,8 +642,18 @@ static const struct stm32mp1_clk_sel
stm32mp1_clk_sel[_PARENT_SEL_NB] = {
};
#ifdef STM32MP1_CLOCK_TREE_INIT
+
/* define characteristic of PLL according type */
+#define DIVM_MIN 0
+#define DIVM_MAX 63
#define DIVN_MIN 24
+#define DIVP_MIN 0
+#define DIVP_MAX 127
+#define FRAC_MAX 8192
+
+#define PLL1600_VCO_MIN8
+#define PLL1600_VCO_MAX16
+
static const struct stm32mp1_pll stm32mp1_pll[PLL_TYPE_NB] = {
[PLL_800] = {
.refclk_min = 4,
@@ -1186,6 +1197,208 @@ static ulong stm32mp1_clk_get_rate(struct clk *clk)
}
#ifdef STM32MP1_CLOCK_TREE_INIT
+
+bool stm32mp1_supports_opp(u32 opp_id, u32 cpu_type)
+{
+ unsigned int id;
+
+ switch (opp_id) {
+ case 1:
+ case 2:
+ id = opp_id;
+ break;
+ default:
+ id = 1; /* default value */
+ break;
+ }
+
+ switch (cpu_type) {
+ case CPU_STM32MP157Fxx:
+ case CPU_STM32MP157Dxx:
+ case CPU_STM32MP153Fxx:
+ case CPU_STM32MP153Dxx:
+ case CPU_STM32MP151Fxx:
+ case CPU_STM32MP151Dxx:
+ return true;
+ default:
+ return id == 1;
+ }
+}
+
+/*
+ * gets OPP parameters (frequency in KHz and voltage in mV) from
+ * an OPP table subnode. Platform HW support capabilities are also checked.
+ * Returns 0 on success and a negative FDT error code on failure.
+ */
+static int stm32mp1_get_opp(u32 cpu_type, ofnode subnode,
+ u32 *freq_khz, u32 *voltage_mv)
+{
+ u32 opp_hw;
+ u64 read_freq_64;
+ u32 read_voltage_32;
+
+ *freq_khz = 0;
+ *voltage_mv = 0;
+
+ opp_hw = ofnode_read_u32_default(subnode, "opp-supported-hw", 0);
+ if (opp_hw)
+ if (!stm32mp1_supports_opp(opp_hw, cpu_type))
+ return -FDT_ERR_BADVALUE;
+
+ read_freq_64 = ofnode_read_u64_default(subnode, "opp-hz", 0) /
+ 1000ULL;
+ read_voltage_32 = ofnode_read_u32_default(subnode, "opp-microvolt", 0) /
+ 1000U;
+
+ if (!read_voltage_32 || !read_freq_64)
+ return -FDT_ERR_NOTFOUND;
+
+ /* Frequency value expressed in KHz must fit on 32 bits */
+ if (read_freq_64 > U32_MAX)
+ return -FDT_ERR_BADVALUE;
+
+ /* Millivolt value must fit on 16 bits */
+ if (read_voltage_32 > U16_MAX)
+ return -FDT_ERR_BADVALUE;
+
+ *freq_khz = (u32)read_freq_64;
+ *voltage_mv = read_voltage_32;
+
+ return 0;
+}
+
+/*
+ * parses OPP table in DT and finds the parameters for the
+ * highest frequency supported by the HW platform.
+ * Returns 0 on success and a negative FDT error code on failure.
+ */
+int stm32mp1_get_max_opp_freq(struct stm32mp1_clk_priv *priv, u64 *freq_hz)
+{
+ ofnode node, subnode;
+ int ret;
+ u32 freq = 0U, voltage = 0U;
+ u32 cpu_type = get_cpu_type();
+
+ node = ofnode_by_compatible(ofnode_null(), "operating-points-v2");
+ if (!ofnode_valid(node))
+ return -FDT_ERR_NOTFOUND;
+
+ ofnode_for_each_subnode(subnode, node) {
+ unsigned int read_freq;
+ unsigned int read_voltage;
+
+ ret = stm32mp1_get_opp(cpu_type, subnode,
+ _freq, _voltage);
+ if (ret)
+ continue;
+
+ if (read_freq > freq) {
+ freq = read_freq;
+ voltage = read_voltage;
+ }
+ }
+
+ if (!freq || !voltage)
+
