Re: [PATCH 5/7] ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY
On 2023/4/17 17:19, Eugen Hristev wrote:
From: Joseph Chen
Add the node for pciE 2x1l 2 device together with the corresponding
combphy.
Signed-off-by: Joseph Chen
[eugen.hris...@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev
---
arch/arm/dts/rk3588s-u-boot.dtsi | 73
1 file changed, 73 insertions(+)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index f23112bf7ab6..17348c8f9789 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include "rockchip-u-boot.dtsi"
+#include
/ {
dmc {
@@ -58,6 +59,11 @@
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
+ pipe_phy0_grf: syscon@fd5bc000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5bc000 0x0 0x100>;
+ };
+
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
@@ -104,6 +110,58 @@
};
};
+ pcie2x1l2: pcie@fe19 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
The mainline kernel should have this node, we should sync with kernel?
Thanks,
- Kever
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x40 0x4f>;
+ clocks = < ACLK_PCIE_1L2_MSTR>, < ACLK_PCIE_1L2_SLV>,
+< ACLK_PCIE_1L2_DBI>, < PCLK_PCIE_1L2>,
+< CLK_PCIE_AUX4>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+ device_type = "pci";
+ interrupts = ,
+,
+,
+,
+;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 _intc 0>,
+ <0 0 0 2 _intc 1>,
+ <0 0 0 3 _intc 2>,
+ <0 0 0 4 _intc 3>;
+ linux,pci-domain = <4>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ max-link-speed = <2>;
+ msi-map = <0x4000 0x4000 0x1000>;
+ num-lanes = <1>;
+ phys = <_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = < RK3588_PD_PHP>;
+ ranges = <0x0800 0x0 0xf400 0x0 0xf400 0x0 0x10
+ 0x8100 0x0 0xf410 0x0 0xf410 0x0 0x10
+ 0x8200 0x0 0xf420 0x0 0xf420 0x0 0xe0
+ 0xc300 0xa 0x 0xa 0x 0x0
0x4000>;
+ reg = <0xa 0x4100 0x0 0x40>,
+ <0x0 0xfe19 0x0 0x1>;
+ reg-names = "pcie-dbi", "pcie-apb";
+ resets = < SRST_PCIE4_POWER_UP>;
+ reset-names = "pipe";
+ status = "disabled";
+
+ pcie2x1l2_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <>;
+ interrupts = ;
+ };
+ };
+
sfc: spi@fe2b {
compatible = "rockchip,sfc";
reg = <0x0 0xfe2b 0x0 0x4000>;
@@ -128,6 +186,21 @@
reg = <0x07 0x10>;
};
};
+
+ combphy0_ps: phy@fee0 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee0 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = < CLK_REF_PIPE_PHY0>, <
PCLK_PCIE_COMBO_PIPE_PHY0>;
+ clock-names = "refclk", "apbclk";
+ assigned-clocks = < CLK_REF_PIPE_PHY0>;
+ assigned-clock-rates = <1>;
+ resets = < SRST_P_PCIE2_PHY0>, < SRST_REF_PIPE_PHY0>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <_grf>;
+ rockchip,pipe-phy-grf = <_phy0_grf>;
+ status = "disabled";
+ };
};
{
Re: [PATCH 5/7] ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY
On 2023-04-18 22:54, Jonas Karlman wrote:
> Hi Eugen,
>
> On 2023-04-17 11:19, Eugen Hristev wrote:
>> From: Joseph Chen
>>
>> Add the node for pciE 2x1l 2 device together with the corresponding
>> combphy.
>>
>> Signed-off-by: Joseph Chen
>> [eugen.hris...@collabora.com: moved to -u-boot.dtsi, minor
>> adaptations]
>> Signed-off-by: Eugen Hristev
>> ---
>> arch/arm/dts/rk3588s-u-boot.dtsi | 73
>> 1 file changed, 73 insertions(+)
>>
>> diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi
>> b/arch/arm/dts/rk3588s-u-boot.dtsi
>> index f23112bf7ab6..17348c8f9789 100644
>> --- a/arch/arm/dts/rk3588s-u-boot.dtsi
>> +++ b/arch/arm/dts/rk3588s-u-boot.dtsi
>> @@ -4,6 +4,7 @@
>> */
>>
>> #include "rockchip-u-boot.dtsi"
>> +#include
>>
>> / {
>> dmc {
>> @@ -58,6 +59,11 @@
>> reg = <0x0 0xfd58a000 0x0 0x2000>;
>> };
>>
>> +pipe_phy0_grf: syscon@fd5bc000 {
>> +compatible = "rockchip,pipe-phy-grf", "syscon";
>> +reg = <0x0 0xfd5bc000 0x0 0x100>;
>> +};
>> +
>> usb2phy2_grf: syscon@fd5d8000 {
>> compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
>> "simple-mfd";
>> @@ -104,6 +110,58 @@
>> };
>> };
>>
>> +pcie2x1l2: pcie@fe19 {
>> +compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
>> +#address-cells = <3>;
>> +#size-cells = <2>;
>> +bus-range = <0x40 0x4f>;
>> +clocks = < ACLK_PCIE_1L2_MSTR>, < ACLK_PCIE_1L2_SLV>,
>> + < ACLK_PCIE_1L2_DBI>, < PCLK_PCIE_1L2>,
>> + < CLK_PCIE_AUX4>;
>> +clock-names = "aclk_mst", "aclk_slv",
>> + "aclk_dbi", "pclk", "aux";
>> +device_type = "pci";
>> +interrupts = ,
>> + ,
>> + ,
>> + ,
>> + ;
>> +interrupt-names = "sys", "pmc", "msg", "legacy", "err";
>> +#interrupt-cells = <1>;
>> +interrupt-map-mask = <0 0 0 7>;
>> +interrupt-map = <0 0 0 1 _intc 0>,
>> +<0 0 0 2 _intc 1>,
>> +<0 0 0 3 _intc 2>,
>> +<0 0 0 4 _intc 3>;
>> +linux,pci-domain = <4>;
>> +num-ib-windows = <8>;
>> +num-ob-windows = <8>;
>> +max-link-speed = <2>;
>> +msi-map = <0x4000 0x4000 0x1000>;
>> +num-lanes = <1>;
>> +phys = <_ps PHY_TYPE_PCIE>;
>> +phy-names = "pcie-phy";
>> +power-domains = < RK3588_PD_PHP>;
>> +ranges = <0x0800 0x0 0xf400 0x0 0xf400 0x0 0x10
>> + 0x8100 0x0 0xf410 0x0 0xf410 0x0 0x10
>> + 0x8200 0x0 0xf420 0x0 0xf420 0x0 0xe0
>> + 0xc300 0xa 0x 0xa 0x 0x0
>> 0x4000>;
>> +reg = <0xa 0x4100 0x0 0x40>,
>> + <0x0 0xfe19 0x0 0x1>;
>> +reg-names = "pcie-dbi", "pcie-apb";
>
> These reg-names are not fully compatible with the mainline linux binding
> for the rk3568 variant, see [1]. Please use the reg-names as defined in
> the mainline binding: dbi and apb.
>
> In a pending patch to fix pcie/nvme on rk3568 I am planing to change to
> get reg addr by name instead of index, as part of the fix to use correct
> cfg_base.
I tested this series together with work-in-progress patches for rk3568,
see [1], still an issue with BARs from the RC claiming the entire memory
region to work around on rk3568.
Made small fixups for this series to base the device tree node on
mainline node at [3]. I also made a small adjustment to the ranges so
that the memory region falls within a 32-bit address space.
Please feel free to squash the fixups if you agree with them :-)
On my ROCK 5 Model B:
=> pci enum
PCI Autoconfig: Bus Memory region: [4000-7fff],
Physical Memory [a-a3fff]
PCI Autoconfig: Bus I/O region: [f410-f41f],
Physical Memory [f410-f41f]
PCI Autoconfig: ROM, size=0x1, address=0x4000 bus_lower=0x4001
PCI Autoconfig: BAR 0, I/O, size=0x100, address=0xf410
bus_lower=0xf4100100
PCI Autoconfig: BAR 1, Mem64, size=0x1, address=0x4010
bus_lower=0x4011
PCI Autoconfig: BAR 2, Mem64, size=0x4000, address=0x4011
bus_lower=0x40114000
=> pci
BusDevFun VendorId DeviceId Device Class Sub-Class
_
00.00.00 0x1d87 0x3588 Bridge device 0x04
01.00.00 0x10ec 0x8125 Network controller 0x00
[2] https://github.com/Kwiboo/u-boot-rockchip/commits/rk3568-pcie-v1
[3]
Re: [PATCH 5/7] ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY
Hi Eugen,
On 2023-04-17 11:19, Eugen Hristev wrote:
> From: Joseph Chen
>
> Add the node for pciE 2x1l 2 device together with the corresponding
> combphy.
>
> Signed-off-by: Joseph Chen
> [eugen.hris...@collabora.com: moved to -u-boot.dtsi, minor
> adaptations]
> Signed-off-by: Eugen Hristev
> ---
> arch/arm/dts/rk3588s-u-boot.dtsi | 73
> 1 file changed, 73 insertions(+)
>
> diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi
> b/arch/arm/dts/rk3588s-u-boot.dtsi
> index f23112bf7ab6..17348c8f9789 100644
> --- a/arch/arm/dts/rk3588s-u-boot.dtsi
> +++ b/arch/arm/dts/rk3588s-u-boot.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include "rockchip-u-boot.dtsi"
> +#include
>
> / {
> dmc {
> @@ -58,6 +59,11 @@
> reg = <0x0 0xfd58a000 0x0 0x2000>;
> };
>
> + pipe_phy0_grf: syscon@fd5bc000 {
> + compatible = "rockchip,pipe-phy-grf", "syscon";
> + reg = <0x0 0xfd5bc000 0x0 0x100>;
> + };
> +
> usb2phy2_grf: syscon@fd5d8000 {
> compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
>"simple-mfd";
> @@ -104,6 +110,58 @@
> };
> };
>
> + pcie2x1l2: pcie@fe19 {
> + compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + bus-range = <0x40 0x4f>;
> + clocks = < ACLK_PCIE_1L2_MSTR>, < ACLK_PCIE_1L2_SLV>,
> + < ACLK_PCIE_1L2_DBI>, < PCLK_PCIE_1L2>,
> + < CLK_PCIE_AUX4>;
> + clock-names = "aclk_mst", "aclk_slv",
> + "aclk_dbi", "pclk", "aux";
> + device_type = "pci";
> + interrupts = ,
> + ,
> + ,
> + ,
> + ;
> + interrupt-names = "sys", "pmc", "msg", "legacy", "err";
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0 0 0 1 _intc 0>,
> + <0 0 0 2 _intc 1>,
> + <0 0 0 3 _intc 2>,
> + <0 0 0 4 _intc 3>;
> + linux,pci-domain = <4>;
> + num-ib-windows = <8>;
> + num-ob-windows = <8>;
> + max-link-speed = <2>;
> + msi-map = <0x4000 0x4000 0x1000>;
> + num-lanes = <1>;
> + phys = <_ps PHY_TYPE_PCIE>;
> + phy-names = "pcie-phy";
> + power-domains = < RK3588_PD_PHP>;
> + ranges = <0x0800 0x0 0xf400 0x0 0xf400 0x0 0x10
> + 0x8100 0x0 0xf410 0x0 0xf410 0x0 0x10
> + 0x8200 0x0 0xf420 0x0 0xf420 0x0 0xe0
> + 0xc300 0xa 0x 0xa 0x 0x0
> 0x4000>;
> + reg = <0xa 0x4100 0x0 0x40>,
> + <0x0 0xfe19 0x0 0x1>;
> + reg-names = "pcie-dbi", "pcie-apb";
These reg-names are not fully compatible with the mainline linux binding
for the rk3568 variant, see [1]. Please use the reg-names as defined in
the mainline binding: dbi and apb.
In a pending patch to fix pcie/nvme on rk3568 I am planing to change to
get reg addr by name instead of index, as part of the fix to use correct
cfg_base.
[1]
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml#n37
Regards,
Jonas
> + resets = < SRST_PCIE4_POWER_UP>;
> + reset-names = "pipe";
> + status = "disabled";
> +
> + pcie2x1l2_intc: legacy-interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + interrupt-parent = <>;
> + interrupts = ;
> + };
> + };
> +
> sfc: spi@fe2b {
> compatible = "rockchip,sfc";
> reg = <0x0 0xfe2b 0x0 0x4000>;
> @@ -128,6 +186,21 @@
> reg = <0x07 0x10>;
> };
> };
> +
> + combphy0_ps: phy@fee0 {
> + compatible = "rockchip,rk3588-naneng-combphy";
> + reg = <0x0 0xfee0 0x0 0x100>;
> + #phy-cells = <1>;
> + clocks = < CLK_REF_PIPE_PHY0>, <
> PCLK_PCIE_COMBO_PIPE_PHY0>;
> + clock-names = "refclk", "apbclk";
> + assigned-clocks = < CLK_REF_PIPE_PHY0>;
> + assigned-clock-rates = <1>;
> + resets = < SRST_P_PCIE2_PHY0>, < SRST_REF_PIPE_PHY0>;
> + reset-names = "combphy-apb", "combphy";
> + rockchip,pipe-grf = <_grf>;
> + rockchip,pipe-phy-grf = <_phy0_grf>;
> + status = "disabled";
> + };
> };
>
> {
[PATCH 5/7] ARM: dts: rockchip: rk3588s-u-boot: add pcie2x1l2 with PHY
From: Joseph Chen
Add the node for pciE 2x1l 2 device together with the corresponding
combphy.
Signed-off-by: Joseph Chen
[eugen.hris...@collabora.com: moved to -u-boot.dtsi, minor
adaptations]
Signed-off-by: Eugen Hristev
---
arch/arm/dts/rk3588s-u-boot.dtsi | 73
1 file changed, 73 insertions(+)
diff --git a/arch/arm/dts/rk3588s-u-boot.dtsi b/arch/arm/dts/rk3588s-u-boot.dtsi
index f23112bf7ab6..17348c8f9789 100644
--- a/arch/arm/dts/rk3588s-u-boot.dtsi
+++ b/arch/arm/dts/rk3588s-u-boot.dtsi
@@ -4,6 +4,7 @@
*/
#include "rockchip-u-boot.dtsi"
+#include
/ {
dmc {
@@ -58,6 +59,11 @@
reg = <0x0 0xfd58a000 0x0 0x2000>;
};
+ pipe_phy0_grf: syscon@fd5bc000 {
+ compatible = "rockchip,pipe-phy-grf", "syscon";
+ reg = <0x0 0xfd5bc000 0x0 0x100>;
+ };
+
usb2phy2_grf: syscon@fd5d8000 {
compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
"simple-mfd";
@@ -104,6 +110,58 @@
};
};
+ pcie2x1l2: pcie@fe19 {
+ compatible = "rockchip,rk3588-pcie", "snps,dw-pcie";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ bus-range = <0x40 0x4f>;
+ clocks = < ACLK_PCIE_1L2_MSTR>, < ACLK_PCIE_1L2_SLV>,
+< ACLK_PCIE_1L2_DBI>, < PCLK_PCIE_1L2>,
+< CLK_PCIE_AUX4>;
+ clock-names = "aclk_mst", "aclk_slv",
+ "aclk_dbi", "pclk", "aux";
+ device_type = "pci";
+ interrupts = ,
+,
+,
+,
+;
+ interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0 0 0 1 _intc 0>,
+ <0 0 0 2 _intc 1>,
+ <0 0 0 3 _intc 2>,
+ <0 0 0 4 _intc 3>;
+ linux,pci-domain = <4>;
+ num-ib-windows = <8>;
+ num-ob-windows = <8>;
+ max-link-speed = <2>;
+ msi-map = <0x4000 0x4000 0x1000>;
+ num-lanes = <1>;
+ phys = <_ps PHY_TYPE_PCIE>;
+ phy-names = "pcie-phy";
+ power-domains = < RK3588_PD_PHP>;
+ ranges = <0x0800 0x0 0xf400 0x0 0xf400 0x0 0x10
+ 0x8100 0x0 0xf410 0x0 0xf410 0x0 0x10
+ 0x8200 0x0 0xf420 0x0 0xf420 0x0 0xe0
+ 0xc300 0xa 0x 0xa 0x 0x0
0x4000>;
+ reg = <0xa 0x4100 0x0 0x40>,
+ <0x0 0xfe19 0x0 0x1>;
+ reg-names = "pcie-dbi", "pcie-apb";
+ resets = < SRST_PCIE4_POWER_UP>;
+ reset-names = "pipe";
+ status = "disabled";
+
+ pcie2x1l2_intc: legacy-interrupt-controller {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-parent = <>;
+ interrupts = ;
+ };
+ };
+
sfc: spi@fe2b {
compatible = "rockchip,sfc";
reg = <0x0 0xfe2b 0x0 0x4000>;
@@ -128,6 +186,21 @@
reg = <0x07 0x10>;
};
};
+
+ combphy0_ps: phy@fee0 {
+ compatible = "rockchip,rk3588-naneng-combphy";
+ reg = <0x0 0xfee0 0x0 0x100>;
+ #phy-cells = <1>;
+ clocks = < CLK_REF_PIPE_PHY0>, <
PCLK_PCIE_COMBO_PIPE_PHY0>;
+ clock-names = "refclk", "apbclk";
+ assigned-clocks = < CLK_REF_PIPE_PHY0>;
+ assigned-clock-rates = <1>;
+ resets = < SRST_P_PCIE2_PHY0>, < SRST_REF_PIPE_PHY0>;
+ reset-names = "combphy-apb", "combphy";
+ rockchip,pipe-grf = <_grf>;
+ rockchip,pipe-phy-grf = <_phy0_grf>;
+ status = "disabled";
+ };
};
{
--
2.34.1
