Re: [PATCH 6/7] arm: mvebu: Add RD-AC5X board
On Fri, 16 Sep 2022, 10:58 PM Pali Rohár, wrote:
> On Friday 16 September 2022 16:54:22 Chris Packham wrote:
> > +&spi0 {
> > + status = "okay";
> > +
> > + spiflash0: flash@0 {
> > + compatible = "jedec,spi-nor";
> > + spi-max-frequency = <5000>;
> > + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> > + reg = <0>;
> > +
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + partition@0 {
> > + label = "spi_flash_part0";
>
> I guess such label is useless. There is something stored, so it would be
> a wise idea to put there correct label. I do not know how it is on this
> platform, but on A3720 at offset 0 is "firmware", which consist of CM3
> part, A53 part and U-Boot. It is not even U-Boot itself.
>
These are the names from the Linux SDK for the board. The first part will
be the bootloader (mvddr+atf+u-boot). Somewhere in there is also the u-boot
environment. I'm tempted just to drop the partitions altogether, they don't
do anything useful for u-boot.
>
> > + reg = <0x0 0x80>;
> > + };
> > +
> > + parition@1 {
> > + label = "spi_flash_part1";
> > + reg = <0x80 0x70>;
> > + };
> > +
> > + parition@2 {
> > + label = "spi_flash_part2";
> > + reg = <0xF0 0x10>;
> > + };
> > + };
> > +};
>
> ...
>
> > +/* Default Env vars */
> > +#define CONFIG_IPADDR 0.0.0.0 /* In order to cause an error */
> > +#define CONFIG_SERVERIP 0.0.0.0 /* In order to cause an error */
> > +#define CONFIG_NETMASK 255.255.255.0
> > +#define CONFIG_GATEWAYIP0.0.0.0
> > +#define CONFIG_ETHPRIME "eth0"
> > +#define CONFIG_ROOTPATH "/srv/nfs/" /* Default Dir for
> NFS */
> > +#define CONFIG_ENV_OVERWRITE/* ethaddr can be reprogrammed */
> > +#define CONFIG_EXTRA_ENV_SETTINGS "bootcmd=run get_images; " \
> > + "run set_bootargs; " \
> > + "booti $kernel_addr_r " \
> > + "$ramdisk_addr_r " \
> > + "$fdt_addr_r\0" \
> > + "extra_params=pci=pcie_bus_safe\0" \
> > + "kernel_addr_r=0x20200\0" \
> > + "initrd_addr=0x20600\0"\
> > + "initrd_size=0x200\0" \
> > + "fdt_addr_r=0x20100\0"\
> > + "loadaddr=0x20200\0" \
> > + "hostname=marvell\0"\
> > + "ramdisk_addr_r=0x20600\0"\
> > + "ramfs_name=-\0"\
> > + "cpuidle=cpuidle.off=1\0" \
> > + "fdt_name=fdt.dtb\0"\
> > + "netdev=eth0\0" \
> > + "ethaddr=00:51:82:11:22:00\0" \
> > + "eth1addr=00:51:82:11:22:01\0" \
> > + "image_name=Image\0"\
> > + "get_ramfs=if test \"${ramfs_name}\"" \
> > + " != \"-\"; then setenv " \
> > + "ramdisk_addr_r 0x800; " \
> > + "tftpboot $ramdisk_addr_r " \
> > + "$ramfs_name; else setenv " \
> > + "ramdisk_addr_r -;fi\0" \
> > + "get_images=tftpboot $kernel_addr_r " \
> > + "$image_name; tftpboot " \
> > + "$fdt_addr_r $fdt_name; " \
> > + "run get_ramfs\0" \
> > + "console=" "console=ttyS0,115200 "\
> > + "earlycon=uart8250,mmio32,0xf0512000\0"\
> > + "root=root=/dev/nfs rw\0" \
> > + "set_bootargs=setenv bootargs $console"\
> > + " $root ip=$ipaddr:$serverip:" \
> > + "$gatewayip:$netmask:$hostname"\
> > + ":$netdev:none nfsroot="\
> > + "$serverip:$rootpath,tcp,v3 " \
> > + "$extra_params " \
> > + "$cpuidle"
>
> This is hard to read, where is the variable name, where there is its
> value, etc...
>
> And it would be better to use distroboot instead of manually written
> boot script.
>
Yep I'll try to clean that up. Again this is straight from the older SDK so
it'snot follow current best practice.
>
Re: [PATCH 6/7] arm: mvebu: Add RD-AC5X board
On Friday 16 September 2022 16:54:22 Chris Packham wrote:
> +&spi0 {
> + status = "okay";
> +
> + spiflash0: flash@0 {
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <5000>;
> + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> + reg = <0>;
> +
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition@0 {
> + label = "spi_flash_part0";
I guess such label is useless. There is something stored, so it would be
a wise idea to put there correct label. I do not know how it is on this
platform, but on A3720 at offset 0 is "firmware", which consist of CM3
part, A53 part and U-Boot. It is not even U-Boot itself.
> + reg = <0x0 0x80>;
> + };
> +
> + parition@1 {
> + label = "spi_flash_part1";
> + reg = <0x80 0x70>;
> + };
> +
> + parition@2 {
> + label = "spi_flash_part2";
> + reg = <0xF0 0x10>;
> + };
> + };
> +};
...
> +/* Default Env vars */
> +#define CONFIG_IPADDR 0.0.0.0 /* In order to cause an error */
> +#define CONFIG_SERVERIP 0.0.0.0 /* In order to cause an error */
> +#define CONFIG_NETMASK 255.255.255.0
> +#define CONFIG_GATEWAYIP0.0.0.0
> +#define CONFIG_ETHPRIME "eth0"
> +#define CONFIG_ROOTPATH "/srv/nfs/" /* Default Dir for NFS */
> +#define CONFIG_ENV_OVERWRITE/* ethaddr can be reprogrammed */
> +#define CONFIG_EXTRA_ENV_SETTINGS "bootcmd=run get_images; " \
> + "run set_bootargs; " \
> + "booti $kernel_addr_r " \
> + "$ramdisk_addr_r " \
> + "$fdt_addr_r\0" \
> + "extra_params=pci=pcie_bus_safe\0" \
> + "kernel_addr_r=0x20200\0" \
> + "initrd_addr=0x20600\0"\
> + "initrd_size=0x200\0" \
> + "fdt_addr_r=0x20100\0"\
> + "loadaddr=0x20200\0" \
> + "hostname=marvell\0"\
> + "ramdisk_addr_r=0x20600\0"\
> + "ramfs_name=-\0"\
> + "cpuidle=cpuidle.off=1\0" \
> + "fdt_name=fdt.dtb\0"\
> + "netdev=eth0\0" \
> + "ethaddr=00:51:82:11:22:00\0" \
> + "eth1addr=00:51:82:11:22:01\0" \
> + "image_name=Image\0"\
> + "get_ramfs=if test \"${ramfs_name}\"" \
> + " != \"-\"; then setenv " \
> + "ramdisk_addr_r 0x800; " \
> + "tftpboot $ramdisk_addr_r " \
> + "$ramfs_name; else setenv " \
> + "ramdisk_addr_r -;fi\0" \
> + "get_images=tftpboot $kernel_addr_r " \
> + "$image_name; tftpboot " \
> + "$fdt_addr_r $fdt_name; " \
> + "run get_ramfs\0" \
> + "console=" "console=ttyS0,115200 "\
> + "earlycon=uart8250,mmio32,0xf0512000\0"\
> + "root=root=/dev/nfs rw\0" \
> + "set_bootargs=setenv bootargs $console"\
> + " $root ip=$ipaddr:$serverip:" \
> + "$gatewayip:$netmask:$hostname"\
> + ":$netdev:none nfsroot="\
> + "$serverip:$rootpath,tcp,v3 " \
> + "$extra_params " \
> + "$cpuidle"
This is hard to read, where is the variable name, where there is its
value, etc...
And it would be better to use distroboot instead of manually written
boot script.
[PATCH 6/7] arm: mvebu: Add RD-AC5X board
The RD-AC5X-32G16HVG6HLG-A0 development board main components and features
include:
* Main 12V/54V power supply
* 270 Gbps throughput packet processor on the main board
* DDR4:
* SR1: 2GB DDR4 2400MT/S(1GB x 2 pcs ) with ECC(1GB x 1 pcs)
* SR2: 4GB DDR4 2400MT/S(2GB x 2 pcs ) with ECC(2GB x 1 pcs)
* PCB co-layout with 4GB device to support 8GB (Dual CS) requirement
* 16GB eMMC (Samsung KLMAG1JETD-B041006)
* 16MB SPI NOR(GD25Q127C)
* 32 x 1000 Base-T interfaces
* 16 x 2500 Base-T interfaces
* SR1: 88E2540*4
* SR2: 88E2580*1+88E2540*2
* Six (6) x 25G Base-R SFP28 interfaces
* One (1) x RJ-45 console connector, interfacing to the on board UART
* One (1) x USB Type-A connector, interfacing to the USB 2.0 port (0)
* One (1) x USB Type-mini B connector, interfacing to the USB 2.0 port (1)
* One (1) x RJ-45 1G Base-T Management port, interfacing to the host port
(shared with PCIe)
Connected to 88E1512 Gigabit Ethernet Phy
* One (1) x Oculink port, interfacing to the PCIe port for external CPU
connection
* POE 802.3AT support on Port 1 ~ Port 32, 802.3BT support on Port 33 ~ Port 48
(Microsemi PD69208T4, PD69208M or TI TPS2388,TPS23881 solution)
* POE total power budget 780W
* LED interfaces per network port/POE
* LED interfaces (common) showing system status
* PTP TC mode Supported (Reserved M.2 connector to support BC mode)
Signed-off-by: Chris Packham
---
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/ac5-98dx35xx-rd.dts | 155 +
arch/arm/mach-mvebu/Kconfig| 9 +-
board/Marvell/mvebu_alleycat-5/MAINTAINERS | 6 +
board/Marvell/mvebu_alleycat-5/Makefile| 3 +
board/Marvell/mvebu_alleycat-5/board.c | 35 +
configs/mvebu_ac5_rd_defconfig | 89
include/configs/mvebu_alleycat-5.h | 92
8 files changed, 390 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/dts/ac5-98dx35xx-rd.dts
create mode 100644 board/Marvell/mvebu_alleycat-5/MAINTAINERS
create mode 100644 board/Marvell/mvebu_alleycat-5/Makefile
create mode 100644 board/Marvell/mvebu_alleycat-5/board.c
create mode 100644 configs/mvebu_ac5_rd_defconfig
create mode 100644 include/configs/mvebu_alleycat-5.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 7330121dba..a334596ada 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -274,7 +274,8 @@ dtb-$(CONFIG_ARCH_MVEBU) += \
cn9132-db-A.dtb \
cn9132-db-B.dtb \
cn9130-crb-A.dtb\
- cn9130-crb-B.dtb
+ cn9130-crb-B.dtb\
+ ac5-98dx35xx-rd.dtb
endif
dtb-$(CONFIG_ARCH_SYNQUACER) += synquacer-sc2a11-developerbox.dtb
diff --git a/arch/arm/dts/ac5-98dx35xx-rd.dts b/arch/arm/dts/ac5-98dx35xx-rd.dts
new file mode 100644
index 00..94eadd6f71
--- /dev/null
+++ b/arch/arm/dts/ac5-98dx35xx-rd.dts
@@ -0,0 +1,155 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree For RD-AC5X.
+ *
+ * Copyright (C) 2021 Marvell
+ * Copyright (C) 2022 Allied Telesis Labs
+ */
+/*
+ * Device Tree file for Marvell Alleycat 5X development board
+ * This board file supports the B configuration of the board
+ */
+
+/dts-v1/;
+
+#include "ac5-98dx35xx.dtsi"
+
+/ {
+ model = "Marvell RD-AC5X Board";
+ compatible = "marvell,rd-ac5x", "marvell,ac5x", "marvell,ac5";
+
+ aliases {
+ serial0 = &uart0;
+ spiflash0 = &spiflash0;
+ gpio0 = &gpio0;
+ gpio1 = &gpio1;
+ ethernet0 = ð0;
+ ethernet1 = ð1;
+ spi0 = &spi0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ pinctrl0 = &pinctrl0;
+ sar-reg0 = "/config-space/sar-reg";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x2 0x 0x0 0x4000>;
+ };
+
+ usb1phy: usb-phy {
+ compatible = "usb-nop-xceiv";
+ #phy-cells = <0>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ config-space {
+ sar-reg {
+ reg = <0x944F8204 0x1>;
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+ð0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+};
+
+/* USB0 is a host USB */
+&usb0 {
+ status = "okay";
+};
+
+/* USB1 is a peripheral USB */
+&usb1 {
+ status = "okay";
+ phys = <&usb1phy>;
+ phy-names = "usb-phy";
+ dr_mode = "peripheral";
+};
+
+&spi0 {
+ status = "okay";
+
+ spiflash0: flash@0 {
+ compatible = "jedec,spi-n
